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radeonsi: use an SGPR instead of VGT_INDX_OFFSET
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "../radeon/r600_cs.h"
30 #include "sid.h"
31
32 #include "util/u_blitter.h"
33 #include "util/u_format.h"
34 #include "util/u_index_modify.h"
35 #include "util/u_memory.h"
36 #include "util/u_upload_mgr.h"
37
38 /*
39 * Shaders
40 */
41
42 static void si_pipe_shader_es(struct pipe_context *ctx, struct si_pipe_shader *shader)
43 {
44 struct si_context *sctx = (struct si_context *)ctx;
45 struct si_pm4_state *pm4;
46 unsigned num_sgprs, num_user_sgprs;
47 unsigned vgpr_comp_cnt;
48 uint64_t va;
49
50 si_pm4_delete_state(sctx, es, shader->pm4);
51 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
52
53 if (pm4 == NULL)
54 return;
55
56 va = r600_resource_va(ctx->screen, (void *)shader->bo);
57 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
58
59 vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
60
61 num_user_sgprs = SI_VS_NUM_USER_SGPR;
62 num_sgprs = shader->num_sgprs;
63 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
64 if ((num_user_sgprs + 1) > num_sgprs) {
65 /* Last 2 reserved SGPRs are used for VCC */
66 num_sgprs = num_user_sgprs + 1 + 2;
67 }
68 assert(num_sgprs <= 104);
69
70 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
71 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
72 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
73 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
74 S_00B328_SGPRS((num_sgprs - 1) / 8) |
75 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt));
76 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
77 S_00B32C_USER_SGPR(num_user_sgprs));
78
79 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
80 }
81
82 static void si_pipe_shader_gs(struct pipe_context *ctx, struct si_pipe_shader *shader)
83 {
84 struct si_context *sctx = (struct si_context *)ctx;
85 unsigned gs_vert_itemsize = shader->shader.noutput * (16 >> 2);
86 unsigned gs_max_vert_out = shader->shader.gs_max_out_vertices;
87 unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
88 unsigned cut_mode;
89 struct si_pm4_state *pm4;
90 unsigned num_sgprs, num_user_sgprs;
91 uint64_t va;
92
93 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
94 assert(gsvs_itemsize < (1 << 15));
95
96 si_pm4_delete_state(sctx, gs, shader->pm4);
97 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
98
99 if (pm4 == NULL)
100 return;
101
102 if (gs_max_vert_out <= 128) {
103 cut_mode = V_028A40_GS_CUT_128;
104 } else if (gs_max_vert_out <= 256) {
105 cut_mode = V_028A40_GS_CUT_256;
106 } else if (gs_max_vert_out <= 512) {
107 cut_mode = V_028A40_GS_CUT_512;
108 } else {
109 assert(gs_max_vert_out <= 1024);
110 cut_mode = V_028A40_GS_CUT_1024;
111 }
112
113 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
114 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
115 S_028A40_CUT_MODE(cut_mode)|
116 S_028A40_ES_WRITE_OPTIMIZE(1) |
117 S_028A40_GS_WRITE_OPTIMIZE(1));
118
119 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
120 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize);
121 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize);
122
123 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
124 shader->shader.nparam * (16 >> 2));
125 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
126
127 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
128
129 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
130
131 va = r600_resource_va(ctx->screen, (void *)shader->bo);
132 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
133 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
134 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
135
136 num_user_sgprs = SI_GS_NUM_USER_SGPR;
137 num_sgprs = shader->num_sgprs;
138 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
139 if ((num_user_sgprs + 2) > num_sgprs) {
140 /* Last 2 reserved SGPRs are used for VCC */
141 num_sgprs = num_user_sgprs + 2 + 2;
142 }
143 assert(num_sgprs <= 104);
144
145 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
146 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
147 S_00B228_SGPRS((num_sgprs - 1) / 8));
148 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
149 S_00B22C_USER_SGPR(num_user_sgprs));
150
151 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
152 }
153
154 static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
155 {
156 struct si_context *sctx = (struct si_context *)ctx;
157 struct si_pm4_state *pm4;
158 unsigned num_sgprs, num_user_sgprs;
159 unsigned nparams, i, vgpr_comp_cnt;
160 uint64_t va;
161
162 si_pm4_delete_state(sctx, vs, shader->pm4);
163 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
164
165 if (pm4 == NULL)
166 return;
167
168 va = r600_resource_va(ctx->screen, (void *)shader->bo);
169 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
170
171 vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
172
173 num_user_sgprs = SI_VS_NUM_USER_SGPR;
174 num_sgprs = shader->num_sgprs;
175 if (num_user_sgprs > num_sgprs) {
176 /* Last 2 reserved SGPRs are used for VCC */
177 num_sgprs = num_user_sgprs + 2;
178 }
179 assert(num_sgprs <= 104);
180
181 /* Certain attributes (position, psize, etc.) don't count as params.
182 * VS is required to export at least one param and r600_shader_from_tgsi()
183 * takes care of adding a dummy export.
184 */
185 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
186 switch (shader->shader.output[i].name) {
187 case TGSI_SEMANTIC_CLIPVERTEX:
188 case TGSI_SEMANTIC_POSITION:
189 case TGSI_SEMANTIC_PSIZE:
190 break;
191 default:
192 nparams++;
193 }
194 }
195 if (nparams < 1)
196 nparams = 1;
197
198 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
199 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
200
201 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
202 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
203 S_02870C_POS1_EXPORT_FORMAT(shader->shader.nr_pos_exports > 1 ?
204 V_02870C_SPI_SHADER_4COMP :
205 V_02870C_SPI_SHADER_NONE) |
206 S_02870C_POS2_EXPORT_FORMAT(shader->shader.nr_pos_exports > 2 ?
207 V_02870C_SPI_SHADER_4COMP :
208 V_02870C_SPI_SHADER_NONE) |
209 S_02870C_POS3_EXPORT_FORMAT(shader->shader.nr_pos_exports > 3 ?
210 V_02870C_SPI_SHADER_4COMP :
211 V_02870C_SPI_SHADER_NONE));
212
213 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
214 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
215 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
216 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
217 S_00B128_SGPRS((num_sgprs - 1) / 8) |
218 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
219 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
220 S_00B12C_USER_SGPR(num_user_sgprs) |
221 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
222 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
223 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
224 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
225 S_00B12C_SO_EN(!!shader->selector->so.num_outputs));
226
227 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
228 }
229
230 static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
231 {
232 struct si_context *sctx = (struct si_context *)ctx;
233 struct si_pm4_state *pm4;
234 unsigned i, spi_ps_in_control, db_shader_control;
235 unsigned num_sgprs, num_user_sgprs;
236 unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
237 uint64_t va;
238
239 si_pm4_delete_state(sctx, ps, shader->pm4);
240 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
241
242 if (pm4 == NULL)
243 return;
244
245 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
246 S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer);
247
248 for (i = 0; i < shader->shader.ninput; i++) {
249 switch (shader->shader.input[i].name) {
250 case TGSI_SEMANTIC_POSITION:
251 if (shader->shader.input[i].centroid) {
252 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
253 * Possible vaules:
254 * 0 -> Position = pixel center (default)
255 * 1 -> Position = pixel centroid
256 * 2 -> Position = iterated sample number XXX:
257 * What does this mean?
258 */
259 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
260 }
261 /* Fall through */
262 case TGSI_SEMANTIC_FACE:
263 continue;
264 }
265 }
266
267 db_shader_control |= shader->db_shader_control;
268
269 if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
270 db_shader_control |= S_02880C_KILL_ENABLE(1);
271
272 if (sctx->b.chip_class >= CIK)
273 db_shader_control |=
274 S_02880C_CONSERVATIVE_Z_EXPORT(shader->shader.ps_conservative_z);
275
276 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.nparam) |
277 S_0286D8_BC_OPTIMIZE_DISABLE(1);
278
279 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
280 spi_ps_input_ena = shader->spi_ps_input_ena;
281 /* we need to enable at least one of them, otherwise we hang the GPU */
282 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
283 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
284 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
285 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
286 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
287 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
288 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
289 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
290
291 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
292 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
293 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
294
295 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
296 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
297 shader->spi_shader_col_format);
298 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
299
300 va = r600_resource_va(ctx->screen, (void *)shader->bo);
301 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
302 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
303 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
304
305 num_user_sgprs = SI_PS_NUM_USER_SGPR;
306 num_sgprs = shader->num_sgprs;
307 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
308 if ((num_user_sgprs + 1) > num_sgprs) {
309 /* Last 2 reserved SGPRs are used for VCC */
310 num_sgprs = num_user_sgprs + 1 + 2;
311 }
312 assert(num_sgprs <= 104);
313
314 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
315 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
316 S_00B028_SGPRS((num_sgprs - 1) / 8));
317 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
318 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
319 S_00B02C_USER_SGPR(num_user_sgprs));
320
321 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
322
323 shader->cb0_is_integer = sctx->framebuffer.cb0_is_integer;
324 shader->sprite_coord_enable = sctx->sprite_coord_enable;
325 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
326 }
327
328 /*
329 * Drawing
330 */
331
332 static unsigned si_conv_pipe_prim(unsigned pprim)
333 {
334 static const unsigned prim_conv[] = {
335 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
336 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
337 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
338 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
339 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
340 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
341 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
342 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
343 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
344 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
345 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
346 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
347 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
348 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ
349 };
350 unsigned result = prim_conv[pprim];
351 if (result == ~0) {
352 R600_ERR("unsupported primitive type %d\n", pprim);
353 }
354 return result;
355 }
356
357 static unsigned si_conv_prim_to_gs_out(unsigned mode)
358 {
359 static const int prim_conv[] = {
360 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
361 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
362 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
363 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
364 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
365 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
366 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
367 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
368 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
369 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
370 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
371 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
372 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
373 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
374 };
375 assert(mode < Elements(prim_conv));
376
377 return prim_conv[mode];
378 }
379
380 static bool si_update_draw_info_state(struct si_context *sctx,
381 const struct pipe_draw_info *info,
382 const struct pipe_index_buffer *ib)
383 {
384 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
385 struct si_shader *vs = si_get_vs_state(sctx);
386 unsigned prim = si_conv_pipe_prim(info->mode);
387 unsigned gs_out_prim =
388 si_conv_prim_to_gs_out(sctx->gs_shader ?
389 sctx->gs_shader->current->shader.gs_output_prim :
390 info->mode);
391 unsigned ls_mask = 0;
392
393 if (pm4 == NULL)
394 return false;
395
396 if (prim == ~0) {
397 FREE(pm4);
398 return false;
399 }
400
401 if (sctx->b.chip_class >= CIK) {
402 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
403 bool wd_switch_on_eop = prim == V_008958_DI_PT_POLYGON ||
404 prim == V_008958_DI_PT_LINELOOP ||
405 prim == V_008958_DI_PT_TRIFAN ||
406 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
407 info->primitive_restart ||
408 (rs ? rs->line_stipple_enable : false);
409 /* If the WD switch is false, the IA switch must be false too. */
410 bool ia_switch_on_eop = wd_switch_on_eop;
411
412 si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
413 ib->index_size == 4 ? 0xFC000000 : 0xFC00);
414
415 si_pm4_cmd_begin(pm4, PKT3_DRAW_PREAMBLE);
416 si_pm4_cmd_add(pm4, prim); /* VGT_PRIMITIVE_TYPE */
417 si_pm4_cmd_add(pm4, /* IA_MULTI_VGT_PARAM */
418 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
419 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
420 S_028AA8_PRIMGROUP_SIZE(63) |
421 S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
422 si_pm4_cmd_add(pm4, 0); /* VGT_LS_HS_CONFIG */
423 si_pm4_cmd_end(pm4, false);
424 } else {
425 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
426 }
427
428 si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
429 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
430 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
431
432 if (prim == V_008958_DI_PT_LINELIST)
433 ls_mask = 1;
434 else if (prim == V_008958_DI_PT_LINESTRIP)
435 ls_mask = 2;
436 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
437 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
438 sctx->pa_sc_line_stipple);
439
440 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
441 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
442 S_028814_PROVOKING_VTX_LAST(1) | sctx->pa_su_sc_mode_cntl);
443 } else {
444 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, sctx->pa_su_sc_mode_cntl);
445 }
446 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
447 S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
448 S_02881C_USE_VTX_EDGE_FLAG(vs->vs_out_edgeflag) |
449 S_02881C_USE_VTX_RENDER_TARGET_INDX(vs->vs_out_layer) |
450 S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs->clip_dist_write & 0x0F) != 0) |
451 S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs->clip_dist_write & 0xF0) != 0) |
452 S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write) |
453 (sctx->queued.named.rasterizer->clip_plane_enable &
454 vs->clip_dist_write));
455 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL,
456 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
457 (vs->clip_dist_write ? 0 :
458 sctx->queued.named.rasterizer->clip_plane_enable & 0x3F));
459
460 si_pm4_set_state(sctx, draw_info, pm4);
461 return true;
462 }
463
464 static void si_update_spi_map(struct si_context *sctx)
465 {
466 struct si_shader *ps = &sctx->ps_shader->current->shader;
467 struct si_shader *vs = si_get_vs_state(sctx);
468 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
469 unsigned i, j, tmp;
470
471 for (i = 0; i < ps->ninput; i++) {
472 unsigned name = ps->input[i].name;
473 unsigned param_offset = ps->input[i].param_offset;
474
475 if (name == TGSI_SEMANTIC_POSITION)
476 /* Read from preloaded VGPRs, not parameters */
477 continue;
478
479 bcolor:
480 tmp = 0;
481
482 if (ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
483 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
484 sctx->ps_shader->current->key.ps.flatshade)) {
485 tmp |= S_028644_FLAT_SHADE(1);
486 }
487
488 if (name == TGSI_SEMANTIC_GENERIC &&
489 sctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
490 tmp |= S_028644_PT_SPRITE_TEX(1);
491 }
492
493 for (j = 0; j < vs->noutput; j++) {
494 if (name == vs->output[j].name &&
495 ps->input[i].sid == vs->output[j].sid) {
496 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
497 break;
498 }
499 }
500
501 if (j == vs->noutput) {
502 /* No corresponding output found, load defaults into input */
503 tmp |= S_028644_OFFSET(0x20);
504 }
505
506 si_pm4_set_reg(pm4,
507 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
508 tmp);
509
510 if (name == TGSI_SEMANTIC_COLOR &&
511 sctx->ps_shader->current->key.ps.color_two_side) {
512 name = TGSI_SEMANTIC_BCOLOR;
513 param_offset++;
514 goto bcolor;
515 }
516 }
517
518 si_pm4_set_state(sctx, spi, pm4);
519 }
520
521 /* Initialize state related to ESGS / GSVS ring buffers */
522 static void si_init_gs_rings(struct si_context *sctx)
523 {
524 unsigned size = 128 * 1024;
525
526 assert(!sctx->gs_rings);
527 sctx->gs_rings = si_pm4_alloc_state(sctx);
528
529 sctx->esgs_ring.buffer =
530 pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
531 PIPE_USAGE_DEFAULT, size);
532 sctx->esgs_ring.buffer_size = size;
533
534 size = 64 * 1024 * 1024;
535 sctx->gsvs_ring.buffer =
536 pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
537 PIPE_USAGE_DEFAULT, size);
538 sctx->gsvs_ring.buffer_size = size;
539
540 if (sctx->b.chip_class >= CIK) {
541 si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
542 sctx->esgs_ring.buffer_size / 256);
543 si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
544 sctx->gsvs_ring.buffer_size / 256);
545 } else {
546 si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
547 sctx->esgs_ring.buffer_size / 256);
548 si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
549 sctx->gsvs_ring.buffer_size / 256);
550 }
551
552 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
553 &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size,
554 true, true, 4, 64);
555 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
556 &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size,
557 false, false, 0, 0);
558 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
559 &sctx->gsvs_ring, 0, sctx->gsvs_ring.buffer_size,
560 false, false, 0, 0);
561 }
562
563 static void si_update_derived_state(struct si_context *sctx)
564 {
565 struct pipe_context * ctx = (struct pipe_context*)sctx;
566
567 if (!sctx->blitter->running) {
568 /* Flush depth textures which need to be flushed. */
569 for (int i = 0; i < SI_NUM_SHADERS; i++) {
570 if (sctx->samplers[i].depth_texture_mask) {
571 si_flush_depth_textures(sctx, &sctx->samplers[i]);
572 }
573 if (sctx->samplers[i].compressed_colortex_mask) {
574 si_decompress_color_textures(sctx, &sctx->samplers[i]);
575 }
576 }
577 }
578
579 if (sctx->gs_shader) {
580 si_shader_select(ctx, sctx->gs_shader);
581
582 if (!sctx->gs_shader->current->pm4) {
583 si_pipe_shader_gs(ctx, sctx->gs_shader->current);
584 si_pipe_shader_vs(ctx,
585 sctx->gs_shader->current->gs_copy_shader);
586 }
587
588 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
589 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
590
591 sctx->b.streamout.stride_in_dw = sctx->gs_shader->so.stride;
592
593 si_shader_select(ctx, sctx->vs_shader);
594
595 if (!sctx->vs_shader->current->pm4)
596 si_pipe_shader_es(ctx, sctx->vs_shader->current);
597
598 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
599
600 if (!sctx->gs_rings)
601 si_init_gs_rings(sctx);
602 if (sctx->emitted.named.gs_rings != sctx->gs_rings)
603 sctx->b.flags |= R600_CONTEXT_VGT_FLUSH;
604 si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
605
606 si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
607 &sctx->gsvs_ring,
608 sctx->gs_shader->current->shader.gs_max_out_vertices *
609 sctx->gs_shader->current->shader.noutput * 16,
610 64, true, true, 4, 16);
611
612 if (!sctx->gs_on) {
613 sctx->gs_on = si_pm4_alloc_state(sctx);
614
615 si_pm4_set_reg(sctx->gs_on, R_028B54_VGT_SHADER_STAGES_EN,
616 S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
617 S_028B54_GS_EN(1) |
618 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER));
619 }
620 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_on);
621 } else {
622 si_shader_select(ctx, sctx->vs_shader);
623
624 if (!sctx->vs_shader->current->pm4)
625 si_pipe_shader_vs(ctx, sctx->vs_shader->current);
626
627 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
628
629 sctx->b.streamout.stride_in_dw = sctx->vs_shader->so.stride;
630
631 if (!sctx->gs_off) {
632 sctx->gs_off = si_pm4_alloc_state(sctx);
633
634 si_pm4_set_reg(sctx->gs_off, R_028A40_VGT_GS_MODE, 0);
635 si_pm4_set_reg(sctx->gs_off, R_028B54_VGT_SHADER_STAGES_EN, 0);
636 }
637 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_off);
638 si_pm4_bind_state(sctx, gs_rings, NULL);
639 si_pm4_bind_state(sctx, gs, NULL);
640 si_pm4_bind_state(sctx, es, NULL);
641 }
642
643 si_shader_select(ctx, sctx->ps_shader);
644
645 if (!sctx->ps_shader->current->pm4 ||
646 sctx->ps_shader->current->cb0_is_integer != sctx->framebuffer.cb0_is_integer)
647 si_pipe_shader_ps(ctx, sctx->ps_shader->current);
648
649 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
650
651 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs)) {
652 /* XXX: Emitting the PS state even when only the VS changed
653 * fixes random failures with piglit glsl-max-varyings.
654 * Not sure why...
655 */
656 sctx->emitted.named.ps = NULL;
657 si_update_spi_map(sctx);
658 }
659 }
660
661 static void si_vertex_buffer_update(struct si_context *sctx)
662 {
663 struct pipe_context *ctx = &sctx->b.b;
664 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
665 bool bound[PIPE_MAX_ATTRIBS] = {};
666 unsigned i, count;
667 uint64_t va;
668
669 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
670
671 count = sctx->vertex_elements->count;
672 assert(count <= 256 / 4);
673
674 si_pm4_sh_data_begin(pm4);
675 for (i = 0 ; i < count; i++) {
676 struct pipe_vertex_element *ve = &sctx->vertex_elements->elements[i];
677 struct pipe_vertex_buffer *vb;
678 struct r600_resource *rbuffer;
679 unsigned offset;
680
681 if (ve->vertex_buffer_index >= sctx->nr_vertex_buffers)
682 continue;
683
684 vb = &sctx->vertex_buffer[ve->vertex_buffer_index];
685 rbuffer = (struct r600_resource*)vb->buffer;
686 if (rbuffer == NULL)
687 continue;
688
689 offset = 0;
690 offset += vb->buffer_offset;
691 offset += ve->src_offset;
692
693 va = r600_resource_va(ctx->screen, (void*)rbuffer);
694 va += offset;
695
696 /* Fill in T# buffer resource description */
697 si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF);
698 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
699 S_008F04_STRIDE(vb->stride)));
700 if (vb->stride)
701 /* Round up by rounding down and adding 1 */
702 si_pm4_sh_data_add(pm4,
703 (vb->buffer->width0 - offset -
704 util_format_get_blocksize(ve->src_format)) /
705 vb->stride + 1);
706 else
707 si_pm4_sh_data_add(pm4, vb->buffer->width0 - offset);
708 si_pm4_sh_data_add(pm4, sctx->vertex_elements->rsrc_word3[i]);
709
710 if (!bound[ve->vertex_buffer_index]) {
711 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ,
712 RADEON_PRIO_SHADER_BUFFER_RO);
713 bound[ve->vertex_buffer_index] = true;
714 }
715 }
716 si_pm4_sh_data_end(pm4, sctx->gs_shader ?
717 R_00B330_SPI_SHADER_USER_DATA_ES_0 :
718 R_00B130_SPI_SHADER_USER_DATA_VS_0,
719 SI_SGPR_VERTEX_BUFFER);
720 si_pm4_set_state(sctx, vertex_buffers, pm4);
721 }
722
723 static void si_state_draw(struct si_context *sctx,
724 const struct pipe_draw_info *info,
725 const struct pipe_index_buffer *ib)
726 {
727 unsigned sh_base_reg = (sctx->gs_shader ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
728 R_00B130_SPI_SHADER_USER_DATA_VS_0);
729 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
730
731 if (pm4 == NULL)
732 return;
733
734 /* queries need some special values
735 * (this is non-zero if any query is active) */
736 if (sctx->b.num_occlusion_queries > 0) {
737 if (sctx->b.chip_class >= CIK) {
738 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
739 S_028004_PERFECT_ZPASS_COUNTS(1) |
740 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
741 S_028004_ZPASS_ENABLE(1) |
742 S_028004_SLICE_EVEN_ENABLE(1) |
743 S_028004_SLICE_ODD_ENABLE(1));
744 } else {
745 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
746 S_028004_PERFECT_ZPASS_COUNTS(1) |
747 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
748 }
749 }
750
751 if (info->count_from_stream_output) {
752 struct r600_so_target *t =
753 (struct r600_so_target*)info->count_from_stream_output;
754 uint64_t va = r600_resource_va(&sctx->screen->b.b,
755 &t->buf_filled_size->b.b);
756 va += t->buf_filled_size_offset;
757
758 si_pm4_set_reg(pm4, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
759 t->stride_in_dw);
760
761 si_pm4_cmd_begin(pm4, PKT3_COPY_DATA);
762 si_pm4_cmd_add(pm4,
763 COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
764 COPY_DATA_DST_SEL(COPY_DATA_REG) |
765 COPY_DATA_WR_CONFIRM);
766 si_pm4_cmd_add(pm4, va); /* src address lo */
767 si_pm4_cmd_add(pm4, va >> 32UL); /* src address hi */
768 si_pm4_cmd_add(pm4, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
769 si_pm4_cmd_add(pm4, 0); /* unused */
770 si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ,
771 RADEON_PRIO_MIN);
772 si_pm4_cmd_end(pm4, true);
773 }
774
775 /* draw packet */
776 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
777 if (ib->index_size == 4) {
778 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (SI_BIG_ENDIAN ?
779 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
780 } else {
781 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (SI_BIG_ENDIAN ?
782 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
783 }
784 si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
785
786 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
787 si_pm4_cmd_add(pm4, info->instance_count);
788 si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
789
790 if (!info->indirect) {
791 si_pm4_set_reg(pm4, sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
792 info->indexed ? info->index_bias : info->start);
793 si_pm4_set_reg(pm4, sh_base_reg + SI_SGPR_START_INSTANCE * 4,
794 info->start_instance);
795 }
796
797 if (info->indexed) {
798 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
799 sctx->index_buffer.index_size;
800 uint64_t va;
801 va = r600_resource_va(&sctx->screen->b.b, ib->buffer);
802 va += ib->offset;
803
804 si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ,
805 RADEON_PRIO_MIN);
806 si_cmd_draw_index_2(pm4, max_size, va, info->count,
807 V_0287F0_DI_SRC_SEL_DMA,
808 sctx->b.predicate_drawing);
809 } else {
810 uint32_t initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
811 initiator |= S_0287F0_USE_OPAQUE(!!info->count_from_stream_output);
812 si_cmd_draw_index_auto(pm4, info->count, initiator, sctx->b.predicate_drawing);
813 }
814
815 si_pm4_set_state(sctx, draw, pm4);
816 }
817
818 void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom)
819 {
820 struct radeon_winsys_cs *cs = sctx->rings.gfx.cs;
821 uint32_t cp_coher_cntl = 0;
822
823 /* XXX SI flushes both ICACHE and KCACHE if either flag is set.
824 * XXX CIK shouldn't have this issue. Test CIK before separating the flags
825 * XXX to ensure there is no regression. Also find out if there is another
826 * XXX way to flush either ICACHE or KCACHE but not both for SI. */
827 if (sctx->flags & (R600_CONTEXT_INV_SHADER_CACHE |
828 R600_CONTEXT_INV_CONST_CACHE)) {
829 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1) |
830 S_0085F0_SH_KCACHE_ACTION_ENA(1);
831 }
832 if (sctx->flags & (R600_CONTEXT_INV_TEX_CACHE |
833 R600_CONTEXT_STREAMOUT_FLUSH)) {
834 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1) |
835 S_0085F0_TCL1_ACTION_ENA(1);
836 }
837 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB) {
838 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
839 S_0085F0_CB0_DEST_BASE_ENA(1) |
840 S_0085F0_CB1_DEST_BASE_ENA(1) |
841 S_0085F0_CB2_DEST_BASE_ENA(1) |
842 S_0085F0_CB3_DEST_BASE_ENA(1) |
843 S_0085F0_CB4_DEST_BASE_ENA(1) |
844 S_0085F0_CB5_DEST_BASE_ENA(1) |
845 S_0085F0_CB6_DEST_BASE_ENA(1) |
846 S_0085F0_CB7_DEST_BASE_ENA(1);
847 }
848 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB) {
849 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
850 S_0085F0_DB_DEST_BASE_ENA(1);
851 }
852
853 if (cp_coher_cntl) {
854 if (sctx->chip_class >= CIK) {
855 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
856 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
857 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
858 radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */
859 radeon_emit(cs, 0); /* CP_COHER_BASE */
860 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
861 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
862 } else {
863 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
864 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
865 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
866 radeon_emit(cs, 0); /* CP_COHER_BASE */
867 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
868 }
869 }
870
871 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META) {
872 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
873 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
874 }
875 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB_META) {
876 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
877 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
878 }
879
880 if (sctx->flags & (R600_CONTEXT_WAIT_3D_IDLE |
881 R600_CONTEXT_PS_PARTIAL_FLUSH)) {
882 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
883 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
884 } else if (sctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
885 /* Needed if streamout buffers are going to be used as a source. */
886 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
887 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
888 }
889
890 if (sctx->flags & R600_CONTEXT_VGT_FLUSH) {
891 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
892 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
893 }
894
895 sctx->flags = 0;
896 }
897
898 const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 13 }; /* number of CS dwords */
899
900 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
901 {
902 struct si_context *sctx = (struct si_context *)ctx;
903 struct pipe_index_buffer ib = {};
904 uint32_t i;
905
906 if (!info->count && (info->indexed || !info->count_from_stream_output))
907 return;
908
909 if (!sctx->ps_shader || !sctx->vs_shader)
910 return;
911
912 si_update_derived_state(sctx);
913 si_vertex_buffer_update(sctx);
914
915 if (info->indexed) {
916 /* Initialize the index buffer struct. */
917 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
918 ib.user_buffer = sctx->index_buffer.user_buffer;
919 ib.index_size = sctx->index_buffer.index_size;
920 ib.offset = sctx->index_buffer.offset + info->start * ib.index_size;
921
922 /* Translate or upload, if needed. */
923 if (ib.index_size == 1) {
924 struct pipe_resource *out_buffer = NULL;
925 unsigned out_offset;
926 void *ptr;
927
928 u_upload_alloc(sctx->b.uploader, 0, info->count * 2,
929 &out_offset, &out_buffer, &ptr);
930
931 util_shorten_ubyte_elts_to_userptr(
932 &sctx->b.b, &ib, 0, ib.offset, info->count, ptr);
933
934 pipe_resource_reference(&ib.buffer, NULL);
935 ib.user_buffer = NULL;
936 ib.buffer = out_buffer;
937 ib.offset = out_offset;
938 ib.index_size = 2;
939 }
940
941 if (ib.user_buffer && !ib.buffer) {
942 u_upload_data(sctx->b.uploader, 0, info->count * ib.index_size,
943 ib.user_buffer, &ib.offset, &ib.buffer);
944 }
945 }
946
947 if (!si_update_draw_info_state(sctx, info, &ib))
948 return;
949
950 si_state_draw(sctx, info, &ib);
951
952 sctx->pm4_dirty_cdwords += si_pm4_dirty_dw(sctx);
953
954 /* Check flush flags. */
955 if (sctx->b.flags)
956 sctx->atoms.s.cache_flush->dirty = true;
957
958 si_need_cs_space(sctx, 0, TRUE);
959
960 /* Emit states. */
961 for (i = 0; i < SI_NUM_ATOMS(sctx); i++) {
962 if (sctx->atoms.array[i]->dirty) {
963 sctx->atoms.array[i]->emit(&sctx->b, sctx->atoms.array[i]);
964 sctx->atoms.array[i]->dirty = false;
965 }
966 }
967
968 si_pm4_emit_dirty(sctx);
969 sctx->pm4_dirty_cdwords = 0;
970
971 #if SI_TRACE_CS
972 if (sctx->screen->b.trace_bo) {
973 si_trace_emit(sctx);
974 }
975 #endif
976
977 /* Set the depth buffer as dirty. */
978 if (sctx->framebuffer.state.zsbuf) {
979 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
980 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
981
982 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
983 }
984 if (sctx->framebuffer.compressed_cb_mask) {
985 struct pipe_surface *surf;
986 struct r600_texture *rtex;
987 unsigned mask = sctx->framebuffer.compressed_cb_mask;
988
989 do {
990 unsigned i = u_bit_scan(&mask);
991 surf = sctx->framebuffer.state.cbufs[i];
992 rtex = (struct r600_texture*)surf->texture;
993
994 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
995 } while (mask);
996 }
997
998 pipe_resource_reference(&ib.buffer, NULL);
999 sctx->b.num_draw_calls++;
1000 }