2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "radeonsi_pipe.h"
32 #include "radeonsi_shader.h"
40 static void si_pipe_shader_vs(struct pipe_context
*ctx
, struct si_pipe_shader
*shader
)
42 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
43 struct si_pm4_state
*pm4
;
44 unsigned num_sgprs
, num_user_sgprs
;
45 unsigned nparams
, i
, vgpr_comp_cnt
;
48 si_pm4_delete_state(rctx
, vs
, shader
->pm4
);
49 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
51 si_pm4_inval_shader_cache(pm4
);
53 /* Certain attributes (position, psize, etc.) don't count as params.
54 * VS is required to export at least one param and r600_shader_from_tgsi()
55 * takes care of adding a dummy export.
57 for (nparams
= 0, i
= 0 ; i
< shader
->shader
.noutput
; i
++) {
58 if (shader
->shader
.output
[i
].name
!= TGSI_SEMANTIC_POSITION
)
64 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
65 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
67 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
68 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
69 S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE
) |
70 S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE
) |
71 S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE
));
73 va
= r600_resource_va(ctx
->screen
, (void *)shader
->bo
);
74 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
);
75 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
76 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, va
>> 40);
78 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
79 num_sgprs
= shader
->num_sgprs
;
80 if (num_user_sgprs
> num_sgprs
)
81 num_sgprs
= num_user_sgprs
;
82 /* Last 2 reserved SGPRs are used for VCC */
84 assert(num_sgprs
<= 104);
86 vgpr_comp_cnt
= shader
->shader
.uses_instanceid
? 3 : 0;
88 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
89 S_00B128_VGPRS((shader
->num_vgprs
- 1) / 4) |
90 S_00B128_SGPRS((num_sgprs
- 1) / 8) |
91 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
));
92 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
93 S_00B12C_USER_SGPR(num_user_sgprs
));
95 si_pm4_bind_state(rctx
, vs
, shader
->pm4
);
98 static void si_pipe_shader_ps(struct pipe_context
*ctx
, struct si_pipe_shader
*shader
)
100 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
101 struct si_pm4_state
*pm4
;
102 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control
, db_shader_control
;
103 unsigned num_sgprs
, num_user_sgprs
;
104 boolean have_linear
= FALSE
, have_centroid
= FALSE
, have_perspective
= FALSE
;
105 unsigned fragcoord_interp_mode
= 0;
106 unsigned spi_baryc_cntl
, spi_ps_input_ena
, spi_shader_z_format
;
109 si_pm4_delete_state(rctx
, ps
, shader
->pm4
);
110 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
112 si_pm4_inval_shader_cache(pm4
);
114 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
115 for (i
= 0; i
< shader
->shader
.ninput
; i
++) {
116 switch (shader
->shader
.input
[i
].name
) {
117 case TGSI_SEMANTIC_POSITION
:
118 if (shader
->shader
.input
[i
].centroid
) {
119 /* fragcoord_interp_mode will be written to
120 * SPI_BARYC_CNTL.POS_FLOAT_LOCATION
122 * 0 -> Position = pixel center (default)
123 * 1 -> Position = pixel centroid
124 * 2 -> Position = iterated sample number XXX:
125 * What does this mean?
127 fragcoord_interp_mode
= 1;
130 case TGSI_SEMANTIC_FACE
:
134 if (shader
->shader
.input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
)
136 if (shader
->shader
.input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
137 have_perspective
= TRUE
;
138 if (shader
->shader
.input
[i
].centroid
)
139 have_centroid
= TRUE
;
142 for (i
= 0; i
< shader
->shader
.noutput
; i
++) {
143 if (shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_POSITION
)
144 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(1);
145 if (shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
146 db_shader_control
|= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
148 if (shader
->shader
.uses_kill
|| shader
->key
.ps
.alpha_func
!= PIPE_FUNC_ALWAYS
)
149 db_shader_control
|= S_02880C_KILL_ENABLE(1);
153 for (i
= 0; i
< shader
->shader
.noutput
; i
++) {
154 if (shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_POSITION
||
155 shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
157 else if (shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
158 if (shader
->shader
.fs_write_all
)
159 num_cout
= shader
->shader
.nr_cbufs
;
165 /* always at least export 1 component per pixel */
169 spi_ps_in_control
= S_0286D8_NUM_INTERP(shader
->shader
.ninterp
);
172 if (have_perspective
)
173 spi_baryc_cntl
|= have_centroid
?
174 S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1);
176 spi_baryc_cntl
|= have_centroid
?
177 S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1);
178 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(fragcoord_interp_mode
);
180 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
181 spi_ps_input_ena
= shader
->spi_ps_input_ena
;
182 /* we need to enable at least one of them, otherwise we hang the GPU */
183 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena
) ||
184 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) ||
185 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) ||
186 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena
) ||
187 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena
) ||
188 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
) ||
189 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
) ||
190 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena
));
192 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, spi_ps_input_ena
);
193 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
, spi_ps_input_ena
);
194 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
196 if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control
))
197 spi_shader_z_format
= V_028710_SPI_SHADER_32_GR
;
198 else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control
))
199 spi_shader_z_format
= V_028710_SPI_SHADER_32_R
;
201 spi_shader_z_format
= 0;
202 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
, spi_shader_z_format
);
203 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
,
204 shader
->spi_shader_col_format
);
206 va
= r600_resource_va(ctx
->screen
, (void *)shader
->bo
);
207 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
);
208 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
209 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, va
>> 40);
211 num_user_sgprs
= SI_PS_NUM_USER_SGPR
;
212 num_sgprs
= shader
->num_sgprs
;
213 if (num_user_sgprs
> num_sgprs
)
214 num_sgprs
= num_user_sgprs
;
215 /* Last 2 reserved SGPRs are used for VCC */
217 assert(num_sgprs
<= 104);
219 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
220 S_00B028_VGPRS((shader
->num_vgprs
- 1) / 4) |
221 S_00B028_SGPRS((num_sgprs
- 1) / 8));
222 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
223 S_00B02C_USER_SGPR(num_user_sgprs
));
225 si_pm4_set_reg(pm4
, R_02880C_DB_SHADER_CONTROL
, db_shader_control
);
227 shader
->sprite_coord_enable
= rctx
->sprite_coord_enable
;
228 si_pm4_bind_state(rctx
, ps
, shader
->pm4
);
235 static unsigned si_conv_pipe_prim(unsigned pprim
)
237 static const unsigned prim_conv
[] = {
238 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
239 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
240 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
241 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
242 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
243 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
244 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
245 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
246 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
247 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
248 [PIPE_PRIM_LINES_ADJACENCY
] = ~0,
249 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = ~0,
250 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = ~0,
251 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = ~0
253 unsigned result
= prim_conv
[pprim
];
255 R600_ERR("unsupported primitive type %d\n", pprim
);
260 static bool si_update_draw_info_state(struct r600_context
*rctx
,
261 const struct pipe_draw_info
*info
)
263 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
264 unsigned prim
= si_conv_pipe_prim(info
->mode
);
265 unsigned ls_mask
= 0;
275 si_pm4_set_reg(pm4
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
276 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
277 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
278 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
,
279 info
->indexed
? info
->index_bias
: info
->start
);
280 si_pm4_set_reg(pm4
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, info
->restart_index
);
281 si_pm4_set_reg(pm4
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, info
->primitive_restart
);
282 si_pm4_set_reg(pm4
, R_00B130_SPI_SHADER_USER_DATA_VS_0
+ SI_SGPR_START_INSTANCE
* 4,
283 info
->start_instance
);
285 if (prim
== V_008958_DI_PT_LINELIST
)
287 else if (prim
== V_008958_DI_PT_LINESTRIP
)
289 si_pm4_set_reg(pm4
, R_028A0C_PA_SC_LINE_STIPPLE
,
290 S_028A0C_AUTO_RESET_CNTL(ls_mask
) |
291 rctx
->pa_sc_line_stipple
);
293 if (info
->mode
== PIPE_PRIM_QUADS
|| info
->mode
== PIPE_PRIM_QUAD_STRIP
|| info
->mode
== PIPE_PRIM_POLYGON
) {
294 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
295 S_028814_PROVOKING_VTX_LAST(1) | rctx
->pa_su_sc_mode_cntl
);
297 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
, rctx
->pa_su_sc_mode_cntl
);
299 si_pm4_set_reg(pm4
, R_02881C_PA_CL_VS_OUT_CNTL
,
300 prim
== PIPE_PRIM_POINTS
? rctx
->pa_cl_vs_out_cntl
: 0
301 /*| (rctx->rasterizer->clip_plane_enable &
302 rctx->vs_shader->shader.clip_dist_write)*/);
303 si_pm4_set_reg(pm4
, R_028810_PA_CL_CLIP_CNTL
, rctx
->pa_cl_clip_cntl
304 /*| (rctx->vs_shader->shader.clip_dist_write ||
305 rctx->vs_shader->shader.vs_prohibit_ucps ?
306 0 : rctx->rasterizer->clip_plane_enable & 0x3F)*/);
308 si_pm4_set_state(rctx
, draw_info
, pm4
);
312 static void si_update_spi_map(struct r600_context
*rctx
)
314 struct si_shader
*ps
= &rctx
->ps_shader
->current
->shader
;
315 struct si_shader
*vs
= &rctx
->vs_shader
->current
->shader
;
316 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
319 for (i
= 0; i
< ps
->ninput
; i
++) {
320 unsigned name
= ps
->input
[i
].name
;
321 unsigned param_offset
= ps
->input
[i
].param_offset
;
323 if (name
== TGSI_SEMANTIC_POSITION
)
324 /* Read from preloaded VGPRs, not parameters */
330 if (ps
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
331 (ps
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
332 rctx
->ps_shader
->current
->key
.ps
.flatshade
)) {
333 tmp
|= S_028644_FLAT_SHADE(1);
336 if (name
== TGSI_SEMANTIC_GENERIC
&&
337 rctx
->sprite_coord_enable
& (1 << ps
->input
[i
].sid
)) {
338 tmp
|= S_028644_PT_SPRITE_TEX(1);
341 for (j
= 0; j
< vs
->noutput
; j
++) {
342 if (name
== vs
->output
[j
].name
&&
343 ps
->input
[i
].sid
== vs
->output
[j
].sid
) {
344 tmp
|= S_028644_OFFSET(vs
->output
[j
].param_offset
);
349 if (j
== vs
->noutput
) {
350 /* No corresponding output found, load defaults into input */
351 tmp
|= S_028644_OFFSET(0x20);
355 R_028644_SPI_PS_INPUT_CNTL_0
+ param_offset
* 4,
358 if (name
== TGSI_SEMANTIC_COLOR
&&
359 rctx
->ps_shader
->current
->key
.ps
.color_two_side
) {
360 name
= TGSI_SEMANTIC_BCOLOR
;
366 si_pm4_set_state(rctx
, spi
, pm4
);
369 static void si_update_derived_state(struct r600_context
*rctx
)
371 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
372 unsigned vs_dirty
= 0, ps_dirty
= 0;
374 if (!rctx
->blitter
->running
) {
375 /* Flush depth textures which need to be flushed. */
376 if (rctx
->vs_samplers
.depth_texture_mask
) {
377 si_flush_depth_textures(rctx
, &rctx
->vs_samplers
);
379 if (rctx
->ps_samplers
.depth_texture_mask
) {
380 si_flush_depth_textures(rctx
, &rctx
->ps_samplers
);
384 si_shader_select(ctx
, rctx
->vs_shader
, &vs_dirty
);
386 if (!rctx
->vs_shader
->current
->pm4
) {
387 si_pipe_shader_vs(ctx
, rctx
->vs_shader
->current
);
392 si_pm4_bind_state(rctx
, vs
, rctx
->vs_shader
->current
->pm4
);
396 si_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
398 if (!rctx
->ps_shader
->current
->pm4
) {
399 si_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
402 if (!rctx
->ps_shader
->current
->bo
) {
403 if (!rctx
->dummy_pixel_shader
->pm4
)
404 si_pipe_shader_ps(ctx
, rctx
->dummy_pixel_shader
);
406 si_pm4_bind_state(rctx
, vs
, rctx
->dummy_pixel_shader
->pm4
);
412 si_pm4_bind_state(rctx
, ps
, rctx
->ps_shader
->current
->pm4
);
415 if (si_pm4_state_changed(rctx
, ps
) || si_pm4_state_changed(rctx
, vs
)) {
416 /* XXX: Emitting the PS state even when only the VS changed
417 * fixes random failures with piglit glsl-max-varyings.
420 rctx
->emitted
.named
.ps
= NULL
;
421 si_update_spi_map(rctx
);
425 static void si_vertex_buffer_update(struct r600_context
*rctx
)
427 struct pipe_context
*ctx
= &rctx
->context
;
428 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
429 bool bound
[PIPE_MAX_ATTRIBS
] = {};
433 si_pm4_inval_texture_cache(pm4
);
435 /* bind vertex buffer once */
436 count
= rctx
->vertex_elements
->count
;
437 assert(count
<= 256 / 4);
439 si_pm4_sh_data_begin(pm4
);
440 for (i
= 0 ; i
< count
; i
++) {
441 struct pipe_vertex_element
*ve
= &rctx
->vertex_elements
->elements
[i
];
442 struct pipe_vertex_buffer
*vb
;
443 struct si_resource
*rbuffer
;
446 if (ve
->vertex_buffer_index
>= rctx
->nr_vertex_buffers
)
449 vb
= &rctx
->vertex_buffer
[ve
->vertex_buffer_index
];
450 rbuffer
= (struct si_resource
*)vb
->buffer
;
455 offset
+= vb
->buffer_offset
;
456 offset
+= ve
->src_offset
;
458 va
= r600_resource_va(ctx
->screen
, (void*)rbuffer
);
461 /* Fill in T# buffer resource description */
462 si_pm4_sh_data_add(pm4
, va
& 0xFFFFFFFF);
463 si_pm4_sh_data_add(pm4
, (S_008F04_BASE_ADDRESS_HI(va
>> 32) |
464 S_008F04_STRIDE(vb
->stride
)));
466 /* Round up by rounding down and adding 1 */
467 si_pm4_sh_data_add(pm4
,
468 (vb
->buffer
->width0
- offset
-
469 util_format_get_blocksize(ve
->src_format
)) /
472 si_pm4_sh_data_add(pm4
, vb
->buffer
->width0
- offset
);
473 si_pm4_sh_data_add(pm4
, rctx
->vertex_elements
->rsrc_word3
[i
]);
475 if (!bound
[ve
->vertex_buffer_index
]) {
476 si_pm4_add_bo(pm4
, rbuffer
, RADEON_USAGE_READ
);
477 bound
[ve
->vertex_buffer_index
] = true;
480 si_pm4_sh_data_end(pm4
, R_00B130_SPI_SHADER_USER_DATA_VS_0
, SI_SGPR_VERTEX_BUFFER
);
481 si_pm4_set_state(rctx
, vertex_buffers
, pm4
);
484 static void si_state_draw(struct r600_context
*rctx
,
485 const struct pipe_draw_info
*info
,
486 const struct pipe_index_buffer
*ib
)
488 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
490 /* queries need some special values
491 * (this is non-zero if any query is active) */
492 if (rctx
->num_cs_dw_queries_suspend
) {
493 struct si_state_dsa
*dsa
= rctx
->queued
.named
.dsa
;
495 si_pm4_set_reg(pm4
, R_028004_DB_COUNT_CONTROL
,
496 S_028004_PERFECT_ZPASS_COUNTS(1));
497 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
,
498 dsa
->db_render_override
|
499 S_02800C_NOOP_CULL_DISABLE(1));
503 si_pm4_cmd_begin(pm4
, PKT3_INDEX_TYPE
);
504 if (ib
->index_size
== 4) {
505 si_pm4_cmd_add(pm4
, V_028A7C_VGT_INDEX_32
| (R600_BIG_ENDIAN
?
506 V_028A7C_VGT_DMA_SWAP_32_BIT
: 0));
508 si_pm4_cmd_add(pm4
, V_028A7C_VGT_INDEX_16
| (R600_BIG_ENDIAN
?
509 V_028A7C_VGT_DMA_SWAP_16_BIT
: 0));
511 si_pm4_cmd_end(pm4
, rctx
->predicate_drawing
);
513 si_pm4_cmd_begin(pm4
, PKT3_NUM_INSTANCES
);
514 si_pm4_cmd_add(pm4
, info
->instance_count
);
515 si_pm4_cmd_end(pm4
, rctx
->predicate_drawing
);
518 uint32_t max_size
= (ib
->buffer
->width0
- ib
->offset
) /
519 rctx
->index_buffer
.index_size
;
521 va
= r600_resource_va(&rctx
->screen
->screen
, ib
->buffer
);
524 si_pm4_add_bo(pm4
, (struct si_resource
*)ib
->buffer
, RADEON_USAGE_READ
);
525 si_cmd_draw_index_2(pm4
, max_size
, va
, info
->count
,
526 V_0287F0_DI_SRC_SEL_DMA
,
527 rctx
->predicate_drawing
);
529 uint32_t initiator
= V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
530 initiator
|= S_0287F0_USE_OPAQUE(!!info
->count_from_stream_output
);
531 si_cmd_draw_index_auto(pm4
, info
->count
, initiator
, rctx
->predicate_drawing
);
533 si_pm4_set_state(rctx
, draw
, pm4
);
536 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
538 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
539 struct pipe_index_buffer ib
= {};
540 uint32_t cp_coher_cntl
;
542 if (!info
->count
&& (info
->indexed
|| !info
->count_from_stream_output
))
545 if (!rctx
->ps_shader
|| !rctx
->vs_shader
)
548 si_update_derived_state(rctx
);
549 si_vertex_buffer_update(rctx
);
552 /* Initialize the index buffer struct. */
553 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
554 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
555 ib
.index_size
= rctx
->index_buffer
.index_size
;
556 ib
.offset
= rctx
->index_buffer
.offset
+ info
->start
* ib
.index_size
;
558 /* Translate or upload, if needed. */
559 r600_translate_index_buffer(rctx
, &ib
, info
->count
);
561 if (ib
.user_buffer
&& !ib
.buffer
) {
562 r600_upload_index_buffer(rctx
, &ib
, info
->count
);
565 } else if (info
->count_from_stream_output
) {
566 r600_context_draw_opaque_count(rctx
, (struct r600_so_target
*)info
->count_from_stream_output
);
569 rctx
->vs_shader_so_strides
= rctx
->vs_shader
->current
->so_strides
;
571 if (!si_update_draw_info_state(rctx
, info
))
574 si_state_draw(rctx
, info
, &ib
);
576 cp_coher_cntl
= si_pm4_sync_flags(rctx
);
578 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
579 si_cmd_surface_sync(pm4
, cp_coher_cntl
);
580 si_pm4_set_state(rctx
, sync
, pm4
);
584 rctx
->pm4_dirty_cdwords
+= si_pm4_dirty_dw(rctx
);
586 si_need_cs_space(rctx
, 0, TRUE
);
588 si_pm4_emit_dirty(rctx
);
589 rctx
->pm4_dirty_cdwords
= 0;
592 if (rctx
->screen
->trace_bo
) {
593 r600_trace_emit(rctx
);
598 /* Enable stream out if needed. */
599 if (rctx
->streamout_start
) {
600 r600_context_streamout_begin(rctx
);
601 rctx
->streamout_start
= FALSE
;
605 rctx
->flags
|= R600_CONTEXT_DST_CACHES_DIRTY
;
607 /* Set the depth buffer as dirty. */
608 if (rctx
->framebuffer
.zsbuf
) {
609 struct pipe_surface
*surf
= rctx
->framebuffer
.zsbuf
;
610 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)surf
->texture
;
612 rtex
->dirty_db_mask
|= 1 << surf
->u
.tex
.level
;
615 pipe_resource_reference(&ib
.buffer
, NULL
);