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radeonsi: make sure LS-HS vector lanes are reasonably occupied
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32
33 #include "ac_debug.h"
34
35 /* special primitive types */
36 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
37
38 static unsigned si_conv_pipe_prim(unsigned mode)
39 {
40 static const unsigned prim_conv[] = {
41 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
42 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
43 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
44 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
45 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
46 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
47 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
48 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
49 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
50 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
51 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
55 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
56 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
57 };
58 assert(mode < ARRAY_SIZE(prim_conv));
59 return prim_conv[mode];
60 }
61
62 /**
63 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
64 * LS.LDS_SIZE is shared by all 3 shader stages.
65 *
66 * The information about LDS and other non-compile-time parameters is then
67 * written to userdata SGPRs.
68 */
69 static bool si_emit_derived_tess_state(struct si_context *sctx,
70 const struct pipe_draw_info *info,
71 unsigned *num_patches)
72 {
73 struct radeon_winsys_cs *cs = sctx->gfx_cs;
74 struct si_shader *ls_current;
75 struct si_shader_selector *ls;
76 /* The TES pointer will only be used for sctx->last_tcs.
77 * It would be wrong to think that TCS = TES. */
78 struct si_shader_selector *tcs =
79 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
80 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
81 bool has_primid_instancing_bug = sctx->chip_class == SI &&
82 sctx->screen->info.max_se == 1;
83 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
84 unsigned num_tcs_input_cp = info->vertices_per_patch;
85 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
86 unsigned num_tcs_patch_outputs;
87 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
88 unsigned input_patch_size, output_patch_size, output_patch0_offset;
89 unsigned perpatch_output_offset, lds_size;
90 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
91 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
92
93 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
94 if (sctx->chip_class >= GFX9) {
95 if (sctx->tcs_shader.cso)
96 ls_current = sctx->tcs_shader.current;
97 else
98 ls_current = sctx->fixed_func_tcs_shader.current;
99
100 ls = ls_current->key.part.tcs.ls;
101 } else {
102 ls_current = sctx->vs_shader.current;
103 ls = sctx->vs_shader.cso;
104 }
105
106 if (sctx->last_ls == ls_current &&
107 sctx->last_tcs == tcs &&
108 sctx->last_tes_sh_base == tes_sh_base &&
109 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
110 (!has_primid_instancing_bug ||
111 (sctx->last_tess_uses_primid == tess_uses_primid))) {
112 *num_patches = sctx->last_num_patches;
113 return false;
114 }
115
116 sctx->last_ls = ls_current;
117 sctx->last_tcs = tcs;
118 sctx->last_tes_sh_base = tes_sh_base;
119 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
120 sctx->last_tess_uses_primid = tess_uses_primid;
121
122 /* This calculates how shader inputs and outputs among VS, TCS, and TES
123 * are laid out in LDS. */
124 num_tcs_inputs = util_last_bit64(ls->outputs_written);
125
126 if (sctx->tcs_shader.cso) {
127 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
128 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
129 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
130 } else {
131 /* No TCS. Route varyings from LS to TES. */
132 num_tcs_outputs = num_tcs_inputs;
133 num_tcs_output_cp = num_tcs_input_cp;
134 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
135 }
136
137 input_vertex_size = num_tcs_inputs * 16;
138 output_vertex_size = num_tcs_outputs * 16;
139
140 input_patch_size = num_tcs_input_cp * input_vertex_size;
141
142 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
143 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
144
145 /* Ensure that we only need one wave per SIMD so we don't need to check
146 * resource usage. Also ensures that the number of tcs in and out
147 * vertices per threadgroup are at most 256.
148 */
149 unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
150 *num_patches = 256 / max_verts_per_patch;
151
152 /* Make sure that the data fits in LDS. This assumes the shaders only
153 * use LDS for the inputs and outputs.
154 *
155 * While CIK can use 64K per threadgroup, there is a hang on Stoney
156 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
157 * uses 32K at most on all GCN chips.
158 */
159 hardware_lds_size = 32768;
160 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
161 output_patch_size));
162
163 /* Make sure the output data fits in the offchip buffer */
164 *num_patches = MIN2(*num_patches,
165 (sctx->screen->tess_offchip_block_dw_size * 4) /
166 output_patch_size);
167
168 /* Not necessary for correctness, but improves performance. The
169 * specific value is taken from the proprietary driver.
170 */
171 *num_patches = MIN2(*num_patches, 40);
172
173 /* Make sure that vector lanes are reasonably occupied. It probably
174 * doesn't matter much because this is LS-HS, and TES is likely to
175 * occupy significantly more CUs.
176 */
177 unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
178 if (temp_verts_per_tg > 64 && temp_verts_per_tg % 64 < 48)
179 *num_patches = (temp_verts_per_tg & ~63) / max_verts_per_patch;
180
181 if (sctx->chip_class == SI) {
182 /* SI bug workaround, related to power management. Limit LS-HS
183 * threadgroups to only one wave.
184 */
185 unsigned one_wave = 64 / max_verts_per_patch;
186 *num_patches = MIN2(*num_patches, one_wave);
187 }
188
189 /* The VGT HS block increments the patch ID unconditionally
190 * within a single threadgroup. This results in incorrect
191 * patch IDs when instanced draws are used.
192 *
193 * The intended solution is to restrict threadgroups to
194 * a single instance by setting SWITCH_ON_EOI, which
195 * should cause IA to split instances up. However, this
196 * doesn't work correctly on SI when there is no other
197 * SE to switch to.
198 */
199 if (has_primid_instancing_bug && tess_uses_primid)
200 *num_patches = 1;
201
202 sctx->last_num_patches = *num_patches;
203
204 output_patch0_offset = input_patch_size * *num_patches;
205 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
206
207 /* Compute userdata SGPRs. */
208 assert(((input_vertex_size / 4) & ~0xff) == 0);
209 assert(((output_vertex_size / 4) & ~0xff) == 0);
210 assert(((input_patch_size / 4) & ~0x1fff) == 0);
211 assert(((output_patch_size / 4) & ~0x1fff) == 0);
212 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
213 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
214 assert(num_tcs_input_cp <= 32);
215 assert(num_tcs_output_cp <= 32);
216
217 uint64_t ring_va = r600_resource(sctx->tess_rings)->gpu_address;
218 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
219
220 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
221 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
222 tcs_out_layout = (output_patch_size / 4) |
223 (num_tcs_input_cp << 13) |
224 ring_va;
225 tcs_out_offsets = (output_patch0_offset / 16) |
226 ((perpatch_output_offset / 16) << 16);
227 offchip_layout = *num_patches |
228 (num_tcs_output_cp << 6) |
229 (pervertex_output_patch_size * *num_patches << 12);
230
231 /* Compute the LDS size. */
232 lds_size = output_patch0_offset + output_patch_size * *num_patches;
233
234 if (sctx->chip_class >= CIK) {
235 assert(lds_size <= 65536);
236 lds_size = align(lds_size, 512) / 512;
237 } else {
238 assert(lds_size <= 32768);
239 lds_size = align(lds_size, 256) / 256;
240 }
241
242 /* Set SI_SGPR_VS_STATE_BITS. */
243 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
244 C_VS_STATE_LS_OUT_VERTEX_SIZE;
245 sctx->current_vs_state |= tcs_in_layout;
246
247 if (sctx->chip_class >= GFX9) {
248 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
249 S_00B42C_LDS_SIZE(lds_size);
250
251 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
252
253 /* Set userdata SGPRs for merged LS-HS. */
254 radeon_set_sh_reg_seq(cs,
255 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
256 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
257 radeon_emit(cs, offchip_layout);
258 radeon_emit(cs, tcs_out_offsets);
259 radeon_emit(cs, tcs_out_layout);
260 } else {
261 unsigned ls_rsrc2 = ls_current->config.rsrc2;
262
263 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
264 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
265
266 /* Due to a hw bug, RSRC2_LS must be written twice with another
267 * LS register written in between. */
268 if (sctx->chip_class == CIK && sctx->family != CHIP_HAWAII)
269 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
270 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
271 radeon_emit(cs, ls_current->config.rsrc1);
272 radeon_emit(cs, ls_rsrc2);
273
274 /* Set userdata SGPRs for TCS. */
275 radeon_set_sh_reg_seq(cs,
276 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
277 radeon_emit(cs, offchip_layout);
278 radeon_emit(cs, tcs_out_offsets);
279 radeon_emit(cs, tcs_out_layout);
280 radeon_emit(cs, tcs_in_layout);
281 }
282
283 /* Set userdata SGPRs for TES. */
284 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
285 radeon_emit(cs, offchip_layout);
286 radeon_emit(cs, ring_va);
287
288 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
289 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
290 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
291
292 if (sctx->last_ls_hs_config != ls_hs_config) {
293 if (sctx->chip_class >= CIK) {
294 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
295 ls_hs_config);
296 } else {
297 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
298 ls_hs_config);
299 }
300 sctx->last_ls_hs_config = ls_hs_config;
301 return true; /* true if the context rolls */
302 }
303 return false;
304 }
305
306 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
307 {
308 switch (info->mode) {
309 case PIPE_PRIM_PATCHES:
310 return info->count / info->vertices_per_patch;
311 case SI_PRIM_RECTANGLE_LIST:
312 return info->count / 3;
313 default:
314 return u_prims_for_vertices(info->mode, info->count);
315 }
316 }
317
318 static unsigned
319 si_get_init_multi_vgt_param(struct si_screen *sscreen,
320 union si_vgt_param_key *key)
321 {
322 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
323 unsigned max_primgroup_in_wave = 2;
324
325 /* SWITCH_ON_EOP(0) is always preferable. */
326 bool wd_switch_on_eop = false;
327 bool ia_switch_on_eop = false;
328 bool ia_switch_on_eoi = false;
329 bool partial_vs_wave = false;
330 bool partial_es_wave = false;
331
332 if (key->u.uses_tess) {
333 /* SWITCH_ON_EOI must be set if PrimID is used. */
334 if (key->u.tess_uses_prim_id)
335 ia_switch_on_eoi = true;
336
337 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
338 if ((sscreen->info.family == CHIP_TAHITI ||
339 sscreen->info.family == CHIP_PITCAIRN ||
340 sscreen->info.family == CHIP_BONAIRE) &&
341 key->u.uses_gs)
342 partial_vs_wave = true;
343
344 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
345 if (sscreen->has_distributed_tess) {
346 if (key->u.uses_gs) {
347 if (sscreen->info.chip_class <= VI)
348 partial_es_wave = true;
349
350 /* GPU hang workaround. */
351 if (sscreen->info.family == CHIP_TONGA ||
352 sscreen->info.family == CHIP_FIJI ||
353 sscreen->info.family == CHIP_POLARIS10 ||
354 sscreen->info.family == CHIP_POLARIS11 ||
355 sscreen->info.family == CHIP_POLARIS12 ||
356 sscreen->info.family == CHIP_VEGAM)
357 partial_vs_wave = true;
358 } else {
359 partial_vs_wave = true;
360 }
361 }
362 }
363
364 /* This is a hardware requirement. */
365 if (key->u.line_stipple_enabled ||
366 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
367 ia_switch_on_eop = true;
368 wd_switch_on_eop = true;
369 }
370
371 if (sscreen->info.chip_class >= CIK) {
372 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
373 * 4 shader engines. Set 1 to pass the assertion below.
374 * The other cases are hardware requirements.
375 *
376 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
377 * for points, line strips, and tri strips.
378 */
379 if (sscreen->info.max_se < 4 ||
380 key->u.prim == PIPE_PRIM_POLYGON ||
381 key->u.prim == PIPE_PRIM_LINE_LOOP ||
382 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
383 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
384 (key->u.primitive_restart &&
385 (sscreen->info.family < CHIP_POLARIS10 ||
386 (key->u.prim != PIPE_PRIM_POINTS &&
387 key->u.prim != PIPE_PRIM_LINE_STRIP &&
388 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
389 key->u.count_from_stream_output)
390 wd_switch_on_eop = true;
391
392 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
393 * We don't know that for indirect drawing, so treat it as
394 * always problematic. */
395 if (sscreen->info.family == CHIP_HAWAII &&
396 key->u.uses_instancing)
397 wd_switch_on_eop = true;
398
399 /* Performance recommendation for 4 SE Gfx7-8 parts if
400 * instances are smaller than a primgroup.
401 * Assume indirect draws always use small instances.
402 * This is needed for good VS wave utilization.
403 */
404 if (sscreen->info.chip_class <= VI &&
405 sscreen->info.max_se == 4 &&
406 key->u.multi_instances_smaller_than_primgroup)
407 wd_switch_on_eop = true;
408
409 /* Required on CIK and later. */
410 if (sscreen->info.max_se > 2 && !wd_switch_on_eop)
411 ia_switch_on_eoi = true;
412
413 /* Required by Hawaii and, for some special cases, by VI. */
414 if (ia_switch_on_eoi &&
415 (sscreen->info.family == CHIP_HAWAII ||
416 (sscreen->info.chip_class == VI &&
417 (key->u.uses_gs || max_primgroup_in_wave != 2))))
418 partial_vs_wave = true;
419
420 /* Instancing bug on Bonaire. */
421 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
422 key->u.uses_instancing)
423 partial_vs_wave = true;
424
425 /* If the WD switch is false, the IA switch must be false too. */
426 assert(wd_switch_on_eop || !ia_switch_on_eop);
427 }
428
429 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
430 if (sscreen->info.chip_class <= VI && ia_switch_on_eoi)
431 partial_es_wave = true;
432
433 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
434 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
435 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
436 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
437 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= CIK ? wd_switch_on_eop : 0) |
438 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
439 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == VI ?
440 max_primgroup_in_wave : 0) |
441 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
442 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
443 }
444
445 void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
446 {
447 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
448 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
449 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
450 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
451 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
452 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
453 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
454 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
455 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
456 union si_vgt_param_key key;
457
458 key.index = 0;
459 key.u.prim = prim;
460 key.u.uses_instancing = uses_instancing;
461 key.u.multi_instances_smaller_than_primgroup = multi_instances;
462 key.u.primitive_restart = primitive_restart;
463 key.u.count_from_stream_output = count_from_so;
464 key.u.line_stipple_enabled = line_stipple;
465 key.u.uses_tess = uses_tess;
466 key.u.tess_uses_prim_id = tess_uses_primid;
467 key.u.uses_gs = uses_gs;
468
469 sctx->ia_multi_vgt_param[key.index] =
470 si_get_init_multi_vgt_param(sctx->screen, &key);
471 }
472 }
473
474 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
475 const struct pipe_draw_info *info,
476 unsigned num_patches)
477 {
478 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
479 unsigned primgroup_size;
480 unsigned ia_multi_vgt_param;
481
482 if (sctx->tes_shader.cso) {
483 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
484 } else if (sctx->gs_shader.cso) {
485 primgroup_size = 64; /* recommended with a GS */
486 } else {
487 primgroup_size = 128; /* recommended without a GS and tess */
488 }
489
490 key.u.prim = info->mode;
491 key.u.uses_instancing = info->indirect || info->instance_count > 1;
492 key.u.multi_instances_smaller_than_primgroup =
493 info->indirect ||
494 (info->instance_count > 1 &&
495 (info->count_from_stream_output ||
496 si_num_prims_for_vertices(info) < primgroup_size));
497 key.u.primitive_restart = info->primitive_restart;
498 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
499
500 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
501 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
502
503 if (sctx->gs_shader.cso) {
504 /* GS requirement. */
505 if (sctx->chip_class <= VI &&
506 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
507 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
508
509 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
510 * The hw doc says all multi-SE chips are affected, but Vulkan
511 * only applies it to Hawaii. Do what Vulkan does.
512 */
513 if (sctx->family == CHIP_HAWAII &&
514 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
515 (info->indirect ||
516 (info->instance_count > 1 &&
517 (info->count_from_stream_output ||
518 si_num_prims_for_vertices(info) <= 1))))
519 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
520 }
521
522 return ia_multi_vgt_param;
523 }
524
525 /* rast_prim is the primitive type after GS. */
526 static bool si_emit_rasterizer_prim_state(struct si_context *sctx)
527 {
528 struct radeon_winsys_cs *cs = sctx->gfx_cs;
529 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
530 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
531
532 /* Skip this if not rendering lines. */
533 if (!util_prim_is_lines(rast_prim))
534 return false;
535
536 if (rast_prim == sctx->last_rast_prim &&
537 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
538 return false;
539
540 /* For lines, reset the stipple pattern at each primitive. Otherwise,
541 * reset the stipple pattern at each packet (line strips, line loops).
542 */
543 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
544 rs->pa_sc_line_stipple |
545 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
546
547 sctx->last_rast_prim = rast_prim;
548 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
549 return true; /* true if the context rolls */
550 }
551
552 static void si_emit_vs_state(struct si_context *sctx,
553 const struct pipe_draw_info *info)
554 {
555 sctx->current_vs_state &= C_VS_STATE_INDEXED;
556 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
557
558 if (sctx->num_vs_blit_sgprs) {
559 /* Re-emit the state after we leave u_blitter. */
560 sctx->last_vs_state = ~0;
561 return;
562 }
563
564 if (sctx->current_vs_state != sctx->last_vs_state) {
565 struct radeon_winsys_cs *cs = sctx->gfx_cs;
566
567 radeon_set_sh_reg(cs,
568 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
569 SI_SGPR_VS_STATE_BITS * 4,
570 sctx->current_vs_state);
571
572 sctx->last_vs_state = sctx->current_vs_state;
573 }
574 }
575
576 static inline bool si_prim_restart_index_changed(struct si_context *sctx,
577 const struct pipe_draw_info *info)
578 {
579 return info->primitive_restart &&
580 (info->restart_index != sctx->last_restart_index ||
581 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
582 }
583
584 static void si_emit_draw_registers(struct si_context *sctx,
585 const struct pipe_draw_info *info,
586 unsigned num_patches)
587 {
588 struct radeon_winsys_cs *cs = sctx->gfx_cs;
589 unsigned prim = si_conv_pipe_prim(info->mode);
590 unsigned ia_multi_vgt_param;
591
592 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
593
594 /* Draw state. */
595 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
596 if (sctx->chip_class >= GFX9)
597 radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
598 else if (sctx->chip_class >= CIK)
599 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
600 else
601 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
602
603 sctx->last_multi_vgt_param = ia_multi_vgt_param;
604 }
605 if (prim != sctx->last_prim) {
606 if (sctx->chip_class >= CIK)
607 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
608 else
609 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
610
611 sctx->last_prim = prim;
612 }
613
614 /* Primitive restart. */
615 if (info->primitive_restart != sctx->last_primitive_restart_en) {
616 if (sctx->chip_class >= GFX9)
617 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
618 info->primitive_restart);
619 else
620 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
621 info->primitive_restart);
622
623 sctx->last_primitive_restart_en = info->primitive_restart;
624
625 }
626 if (si_prim_restart_index_changed(sctx, info)) {
627 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
628 info->restart_index);
629 sctx->last_restart_index = info->restart_index;
630 }
631 }
632
633 static void si_emit_draw_packets(struct si_context *sctx,
634 const struct pipe_draw_info *info,
635 struct pipe_resource *indexbuf,
636 unsigned index_size,
637 unsigned index_offset)
638 {
639 struct pipe_draw_indirect_info *indirect = info->indirect;
640 struct radeon_winsys_cs *cs = sctx->gfx_cs;
641 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
642 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
643 uint32_t index_max_size = 0;
644 uint64_t index_va = 0;
645
646 if (info->count_from_stream_output) {
647 struct si_streamout_target *t =
648 (struct si_streamout_target*)info->count_from_stream_output;
649 uint64_t va = t->buf_filled_size->gpu_address +
650 t->buf_filled_size_offset;
651
652 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
653 t->stride_in_dw);
654
655 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
656 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
657 COPY_DATA_DST_SEL(COPY_DATA_REG) |
658 COPY_DATA_WR_CONFIRM);
659 radeon_emit(cs, va); /* src address lo */
660 radeon_emit(cs, va >> 32); /* src address hi */
661 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
662 radeon_emit(cs, 0); /* unused */
663
664 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
665 t->buf_filled_size, RADEON_USAGE_READ,
666 RADEON_PRIO_SO_FILLED_SIZE);
667 }
668
669 /* draw packet */
670 if (index_size) {
671 if (index_size != sctx->last_index_size) {
672 unsigned index_type;
673
674 /* index type */
675 switch (index_size) {
676 case 1:
677 index_type = V_028A7C_VGT_INDEX_8;
678 break;
679 case 2:
680 index_type = V_028A7C_VGT_INDEX_16 |
681 (SI_BIG_ENDIAN && sctx->chip_class <= CIK ?
682 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
683 break;
684 case 4:
685 index_type = V_028A7C_VGT_INDEX_32 |
686 (SI_BIG_ENDIAN && sctx->chip_class <= CIK ?
687 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
688 break;
689 default:
690 assert(!"unreachable");
691 return;
692 }
693
694 if (sctx->chip_class >= GFX9) {
695 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
696 2, index_type);
697 } else {
698 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
699 radeon_emit(cs, index_type);
700 }
701
702 sctx->last_index_size = index_size;
703 }
704
705 index_max_size = (indexbuf->width0 - index_offset) /
706 index_size;
707 index_va = r600_resource(indexbuf)->gpu_address + index_offset;
708
709 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
710 r600_resource(indexbuf),
711 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
712 } else {
713 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
714 * so the state must be re-emitted before the next indexed draw.
715 */
716 if (sctx->chip_class >= CIK)
717 sctx->last_index_size = -1;
718 }
719
720 if (indirect) {
721 uint64_t indirect_va = r600_resource(indirect->buffer)->gpu_address;
722
723 assert(indirect_va % 8 == 0);
724
725 si_invalidate_draw_sh_constants(sctx);
726
727 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
728 radeon_emit(cs, 1);
729 radeon_emit(cs, indirect_va);
730 radeon_emit(cs, indirect_va >> 32);
731
732 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
733 r600_resource(indirect->buffer),
734 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
735
736 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
737 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
738
739 assert(indirect->offset % 4 == 0);
740
741 if (index_size) {
742 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
743 radeon_emit(cs, index_va);
744 radeon_emit(cs, index_va >> 32);
745
746 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
747 radeon_emit(cs, index_max_size);
748 }
749
750 if (!sctx->screen->has_draw_indirect_multi) {
751 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
752 : PKT3_DRAW_INDIRECT,
753 3, render_cond_bit));
754 radeon_emit(cs, indirect->offset);
755 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
756 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
757 radeon_emit(cs, di_src_sel);
758 } else {
759 uint64_t count_va = 0;
760
761 if (indirect->indirect_draw_count) {
762 struct r600_resource *params_buf =
763 r600_resource(indirect->indirect_draw_count);
764
765 radeon_add_to_buffer_list(
766 sctx, sctx->gfx_cs, params_buf,
767 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
768
769 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
770 }
771
772 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
773 PKT3_DRAW_INDIRECT_MULTI,
774 8, render_cond_bit));
775 radeon_emit(cs, indirect->offset);
776 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
777 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
778 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
779 S_2C3_DRAW_INDEX_ENABLE(1) |
780 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
781 radeon_emit(cs, indirect->draw_count);
782 radeon_emit(cs, count_va);
783 radeon_emit(cs, count_va >> 32);
784 radeon_emit(cs, indirect->stride);
785 radeon_emit(cs, di_src_sel);
786 }
787 } else {
788 int base_vertex;
789
790 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
791 radeon_emit(cs, info->instance_count);
792
793 /* Base vertex and start instance. */
794 base_vertex = index_size ? info->index_bias : info->start;
795
796 if (sctx->num_vs_blit_sgprs) {
797 /* Re-emit draw constants after we leave u_blitter. */
798 si_invalidate_draw_sh_constants(sctx);
799
800 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
801 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
802 sctx->num_vs_blit_sgprs);
803 radeon_emit_array(cs, sctx->vs_blit_sh_data,
804 sctx->num_vs_blit_sgprs);
805 } else if (base_vertex != sctx->last_base_vertex ||
806 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
807 info->start_instance != sctx->last_start_instance ||
808 info->drawid != sctx->last_drawid ||
809 sh_base_reg != sctx->last_sh_base_reg) {
810 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
811 radeon_emit(cs, base_vertex);
812 radeon_emit(cs, info->start_instance);
813 radeon_emit(cs, info->drawid);
814
815 sctx->last_base_vertex = base_vertex;
816 sctx->last_start_instance = info->start_instance;
817 sctx->last_drawid = info->drawid;
818 sctx->last_sh_base_reg = sh_base_reg;
819 }
820
821 if (index_size) {
822 index_va += info->start * index_size;
823
824 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
825 radeon_emit(cs, index_max_size);
826 radeon_emit(cs, index_va);
827 radeon_emit(cs, index_va >> 32);
828 radeon_emit(cs, info->count);
829 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
830 } else {
831 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
832 radeon_emit(cs, info->count);
833 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
834 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
835 }
836 }
837 }
838
839 static void si_emit_surface_sync(struct si_context *sctx,
840 unsigned cp_coher_cntl)
841 {
842 struct radeon_winsys_cs *cs = sctx->gfx_cs;
843
844 if (sctx->chip_class >= GFX9) {
845 /* Flush caches and wait for the caches to assert idle. */
846 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
847 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
848 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
849 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
850 radeon_emit(cs, 0); /* CP_COHER_BASE */
851 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
852 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
853 } else {
854 /* ACQUIRE_MEM is only required on a compute ring. */
855 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
856 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
857 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
858 radeon_emit(cs, 0); /* CP_COHER_BASE */
859 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
860 }
861 }
862
863 void si_emit_cache_flush(struct si_context *sctx)
864 {
865 struct radeon_winsys_cs *cs = sctx->gfx_cs;
866 uint32_t flags = sctx->flags;
867 uint32_t cp_coher_cntl = 0;
868 uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
869 SI_CONTEXT_FLUSH_AND_INV_DB);
870
871 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
872 sctx->num_cb_cache_flushes++;
873 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
874 sctx->num_db_cache_flushes++;
875
876 /* SI has a bug that it always flushes ICACHE and KCACHE if either
877 * bit is set. An alternative way is to write SQC_CACHES, but that
878 * doesn't seem to work reliably. Since the bug doesn't affect
879 * correctness (it only does more work than necessary) and
880 * the performance impact is likely negligible, there is no plan
881 * to add a workaround for it.
882 */
883
884 if (flags & SI_CONTEXT_INV_ICACHE)
885 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
886 if (flags & SI_CONTEXT_INV_SMEM_L1)
887 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
888
889 if (sctx->chip_class <= VI) {
890 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
891 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
892 S_0085F0_CB0_DEST_BASE_ENA(1) |
893 S_0085F0_CB1_DEST_BASE_ENA(1) |
894 S_0085F0_CB2_DEST_BASE_ENA(1) |
895 S_0085F0_CB3_DEST_BASE_ENA(1) |
896 S_0085F0_CB4_DEST_BASE_ENA(1) |
897 S_0085F0_CB5_DEST_BASE_ENA(1) |
898 S_0085F0_CB6_DEST_BASE_ENA(1) |
899 S_0085F0_CB7_DEST_BASE_ENA(1);
900
901 /* Necessary for DCC */
902 if (sctx->chip_class == VI)
903 si_gfx_write_event_eop(sctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
904 0, EOP_DATA_SEL_DISCARD, NULL,
905 0, 0, SI_NOT_QUERY);
906 }
907 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
908 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
909 S_0085F0_DB_DEST_BASE_ENA(1);
910 }
911
912 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
913 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
914 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
915 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
916 }
917 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
918 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
919 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
920 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
921 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
922 }
923
924 /* Wait for shader engines to go idle.
925 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
926 * for everything including CB/DB cache flushes.
927 */
928 if (!flush_cb_db) {
929 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
930 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
931 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
932 /* Only count explicit shader flushes, not implicit ones
933 * done by SURFACE_SYNC.
934 */
935 sctx->num_vs_flushes++;
936 sctx->num_ps_flushes++;
937 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
938 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
939 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
940 sctx->num_vs_flushes++;
941 }
942 }
943
944 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
945 sctx->compute_is_busy) {
946 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
947 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
948 sctx->num_cs_flushes++;
949 sctx->compute_is_busy = false;
950 }
951
952 /* VGT state synchronization. */
953 if (flags & SI_CONTEXT_VGT_FLUSH) {
954 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
955 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
956 }
957 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
958 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
959 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
960 }
961
962 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
963 * wait for idle on GFX9. We have to use a TS event.
964 */
965 if (sctx->chip_class >= GFX9 && flush_cb_db) {
966 uint64_t va;
967 unsigned tc_flags, cb_db_event;
968
969 /* Set the CB/DB flush event. */
970 switch (flush_cb_db) {
971 case SI_CONTEXT_FLUSH_AND_INV_CB:
972 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
973 break;
974 case SI_CONTEXT_FLUSH_AND_INV_DB:
975 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
976 break;
977 default:
978 /* both CB & DB */
979 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
980 }
981
982 /* These are the only allowed combinations. If you need to
983 * do multiple operations at once, do them separately.
984 * All operations that invalidate L2 also seem to invalidate
985 * metadata. Volatile (VOL) and WC flushes are not listed here.
986 *
987 * TC | TC_WB = writeback & invalidate L2 & L1
988 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
989 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
990 * TC | TC_NC = invalidate L2 for MTYPE == NC
991 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
992 * TCL1 = invalidate L1
993 */
994 tc_flags = 0;
995
996 if (flags & SI_CONTEXT_INV_L2_METADATA) {
997 tc_flags = EVENT_TC_ACTION_ENA |
998 EVENT_TC_MD_ACTION_ENA;
999 }
1000
1001 /* Ideally flush TC together with CB/DB. */
1002 if (flags & SI_CONTEXT_INV_GLOBAL_L2) {
1003 /* Writeback and invalidate everything in L2 & L1. */
1004 tc_flags = EVENT_TC_ACTION_ENA |
1005 EVENT_TC_WB_ACTION_ENA;
1006
1007 /* Clear the flags. */
1008 flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
1009 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
1010 SI_CONTEXT_INV_VMEM_L1);
1011 sctx->num_L2_invalidates++;
1012 }
1013
1014 /* Do the flush (enqueue the event and wait for it). */
1015 va = sctx->wait_mem_scratch->gpu_address;
1016 sctx->wait_mem_number++;
1017
1018 si_gfx_write_event_eop(sctx, cb_db_event, tc_flags,
1019 EOP_DATA_SEL_VALUE_32BIT,
1020 sctx->wait_mem_scratch, va,
1021 sctx->wait_mem_number, SI_NOT_QUERY);
1022 si_gfx_wait_fence(sctx, va, sctx->wait_mem_number, 0xffffffff);
1023 }
1024
1025 /* Make sure ME is idle (it executes most packets) before continuing.
1026 * This prevents read-after-write hazards between PFP and ME.
1027 */
1028 if (cp_coher_cntl ||
1029 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1030 SI_CONTEXT_INV_VMEM_L1 |
1031 SI_CONTEXT_INV_GLOBAL_L2 |
1032 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1033 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1034 radeon_emit(cs, 0);
1035 }
1036
1037 /* SI-CI-VI only:
1038 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1039 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1040 *
1041 * cp_coher_cntl should contain all necessary flags except TC flags
1042 * at this point.
1043 *
1044 * SI-CIK don't support L2 write-back.
1045 */
1046 if (flags & SI_CONTEXT_INV_GLOBAL_L2 ||
1047 (sctx->chip_class <= CIK &&
1048 (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1049 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
1050 * WB must be set on VI+ when TC_ACTION is set.
1051 */
1052 si_emit_surface_sync(sctx, cp_coher_cntl |
1053 S_0085F0_TC_ACTION_ENA(1) |
1054 S_0085F0_TCL1_ACTION_ENA(1) |
1055 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= VI));
1056 cp_coher_cntl = 0;
1057 sctx->num_L2_invalidates++;
1058 } else {
1059 /* L1 invalidation and L2 writeback must be done separately,
1060 * because both operations can't be done together.
1061 */
1062 if (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
1063 /* WB = write-back
1064 * NC = apply to non-coherent MTYPEs
1065 * (i.e. MTYPE <= 1, which is what we use everywhere)
1066 *
1067 * WB doesn't work without NC.
1068 */
1069 si_emit_surface_sync(sctx, cp_coher_cntl |
1070 S_0301F0_TC_WB_ACTION_ENA(1) |
1071 S_0301F0_TC_NC_ACTION_ENA(1));
1072 cp_coher_cntl = 0;
1073 sctx->num_L2_writebacks++;
1074 }
1075 if (flags & SI_CONTEXT_INV_VMEM_L1) {
1076 /* Invalidate per-CU VMEM L1. */
1077 si_emit_surface_sync(sctx, cp_coher_cntl |
1078 S_0085F0_TCL1_ACTION_ENA(1));
1079 cp_coher_cntl = 0;
1080 }
1081 }
1082
1083 /* If TC flushes haven't cleared this... */
1084 if (cp_coher_cntl)
1085 si_emit_surface_sync(sctx, cp_coher_cntl);
1086
1087 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1088 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1089 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1090 EVENT_INDEX(0));
1091 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1092 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1093 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1094 EVENT_INDEX(0));
1095 }
1096
1097 sctx->flags = 0;
1098 }
1099
1100 static void si_get_draw_start_count(struct si_context *sctx,
1101 const struct pipe_draw_info *info,
1102 unsigned *start, unsigned *count)
1103 {
1104 struct pipe_draw_indirect_info *indirect = info->indirect;
1105
1106 if (indirect) {
1107 unsigned indirect_count;
1108 struct pipe_transfer *transfer;
1109 unsigned begin, end;
1110 unsigned map_size;
1111 unsigned *data;
1112
1113 if (indirect->indirect_draw_count) {
1114 data = pipe_buffer_map_range(&sctx->b,
1115 indirect->indirect_draw_count,
1116 indirect->indirect_draw_count_offset,
1117 sizeof(unsigned),
1118 PIPE_TRANSFER_READ, &transfer);
1119
1120 indirect_count = *data;
1121
1122 pipe_buffer_unmap(&sctx->b, transfer);
1123 } else {
1124 indirect_count = indirect->draw_count;
1125 }
1126
1127 if (!indirect_count) {
1128 *start = *count = 0;
1129 return;
1130 }
1131
1132 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1133 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1134 indirect->offset, map_size,
1135 PIPE_TRANSFER_READ, &transfer);
1136
1137 begin = UINT_MAX;
1138 end = 0;
1139
1140 for (unsigned i = 0; i < indirect_count; ++i) {
1141 unsigned count = data[0];
1142 unsigned start = data[2];
1143
1144 if (count > 0) {
1145 begin = MIN2(begin, start);
1146 end = MAX2(end, start + count);
1147 }
1148
1149 data += indirect->stride / sizeof(unsigned);
1150 }
1151
1152 pipe_buffer_unmap(&sctx->b, transfer);
1153
1154 if (begin < end) {
1155 *start = begin;
1156 *count = end - begin;
1157 } else {
1158 *start = *count = 0;
1159 }
1160 } else {
1161 *start = info->start;
1162 *count = info->count;
1163 }
1164 }
1165
1166 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1167 unsigned skip_atom_mask)
1168 {
1169 unsigned num_patches = 0;
1170 bool context_roll = false; /* set correctly for GFX9 only */
1171
1172 context_roll |= si_emit_rasterizer_prim_state(sctx);
1173 if (sctx->tes_shader.cso)
1174 context_roll |= si_emit_derived_tess_state(sctx, info, &num_patches);
1175 if (info->count_from_stream_output)
1176 context_roll = true;
1177
1178 /* Vega10/Raven scissor bug workaround. When any context register is
1179 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
1180 * registers must be written too.
1181 */
1182 if ((sctx->family == CHIP_VEGA10 || sctx->family == CHIP_RAVEN) &&
1183 (context_roll ||
1184 sctx->dirty_atoms & si_atoms_that_roll_context() ||
1185 sctx->dirty_states & si_states_that_roll_context() ||
1186 si_prim_restart_index_changed(sctx, info))) {
1187 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1188 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1189 }
1190
1191 /* Emit state atoms. */
1192 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1193 while (mask)
1194 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1195
1196 sctx->dirty_atoms &= skip_atom_mask;
1197
1198 /* Emit states. */
1199 mask = sctx->dirty_states;
1200 while (mask) {
1201 unsigned i = u_bit_scan(&mask);
1202 struct si_pm4_state *state = sctx->queued.array[i];
1203
1204 if (!state || sctx->emitted.array[i] == state)
1205 continue;
1206
1207 si_pm4_emit(sctx, state);
1208 sctx->emitted.array[i] = state;
1209 }
1210 sctx->dirty_states = 0;
1211
1212 /* Emit draw states. */
1213 si_emit_vs_state(sctx, info);
1214 si_emit_draw_registers(sctx, info, num_patches);
1215 }
1216
1217 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1218 {
1219 struct si_context *sctx = (struct si_context *)ctx;
1220 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1221 struct pipe_resource *indexbuf = info->index.resource;
1222 unsigned dirty_tex_counter;
1223 enum pipe_prim_type rast_prim;
1224 unsigned index_size = info->index_size;
1225 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1226
1227 if (likely(!info->indirect)) {
1228 /* SI-CI treat instance_count==0 as instance_count==1. There is
1229 * no workaround for indirect draws, but we can at least skip
1230 * direct draws.
1231 */
1232 if (unlikely(!info->instance_count))
1233 return;
1234
1235 /* Handle count == 0. */
1236 if (unlikely(!info->count &&
1237 (index_size || !info->count_from_stream_output)))
1238 return;
1239 }
1240
1241 if (unlikely(!sctx->vs_shader.cso ||
1242 !rs ||
1243 (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
1244 (!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES)))) {
1245 assert(0);
1246 return;
1247 }
1248
1249 /* Recompute and re-emit the texture resource states if needed. */
1250 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1251 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1252 sctx->last_dirty_tex_counter = dirty_tex_counter;
1253 sctx->framebuffer.dirty_cbufs |=
1254 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1255 sctx->framebuffer.dirty_zsbuf = true;
1256 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1257 si_update_all_texture_descriptors(sctx);
1258 }
1259
1260 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1261
1262 /* Set the rasterization primitive type.
1263 *
1264 * This must be done after si_decompress_textures, which can call
1265 * draw_vbo recursively, and before si_update_shaders, which uses
1266 * current_rast_prim for this draw_vbo call. */
1267 if (sctx->gs_shader.cso)
1268 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1269 else if (sctx->tes_shader.cso) {
1270 if (sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1271 rast_prim = PIPE_PRIM_POINTS;
1272 else
1273 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1274 } else
1275 rast_prim = info->mode;
1276
1277 if (rast_prim != sctx->current_rast_prim) {
1278 if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
1279 util_prim_is_points_or_lines(rast_prim))
1280 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1281
1282 sctx->current_rast_prim = rast_prim;
1283 sctx->do_update_shaders = true;
1284 }
1285
1286 if (sctx->tes_shader.cso &&
1287 sctx->screen->has_ls_vgpr_init_bug) {
1288 /* Determine whether the LS VGPR fix should be applied.
1289 *
1290 * It is only required when num input CPs > num output CPs,
1291 * which cannot happen with the fixed function TCS. We should
1292 * also update this bit when switching from TCS to fixed
1293 * function TCS.
1294 */
1295 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1296 bool ls_vgpr_fix =
1297 tcs &&
1298 info->vertices_per_patch >
1299 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1300
1301 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1302 sctx->ls_vgpr_fix = ls_vgpr_fix;
1303 sctx->do_update_shaders = true;
1304 }
1305 }
1306
1307 if (sctx->gs_shader.cso) {
1308 /* Determine whether the GS triangle strip adjacency fix should
1309 * be applied. Rotate every other triangle if
1310 * - triangle strips with adjacency are fed to the GS and
1311 * - primitive restart is disabled (the rotation doesn't help
1312 * when the restart occurs after an odd number of triangles).
1313 */
1314 bool gs_tri_strip_adj_fix =
1315 !sctx->tes_shader.cso &&
1316 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1317 !info->primitive_restart;
1318
1319 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1320 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1321 sctx->do_update_shaders = true;
1322 }
1323 }
1324
1325 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1326 return;
1327
1328 if (index_size) {
1329 /* Translate or upload, if needed. */
1330 /* 8-bit indices are supported on VI. */
1331 if (sctx->chip_class <= CIK && index_size == 1) {
1332 unsigned start, count, start_offset, size, offset;
1333 void *ptr;
1334
1335 si_get_draw_start_count(sctx, info, &start, &count);
1336 start_offset = start * 2;
1337 size = count * 2;
1338
1339 indexbuf = NULL;
1340 u_upload_alloc(ctx->stream_uploader, start_offset,
1341 size,
1342 si_optimal_tcc_alignment(sctx, size),
1343 &offset, &indexbuf, &ptr);
1344 if (!indexbuf)
1345 return;
1346
1347 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1348 index_offset + start,
1349 count, ptr);
1350
1351 /* info->start will be added by the drawing code */
1352 index_offset = offset - start_offset;
1353 index_size = 2;
1354 } else if (info->has_user_indices) {
1355 unsigned start_offset;
1356
1357 assert(!info->indirect);
1358 start_offset = info->start * index_size;
1359
1360 indexbuf = NULL;
1361 u_upload_data(ctx->stream_uploader, start_offset,
1362 info->count * index_size,
1363 sctx->screen->info.tcc_cache_line_size,
1364 (char*)info->index.user + start_offset,
1365 &index_offset, &indexbuf);
1366 if (!indexbuf)
1367 return;
1368
1369 /* info->start will be added by the drawing code */
1370 index_offset -= start_offset;
1371 } else if (sctx->chip_class <= CIK &&
1372 r600_resource(indexbuf)->TC_L2_dirty) {
1373 /* VI reads index buffers through TC L2, so it doesn't
1374 * need this. */
1375 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1376 r600_resource(indexbuf)->TC_L2_dirty = false;
1377 }
1378 }
1379
1380 if (info->indirect) {
1381 struct pipe_draw_indirect_info *indirect = info->indirect;
1382
1383 /* Add the buffer size for memory checking in need_cs_space. */
1384 si_context_add_resource_size(sctx, indirect->buffer);
1385
1386 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1387 if (sctx->chip_class <= VI) {
1388 if (r600_resource(indirect->buffer)->TC_L2_dirty) {
1389 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1390 r600_resource(indirect->buffer)->TC_L2_dirty = false;
1391 }
1392
1393 if (indirect->indirect_draw_count &&
1394 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1395 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1396 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1397 }
1398 }
1399 }
1400
1401 si_need_gfx_cs_space(sctx);
1402
1403 /* Since we've called si_context_add_resource_size for vertex buffers,
1404 * this must be called after si_need_cs_space, because we must let
1405 * need_cs_space flush before we add buffers to the buffer list.
1406 */
1407 if (!si_upload_vertex_buffer_descriptors(sctx))
1408 return;
1409
1410 /* Use optimal packet order based on whether we need to sync the pipeline. */
1411 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1412 SI_CONTEXT_FLUSH_AND_INV_DB |
1413 SI_CONTEXT_PS_PARTIAL_FLUSH |
1414 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1415 /* If we have to wait for idle, set all states first, so that all
1416 * SET packets are processed in parallel with previous draw calls.
1417 * Then draw and prefetch at the end. This ensures that the time
1418 * the CUs are idle is very short.
1419 */
1420 unsigned masked_atoms = 0;
1421
1422 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
1423 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
1424
1425 if (!si_upload_graphics_shader_descriptors(sctx))
1426 return;
1427
1428 /* Emit all states except possibly render condition. */
1429 si_emit_all_states(sctx, info, masked_atoms);
1430 si_emit_cache_flush(sctx);
1431 /* <-- CUs are idle here. */
1432
1433 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
1434 sctx->atoms.s.render_cond.emit(sctx);
1435 sctx->dirty_atoms = 0;
1436
1437 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1438 /* <-- CUs are busy here. */
1439
1440 /* Start prefetches after the draw has been started. Both will run
1441 * in parallel, but starting the draw first is more important.
1442 */
1443 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1444 cik_emit_prefetch_L2(sctx, false);
1445 } else {
1446 /* If we don't wait for idle, start prefetches first, then set
1447 * states, and draw at the end.
1448 */
1449 if (sctx->flags)
1450 si_emit_cache_flush(sctx);
1451
1452 /* Only prefetch the API VS and VBO descriptors. */
1453 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1454 cik_emit_prefetch_L2(sctx, true);
1455
1456 if (!si_upload_graphics_shader_descriptors(sctx))
1457 return;
1458
1459 si_emit_all_states(sctx, info, 0);
1460 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1461
1462 /* Prefetch the remaining shaders after the draw has been
1463 * started. */
1464 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1465 cik_emit_prefetch_L2(sctx, false);
1466 }
1467
1468 if (unlikely(sctx->current_saved_cs)) {
1469 si_trace_emit(sctx);
1470 si_log_draw_state(sctx, sctx->log);
1471 }
1472
1473 /* Workaround for a VGT hang when streamout is enabled.
1474 * It must be done after drawing. */
1475 if ((sctx->family == CHIP_HAWAII ||
1476 sctx->family == CHIP_TONGA ||
1477 sctx->family == CHIP_FIJI) &&
1478 si_get_strmout_en(sctx)) {
1479 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1480 }
1481
1482 if (unlikely(sctx->decompression_enabled)) {
1483 sctx->num_decompress_calls++;
1484 } else {
1485 sctx->num_draw_calls++;
1486 if (sctx->framebuffer.state.nr_cbufs > 1)
1487 sctx->num_mrt_draw_calls++;
1488 if (info->primitive_restart)
1489 sctx->num_prim_restart_calls++;
1490 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1491 sctx->num_spill_draw_calls++;
1492 }
1493 if (index_size && indexbuf != info->index.resource)
1494 pipe_resource_reference(&indexbuf, NULL);
1495 }
1496
1497 void si_draw_rectangle(struct blitter_context *blitter,
1498 void *vertex_elements_cso,
1499 blitter_get_vs_func get_vs,
1500 int x1, int y1, int x2, int y2,
1501 float depth, unsigned num_instances,
1502 enum blitter_attrib_type type,
1503 const union blitter_attrib *attrib)
1504 {
1505 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
1506 struct si_context *sctx = (struct si_context*)pipe;
1507
1508 /* Pack position coordinates as signed int16. */
1509 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
1510 ((uint32_t)(y1 & 0xffff) << 16);
1511 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
1512 ((uint32_t)(y2 & 0xffff) << 16);
1513 sctx->vs_blit_sh_data[2] = fui(depth);
1514
1515 switch (type) {
1516 case UTIL_BLITTER_ATTRIB_COLOR:
1517 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
1518 sizeof(float)*4);
1519 break;
1520 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
1521 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
1522 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
1523 sizeof(attrib->texcoord));
1524 break;
1525 case UTIL_BLITTER_ATTRIB_NONE:;
1526 }
1527
1528 pipe->bind_vs_state(pipe, si_get_blit_vs(sctx, type, num_instances));
1529
1530 struct pipe_draw_info info = {};
1531 info.mode = SI_PRIM_RECTANGLE_LIST;
1532 info.count = 3;
1533 info.instance_count = num_instances;
1534
1535 /* Don't set per-stage shader pointers for VS. */
1536 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
1537 sctx->vertex_buffer_pointer_dirty = false;
1538
1539 si_draw_vbo(pipe, &info);
1540 }
1541
1542 void si_trace_emit(struct si_context *sctx)
1543 {
1544 struct radeon_winsys_cs *cs = sctx->gfx_cs;
1545 uint64_t va = sctx->current_saved_cs->trace_buf->gpu_address;
1546 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
1547
1548 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1549 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1550 S_370_WR_CONFIRM(1) |
1551 S_370_ENGINE_SEL(V_370_ME));
1552 radeon_emit(cs, va);
1553 radeon_emit(cs, va >> 32);
1554 radeon_emit(cs, trace_id);
1555 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1556 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
1557
1558 if (sctx->log)
1559 u_log_flush(sctx->log);
1560 }