2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
28 #include "radeon/r600_cs.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
38 static unsigned si_conv_pipe_prim(unsigned mode
)
40 static const unsigned prim_conv
[] = {
41 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
42 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
43 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
44 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
45 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
46 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
47 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
48 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
49 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
50 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
51 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
55 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
56 [R600_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
58 assert(mode
< ARRAY_SIZE(prim_conv
));
59 return prim_conv
[mode
];
62 static unsigned si_conv_prim_to_gs_out(unsigned mode
)
64 static const int prim_conv
[] = {
65 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
66 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
67 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
68 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
69 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
70 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
71 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
72 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
73 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
74 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
75 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
76 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
77 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
78 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
79 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
80 [R600_PRIM_RECTANGLE_LIST
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
82 assert(mode
< ARRAY_SIZE(prim_conv
));
84 return prim_conv
[mode
];
88 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
89 * LS.LDS_SIZE is shared by all 3 shader stages.
91 * The information about LDS and other non-compile-time parameters is then
92 * written to userdata SGPRs.
94 static void si_emit_derived_tess_state(struct si_context
*sctx
,
95 const struct pipe_draw_info
*info
,
96 unsigned *num_patches
)
98 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
99 struct si_shader
*ls_current
;
100 struct si_shader_selector
*ls
;
101 /* The TES pointer will only be used for sctx->last_tcs.
102 * It would be wrong to think that TCS = TES. */
103 struct si_shader_selector
*tcs
=
104 sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.cso
: sctx
->tes_shader
.cso
;
105 unsigned tess_uses_primid
= sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
;
106 bool has_primid_instancing_bug
= sctx
->b
.chip_class
== SI
&&
107 sctx
->b
.screen
->info
.max_se
== 1;
108 unsigned tes_sh_base
= sctx
->shader_pointers
.sh_base
[PIPE_SHADER_TESS_EVAL
];
109 unsigned num_tcs_input_cp
= info
->vertices_per_patch
;
110 unsigned num_tcs_output_cp
, num_tcs_inputs
, num_tcs_outputs
;
111 unsigned num_tcs_patch_outputs
;
112 unsigned input_vertex_size
, output_vertex_size
, pervertex_output_patch_size
;
113 unsigned input_patch_size
, output_patch_size
, output_patch0_offset
;
114 unsigned perpatch_output_offset
, lds_size
;
115 unsigned tcs_in_layout
, tcs_out_layout
, tcs_out_offsets
;
116 unsigned offchip_layout
, hardware_lds_size
, ls_hs_config
;
118 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
119 if (sctx
->b
.chip_class
>= GFX9
) {
120 if (sctx
->tcs_shader
.cso
)
121 ls_current
= sctx
->tcs_shader
.current
;
123 ls_current
= sctx
->fixed_func_tcs_shader
.current
;
125 ls
= ls_current
->key
.part
.tcs
.ls
;
127 ls_current
= sctx
->vs_shader
.current
;
128 ls
= sctx
->vs_shader
.cso
;
131 if (sctx
->last_ls
== ls_current
&&
132 sctx
->last_tcs
== tcs
&&
133 sctx
->last_tes_sh_base
== tes_sh_base
&&
134 sctx
->last_num_tcs_input_cp
== num_tcs_input_cp
&&
135 (!has_primid_instancing_bug
||
136 (sctx
->last_tess_uses_primid
== tess_uses_primid
))) {
137 *num_patches
= sctx
->last_num_patches
;
141 sctx
->last_ls
= ls_current
;
142 sctx
->last_tcs
= tcs
;
143 sctx
->last_tes_sh_base
= tes_sh_base
;
144 sctx
->last_num_tcs_input_cp
= num_tcs_input_cp
;
145 sctx
->last_tess_uses_primid
= tess_uses_primid
;
147 /* This calculates how shader inputs and outputs among VS, TCS, and TES
148 * are laid out in LDS. */
149 num_tcs_inputs
= util_last_bit64(ls
->outputs_written
);
151 if (sctx
->tcs_shader
.cso
) {
152 num_tcs_outputs
= util_last_bit64(tcs
->outputs_written
);
153 num_tcs_output_cp
= tcs
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
154 num_tcs_patch_outputs
= util_last_bit64(tcs
->patch_outputs_written
);
156 /* No TCS. Route varyings from LS to TES. */
157 num_tcs_outputs
= num_tcs_inputs
;
158 num_tcs_output_cp
= num_tcs_input_cp
;
159 num_tcs_patch_outputs
= 2; /* TESSINNER + TESSOUTER */
162 input_vertex_size
= num_tcs_inputs
* 16;
163 output_vertex_size
= num_tcs_outputs
* 16;
165 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
167 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
168 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
170 /* Ensure that we only need one wave per SIMD so we don't need to check
171 * resource usage. Also ensures that the number of tcs in and out
172 * vertices per threadgroup are at most 256.
174 *num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
176 /* Make sure that the data fits in LDS. This assumes the shaders only
177 * use LDS for the inputs and outputs.
179 * While CIK can use 64K per threadgroup, there is a hang on Stoney
180 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
181 * uses 32K at most on all GCN chips.
183 hardware_lds_size
= 32768;
184 *num_patches
= MIN2(*num_patches
, hardware_lds_size
/ (input_patch_size
+
187 /* Make sure the output data fits in the offchip buffer */
188 *num_patches
= MIN2(*num_patches
,
189 (sctx
->screen
->tess_offchip_block_dw_size
* 4) /
192 /* Not necessary for correctness, but improves performance. The
193 * specific value is taken from the proprietary driver.
195 *num_patches
= MIN2(*num_patches
, 40);
197 if (sctx
->b
.chip_class
== SI
) {
198 /* SI bug workaround, related to power management. Limit LS-HS
199 * threadgroups to only one wave.
201 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
202 *num_patches
= MIN2(*num_patches
, one_wave
);
205 /* The VGT HS block increments the patch ID unconditionally
206 * within a single threadgroup. This results in incorrect
207 * patch IDs when instanced draws are used.
209 * The intended solution is to restrict threadgroups to
210 * a single instance by setting SWITCH_ON_EOI, which
211 * should cause IA to split instances up. However, this
212 * doesn't work correctly on SI when there is no other
215 if (has_primid_instancing_bug
)
218 sctx
->last_num_patches
= *num_patches
;
220 output_patch0_offset
= input_patch_size
* *num_patches
;
221 perpatch_output_offset
= output_patch0_offset
+ pervertex_output_patch_size
;
223 /* Compute userdata SGPRs. */
224 assert(((input_vertex_size
/ 4) & ~0xff) == 0);
225 assert(((output_vertex_size
/ 4) & ~0xff) == 0);
226 assert(((input_patch_size
/ 4) & ~0x1fff) == 0);
227 assert(((output_patch_size
/ 4) & ~0x1fff) == 0);
228 assert(((output_patch0_offset
/ 16) & ~0xffff) == 0);
229 assert(((perpatch_output_offset
/ 16) & ~0xffff) == 0);
230 assert(num_tcs_input_cp
<= 32);
231 assert(num_tcs_output_cp
<= 32);
233 tcs_in_layout
= S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size
/ 4) |
234 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size
/ 4);
235 tcs_out_layout
= (output_patch_size
/ 4) |
236 ((output_vertex_size
/ 4) << 13);
237 tcs_out_offsets
= (output_patch0_offset
/ 16) |
238 ((perpatch_output_offset
/ 16) << 16);
239 offchip_layout
= *num_patches
|
240 (num_tcs_output_cp
<< 6) |
241 (pervertex_output_patch_size
* *num_patches
<< 12);
243 /* Compute the LDS size. */
244 lds_size
= output_patch0_offset
+ output_patch_size
* *num_patches
;
246 if (sctx
->b
.chip_class
>= CIK
) {
247 assert(lds_size
<= 65536);
248 lds_size
= align(lds_size
, 512) / 512;
250 assert(lds_size
<= 32768);
251 lds_size
= align(lds_size
, 256) / 256;
254 /* Set SI_SGPR_VS_STATE_BITS. */
255 sctx
->current_vs_state
&= C_VS_STATE_LS_OUT_PATCH_SIZE
&
256 C_VS_STATE_LS_OUT_VERTEX_SIZE
;
257 sctx
->current_vs_state
|= tcs_in_layout
;
259 if (sctx
->b
.chip_class
>= GFX9
) {
260 unsigned hs_rsrc2
= ls_current
->config
.rsrc2
|
261 S_00B42C_LDS_SIZE(lds_size
);
263 radeon_set_sh_reg(cs
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
, hs_rsrc2
);
265 /* Set userdata SGPRs for merged LS-HS. */
266 radeon_set_sh_reg_seq(cs
,
267 R_00B430_SPI_SHADER_USER_DATA_LS_0
+
268 GFX9_SGPR_TCS_OFFCHIP_LAYOUT
* 4, 3);
269 radeon_emit(cs
, offchip_layout
);
270 radeon_emit(cs
, tcs_out_offsets
);
271 radeon_emit(cs
, tcs_out_layout
| (num_tcs_input_cp
<< 26));
273 unsigned ls_rsrc2
= ls_current
->config
.rsrc2
;
275 si_multiwave_lds_size_workaround(sctx
->screen
, &lds_size
);
276 ls_rsrc2
|= S_00B52C_LDS_SIZE(lds_size
);
278 /* Due to a hw bug, RSRC2_LS must be written twice with another
279 * LS register written in between. */
280 if (sctx
->b
.chip_class
== CIK
&& sctx
->b
.family
!= CHIP_HAWAII
)
281 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, ls_rsrc2
);
282 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
283 radeon_emit(cs
, ls_current
->config
.rsrc1
);
284 radeon_emit(cs
, ls_rsrc2
);
286 /* Set userdata SGPRs for TCS. */
287 radeon_set_sh_reg_seq(cs
,
288 R_00B430_SPI_SHADER_USER_DATA_HS_0
+ GFX6_SGPR_TCS_OFFCHIP_LAYOUT
* 4, 4);
289 radeon_emit(cs
, offchip_layout
);
290 radeon_emit(cs
, tcs_out_offsets
);
291 radeon_emit(cs
, tcs_out_layout
| (num_tcs_input_cp
<< 26));
292 radeon_emit(cs
, tcs_in_layout
);
295 /* Set userdata SGPRs for TES. */
296 radeon_set_sh_reg_seq(cs
, tes_sh_base
+ SI_SGPR_TES_OFFCHIP_LAYOUT
* 4, 2);
297 radeon_emit(cs
, offchip_layout
);
298 radeon_emit(cs
, r600_resource(sctx
->tess_offchip_ring
)->gpu_address
>> 16);
300 ls_hs_config
= S_028B58_NUM_PATCHES(*num_patches
) |
301 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
302 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
304 if (sctx
->b
.chip_class
>= CIK
)
305 radeon_set_context_reg_idx(cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
308 radeon_set_context_reg(cs
, R_028B58_VGT_LS_HS_CONFIG
,
312 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info
*info
)
314 switch (info
->mode
) {
315 case PIPE_PRIM_PATCHES
:
316 return info
->count
/ info
->vertices_per_patch
;
317 case R600_PRIM_RECTANGLE_LIST
:
318 return info
->count
/ 3;
320 return u_prims_for_vertices(info
->mode
, info
->count
);
325 si_get_init_multi_vgt_param(struct si_screen
*sscreen
,
326 union si_vgt_param_key
*key
)
328 STATIC_ASSERT(sizeof(union si_vgt_param_key
) == 4);
329 unsigned max_primgroup_in_wave
= 2;
331 /* SWITCH_ON_EOP(0) is always preferable. */
332 bool wd_switch_on_eop
= false;
333 bool ia_switch_on_eop
= false;
334 bool ia_switch_on_eoi
= false;
335 bool partial_vs_wave
= false;
336 bool partial_es_wave
= false;
338 if (key
->u
.uses_tess
) {
339 /* SWITCH_ON_EOI must be set if PrimID is used. */
340 if (key
->u
.tess_uses_prim_id
)
341 ia_switch_on_eoi
= true;
343 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
344 if ((sscreen
->b
.family
== CHIP_TAHITI
||
345 sscreen
->b
.family
== CHIP_PITCAIRN
||
346 sscreen
->b
.family
== CHIP_BONAIRE
) &&
348 partial_vs_wave
= true;
350 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
351 if (sscreen
->has_distributed_tess
) {
352 if (key
->u
.uses_gs
) {
353 if (sscreen
->b
.chip_class
<= VI
)
354 partial_es_wave
= true;
356 /* GPU hang workaround. */
357 if (sscreen
->b
.family
== CHIP_TONGA
||
358 sscreen
->b
.family
== CHIP_FIJI
||
359 sscreen
->b
.family
== CHIP_POLARIS10
||
360 sscreen
->b
.family
== CHIP_POLARIS11
||
361 sscreen
->b
.family
== CHIP_POLARIS12
)
362 partial_vs_wave
= true;
364 partial_vs_wave
= true;
369 /* This is a hardware requirement. */
370 if (key
->u
.line_stipple_enabled
||
371 (sscreen
->b
.debug_flags
& DBG_SWITCH_ON_EOP
)) {
372 ia_switch_on_eop
= true;
373 wd_switch_on_eop
= true;
376 if (sscreen
->b
.chip_class
>= CIK
) {
377 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
378 * 4 shader engines. Set 1 to pass the assertion below.
379 * The other cases are hardware requirements.
381 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
382 * for points, line strips, and tri strips.
384 if (sscreen
->b
.info
.max_se
< 4 ||
385 key
->u
.prim
== PIPE_PRIM_POLYGON
||
386 key
->u
.prim
== PIPE_PRIM_LINE_LOOP
||
387 key
->u
.prim
== PIPE_PRIM_TRIANGLE_FAN
||
388 key
->u
.prim
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
||
389 (key
->u
.primitive_restart
&&
390 (sscreen
->b
.family
< CHIP_POLARIS10
||
391 (key
->u
.prim
!= PIPE_PRIM_POINTS
&&
392 key
->u
.prim
!= PIPE_PRIM_LINE_STRIP
&&
393 key
->u
.prim
!= PIPE_PRIM_TRIANGLE_STRIP
))) ||
394 key
->u
.count_from_stream_output
)
395 wd_switch_on_eop
= true;
397 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
398 * We don't know that for indirect drawing, so treat it as
399 * always problematic. */
400 if (sscreen
->b
.family
== CHIP_HAWAII
&&
401 key
->u
.uses_instancing
)
402 wd_switch_on_eop
= true;
404 /* Performance recommendation for 4 SE Gfx7-8 parts if
405 * instances are smaller than a primgroup.
406 * Assume indirect draws always use small instances.
407 * This is needed for good VS wave utilization.
409 if (sscreen
->b
.chip_class
<= VI
&&
410 sscreen
->b
.info
.max_se
== 4 &&
411 key
->u
.multi_instances_smaller_than_primgroup
)
412 wd_switch_on_eop
= true;
414 /* Required on CIK and later. */
415 if (sscreen
->b
.info
.max_se
> 2 && !wd_switch_on_eop
)
416 ia_switch_on_eoi
= true;
418 /* Required by Hawaii and, for some special cases, by VI. */
419 if (ia_switch_on_eoi
&&
420 (sscreen
->b
.family
== CHIP_HAWAII
||
421 (sscreen
->b
.chip_class
== VI
&&
422 (key
->u
.uses_gs
|| max_primgroup_in_wave
!= 2))))
423 partial_vs_wave
= true;
425 /* Instancing bug on Bonaire. */
426 if (sscreen
->b
.family
== CHIP_BONAIRE
&& ia_switch_on_eoi
&&
427 key
->u
.uses_instancing
)
428 partial_vs_wave
= true;
430 /* If the WD switch is false, the IA switch must be false too. */
431 assert(wd_switch_on_eop
|| !ia_switch_on_eop
);
434 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
435 if (sscreen
->b
.chip_class
<= VI
&& ia_switch_on_eoi
)
436 partial_es_wave
= true;
438 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
439 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi
) |
440 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
441 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave
) |
442 S_028AA8_WD_SWITCH_ON_EOP(sscreen
->b
.chip_class
>= CIK
? wd_switch_on_eop
: 0) |
443 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
444 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen
->b
.chip_class
== VI
?
445 max_primgroup_in_wave
: 0) |
446 S_030960_EN_INST_OPT_BASIC(sscreen
->b
.chip_class
>= GFX9
) |
447 S_030960_EN_INST_OPT_ADV(sscreen
->b
.chip_class
>= GFX9
);
450 void si_init_ia_multi_vgt_param_table(struct si_context
*sctx
)
452 for (int prim
= 0; prim
<= R600_PRIM_RECTANGLE_LIST
; prim
++)
453 for (int uses_instancing
= 0; uses_instancing
< 2; uses_instancing
++)
454 for (int multi_instances
= 0; multi_instances
< 2; multi_instances
++)
455 for (int primitive_restart
= 0; primitive_restart
< 2; primitive_restart
++)
456 for (int count_from_so
= 0; count_from_so
< 2; count_from_so
++)
457 for (int line_stipple
= 0; line_stipple
< 2; line_stipple
++)
458 for (int uses_tess
= 0; uses_tess
< 2; uses_tess
++)
459 for (int tess_uses_primid
= 0; tess_uses_primid
< 2; tess_uses_primid
++)
460 for (int uses_gs
= 0; uses_gs
< 2; uses_gs
++) {
461 union si_vgt_param_key key
;
465 key
.u
.uses_instancing
= uses_instancing
;
466 key
.u
.multi_instances_smaller_than_primgroup
= multi_instances
;
467 key
.u
.primitive_restart
= primitive_restart
;
468 key
.u
.count_from_stream_output
= count_from_so
;
469 key
.u
.line_stipple_enabled
= line_stipple
;
470 key
.u
.uses_tess
= uses_tess
;
471 key
.u
.tess_uses_prim_id
= tess_uses_primid
;
472 key
.u
.uses_gs
= uses_gs
;
474 sctx
->ia_multi_vgt_param
[key
.index
] =
475 si_get_init_multi_vgt_param(sctx
->screen
, &key
);
479 static unsigned si_get_ia_multi_vgt_param(struct si_context
*sctx
,
480 const struct pipe_draw_info
*info
,
481 unsigned num_patches
)
483 union si_vgt_param_key key
= sctx
->ia_multi_vgt_param_key
;
484 unsigned primgroup_size
;
485 unsigned ia_multi_vgt_param
;
487 if (sctx
->tes_shader
.cso
) {
488 primgroup_size
= num_patches
; /* must be a multiple of NUM_PATCHES */
489 } else if (sctx
->gs_shader
.cso
) {
490 primgroup_size
= 64; /* recommended with a GS */
492 primgroup_size
= 128; /* recommended without a GS and tess */
495 key
.u
.prim
= info
->mode
;
496 key
.u
.uses_instancing
= info
->indirect
|| info
->instance_count
> 1;
497 key
.u
.multi_instances_smaller_than_primgroup
=
499 (info
->instance_count
> 1 &&
500 (info
->count_from_stream_output
||
501 si_num_prims_for_vertices(info
) < primgroup_size
));
502 key
.u
.primitive_restart
= info
->primitive_restart
;
503 key
.u
.count_from_stream_output
= info
->count_from_stream_output
!= NULL
;
505 ia_multi_vgt_param
= sctx
->ia_multi_vgt_param
[key
.index
] |
506 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1);
508 if (sctx
->gs_shader
.cso
) {
509 /* GS requirement. */
510 if (sctx
->b
.chip_class
<= VI
&&
511 SI_GS_PER_ES
/ primgroup_size
>= sctx
->screen
->gs_table_depth
- 3)
512 ia_multi_vgt_param
|= S_028AA8_PARTIAL_ES_WAVE_ON(1);
514 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
515 * The hw doc says all multi-SE chips are affected, but Vulkan
516 * only applies it to Hawaii. Do what Vulkan does.
518 if (sctx
->b
.family
== CHIP_HAWAII
&&
519 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param
) &&
521 (info
->instance_count
> 1 &&
522 (info
->count_from_stream_output
||
523 si_num_prims_for_vertices(info
) <= 1))))
524 sctx
->b
.flags
|= SI_CONTEXT_VGT_FLUSH
;
527 return ia_multi_vgt_param
;
530 /* rast_prim is the primitive type after GS. */
531 static void si_emit_rasterizer_prim_state(struct si_context
*sctx
)
533 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
534 enum pipe_prim_type rast_prim
= sctx
->current_rast_prim
;
535 struct si_state_rasterizer
*rs
= sctx
->emitted
.named
.rasterizer
;
537 /* Skip this if not rendering lines. */
538 if (rast_prim
!= PIPE_PRIM_LINES
&&
539 rast_prim
!= PIPE_PRIM_LINE_LOOP
&&
540 rast_prim
!= PIPE_PRIM_LINE_STRIP
&&
541 rast_prim
!= PIPE_PRIM_LINES_ADJACENCY
&&
542 rast_prim
!= PIPE_PRIM_LINE_STRIP_ADJACENCY
)
545 if (rast_prim
== sctx
->last_rast_prim
&&
546 rs
->pa_sc_line_stipple
== sctx
->last_sc_line_stipple
)
549 /* For lines, reset the stipple pattern at each primitive. Otherwise,
550 * reset the stipple pattern at each packet (line strips, line loops).
552 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
553 rs
->pa_sc_line_stipple
|
554 S_028A0C_AUTO_RESET_CNTL(rast_prim
== PIPE_PRIM_LINES
? 1 : 2));
556 sctx
->last_rast_prim
= rast_prim
;
557 sctx
->last_sc_line_stipple
= rs
->pa_sc_line_stipple
;
560 static void si_emit_vs_state(struct si_context
*sctx
,
561 const struct pipe_draw_info
*info
)
563 sctx
->current_vs_state
&= C_VS_STATE_INDEXED
;
564 sctx
->current_vs_state
|= S_VS_STATE_INDEXED(!!info
->index_size
);
566 if (sctx
->current_vs_state
!= sctx
->last_vs_state
) {
567 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
569 radeon_set_sh_reg(cs
,
570 sctx
->shader_pointers
.sh_base
[PIPE_SHADER_VERTEX
] +
571 SI_SGPR_VS_STATE_BITS
* 4,
572 sctx
->current_vs_state
);
574 sctx
->last_vs_state
= sctx
->current_vs_state
;
578 static void si_emit_draw_registers(struct si_context
*sctx
,
579 const struct pipe_draw_info
*info
,
580 unsigned num_patches
)
582 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
583 unsigned prim
= si_conv_pipe_prim(info
->mode
);
584 unsigned gs_out_prim
= si_conv_prim_to_gs_out(sctx
->current_rast_prim
);
585 unsigned ia_multi_vgt_param
;
587 ia_multi_vgt_param
= si_get_ia_multi_vgt_param(sctx
, info
, num_patches
);
590 if (ia_multi_vgt_param
!= sctx
->last_multi_vgt_param
) {
591 if (sctx
->b
.chip_class
>= GFX9
)
592 radeon_set_uconfig_reg_idx(cs
, R_030960_IA_MULTI_VGT_PARAM
, 4, ia_multi_vgt_param
);
593 else if (sctx
->b
.chip_class
>= CIK
)
594 radeon_set_context_reg_idx(cs
, R_028AA8_IA_MULTI_VGT_PARAM
, 1, ia_multi_vgt_param
);
596 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
, ia_multi_vgt_param
);
598 sctx
->last_multi_vgt_param
= ia_multi_vgt_param
;
600 if (prim
!= sctx
->last_prim
) {
601 if (sctx
->b
.chip_class
>= CIK
)
602 radeon_set_uconfig_reg_idx(cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
604 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
606 sctx
->last_prim
= prim
;
609 if (gs_out_prim
!= sctx
->last_gs_out_prim
) {
610 radeon_set_context_reg(cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out_prim
);
611 sctx
->last_gs_out_prim
= gs_out_prim
;
614 /* Primitive restart. */
615 if (info
->primitive_restart
!= sctx
->last_primitive_restart_en
) {
616 if (sctx
->b
.chip_class
>= GFX9
)
617 radeon_set_uconfig_reg(cs
, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
618 info
->primitive_restart
);
620 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
621 info
->primitive_restart
);
623 sctx
->last_primitive_restart_en
= info
->primitive_restart
;
626 if (info
->primitive_restart
&&
627 (info
->restart_index
!= sctx
->last_restart_index
||
628 sctx
->last_restart_index
== SI_RESTART_INDEX_UNKNOWN
)) {
629 radeon_set_context_reg(cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
630 info
->restart_index
);
631 sctx
->last_restart_index
= info
->restart_index
;
635 static void si_emit_draw_packets(struct si_context
*sctx
,
636 const struct pipe_draw_info
*info
,
637 struct pipe_resource
*indexbuf
,
639 unsigned index_offset
)
641 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
642 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
643 unsigned sh_base_reg
= sctx
->shader_pointers
.sh_base
[PIPE_SHADER_VERTEX
];
644 bool render_cond_bit
= sctx
->b
.render_cond
&& !sctx
->b
.render_cond_force_off
;
645 uint32_t index_max_size
= 0;
646 uint64_t index_va
= 0;
648 if (info
->count_from_stream_output
) {
649 struct r600_so_target
*t
=
650 (struct r600_so_target
*)info
->count_from_stream_output
;
651 uint64_t va
= t
->buf_filled_size
->gpu_address
+
652 t
->buf_filled_size_offset
;
654 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
657 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
658 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
659 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
660 COPY_DATA_WR_CONFIRM
);
661 radeon_emit(cs
, va
); /* src address lo */
662 radeon_emit(cs
, va
>> 32); /* src address hi */
663 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
664 radeon_emit(cs
, 0); /* unused */
666 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
667 t
->buf_filled_size
, RADEON_USAGE_READ
,
668 RADEON_PRIO_SO_FILLED_SIZE
);
673 if (index_size
!= sctx
->last_index_size
) {
677 switch (index_size
) {
679 index_type
= V_028A7C_VGT_INDEX_8
;
682 index_type
= V_028A7C_VGT_INDEX_16
|
683 (SI_BIG_ENDIAN
&& sctx
->b
.chip_class
<= CIK
?
684 V_028A7C_VGT_DMA_SWAP_16_BIT
: 0);
687 index_type
= V_028A7C_VGT_INDEX_32
|
688 (SI_BIG_ENDIAN
&& sctx
->b
.chip_class
<= CIK
?
689 V_028A7C_VGT_DMA_SWAP_32_BIT
: 0);
692 assert(!"unreachable");
696 if (sctx
->b
.chip_class
>= GFX9
) {
697 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
700 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
701 radeon_emit(cs
, index_type
);
704 sctx
->last_index_size
= index_size
;
707 index_max_size
= (indexbuf
->width0
- index_offset
) /
709 index_va
= r600_resource(indexbuf
)->gpu_address
+ index_offset
;
711 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
712 (struct r600_resource
*)indexbuf
,
713 RADEON_USAGE_READ
, RADEON_PRIO_INDEX_BUFFER
);
715 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
716 * so the state must be re-emitted before the next indexed draw.
718 if (sctx
->b
.chip_class
>= CIK
)
719 sctx
->last_index_size
= -1;
723 uint64_t indirect_va
= r600_resource(indirect
->buffer
)->gpu_address
;
725 assert(indirect_va
% 8 == 0);
727 si_invalidate_draw_sh_constants(sctx
);
729 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
731 radeon_emit(cs
, indirect_va
);
732 radeon_emit(cs
, indirect_va
>> 32);
734 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
735 (struct r600_resource
*)indirect
->buffer
,
736 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
738 unsigned di_src_sel
= index_size
? V_0287F0_DI_SRC_SEL_DMA
739 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
741 assert(indirect
->offset
% 4 == 0);
744 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
745 radeon_emit(cs
, index_va
);
746 radeon_emit(cs
, index_va
>> 32);
748 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
749 radeon_emit(cs
, index_max_size
);
752 if (!sctx
->screen
->has_draw_indirect_multi
) {
753 radeon_emit(cs
, PKT3(index_size
? PKT3_DRAW_INDEX_INDIRECT
754 : PKT3_DRAW_INDIRECT
,
755 3, render_cond_bit
));
756 radeon_emit(cs
, indirect
->offset
);
757 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
758 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
759 radeon_emit(cs
, di_src_sel
);
761 uint64_t count_va
= 0;
763 if (indirect
->indirect_draw_count
) {
764 struct r600_resource
*params_buf
=
765 (struct r600_resource
*)indirect
->indirect_draw_count
;
767 radeon_add_to_buffer_list(
768 &sctx
->b
, &sctx
->b
.gfx
, params_buf
,
769 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
771 count_va
= params_buf
->gpu_address
+ indirect
->indirect_draw_count_offset
;
774 radeon_emit(cs
, PKT3(index_size
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
775 PKT3_DRAW_INDIRECT_MULTI
,
776 8, render_cond_bit
));
777 radeon_emit(cs
, indirect
->offset
);
778 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
779 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
780 radeon_emit(cs
, ((sh_base_reg
+ SI_SGPR_DRAWID
* 4 - SI_SH_REG_OFFSET
) >> 2) |
781 S_2C3_DRAW_INDEX_ENABLE(1) |
782 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect
->indirect_draw_count
));
783 radeon_emit(cs
, indirect
->draw_count
);
784 radeon_emit(cs
, count_va
);
785 radeon_emit(cs
, count_va
>> 32);
786 radeon_emit(cs
, indirect
->stride
);
787 radeon_emit(cs
, di_src_sel
);
792 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
793 radeon_emit(cs
, info
->instance_count
);
795 /* Base vertex and start instance. */
796 base_vertex
= index_size
? info
->index_bias
: info
->start
;
798 if (base_vertex
!= sctx
->last_base_vertex
||
799 sctx
->last_base_vertex
== SI_BASE_VERTEX_UNKNOWN
||
800 info
->start_instance
!= sctx
->last_start_instance
||
801 info
->drawid
!= sctx
->last_drawid
||
802 sh_base_reg
!= sctx
->last_sh_base_reg
) {
803 radeon_set_sh_reg_seq(cs
, sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4, 3);
804 radeon_emit(cs
, base_vertex
);
805 radeon_emit(cs
, info
->start_instance
);
806 radeon_emit(cs
, info
->drawid
);
808 sctx
->last_base_vertex
= base_vertex
;
809 sctx
->last_start_instance
= info
->start_instance
;
810 sctx
->last_drawid
= info
->drawid
;
811 sctx
->last_sh_base_reg
= sh_base_reg
;
815 index_va
+= info
->start
* index_size
;
817 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, render_cond_bit
));
818 radeon_emit(cs
, index_max_size
);
819 radeon_emit(cs
, index_va
);
820 radeon_emit(cs
, index_va
>> 32);
821 radeon_emit(cs
, info
->count
);
822 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
824 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
825 radeon_emit(cs
, info
->count
);
826 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
827 S_0287F0_USE_OPAQUE(!!info
->count_from_stream_output
));
832 static void si_emit_surface_sync(struct r600_common_context
*rctx
,
833 unsigned cp_coher_cntl
)
835 struct radeon_winsys_cs
*cs
= rctx
->gfx
.cs
;
837 if (rctx
->chip_class
>= GFX9
) {
838 /* Flush caches and wait for the caches to assert idle. */
839 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 5, 0));
840 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
841 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
842 radeon_emit(cs
, 0xffffff); /* CP_COHER_SIZE_HI */
843 radeon_emit(cs
, 0); /* CP_COHER_BASE */
844 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
845 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
847 /* ACQUIRE_MEM is only required on a compute ring. */
848 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, 0));
849 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
850 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
851 radeon_emit(cs
, 0); /* CP_COHER_BASE */
852 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
856 void si_emit_cache_flush(struct si_context
*sctx
)
858 struct r600_common_context
*rctx
= &sctx
->b
;
859 struct radeon_winsys_cs
*cs
= rctx
->gfx
.cs
;
860 uint32_t cp_coher_cntl
= 0;
861 uint32_t flush_cb_db
= rctx
->flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
|
862 SI_CONTEXT_FLUSH_AND_INV_DB
);
864 if (rctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_CB
)
865 sctx
->b
.num_cb_cache_flushes
++;
866 if (rctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_DB
)
867 sctx
->b
.num_db_cache_flushes
++;
869 /* SI has a bug that it always flushes ICACHE and KCACHE if either
870 * bit is set. An alternative way is to write SQC_CACHES, but that
871 * doesn't seem to work reliably. Since the bug doesn't affect
872 * correctness (it only does more work than necessary) and
873 * the performance impact is likely negligible, there is no plan
874 * to add a workaround for it.
877 if (rctx
->flags
& SI_CONTEXT_INV_ICACHE
)
878 cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1);
879 if (rctx
->flags
& SI_CONTEXT_INV_SMEM_L1
)
880 cp_coher_cntl
|= S_0085F0_SH_KCACHE_ACTION_ENA(1);
882 if (rctx
->chip_class
<= VI
) {
883 if (rctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
884 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
885 S_0085F0_CB0_DEST_BASE_ENA(1) |
886 S_0085F0_CB1_DEST_BASE_ENA(1) |
887 S_0085F0_CB2_DEST_BASE_ENA(1) |
888 S_0085F0_CB3_DEST_BASE_ENA(1) |
889 S_0085F0_CB4_DEST_BASE_ENA(1) |
890 S_0085F0_CB5_DEST_BASE_ENA(1) |
891 S_0085F0_CB6_DEST_BASE_ENA(1) |
892 S_0085F0_CB7_DEST_BASE_ENA(1);
894 /* Necessary for DCC */
895 if (rctx
->chip_class
== VI
)
896 r600_gfx_write_event_eop(rctx
, V_028A90_FLUSH_AND_INV_CB_DATA_TS
,
897 0, 0, NULL
, 0, 0, 0);
899 if (rctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_DB
)
900 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
901 S_0085F0_DB_DEST_BASE_ENA(1);
904 if (rctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
905 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
906 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
907 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
909 if (rctx
->flags
& SI_CONTEXT_FLUSH_AND_INV_DB
) {
910 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
911 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
912 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
915 /* Wait for shader engines to go idle.
916 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
917 * for everything including CB/DB cache flushes.
920 if (rctx
->flags
& SI_CONTEXT_PS_PARTIAL_FLUSH
) {
921 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
922 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
923 /* Only count explicit shader flushes, not implicit ones
924 * done by SURFACE_SYNC.
926 rctx
->num_vs_flushes
++;
927 rctx
->num_ps_flushes
++;
928 } else if (rctx
->flags
& SI_CONTEXT_VS_PARTIAL_FLUSH
) {
929 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
930 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
931 rctx
->num_vs_flushes
++;
935 if (rctx
->flags
& SI_CONTEXT_CS_PARTIAL_FLUSH
&&
936 sctx
->compute_is_busy
) {
937 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
938 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
| EVENT_INDEX(4)));
939 rctx
->num_cs_flushes
++;
940 sctx
->compute_is_busy
= false;
943 /* VGT state synchronization. */
944 if (rctx
->flags
& SI_CONTEXT_VGT_FLUSH
) {
945 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
946 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
948 if (rctx
->flags
& SI_CONTEXT_VGT_STREAMOUT_SYNC
) {
949 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
950 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC
) | EVENT_INDEX(0));
953 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
954 * wait for idle on GFX9. We have to use a TS event.
956 if (sctx
->b
.chip_class
>= GFX9
&& flush_cb_db
) {
958 unsigned tc_flags
, cb_db_event
;
960 /* Set the CB/DB flush event. */
961 switch (flush_cb_db
) {
962 case SI_CONTEXT_FLUSH_AND_INV_CB
:
963 cb_db_event
= V_028A90_FLUSH_AND_INV_CB_DATA_TS
;
965 case SI_CONTEXT_FLUSH_AND_INV_DB
:
966 cb_db_event
= V_028A90_FLUSH_AND_INV_DB_DATA_TS
;
970 cb_db_event
= V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
;
973 /* TC | TC_WB = invalidate L2 data
974 * TC_MD | TC_WB = invalidate L2 metadata (DCC, etc.)
975 * TC | TC_WB | TC_MD = invalidate L2 data & metadata
979 /* Ideally flush TC together with CB/DB. */
980 if (rctx
->flags
& SI_CONTEXT_INV_GLOBAL_L2
) {
981 tc_flags
|= EVENT_TC_ACTION_ENA
|
982 EVENT_TC_WB_ACTION_ENA
|
983 EVENT_TCL1_ACTION_ENA
;
985 /* Clear the flags. */
986 rctx
->flags
&= ~(SI_CONTEXT_INV_GLOBAL_L2
|
987 SI_CONTEXT_WRITEBACK_GLOBAL_L2
|
988 SI_CONTEXT_INV_VMEM_L1
);
989 sctx
->b
.num_L2_invalidates
++;
992 /* Do the flush (enqueue the event and wait for it). */
993 va
= sctx
->wait_mem_scratch
->gpu_address
;
994 sctx
->wait_mem_number
++;
996 r600_gfx_write_event_eop(rctx
, cb_db_event
, tc_flags
, 1,
997 sctx
->wait_mem_scratch
, va
,
998 sctx
->wait_mem_number
- 1,
999 sctx
->wait_mem_number
);
1000 r600_gfx_wait_fence(rctx
, va
, sctx
->wait_mem_number
, 0xffffffff);
1003 /* Make sure ME is idle (it executes most packets) before continuing.
1004 * This prevents read-after-write hazards between PFP and ME.
1006 if (cp_coher_cntl
||
1007 (rctx
->flags
& (SI_CONTEXT_CS_PARTIAL_FLUSH
|
1008 SI_CONTEXT_INV_VMEM_L1
|
1009 SI_CONTEXT_INV_GLOBAL_L2
|
1010 SI_CONTEXT_WRITEBACK_GLOBAL_L2
))) {
1011 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1016 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1017 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1019 * cp_coher_cntl should contain all necessary flags except TC flags
1022 * SI-CIK don't support L2 write-back.
1024 if (rctx
->flags
& SI_CONTEXT_INV_GLOBAL_L2
||
1025 (rctx
->chip_class
<= CIK
&&
1026 (rctx
->flags
& SI_CONTEXT_WRITEBACK_GLOBAL_L2
))) {
1027 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
1028 * WB must be set on VI+ when TC_ACTION is set.
1030 si_emit_surface_sync(rctx
, cp_coher_cntl
|
1031 S_0085F0_TC_ACTION_ENA(1) |
1032 S_0085F0_TCL1_ACTION_ENA(1) |
1033 S_0301F0_TC_WB_ACTION_ENA(rctx
->chip_class
>= VI
));
1035 sctx
->b
.num_L2_invalidates
++;
1037 /* L1 invalidation and L2 writeback must be done separately,
1038 * because both operations can't be done together.
1040 if (rctx
->flags
& SI_CONTEXT_WRITEBACK_GLOBAL_L2
) {
1042 * NC = apply to non-coherent MTYPEs
1043 * (i.e. MTYPE <= 1, which is what we use everywhere)
1045 * WB doesn't work without NC.
1047 si_emit_surface_sync(rctx
, cp_coher_cntl
|
1048 S_0301F0_TC_WB_ACTION_ENA(1) |
1049 S_0301F0_TC_NC_ACTION_ENA(1));
1051 sctx
->b
.num_L2_writebacks
++;
1053 if (rctx
->flags
& SI_CONTEXT_INV_VMEM_L1
) {
1054 /* Invalidate per-CU VMEM L1. */
1055 si_emit_surface_sync(rctx
, cp_coher_cntl
|
1056 S_0085F0_TCL1_ACTION_ENA(1));
1061 /* If TC flushes haven't cleared this... */
1063 si_emit_surface_sync(rctx
, cp_coher_cntl
);
1065 if (rctx
->flags
& R600_CONTEXT_START_PIPELINE_STATS
) {
1066 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1067 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
1069 } else if (rctx
->flags
& R600_CONTEXT_STOP_PIPELINE_STATS
) {
1070 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1071 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP
) |
1078 static void si_get_draw_start_count(struct si_context
*sctx
,
1079 const struct pipe_draw_info
*info
,
1080 unsigned *start
, unsigned *count
)
1082 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
1085 unsigned indirect_count
;
1086 struct pipe_transfer
*transfer
;
1087 unsigned begin
, end
;
1091 if (indirect
->indirect_draw_count
) {
1092 data
= pipe_buffer_map_range(&sctx
->b
.b
,
1093 indirect
->indirect_draw_count
,
1094 indirect
->indirect_draw_count_offset
,
1096 PIPE_TRANSFER_READ
, &transfer
);
1098 indirect_count
= *data
;
1100 pipe_buffer_unmap(&sctx
->b
.b
, transfer
);
1102 indirect_count
= indirect
->draw_count
;
1105 if (!indirect_count
) {
1106 *start
= *count
= 0;
1110 map_size
= (indirect_count
- 1) * indirect
->stride
+ 3 * sizeof(unsigned);
1111 data
= pipe_buffer_map_range(&sctx
->b
.b
, indirect
->buffer
,
1112 indirect
->offset
, map_size
,
1113 PIPE_TRANSFER_READ
, &transfer
);
1118 for (unsigned i
= 0; i
< indirect_count
; ++i
) {
1119 unsigned count
= data
[0];
1120 unsigned start
= data
[2];
1123 begin
= MIN2(begin
, start
);
1124 end
= MAX2(end
, start
+ count
);
1127 data
+= indirect
->stride
/ sizeof(unsigned);
1130 pipe_buffer_unmap(&sctx
->b
.b
, transfer
);
1134 *count
= end
- begin
;
1136 *start
= *count
= 0;
1139 *start
= info
->start
;
1140 *count
= info
->count
;
1144 void si_ce_pre_draw_synchronization(struct si_context
*sctx
)
1146 if (sctx
->ce_need_synchronization
) {
1147 radeon_emit(sctx
->ce_ib
, PKT3(PKT3_INCREMENT_CE_COUNTER
, 0, 0));
1148 radeon_emit(sctx
->ce_ib
, 1); /* 1 = increment CE counter */
1150 radeon_emit(sctx
->b
.gfx
.cs
, PKT3(PKT3_WAIT_ON_CE_COUNTER
, 0, 0));
1151 radeon_emit(sctx
->b
.gfx
.cs
, 0); /* 0 = don't flush sL1 conditionally */
1155 void si_ce_post_draw_synchronization(struct si_context
*sctx
)
1157 if (sctx
->ce_need_synchronization
) {
1158 radeon_emit(sctx
->b
.gfx
.cs
, PKT3(PKT3_INCREMENT_DE_COUNTER
, 0, 0));
1159 radeon_emit(sctx
->b
.gfx
.cs
, 0); /* unused */
1161 sctx
->ce_need_synchronization
= false;
1165 static void si_emit_all_states(struct si_context
*sctx
, const struct pipe_draw_info
*info
,
1166 unsigned skip_atom_mask
)
1168 /* Emit state atoms. */
1169 unsigned mask
= sctx
->dirty_atoms
& ~skip_atom_mask
;
1171 struct r600_atom
*atom
= sctx
->atoms
.array
[u_bit_scan(&mask
)];
1173 atom
->emit(&sctx
->b
, atom
);
1175 sctx
->dirty_atoms
&= skip_atom_mask
;
1178 mask
= sctx
->dirty_states
;
1180 unsigned i
= u_bit_scan(&mask
);
1181 struct si_pm4_state
*state
= sctx
->queued
.array
[i
];
1183 if (!state
|| sctx
->emitted
.array
[i
] == state
)
1186 si_pm4_emit(sctx
, state
);
1187 sctx
->emitted
.array
[i
] = state
;
1189 sctx
->dirty_states
= 0;
1191 /* Emit draw states. */
1192 unsigned num_patches
= 0;
1194 si_emit_rasterizer_prim_state(sctx
);
1195 if (sctx
->tes_shader
.cso
)
1196 si_emit_derived_tess_state(sctx
, info
, &num_patches
);
1197 si_emit_vs_state(sctx
, info
);
1198 si_emit_draw_registers(sctx
, info
, num_patches
);
1201 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
1203 struct si_context
*sctx
= (struct si_context
*)ctx
;
1204 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1205 struct pipe_resource
*indexbuf
= info
->index
.resource
;
1206 unsigned dirty_tex_counter
;
1207 enum pipe_prim_type rast_prim
;
1208 unsigned index_size
= info
->index_size
;
1209 unsigned index_offset
= info
->indirect
? info
->start
* index_size
: 0;
1211 if (likely(!info
->indirect
)) {
1212 /* SI-CI treat instance_count==0 as instance_count==1. There is
1213 * no workaround for indirect draws, but we can at least skip
1216 if (unlikely(!info
->instance_count
))
1219 /* Handle count == 0. */
1220 if (unlikely(!info
->count
&&
1221 (index_size
|| !info
->count_from_stream_output
)))
1225 if (unlikely(!sctx
->vs_shader
.cso
)) {
1229 if (unlikely(!sctx
->ps_shader
.cso
&& (!rs
|| !rs
->rasterizer_discard
))) {
1233 if (unlikely(!!sctx
->tes_shader
.cso
!= (info
->mode
== PIPE_PRIM_PATCHES
))) {
1238 /* Recompute and re-emit the texture resource states if needed. */
1239 dirty_tex_counter
= p_atomic_read(&sctx
->b
.screen
->dirty_tex_counter
);
1240 if (unlikely(dirty_tex_counter
!= sctx
->b
.last_dirty_tex_counter
)) {
1241 sctx
->b
.last_dirty_tex_counter
= dirty_tex_counter
;
1242 sctx
->framebuffer
.dirty_cbufs
|=
1243 ((1 << sctx
->framebuffer
.state
.nr_cbufs
) - 1);
1244 sctx
->framebuffer
.dirty_zsbuf
= true;
1245 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
);
1246 si_update_all_texture_descriptors(sctx
);
1249 si_decompress_graphics_textures(sctx
);
1251 /* Set the rasterization primitive type.
1253 * This must be done after si_decompress_textures, which can call
1254 * draw_vbo recursively, and before si_update_shaders, which uses
1255 * current_rast_prim for this draw_vbo call. */
1256 if (sctx
->gs_shader
.cso
)
1257 rast_prim
= sctx
->gs_shader
.cso
->gs_output_prim
;
1258 else if (sctx
->tes_shader
.cso
)
1259 rast_prim
= sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1261 rast_prim
= info
->mode
;
1263 if (rast_prim
!= sctx
->current_rast_prim
) {
1264 sctx
->current_rast_prim
= rast_prim
;
1265 sctx
->do_update_shaders
= true;
1268 if (sctx
->gs_shader
.cso
) {
1269 /* Determine whether the GS triangle strip adjacency fix should
1270 * be applied. Rotate every other triangle if
1271 * - triangle strips with adjacency are fed to the GS and
1272 * - primitive restart is disabled (the rotation doesn't help
1273 * when the restart occurs after an odd number of triangles).
1275 bool gs_tri_strip_adj_fix
=
1276 !sctx
->tes_shader
.cso
&&
1277 info
->mode
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
&&
1278 !info
->primitive_restart
;
1280 if (gs_tri_strip_adj_fix
!= sctx
->gs_tri_strip_adj_fix
) {
1281 sctx
->gs_tri_strip_adj_fix
= gs_tri_strip_adj_fix
;
1282 sctx
->do_update_shaders
= true;
1286 if (sctx
->do_update_shaders
&& !si_update_shaders(sctx
))
1290 /* Translate or upload, if needed. */
1291 /* 8-bit indices are supported on VI. */
1292 if (sctx
->b
.chip_class
<= CIK
&& index_size
== 1) {
1293 unsigned start
, count
, start_offset
, size
, offset
;
1296 si_get_draw_start_count(sctx
, info
, &start
, &count
);
1297 start_offset
= start
* 2;
1301 u_upload_alloc(ctx
->stream_uploader
, start_offset
,
1303 si_optimal_tcc_alignment(sctx
, size
),
1304 &offset
, &indexbuf
, &ptr
);
1308 util_shorten_ubyte_elts_to_userptr(&sctx
->b
.b
, info
, 0, 0,
1309 index_offset
+ start
,
1312 /* info->start will be added by the drawing code */
1313 index_offset
= offset
- start_offset
;
1315 } else if (info
->has_user_indices
) {
1316 unsigned start_offset
;
1318 assert(!info
->indirect
);
1319 start_offset
= info
->start
* index_size
;
1322 u_upload_data(ctx
->stream_uploader
, start_offset
,
1323 info
->count
* index_size
,
1324 sctx
->screen
->b
.info
.tcc_cache_line_size
,
1325 (char*)info
->index
.user
+ start_offset
,
1326 &index_offset
, &indexbuf
);
1330 /* info->start will be added by the drawing code */
1331 index_offset
-= start_offset
;
1332 } else if (sctx
->b
.chip_class
<= CIK
&&
1333 r600_resource(indexbuf
)->TC_L2_dirty
) {
1334 /* VI reads index buffers through TC L2, so it doesn't
1336 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1337 r600_resource(indexbuf
)->TC_L2_dirty
= false;
1341 if (info
->indirect
) {
1342 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
1344 /* Add the buffer size for memory checking in need_cs_space. */
1345 r600_context_add_resource_size(ctx
, indirect
->buffer
);
1347 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1348 if (sctx
->b
.chip_class
<= VI
) {
1349 if (r600_resource(indirect
->buffer
)->TC_L2_dirty
) {
1350 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1351 r600_resource(indirect
->buffer
)->TC_L2_dirty
= false;
1354 if (indirect
->indirect_draw_count
&&
1355 r600_resource(indirect
->indirect_draw_count
)->TC_L2_dirty
) {
1356 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1357 r600_resource(indirect
->indirect_draw_count
)->TC_L2_dirty
= false;
1362 si_need_cs_space(sctx
);
1364 /* Since we've called r600_context_add_resource_size for vertex buffers,
1365 * this must be called after si_need_cs_space, because we must let
1366 * need_cs_space flush before we add buffers to the buffer list.
1368 if (!si_upload_vertex_buffer_descriptors(sctx
))
1371 /* GFX9 scissor bug workaround. There is also a more efficient but
1372 * more involved alternative workaround. */
1373 if (sctx
->b
.chip_class
== GFX9
&&
1374 si_is_atom_dirty(sctx
, &sctx
->b
.scissors
.atom
))
1375 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
;
1377 /* Use optimal packet order based on whether we need to sync the pipeline. */
1378 if (unlikely(sctx
->b
.flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
|
1379 SI_CONTEXT_FLUSH_AND_INV_DB
|
1380 SI_CONTEXT_PS_PARTIAL_FLUSH
|
1381 SI_CONTEXT_CS_PARTIAL_FLUSH
))) {
1382 /* If we have to wait for idle, set all states first, so that all
1383 * SET packets are processed in parallel with previous draw calls.
1384 * Then upload descriptors, set shader pointers, and draw, and
1385 * prefetch at the end. This ensures that the time the CUs
1386 * are idle is very short. (there are only SET_SH packets between
1387 * the wait and the draw)
1389 struct r600_atom
*shader_pointers
= &sctx
->shader_pointers
.atom
;
1391 /* Emit all states except shader pointers. */
1392 si_emit_all_states(sctx
, info
, 1 << shader_pointers
->id
);
1393 si_emit_cache_flush(sctx
);
1395 /* <-- CUs are idle here. */
1396 if (!si_upload_graphics_shader_descriptors(sctx
))
1399 /* Set shader pointers after descriptors are uploaded. */
1400 if (si_is_atom_dirty(sctx
, shader_pointers
)) {
1401 shader_pointers
->emit(&sctx
->b
, NULL
);
1402 sctx
->dirty_atoms
= 0;
1405 si_ce_pre_draw_synchronization(sctx
);
1406 si_emit_draw_packets(sctx
, info
, indexbuf
, index_size
, index_offset
);
1407 /* <-- CUs are busy here. */
1409 /* Start prefetches after the draw has been started. Both will run
1410 * in parallel, but starting the draw first is more important.
1412 if (sctx
->b
.chip_class
>= CIK
&& sctx
->prefetch_L2_mask
)
1413 cik_emit_prefetch_L2(sctx
);
1415 /* If we don't wait for idle, start prefetches first, then set
1416 * states, and draw at the end.
1419 si_emit_cache_flush(sctx
);
1421 if (sctx
->b
.chip_class
>= CIK
&& sctx
->prefetch_L2_mask
)
1422 cik_emit_prefetch_L2(sctx
);
1424 if (!si_upload_graphics_shader_descriptors(sctx
))
1427 si_emit_all_states(sctx
, info
, 0);
1428 si_ce_pre_draw_synchronization(sctx
);
1429 si_emit_draw_packets(sctx
, info
, indexbuf
, index_size
, index_offset
);
1432 si_ce_post_draw_synchronization(sctx
);
1434 if (sctx
->trace_buf
)
1435 si_trace_emit(sctx
);
1437 /* Workaround for a VGT hang when streamout is enabled.
1438 * It must be done after drawing. */
1439 if ((sctx
->b
.family
== CHIP_HAWAII
||
1440 sctx
->b
.family
== CHIP_TONGA
||
1441 sctx
->b
.family
== CHIP_FIJI
) &&
1442 r600_get_strmout_en(&sctx
->b
)) {
1443 sctx
->b
.flags
|= SI_CONTEXT_VGT_STREAMOUT_SYNC
;
1446 if (unlikely(sctx
->decompression_enabled
)) {
1447 sctx
->b
.num_decompress_calls
++;
1449 sctx
->b
.num_draw_calls
++;
1450 if (sctx
->framebuffer
.state
.nr_cbufs
> 1)
1451 sctx
->b
.num_mrt_draw_calls
++;
1452 if (info
->primitive_restart
)
1453 sctx
->b
.num_prim_restart_calls
++;
1454 if (G_0286E8_WAVESIZE(sctx
->spi_tmpring_size
))
1455 sctx
->b
.num_spill_draw_calls
++;
1457 if (index_size
&& indexbuf
!= info
->index
.resource
)
1458 pipe_resource_reference(&indexbuf
, NULL
);
1461 void si_trace_emit(struct si_context
*sctx
)
1463 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1466 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
, sctx
->trace_buf
,
1467 RADEON_USAGE_READWRITE
, RADEON_PRIO_TRACE
);
1469 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
1470 radeon_emit(cs
, S_370_DST_SEL(V_370_MEMORY_SYNC
) |
1471 S_370_WR_CONFIRM(1) |
1472 S_370_ENGINE_SEL(V_370_ME
));
1473 radeon_emit(cs
, sctx
->trace_buf
->gpu_address
);
1474 radeon_emit(cs
, sctx
->trace_buf
->gpu_address
>> 32);
1475 radeon_emit(cs
, sctx
->trace_id
);
1476 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1477 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(sctx
->trace_id
));
1480 struct radeon_winsys_cs
*ce
= sctx
->ce_ib
;
1482 radeon_emit(ce
, PKT3(PKT3_WRITE_DATA
, 3, 0));
1483 radeon_emit(ce
, S_370_DST_SEL(V_370_MEM_ASYNC
) |
1484 S_370_WR_CONFIRM(1) |
1485 S_370_ENGINE_SEL(V_370_CE
));
1486 radeon_emit(ce
, sctx
->trace_buf
->gpu_address
+ 4);
1487 radeon_emit(ce
, (sctx
->trace_buf
->gpu_address
+ 4) >> 32);
1488 radeon_emit(ce
, sctx
->trace_id
);
1489 radeon_emit(ce
, PKT3(PKT3_NOP
, 0, 0));
1490 radeon_emit(ce
, AC_ENCODE_TRACE_POINT(sctx
->trace_id
));