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radeonsi: set a better NUM_PATCHES hard limit
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32
33 #include "ac_debug.h"
34
35 /* special primitive types */
36 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
37
38 static unsigned si_conv_pipe_prim(unsigned mode)
39 {
40 static const unsigned prim_conv[] = {
41 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
42 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
43 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
44 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
45 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
46 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
47 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
48 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
49 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
50 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
51 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
55 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
56 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
57 };
58 assert(mode < ARRAY_SIZE(prim_conv));
59 return prim_conv[mode];
60 }
61
62 /**
63 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
64 * LS.LDS_SIZE is shared by all 3 shader stages.
65 *
66 * The information about LDS and other non-compile-time parameters is then
67 * written to userdata SGPRs.
68 */
69 static bool si_emit_derived_tess_state(struct si_context *sctx,
70 const struct pipe_draw_info *info,
71 unsigned *num_patches)
72 {
73 struct radeon_winsys_cs *cs = sctx->gfx_cs;
74 struct si_shader *ls_current;
75 struct si_shader_selector *ls;
76 /* The TES pointer will only be used for sctx->last_tcs.
77 * It would be wrong to think that TCS = TES. */
78 struct si_shader_selector *tcs =
79 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
80 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
81 bool has_primid_instancing_bug = sctx->chip_class == SI &&
82 sctx->screen->info.max_se == 1;
83 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
84 unsigned num_tcs_input_cp = info->vertices_per_patch;
85 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
86 unsigned num_tcs_patch_outputs;
87 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
88 unsigned input_patch_size, output_patch_size, output_patch0_offset;
89 unsigned perpatch_output_offset, lds_size;
90 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
91 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
92
93 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
94 if (sctx->chip_class >= GFX9) {
95 if (sctx->tcs_shader.cso)
96 ls_current = sctx->tcs_shader.current;
97 else
98 ls_current = sctx->fixed_func_tcs_shader.current;
99
100 ls = ls_current->key.part.tcs.ls;
101 } else {
102 ls_current = sctx->vs_shader.current;
103 ls = sctx->vs_shader.cso;
104 }
105
106 if (sctx->last_ls == ls_current &&
107 sctx->last_tcs == tcs &&
108 sctx->last_tes_sh_base == tes_sh_base &&
109 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
110 (!has_primid_instancing_bug ||
111 (sctx->last_tess_uses_primid == tess_uses_primid))) {
112 *num_patches = sctx->last_num_patches;
113 return false;
114 }
115
116 sctx->last_ls = ls_current;
117 sctx->last_tcs = tcs;
118 sctx->last_tes_sh_base = tes_sh_base;
119 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
120 sctx->last_tess_uses_primid = tess_uses_primid;
121
122 /* This calculates how shader inputs and outputs among VS, TCS, and TES
123 * are laid out in LDS. */
124 num_tcs_inputs = util_last_bit64(ls->outputs_written);
125
126 if (sctx->tcs_shader.cso) {
127 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
128 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
129 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
130 } else {
131 /* No TCS. Route varyings from LS to TES. */
132 num_tcs_outputs = num_tcs_inputs;
133 num_tcs_output_cp = num_tcs_input_cp;
134 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
135 }
136
137 input_vertex_size = num_tcs_inputs * 16;
138 output_vertex_size = num_tcs_outputs * 16;
139
140 input_patch_size = num_tcs_input_cp * input_vertex_size;
141
142 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
143 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
144
145 /* Ensure that we only need one wave per SIMD so we don't need to check
146 * resource usage. Also ensures that the number of tcs in and out
147 * vertices per threadgroup are at most 256.
148 */
149 unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
150 *num_patches = 256 / max_verts_per_patch;
151
152 /* Make sure that the data fits in LDS. This assumes the shaders only
153 * use LDS for the inputs and outputs.
154 *
155 * While CIK can use 64K per threadgroup, there is a hang on Stoney
156 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
157 * uses 32K at most on all GCN chips.
158 */
159 hardware_lds_size = 32768;
160 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
161 output_patch_size));
162
163 /* Make sure the output data fits in the offchip buffer */
164 *num_patches = MIN2(*num_patches,
165 (sctx->screen->tess_offchip_block_dw_size * 4) /
166 output_patch_size);
167
168 /* Not necessary for correctness, but improves performance.
169 * The hardware can do more, but the radeonsi shader constant is
170 * limited to 6 bits.
171 */
172 *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */
173
174 /* When distributed tessellation is unsupported, switch between SEs
175 * at a higher frequency to compensate for it.
176 */
177 if (!sctx->screen->has_distributed_tess && sctx->screen->info.max_se > 1)
178 *num_patches = MIN2(*num_patches, 16); /* recommended */
179
180 /* Make sure that vector lanes are reasonably occupied. It probably
181 * doesn't matter much because this is LS-HS, and TES is likely to
182 * occupy significantly more CUs.
183 */
184 unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
185 if (temp_verts_per_tg > 64 && temp_verts_per_tg % 64 < 48)
186 *num_patches = (temp_verts_per_tg & ~63) / max_verts_per_patch;
187
188 if (sctx->chip_class == SI) {
189 /* SI bug workaround, related to power management. Limit LS-HS
190 * threadgroups to only one wave.
191 */
192 unsigned one_wave = 64 / max_verts_per_patch;
193 *num_patches = MIN2(*num_patches, one_wave);
194 }
195
196 /* The VGT HS block increments the patch ID unconditionally
197 * within a single threadgroup. This results in incorrect
198 * patch IDs when instanced draws are used.
199 *
200 * The intended solution is to restrict threadgroups to
201 * a single instance by setting SWITCH_ON_EOI, which
202 * should cause IA to split instances up. However, this
203 * doesn't work correctly on SI when there is no other
204 * SE to switch to.
205 */
206 if (has_primid_instancing_bug && tess_uses_primid)
207 *num_patches = 1;
208
209 sctx->last_num_patches = *num_patches;
210
211 output_patch0_offset = input_patch_size * *num_patches;
212 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
213
214 /* Compute userdata SGPRs. */
215 assert(((input_vertex_size / 4) & ~0xff) == 0);
216 assert(((output_vertex_size / 4) & ~0xff) == 0);
217 assert(((input_patch_size / 4) & ~0x1fff) == 0);
218 assert(((output_patch_size / 4) & ~0x1fff) == 0);
219 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
220 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
221 assert(num_tcs_input_cp <= 32);
222 assert(num_tcs_output_cp <= 32);
223
224 uint64_t ring_va = r600_resource(sctx->tess_rings)->gpu_address;
225 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
226
227 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
228 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
229 tcs_out_layout = (output_patch_size / 4) |
230 (num_tcs_input_cp << 13) |
231 ring_va;
232 tcs_out_offsets = (output_patch0_offset / 16) |
233 ((perpatch_output_offset / 16) << 16);
234 offchip_layout = *num_patches |
235 (num_tcs_output_cp << 6) |
236 (pervertex_output_patch_size * *num_patches << 12);
237
238 /* Compute the LDS size. */
239 lds_size = output_patch0_offset + output_patch_size * *num_patches;
240
241 if (sctx->chip_class >= CIK) {
242 assert(lds_size <= 65536);
243 lds_size = align(lds_size, 512) / 512;
244 } else {
245 assert(lds_size <= 32768);
246 lds_size = align(lds_size, 256) / 256;
247 }
248
249 /* Set SI_SGPR_VS_STATE_BITS. */
250 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
251 C_VS_STATE_LS_OUT_VERTEX_SIZE;
252 sctx->current_vs_state |= tcs_in_layout;
253
254 if (sctx->chip_class >= GFX9) {
255 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
256 S_00B42C_LDS_SIZE(lds_size);
257
258 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
259
260 /* Set userdata SGPRs for merged LS-HS. */
261 radeon_set_sh_reg_seq(cs,
262 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
263 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
264 radeon_emit(cs, offchip_layout);
265 radeon_emit(cs, tcs_out_offsets);
266 radeon_emit(cs, tcs_out_layout);
267 } else {
268 unsigned ls_rsrc2 = ls_current->config.rsrc2;
269
270 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
271 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
272
273 /* Due to a hw bug, RSRC2_LS must be written twice with another
274 * LS register written in between. */
275 if (sctx->chip_class == CIK && sctx->family != CHIP_HAWAII)
276 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
277 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
278 radeon_emit(cs, ls_current->config.rsrc1);
279 radeon_emit(cs, ls_rsrc2);
280
281 /* Set userdata SGPRs for TCS. */
282 radeon_set_sh_reg_seq(cs,
283 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
284 radeon_emit(cs, offchip_layout);
285 radeon_emit(cs, tcs_out_offsets);
286 radeon_emit(cs, tcs_out_layout);
287 radeon_emit(cs, tcs_in_layout);
288 }
289
290 /* Set userdata SGPRs for TES. */
291 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
292 radeon_emit(cs, offchip_layout);
293 radeon_emit(cs, ring_va);
294
295 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
296 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
297 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
298
299 if (sctx->last_ls_hs_config != ls_hs_config) {
300 if (sctx->chip_class >= CIK) {
301 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
302 ls_hs_config);
303 } else {
304 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
305 ls_hs_config);
306 }
307 sctx->last_ls_hs_config = ls_hs_config;
308 return true; /* true if the context rolls */
309 }
310 return false;
311 }
312
313 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
314 {
315 switch (info->mode) {
316 case PIPE_PRIM_PATCHES:
317 return info->count / info->vertices_per_patch;
318 case SI_PRIM_RECTANGLE_LIST:
319 return info->count / 3;
320 default:
321 return u_prims_for_vertices(info->mode, info->count);
322 }
323 }
324
325 static unsigned
326 si_get_init_multi_vgt_param(struct si_screen *sscreen,
327 union si_vgt_param_key *key)
328 {
329 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
330 unsigned max_primgroup_in_wave = 2;
331
332 /* SWITCH_ON_EOP(0) is always preferable. */
333 bool wd_switch_on_eop = false;
334 bool ia_switch_on_eop = false;
335 bool ia_switch_on_eoi = false;
336 bool partial_vs_wave = false;
337 bool partial_es_wave = false;
338
339 if (key->u.uses_tess) {
340 /* SWITCH_ON_EOI must be set if PrimID is used. */
341 if (key->u.tess_uses_prim_id)
342 ia_switch_on_eoi = true;
343
344 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
345 if ((sscreen->info.family == CHIP_TAHITI ||
346 sscreen->info.family == CHIP_PITCAIRN ||
347 sscreen->info.family == CHIP_BONAIRE) &&
348 key->u.uses_gs)
349 partial_vs_wave = true;
350
351 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
352 if (sscreen->has_distributed_tess) {
353 if (key->u.uses_gs) {
354 if (sscreen->info.chip_class <= VI)
355 partial_es_wave = true;
356
357 /* GPU hang workaround. */
358 if (sscreen->info.family == CHIP_TONGA ||
359 sscreen->info.family == CHIP_FIJI ||
360 sscreen->info.family == CHIP_POLARIS10 ||
361 sscreen->info.family == CHIP_POLARIS11 ||
362 sscreen->info.family == CHIP_POLARIS12 ||
363 sscreen->info.family == CHIP_VEGAM)
364 partial_vs_wave = true;
365 } else {
366 partial_vs_wave = true;
367 }
368 }
369 }
370
371 /* This is a hardware requirement. */
372 if (key->u.line_stipple_enabled ||
373 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
374 ia_switch_on_eop = true;
375 wd_switch_on_eop = true;
376 }
377
378 if (sscreen->info.chip_class >= CIK) {
379 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
380 * 4 shader engines. Set 1 to pass the assertion below.
381 * The other cases are hardware requirements.
382 *
383 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
384 * for points, line strips, and tri strips.
385 */
386 if (sscreen->info.max_se < 4 ||
387 key->u.prim == PIPE_PRIM_POLYGON ||
388 key->u.prim == PIPE_PRIM_LINE_LOOP ||
389 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
390 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
391 (key->u.primitive_restart &&
392 (sscreen->info.family < CHIP_POLARIS10 ||
393 (key->u.prim != PIPE_PRIM_POINTS &&
394 key->u.prim != PIPE_PRIM_LINE_STRIP &&
395 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
396 key->u.count_from_stream_output)
397 wd_switch_on_eop = true;
398
399 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
400 * We don't know that for indirect drawing, so treat it as
401 * always problematic. */
402 if (sscreen->info.family == CHIP_HAWAII &&
403 key->u.uses_instancing)
404 wd_switch_on_eop = true;
405
406 /* Performance recommendation for 4 SE Gfx7-8 parts if
407 * instances are smaller than a primgroup.
408 * Assume indirect draws always use small instances.
409 * This is needed for good VS wave utilization.
410 */
411 if (sscreen->info.chip_class <= VI &&
412 sscreen->info.max_se == 4 &&
413 key->u.multi_instances_smaller_than_primgroup)
414 wd_switch_on_eop = true;
415
416 /* Required on CIK and later. */
417 if (sscreen->info.max_se > 2 && !wd_switch_on_eop)
418 ia_switch_on_eoi = true;
419
420 /* Required by Hawaii and, for some special cases, by VI. */
421 if (ia_switch_on_eoi &&
422 (sscreen->info.family == CHIP_HAWAII ||
423 (sscreen->info.chip_class == VI &&
424 (key->u.uses_gs || max_primgroup_in_wave != 2))))
425 partial_vs_wave = true;
426
427 /* Instancing bug on Bonaire. */
428 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
429 key->u.uses_instancing)
430 partial_vs_wave = true;
431
432 /* If the WD switch is false, the IA switch must be false too. */
433 assert(wd_switch_on_eop || !ia_switch_on_eop);
434 }
435
436 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
437 if (sscreen->info.chip_class <= VI && ia_switch_on_eoi)
438 partial_es_wave = true;
439
440 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
441 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
442 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
443 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
444 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= CIK ? wd_switch_on_eop : 0) |
445 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
446 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == VI ?
447 max_primgroup_in_wave : 0) |
448 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
449 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
450 }
451
452 void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
453 {
454 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
455 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
456 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
457 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
458 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
459 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
460 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
461 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
462 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
463 union si_vgt_param_key key;
464
465 key.index = 0;
466 key.u.prim = prim;
467 key.u.uses_instancing = uses_instancing;
468 key.u.multi_instances_smaller_than_primgroup = multi_instances;
469 key.u.primitive_restart = primitive_restart;
470 key.u.count_from_stream_output = count_from_so;
471 key.u.line_stipple_enabled = line_stipple;
472 key.u.uses_tess = uses_tess;
473 key.u.tess_uses_prim_id = tess_uses_primid;
474 key.u.uses_gs = uses_gs;
475
476 sctx->ia_multi_vgt_param[key.index] =
477 si_get_init_multi_vgt_param(sctx->screen, &key);
478 }
479 }
480
481 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
482 const struct pipe_draw_info *info,
483 unsigned num_patches)
484 {
485 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
486 unsigned primgroup_size;
487 unsigned ia_multi_vgt_param;
488
489 if (sctx->tes_shader.cso) {
490 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
491 } else if (sctx->gs_shader.cso) {
492 primgroup_size = 64; /* recommended with a GS */
493 } else {
494 primgroup_size = 128; /* recommended without a GS and tess */
495 }
496
497 key.u.prim = info->mode;
498 key.u.uses_instancing = info->indirect || info->instance_count > 1;
499 key.u.multi_instances_smaller_than_primgroup =
500 info->indirect ||
501 (info->instance_count > 1 &&
502 (info->count_from_stream_output ||
503 si_num_prims_for_vertices(info) < primgroup_size));
504 key.u.primitive_restart = info->primitive_restart;
505 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
506
507 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
508 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
509
510 if (sctx->gs_shader.cso) {
511 /* GS requirement. */
512 if (sctx->chip_class <= VI &&
513 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
514 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
515
516 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
517 * The hw doc says all multi-SE chips are affected, but Vulkan
518 * only applies it to Hawaii. Do what Vulkan does.
519 */
520 if (sctx->family == CHIP_HAWAII &&
521 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
522 (info->indirect ||
523 (info->instance_count > 1 &&
524 (info->count_from_stream_output ||
525 si_num_prims_for_vertices(info) <= 1))))
526 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
527 }
528
529 return ia_multi_vgt_param;
530 }
531
532 /* rast_prim is the primitive type after GS. */
533 static bool si_emit_rasterizer_prim_state(struct si_context *sctx)
534 {
535 struct radeon_winsys_cs *cs = sctx->gfx_cs;
536 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
537 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
538
539 /* Skip this if not rendering lines. */
540 if (!util_prim_is_lines(rast_prim))
541 return false;
542
543 if (rast_prim == sctx->last_rast_prim &&
544 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
545 return false;
546
547 /* For lines, reset the stipple pattern at each primitive. Otherwise,
548 * reset the stipple pattern at each packet (line strips, line loops).
549 */
550 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
551 rs->pa_sc_line_stipple |
552 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
553
554 sctx->last_rast_prim = rast_prim;
555 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
556 return true; /* true if the context rolls */
557 }
558
559 static void si_emit_vs_state(struct si_context *sctx,
560 const struct pipe_draw_info *info)
561 {
562 sctx->current_vs_state &= C_VS_STATE_INDEXED;
563 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
564
565 if (sctx->num_vs_blit_sgprs) {
566 /* Re-emit the state after we leave u_blitter. */
567 sctx->last_vs_state = ~0;
568 return;
569 }
570
571 if (sctx->current_vs_state != sctx->last_vs_state) {
572 struct radeon_winsys_cs *cs = sctx->gfx_cs;
573
574 radeon_set_sh_reg(cs,
575 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
576 SI_SGPR_VS_STATE_BITS * 4,
577 sctx->current_vs_state);
578
579 sctx->last_vs_state = sctx->current_vs_state;
580 }
581 }
582
583 static inline bool si_prim_restart_index_changed(struct si_context *sctx,
584 const struct pipe_draw_info *info)
585 {
586 return info->primitive_restart &&
587 (info->restart_index != sctx->last_restart_index ||
588 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
589 }
590
591 static void si_emit_draw_registers(struct si_context *sctx,
592 const struct pipe_draw_info *info,
593 unsigned num_patches)
594 {
595 struct radeon_winsys_cs *cs = sctx->gfx_cs;
596 unsigned prim = si_conv_pipe_prim(info->mode);
597 unsigned ia_multi_vgt_param;
598
599 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
600
601 /* Draw state. */
602 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
603 if (sctx->chip_class >= GFX9)
604 radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
605 else if (sctx->chip_class >= CIK)
606 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
607 else
608 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
609
610 sctx->last_multi_vgt_param = ia_multi_vgt_param;
611 }
612 if (prim != sctx->last_prim) {
613 if (sctx->chip_class >= CIK)
614 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
615 else
616 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
617
618 sctx->last_prim = prim;
619 }
620
621 /* Primitive restart. */
622 if (info->primitive_restart != sctx->last_primitive_restart_en) {
623 if (sctx->chip_class >= GFX9)
624 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
625 info->primitive_restart);
626 else
627 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
628 info->primitive_restart);
629
630 sctx->last_primitive_restart_en = info->primitive_restart;
631
632 }
633 if (si_prim_restart_index_changed(sctx, info)) {
634 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
635 info->restart_index);
636 sctx->last_restart_index = info->restart_index;
637 }
638 }
639
640 static void si_emit_draw_packets(struct si_context *sctx,
641 const struct pipe_draw_info *info,
642 struct pipe_resource *indexbuf,
643 unsigned index_size,
644 unsigned index_offset)
645 {
646 struct pipe_draw_indirect_info *indirect = info->indirect;
647 struct radeon_winsys_cs *cs = sctx->gfx_cs;
648 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
649 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
650 uint32_t index_max_size = 0;
651 uint64_t index_va = 0;
652
653 if (info->count_from_stream_output) {
654 struct si_streamout_target *t =
655 (struct si_streamout_target*)info->count_from_stream_output;
656 uint64_t va = t->buf_filled_size->gpu_address +
657 t->buf_filled_size_offset;
658
659 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
660 t->stride_in_dw);
661
662 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
663 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
664 COPY_DATA_DST_SEL(COPY_DATA_REG) |
665 COPY_DATA_WR_CONFIRM);
666 radeon_emit(cs, va); /* src address lo */
667 radeon_emit(cs, va >> 32); /* src address hi */
668 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
669 radeon_emit(cs, 0); /* unused */
670
671 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
672 t->buf_filled_size, RADEON_USAGE_READ,
673 RADEON_PRIO_SO_FILLED_SIZE);
674 }
675
676 /* draw packet */
677 if (index_size) {
678 if (index_size != sctx->last_index_size) {
679 unsigned index_type;
680
681 /* index type */
682 switch (index_size) {
683 case 1:
684 index_type = V_028A7C_VGT_INDEX_8;
685 break;
686 case 2:
687 index_type = V_028A7C_VGT_INDEX_16 |
688 (SI_BIG_ENDIAN && sctx->chip_class <= CIK ?
689 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
690 break;
691 case 4:
692 index_type = V_028A7C_VGT_INDEX_32 |
693 (SI_BIG_ENDIAN && sctx->chip_class <= CIK ?
694 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
695 break;
696 default:
697 assert(!"unreachable");
698 return;
699 }
700
701 if (sctx->chip_class >= GFX9) {
702 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
703 2, index_type);
704 } else {
705 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
706 radeon_emit(cs, index_type);
707 }
708
709 sctx->last_index_size = index_size;
710 }
711
712 index_max_size = (indexbuf->width0 - index_offset) /
713 index_size;
714 index_va = r600_resource(indexbuf)->gpu_address + index_offset;
715
716 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
717 r600_resource(indexbuf),
718 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
719 } else {
720 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
721 * so the state must be re-emitted before the next indexed draw.
722 */
723 if (sctx->chip_class >= CIK)
724 sctx->last_index_size = -1;
725 }
726
727 if (indirect) {
728 uint64_t indirect_va = r600_resource(indirect->buffer)->gpu_address;
729
730 assert(indirect_va % 8 == 0);
731
732 si_invalidate_draw_sh_constants(sctx);
733
734 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
735 radeon_emit(cs, 1);
736 radeon_emit(cs, indirect_va);
737 radeon_emit(cs, indirect_va >> 32);
738
739 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
740 r600_resource(indirect->buffer),
741 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
742
743 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
744 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
745
746 assert(indirect->offset % 4 == 0);
747
748 if (index_size) {
749 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
750 radeon_emit(cs, index_va);
751 radeon_emit(cs, index_va >> 32);
752
753 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
754 radeon_emit(cs, index_max_size);
755 }
756
757 if (!sctx->screen->has_draw_indirect_multi) {
758 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
759 : PKT3_DRAW_INDIRECT,
760 3, render_cond_bit));
761 radeon_emit(cs, indirect->offset);
762 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
763 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
764 radeon_emit(cs, di_src_sel);
765 } else {
766 uint64_t count_va = 0;
767
768 if (indirect->indirect_draw_count) {
769 struct r600_resource *params_buf =
770 r600_resource(indirect->indirect_draw_count);
771
772 radeon_add_to_buffer_list(
773 sctx, sctx->gfx_cs, params_buf,
774 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
775
776 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
777 }
778
779 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
780 PKT3_DRAW_INDIRECT_MULTI,
781 8, render_cond_bit));
782 radeon_emit(cs, indirect->offset);
783 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
784 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
785 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
786 S_2C3_DRAW_INDEX_ENABLE(1) |
787 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
788 radeon_emit(cs, indirect->draw_count);
789 radeon_emit(cs, count_va);
790 radeon_emit(cs, count_va >> 32);
791 radeon_emit(cs, indirect->stride);
792 radeon_emit(cs, di_src_sel);
793 }
794 } else {
795 int base_vertex;
796
797 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
798 radeon_emit(cs, info->instance_count);
799
800 /* Base vertex and start instance. */
801 base_vertex = index_size ? info->index_bias : info->start;
802
803 if (sctx->num_vs_blit_sgprs) {
804 /* Re-emit draw constants after we leave u_blitter. */
805 si_invalidate_draw_sh_constants(sctx);
806
807 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
808 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
809 sctx->num_vs_blit_sgprs);
810 radeon_emit_array(cs, sctx->vs_blit_sh_data,
811 sctx->num_vs_blit_sgprs);
812 } else if (base_vertex != sctx->last_base_vertex ||
813 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
814 info->start_instance != sctx->last_start_instance ||
815 info->drawid != sctx->last_drawid ||
816 sh_base_reg != sctx->last_sh_base_reg) {
817 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
818 radeon_emit(cs, base_vertex);
819 radeon_emit(cs, info->start_instance);
820 radeon_emit(cs, info->drawid);
821
822 sctx->last_base_vertex = base_vertex;
823 sctx->last_start_instance = info->start_instance;
824 sctx->last_drawid = info->drawid;
825 sctx->last_sh_base_reg = sh_base_reg;
826 }
827
828 if (index_size) {
829 index_va += info->start * index_size;
830
831 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
832 radeon_emit(cs, index_max_size);
833 radeon_emit(cs, index_va);
834 radeon_emit(cs, index_va >> 32);
835 radeon_emit(cs, info->count);
836 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
837 } else {
838 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
839 radeon_emit(cs, info->count);
840 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
841 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
842 }
843 }
844 }
845
846 static void si_emit_surface_sync(struct si_context *sctx,
847 unsigned cp_coher_cntl)
848 {
849 struct radeon_winsys_cs *cs = sctx->gfx_cs;
850
851 if (sctx->chip_class >= GFX9) {
852 /* Flush caches and wait for the caches to assert idle. */
853 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
854 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
855 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
856 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
857 radeon_emit(cs, 0); /* CP_COHER_BASE */
858 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
859 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
860 } else {
861 /* ACQUIRE_MEM is only required on a compute ring. */
862 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
863 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
864 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
865 radeon_emit(cs, 0); /* CP_COHER_BASE */
866 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
867 }
868 }
869
870 void si_emit_cache_flush(struct si_context *sctx)
871 {
872 struct radeon_winsys_cs *cs = sctx->gfx_cs;
873 uint32_t flags = sctx->flags;
874 uint32_t cp_coher_cntl = 0;
875 uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
876 SI_CONTEXT_FLUSH_AND_INV_DB);
877
878 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
879 sctx->num_cb_cache_flushes++;
880 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
881 sctx->num_db_cache_flushes++;
882
883 /* SI has a bug that it always flushes ICACHE and KCACHE if either
884 * bit is set. An alternative way is to write SQC_CACHES, but that
885 * doesn't seem to work reliably. Since the bug doesn't affect
886 * correctness (it only does more work than necessary) and
887 * the performance impact is likely negligible, there is no plan
888 * to add a workaround for it.
889 */
890
891 if (flags & SI_CONTEXT_INV_ICACHE)
892 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
893 if (flags & SI_CONTEXT_INV_SMEM_L1)
894 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
895
896 if (sctx->chip_class <= VI) {
897 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
898 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
899 S_0085F0_CB0_DEST_BASE_ENA(1) |
900 S_0085F0_CB1_DEST_BASE_ENA(1) |
901 S_0085F0_CB2_DEST_BASE_ENA(1) |
902 S_0085F0_CB3_DEST_BASE_ENA(1) |
903 S_0085F0_CB4_DEST_BASE_ENA(1) |
904 S_0085F0_CB5_DEST_BASE_ENA(1) |
905 S_0085F0_CB6_DEST_BASE_ENA(1) |
906 S_0085F0_CB7_DEST_BASE_ENA(1);
907
908 /* Necessary for DCC */
909 if (sctx->chip_class == VI)
910 si_gfx_write_event_eop(sctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
911 0, EOP_DATA_SEL_DISCARD, NULL,
912 0, 0, SI_NOT_QUERY);
913 }
914 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
915 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
916 S_0085F0_DB_DEST_BASE_ENA(1);
917 }
918
919 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
920 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
921 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
922 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
923 }
924 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
925 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
926 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
927 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
928 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
929 }
930
931 /* Wait for shader engines to go idle.
932 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
933 * for everything including CB/DB cache flushes.
934 */
935 if (!flush_cb_db) {
936 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
937 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
938 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
939 /* Only count explicit shader flushes, not implicit ones
940 * done by SURFACE_SYNC.
941 */
942 sctx->num_vs_flushes++;
943 sctx->num_ps_flushes++;
944 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
945 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
946 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
947 sctx->num_vs_flushes++;
948 }
949 }
950
951 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
952 sctx->compute_is_busy) {
953 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
954 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
955 sctx->num_cs_flushes++;
956 sctx->compute_is_busy = false;
957 }
958
959 /* VGT state synchronization. */
960 if (flags & SI_CONTEXT_VGT_FLUSH) {
961 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
962 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
963 }
964 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
965 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
966 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
967 }
968
969 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
970 * wait for idle on GFX9. We have to use a TS event.
971 */
972 if (sctx->chip_class >= GFX9 && flush_cb_db) {
973 uint64_t va;
974 unsigned tc_flags, cb_db_event;
975
976 /* Set the CB/DB flush event. */
977 switch (flush_cb_db) {
978 case SI_CONTEXT_FLUSH_AND_INV_CB:
979 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
980 break;
981 case SI_CONTEXT_FLUSH_AND_INV_DB:
982 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
983 break;
984 default:
985 /* both CB & DB */
986 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
987 }
988
989 /* These are the only allowed combinations. If you need to
990 * do multiple operations at once, do them separately.
991 * All operations that invalidate L2 also seem to invalidate
992 * metadata. Volatile (VOL) and WC flushes are not listed here.
993 *
994 * TC | TC_WB = writeback & invalidate L2 & L1
995 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
996 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
997 * TC | TC_NC = invalidate L2 for MTYPE == NC
998 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
999 * TCL1 = invalidate L1
1000 */
1001 tc_flags = 0;
1002
1003 if (flags & SI_CONTEXT_INV_L2_METADATA) {
1004 tc_flags = EVENT_TC_ACTION_ENA |
1005 EVENT_TC_MD_ACTION_ENA;
1006 }
1007
1008 /* Ideally flush TC together with CB/DB. */
1009 if (flags & SI_CONTEXT_INV_GLOBAL_L2) {
1010 /* Writeback and invalidate everything in L2 & L1. */
1011 tc_flags = EVENT_TC_ACTION_ENA |
1012 EVENT_TC_WB_ACTION_ENA;
1013
1014 /* Clear the flags. */
1015 flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
1016 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
1017 SI_CONTEXT_INV_VMEM_L1);
1018 sctx->num_L2_invalidates++;
1019 }
1020
1021 /* Do the flush (enqueue the event and wait for it). */
1022 va = sctx->wait_mem_scratch->gpu_address;
1023 sctx->wait_mem_number++;
1024
1025 si_gfx_write_event_eop(sctx, cb_db_event, tc_flags,
1026 EOP_DATA_SEL_VALUE_32BIT,
1027 sctx->wait_mem_scratch, va,
1028 sctx->wait_mem_number, SI_NOT_QUERY);
1029 si_gfx_wait_fence(sctx, va, sctx->wait_mem_number, 0xffffffff);
1030 }
1031
1032 /* Make sure ME is idle (it executes most packets) before continuing.
1033 * This prevents read-after-write hazards between PFP and ME.
1034 */
1035 if (cp_coher_cntl ||
1036 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1037 SI_CONTEXT_INV_VMEM_L1 |
1038 SI_CONTEXT_INV_GLOBAL_L2 |
1039 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1040 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1041 radeon_emit(cs, 0);
1042 }
1043
1044 /* SI-CI-VI only:
1045 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1046 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1047 *
1048 * cp_coher_cntl should contain all necessary flags except TC flags
1049 * at this point.
1050 *
1051 * SI-CIK don't support L2 write-back.
1052 */
1053 if (flags & SI_CONTEXT_INV_GLOBAL_L2 ||
1054 (sctx->chip_class <= CIK &&
1055 (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1056 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
1057 * WB must be set on VI+ when TC_ACTION is set.
1058 */
1059 si_emit_surface_sync(sctx, cp_coher_cntl |
1060 S_0085F0_TC_ACTION_ENA(1) |
1061 S_0085F0_TCL1_ACTION_ENA(1) |
1062 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= VI));
1063 cp_coher_cntl = 0;
1064 sctx->num_L2_invalidates++;
1065 } else {
1066 /* L1 invalidation and L2 writeback must be done separately,
1067 * because both operations can't be done together.
1068 */
1069 if (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
1070 /* WB = write-back
1071 * NC = apply to non-coherent MTYPEs
1072 * (i.e. MTYPE <= 1, which is what we use everywhere)
1073 *
1074 * WB doesn't work without NC.
1075 */
1076 si_emit_surface_sync(sctx, cp_coher_cntl |
1077 S_0301F0_TC_WB_ACTION_ENA(1) |
1078 S_0301F0_TC_NC_ACTION_ENA(1));
1079 cp_coher_cntl = 0;
1080 sctx->num_L2_writebacks++;
1081 }
1082 if (flags & SI_CONTEXT_INV_VMEM_L1) {
1083 /* Invalidate per-CU VMEM L1. */
1084 si_emit_surface_sync(sctx, cp_coher_cntl |
1085 S_0085F0_TCL1_ACTION_ENA(1));
1086 cp_coher_cntl = 0;
1087 }
1088 }
1089
1090 /* If TC flushes haven't cleared this... */
1091 if (cp_coher_cntl)
1092 si_emit_surface_sync(sctx, cp_coher_cntl);
1093
1094 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1095 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1096 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1097 EVENT_INDEX(0));
1098 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1099 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1100 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1101 EVENT_INDEX(0));
1102 }
1103
1104 sctx->flags = 0;
1105 }
1106
1107 static void si_get_draw_start_count(struct si_context *sctx,
1108 const struct pipe_draw_info *info,
1109 unsigned *start, unsigned *count)
1110 {
1111 struct pipe_draw_indirect_info *indirect = info->indirect;
1112
1113 if (indirect) {
1114 unsigned indirect_count;
1115 struct pipe_transfer *transfer;
1116 unsigned begin, end;
1117 unsigned map_size;
1118 unsigned *data;
1119
1120 if (indirect->indirect_draw_count) {
1121 data = pipe_buffer_map_range(&sctx->b,
1122 indirect->indirect_draw_count,
1123 indirect->indirect_draw_count_offset,
1124 sizeof(unsigned),
1125 PIPE_TRANSFER_READ, &transfer);
1126
1127 indirect_count = *data;
1128
1129 pipe_buffer_unmap(&sctx->b, transfer);
1130 } else {
1131 indirect_count = indirect->draw_count;
1132 }
1133
1134 if (!indirect_count) {
1135 *start = *count = 0;
1136 return;
1137 }
1138
1139 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1140 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1141 indirect->offset, map_size,
1142 PIPE_TRANSFER_READ, &transfer);
1143
1144 begin = UINT_MAX;
1145 end = 0;
1146
1147 for (unsigned i = 0; i < indirect_count; ++i) {
1148 unsigned count = data[0];
1149 unsigned start = data[2];
1150
1151 if (count > 0) {
1152 begin = MIN2(begin, start);
1153 end = MAX2(end, start + count);
1154 }
1155
1156 data += indirect->stride / sizeof(unsigned);
1157 }
1158
1159 pipe_buffer_unmap(&sctx->b, transfer);
1160
1161 if (begin < end) {
1162 *start = begin;
1163 *count = end - begin;
1164 } else {
1165 *start = *count = 0;
1166 }
1167 } else {
1168 *start = info->start;
1169 *count = info->count;
1170 }
1171 }
1172
1173 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1174 unsigned skip_atom_mask)
1175 {
1176 unsigned num_patches = 0;
1177 bool context_roll = false; /* set correctly for GFX9 only */
1178
1179 context_roll |= si_emit_rasterizer_prim_state(sctx);
1180 if (sctx->tes_shader.cso)
1181 context_roll |= si_emit_derived_tess_state(sctx, info, &num_patches);
1182 if (info->count_from_stream_output)
1183 context_roll = true;
1184
1185 /* Vega10/Raven scissor bug workaround. When any context register is
1186 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
1187 * registers must be written too.
1188 */
1189 if ((sctx->family == CHIP_VEGA10 || sctx->family == CHIP_RAVEN) &&
1190 (context_roll ||
1191 sctx->dirty_atoms & si_atoms_that_roll_context() ||
1192 sctx->dirty_states & si_states_that_roll_context() ||
1193 si_prim_restart_index_changed(sctx, info))) {
1194 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1195 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1196 }
1197
1198 /* Emit state atoms. */
1199 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1200 while (mask)
1201 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1202
1203 sctx->dirty_atoms &= skip_atom_mask;
1204
1205 /* Emit states. */
1206 mask = sctx->dirty_states;
1207 while (mask) {
1208 unsigned i = u_bit_scan(&mask);
1209 struct si_pm4_state *state = sctx->queued.array[i];
1210
1211 if (!state || sctx->emitted.array[i] == state)
1212 continue;
1213
1214 si_pm4_emit(sctx, state);
1215 sctx->emitted.array[i] = state;
1216 }
1217 sctx->dirty_states = 0;
1218
1219 /* Emit draw states. */
1220 si_emit_vs_state(sctx, info);
1221 si_emit_draw_registers(sctx, info, num_patches);
1222 }
1223
1224 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1225 {
1226 struct si_context *sctx = (struct si_context *)ctx;
1227 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1228 struct pipe_resource *indexbuf = info->index.resource;
1229 unsigned dirty_tex_counter;
1230 enum pipe_prim_type rast_prim;
1231 unsigned index_size = info->index_size;
1232 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1233
1234 if (likely(!info->indirect)) {
1235 /* SI-CI treat instance_count==0 as instance_count==1. There is
1236 * no workaround for indirect draws, but we can at least skip
1237 * direct draws.
1238 */
1239 if (unlikely(!info->instance_count))
1240 return;
1241
1242 /* Handle count == 0. */
1243 if (unlikely(!info->count &&
1244 (index_size || !info->count_from_stream_output)))
1245 return;
1246 }
1247
1248 if (unlikely(!sctx->vs_shader.cso ||
1249 !rs ||
1250 (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
1251 (!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES)))) {
1252 assert(0);
1253 return;
1254 }
1255
1256 /* Recompute and re-emit the texture resource states if needed. */
1257 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1258 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1259 sctx->last_dirty_tex_counter = dirty_tex_counter;
1260 sctx->framebuffer.dirty_cbufs |=
1261 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1262 sctx->framebuffer.dirty_zsbuf = true;
1263 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1264 si_update_all_texture_descriptors(sctx);
1265 }
1266
1267 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1268
1269 /* Set the rasterization primitive type.
1270 *
1271 * This must be done after si_decompress_textures, which can call
1272 * draw_vbo recursively, and before si_update_shaders, which uses
1273 * current_rast_prim for this draw_vbo call. */
1274 if (sctx->gs_shader.cso)
1275 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1276 else if (sctx->tes_shader.cso) {
1277 if (sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1278 rast_prim = PIPE_PRIM_POINTS;
1279 else
1280 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1281 } else
1282 rast_prim = info->mode;
1283
1284 if (rast_prim != sctx->current_rast_prim) {
1285 if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
1286 util_prim_is_points_or_lines(rast_prim))
1287 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1288
1289 sctx->current_rast_prim = rast_prim;
1290 sctx->do_update_shaders = true;
1291 }
1292
1293 if (sctx->tes_shader.cso &&
1294 sctx->screen->has_ls_vgpr_init_bug) {
1295 /* Determine whether the LS VGPR fix should be applied.
1296 *
1297 * It is only required when num input CPs > num output CPs,
1298 * which cannot happen with the fixed function TCS. We should
1299 * also update this bit when switching from TCS to fixed
1300 * function TCS.
1301 */
1302 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1303 bool ls_vgpr_fix =
1304 tcs &&
1305 info->vertices_per_patch >
1306 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1307
1308 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1309 sctx->ls_vgpr_fix = ls_vgpr_fix;
1310 sctx->do_update_shaders = true;
1311 }
1312 }
1313
1314 if (sctx->gs_shader.cso) {
1315 /* Determine whether the GS triangle strip adjacency fix should
1316 * be applied. Rotate every other triangle if
1317 * - triangle strips with adjacency are fed to the GS and
1318 * - primitive restart is disabled (the rotation doesn't help
1319 * when the restart occurs after an odd number of triangles).
1320 */
1321 bool gs_tri_strip_adj_fix =
1322 !sctx->tes_shader.cso &&
1323 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1324 !info->primitive_restart;
1325
1326 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1327 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1328 sctx->do_update_shaders = true;
1329 }
1330 }
1331
1332 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1333 return;
1334
1335 if (index_size) {
1336 /* Translate or upload, if needed. */
1337 /* 8-bit indices are supported on VI. */
1338 if (sctx->chip_class <= CIK && index_size == 1) {
1339 unsigned start, count, start_offset, size, offset;
1340 void *ptr;
1341
1342 si_get_draw_start_count(sctx, info, &start, &count);
1343 start_offset = start * 2;
1344 size = count * 2;
1345
1346 indexbuf = NULL;
1347 u_upload_alloc(ctx->stream_uploader, start_offset,
1348 size,
1349 si_optimal_tcc_alignment(sctx, size),
1350 &offset, &indexbuf, &ptr);
1351 if (!indexbuf)
1352 return;
1353
1354 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1355 index_offset + start,
1356 count, ptr);
1357
1358 /* info->start will be added by the drawing code */
1359 index_offset = offset - start_offset;
1360 index_size = 2;
1361 } else if (info->has_user_indices) {
1362 unsigned start_offset;
1363
1364 assert(!info->indirect);
1365 start_offset = info->start * index_size;
1366
1367 indexbuf = NULL;
1368 u_upload_data(ctx->stream_uploader, start_offset,
1369 info->count * index_size,
1370 sctx->screen->info.tcc_cache_line_size,
1371 (char*)info->index.user + start_offset,
1372 &index_offset, &indexbuf);
1373 if (!indexbuf)
1374 return;
1375
1376 /* info->start will be added by the drawing code */
1377 index_offset -= start_offset;
1378 } else if (sctx->chip_class <= CIK &&
1379 r600_resource(indexbuf)->TC_L2_dirty) {
1380 /* VI reads index buffers through TC L2, so it doesn't
1381 * need this. */
1382 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1383 r600_resource(indexbuf)->TC_L2_dirty = false;
1384 }
1385 }
1386
1387 if (info->indirect) {
1388 struct pipe_draw_indirect_info *indirect = info->indirect;
1389
1390 /* Add the buffer size for memory checking in need_cs_space. */
1391 si_context_add_resource_size(sctx, indirect->buffer);
1392
1393 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1394 if (sctx->chip_class <= VI) {
1395 if (r600_resource(indirect->buffer)->TC_L2_dirty) {
1396 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1397 r600_resource(indirect->buffer)->TC_L2_dirty = false;
1398 }
1399
1400 if (indirect->indirect_draw_count &&
1401 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1402 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1403 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1404 }
1405 }
1406 }
1407
1408 si_need_gfx_cs_space(sctx);
1409
1410 /* Since we've called si_context_add_resource_size for vertex buffers,
1411 * this must be called after si_need_cs_space, because we must let
1412 * need_cs_space flush before we add buffers to the buffer list.
1413 */
1414 if (!si_upload_vertex_buffer_descriptors(sctx))
1415 return;
1416
1417 /* Use optimal packet order based on whether we need to sync the pipeline. */
1418 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1419 SI_CONTEXT_FLUSH_AND_INV_DB |
1420 SI_CONTEXT_PS_PARTIAL_FLUSH |
1421 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1422 /* If we have to wait for idle, set all states first, so that all
1423 * SET packets are processed in parallel with previous draw calls.
1424 * Then draw and prefetch at the end. This ensures that the time
1425 * the CUs are idle is very short.
1426 */
1427 unsigned masked_atoms = 0;
1428
1429 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
1430 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
1431
1432 if (!si_upload_graphics_shader_descriptors(sctx))
1433 return;
1434
1435 /* Emit all states except possibly render condition. */
1436 si_emit_all_states(sctx, info, masked_atoms);
1437 si_emit_cache_flush(sctx);
1438 /* <-- CUs are idle here. */
1439
1440 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
1441 sctx->atoms.s.render_cond.emit(sctx);
1442 sctx->dirty_atoms = 0;
1443
1444 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1445 /* <-- CUs are busy here. */
1446
1447 /* Start prefetches after the draw has been started. Both will run
1448 * in parallel, but starting the draw first is more important.
1449 */
1450 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1451 cik_emit_prefetch_L2(sctx, false);
1452 } else {
1453 /* If we don't wait for idle, start prefetches first, then set
1454 * states, and draw at the end.
1455 */
1456 if (sctx->flags)
1457 si_emit_cache_flush(sctx);
1458
1459 /* Only prefetch the API VS and VBO descriptors. */
1460 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1461 cik_emit_prefetch_L2(sctx, true);
1462
1463 if (!si_upload_graphics_shader_descriptors(sctx))
1464 return;
1465
1466 si_emit_all_states(sctx, info, 0);
1467 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1468
1469 /* Prefetch the remaining shaders after the draw has been
1470 * started. */
1471 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1472 cik_emit_prefetch_L2(sctx, false);
1473 }
1474
1475 if (unlikely(sctx->current_saved_cs)) {
1476 si_trace_emit(sctx);
1477 si_log_draw_state(sctx, sctx->log);
1478 }
1479
1480 /* Workaround for a VGT hang when streamout is enabled.
1481 * It must be done after drawing. */
1482 if ((sctx->family == CHIP_HAWAII ||
1483 sctx->family == CHIP_TONGA ||
1484 sctx->family == CHIP_FIJI) &&
1485 si_get_strmout_en(sctx)) {
1486 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1487 }
1488
1489 if (unlikely(sctx->decompression_enabled)) {
1490 sctx->num_decompress_calls++;
1491 } else {
1492 sctx->num_draw_calls++;
1493 if (sctx->framebuffer.state.nr_cbufs > 1)
1494 sctx->num_mrt_draw_calls++;
1495 if (info->primitive_restart)
1496 sctx->num_prim_restart_calls++;
1497 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1498 sctx->num_spill_draw_calls++;
1499 }
1500 if (index_size && indexbuf != info->index.resource)
1501 pipe_resource_reference(&indexbuf, NULL);
1502 }
1503
1504 void si_draw_rectangle(struct blitter_context *blitter,
1505 void *vertex_elements_cso,
1506 blitter_get_vs_func get_vs,
1507 int x1, int y1, int x2, int y2,
1508 float depth, unsigned num_instances,
1509 enum blitter_attrib_type type,
1510 const union blitter_attrib *attrib)
1511 {
1512 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
1513 struct si_context *sctx = (struct si_context*)pipe;
1514
1515 /* Pack position coordinates as signed int16. */
1516 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
1517 ((uint32_t)(y1 & 0xffff) << 16);
1518 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
1519 ((uint32_t)(y2 & 0xffff) << 16);
1520 sctx->vs_blit_sh_data[2] = fui(depth);
1521
1522 switch (type) {
1523 case UTIL_BLITTER_ATTRIB_COLOR:
1524 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
1525 sizeof(float)*4);
1526 break;
1527 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
1528 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
1529 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
1530 sizeof(attrib->texcoord));
1531 break;
1532 case UTIL_BLITTER_ATTRIB_NONE:;
1533 }
1534
1535 pipe->bind_vs_state(pipe, si_get_blit_vs(sctx, type, num_instances));
1536
1537 struct pipe_draw_info info = {};
1538 info.mode = SI_PRIM_RECTANGLE_LIST;
1539 info.count = 3;
1540 info.instance_count = num_instances;
1541
1542 /* Don't set per-stage shader pointers for VS. */
1543 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
1544 sctx->vertex_buffer_pointer_dirty = false;
1545
1546 si_draw_vbo(pipe, &info);
1547 }
1548
1549 void si_trace_emit(struct si_context *sctx)
1550 {
1551 struct radeon_winsys_cs *cs = sctx->gfx_cs;
1552 uint64_t va = sctx->current_saved_cs->trace_buf->gpu_address;
1553 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
1554
1555 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1556 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1557 S_370_WR_CONFIRM(1) |
1558 S_370_ENGINE_SEL(V_370_ME));
1559 radeon_emit(cs, va);
1560 radeon_emit(cs, va >> 32);
1561 radeon_emit(cs, trace_id);
1562 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1563 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
1564
1565 if (sctx->log)
1566 u_log_flush(sctx->log);
1567 }