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radeonsi: don't always apply the PrimID instancing bug workaround on SI
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "radeon/r600_cs.h"
29 #include "sid.h"
30 #include "gfx9d.h"
31
32 #include "util/u_index_modify.h"
33 #include "util/u_log.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_prim.h"
36
37 #include "ac_debug.h"
38
39 static unsigned si_conv_pipe_prim(unsigned mode)
40 {
41 static const unsigned prim_conv[] = {
42 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
43 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
44 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
45 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
46 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
47 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
48 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
49 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
50 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
51 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
52 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
53 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
54 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
55 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
56 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
57 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
58 };
59 assert(mode < ARRAY_SIZE(prim_conv));
60 return prim_conv[mode];
61 }
62
63 static unsigned si_conv_prim_to_gs_out(unsigned mode)
64 {
65 static const int prim_conv[] = {
66 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
67 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
68 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
69 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
70 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
73 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
74 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
75 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
76 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
77 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
78 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
79 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
80 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
81 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
82 };
83 assert(mode < ARRAY_SIZE(prim_conv));
84
85 return prim_conv[mode];
86 }
87
88 /**
89 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
90 * LS.LDS_SIZE is shared by all 3 shader stages.
91 *
92 * The information about LDS and other non-compile-time parameters is then
93 * written to userdata SGPRs.
94 */
95 static void si_emit_derived_tess_state(struct si_context *sctx,
96 const struct pipe_draw_info *info,
97 unsigned *num_patches)
98 {
99 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
100 struct si_shader *ls_current;
101 struct si_shader_selector *ls;
102 /* The TES pointer will only be used for sctx->last_tcs.
103 * It would be wrong to think that TCS = TES. */
104 struct si_shader_selector *tcs =
105 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
106 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
107 bool has_primid_instancing_bug = sctx->b.chip_class == SI &&
108 sctx->b.screen->info.max_se == 1;
109 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
110 unsigned num_tcs_input_cp = info->vertices_per_patch;
111 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
112 unsigned num_tcs_patch_outputs;
113 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
114 unsigned input_patch_size, output_patch_size, output_patch0_offset;
115 unsigned perpatch_output_offset, lds_size;
116 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
117 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
118
119 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
120 if (sctx->b.chip_class >= GFX9) {
121 if (sctx->tcs_shader.cso)
122 ls_current = sctx->tcs_shader.current;
123 else
124 ls_current = sctx->fixed_func_tcs_shader.current;
125
126 ls = ls_current->key.part.tcs.ls;
127 } else {
128 ls_current = sctx->vs_shader.current;
129 ls = sctx->vs_shader.cso;
130 }
131
132 if (sctx->last_ls == ls_current &&
133 sctx->last_tcs == tcs &&
134 sctx->last_tes_sh_base == tes_sh_base &&
135 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
136 (!has_primid_instancing_bug ||
137 (sctx->last_tess_uses_primid == tess_uses_primid))) {
138 *num_patches = sctx->last_num_patches;
139 return;
140 }
141
142 sctx->last_ls = ls_current;
143 sctx->last_tcs = tcs;
144 sctx->last_tes_sh_base = tes_sh_base;
145 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
146 sctx->last_tess_uses_primid = tess_uses_primid;
147
148 /* This calculates how shader inputs and outputs among VS, TCS, and TES
149 * are laid out in LDS. */
150 num_tcs_inputs = util_last_bit64(ls->outputs_written);
151
152 if (sctx->tcs_shader.cso) {
153 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
154 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
155 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
156 } else {
157 /* No TCS. Route varyings from LS to TES. */
158 num_tcs_outputs = num_tcs_inputs;
159 num_tcs_output_cp = num_tcs_input_cp;
160 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
161 }
162
163 input_vertex_size = num_tcs_inputs * 16;
164 output_vertex_size = num_tcs_outputs * 16;
165
166 input_patch_size = num_tcs_input_cp * input_vertex_size;
167
168 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
169 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
170
171 /* Ensure that we only need one wave per SIMD so we don't need to check
172 * resource usage. Also ensures that the number of tcs in and out
173 * vertices per threadgroup are at most 256.
174 */
175 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
176
177 /* Make sure that the data fits in LDS. This assumes the shaders only
178 * use LDS for the inputs and outputs.
179 *
180 * While CIK can use 64K per threadgroup, there is a hang on Stoney
181 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
182 * uses 32K at most on all GCN chips.
183 */
184 hardware_lds_size = 32768;
185 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
186 output_patch_size));
187
188 /* Make sure the output data fits in the offchip buffer */
189 *num_patches = MIN2(*num_patches,
190 (sctx->screen->tess_offchip_block_dw_size * 4) /
191 output_patch_size);
192
193 /* Not necessary for correctness, but improves performance. The
194 * specific value is taken from the proprietary driver.
195 */
196 *num_patches = MIN2(*num_patches, 40);
197
198 if (sctx->b.chip_class == SI) {
199 /* SI bug workaround, related to power management. Limit LS-HS
200 * threadgroups to only one wave.
201 */
202 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
203 *num_patches = MIN2(*num_patches, one_wave);
204 }
205
206 /* The VGT HS block increments the patch ID unconditionally
207 * within a single threadgroup. This results in incorrect
208 * patch IDs when instanced draws are used.
209 *
210 * The intended solution is to restrict threadgroups to
211 * a single instance by setting SWITCH_ON_EOI, which
212 * should cause IA to split instances up. However, this
213 * doesn't work correctly on SI when there is no other
214 * SE to switch to.
215 */
216 if (has_primid_instancing_bug && tess_uses_primid)
217 *num_patches = 1;
218
219 sctx->last_num_patches = *num_patches;
220
221 output_patch0_offset = input_patch_size * *num_patches;
222 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
223
224 /* Compute userdata SGPRs. */
225 assert(((input_vertex_size / 4) & ~0xff) == 0);
226 assert(((output_vertex_size / 4) & ~0xff) == 0);
227 assert(((input_patch_size / 4) & ~0x1fff) == 0);
228 assert(((output_patch_size / 4) & ~0x1fff) == 0);
229 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
230 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
231 assert(num_tcs_input_cp <= 32);
232 assert(num_tcs_output_cp <= 32);
233
234 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
235 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
236 tcs_out_layout = (output_patch_size / 4) |
237 ((output_vertex_size / 4) << 13);
238 tcs_out_offsets = (output_patch0_offset / 16) |
239 ((perpatch_output_offset / 16) << 16);
240 offchip_layout = *num_patches |
241 (num_tcs_output_cp << 6) |
242 (pervertex_output_patch_size * *num_patches << 12);
243
244 /* Compute the LDS size. */
245 lds_size = output_patch0_offset + output_patch_size * *num_patches;
246
247 if (sctx->b.chip_class >= CIK) {
248 assert(lds_size <= 65536);
249 lds_size = align(lds_size, 512) / 512;
250 } else {
251 assert(lds_size <= 32768);
252 lds_size = align(lds_size, 256) / 256;
253 }
254
255 /* Set SI_SGPR_VS_STATE_BITS. */
256 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
257 C_VS_STATE_LS_OUT_VERTEX_SIZE;
258 sctx->current_vs_state |= tcs_in_layout;
259
260 if (sctx->b.chip_class >= GFX9) {
261 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
262 S_00B42C_LDS_SIZE(lds_size);
263
264 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
265
266 /* Set userdata SGPRs for merged LS-HS. */
267 radeon_set_sh_reg_seq(cs,
268 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
269 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
270 radeon_emit(cs, offchip_layout);
271 radeon_emit(cs, tcs_out_offsets);
272 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
273 } else {
274 unsigned ls_rsrc2 = ls_current->config.rsrc2;
275
276 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
277 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
278
279 /* Due to a hw bug, RSRC2_LS must be written twice with another
280 * LS register written in between. */
281 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
282 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
283 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
284 radeon_emit(cs, ls_current->config.rsrc1);
285 radeon_emit(cs, ls_rsrc2);
286
287 /* Set userdata SGPRs for TCS. */
288 radeon_set_sh_reg_seq(cs,
289 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
290 radeon_emit(cs, offchip_layout);
291 radeon_emit(cs, tcs_out_offsets);
292 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
293 radeon_emit(cs, tcs_in_layout);
294 }
295
296 /* Set userdata SGPRs for TES. */
297 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
298 radeon_emit(cs, offchip_layout);
299 radeon_emit(cs, r600_resource(sctx->tess_offchip_ring)->gpu_address >> 16);
300
301 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
302 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
303 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
304
305 if (sctx->b.chip_class >= CIK)
306 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
307 ls_hs_config);
308 else
309 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
310 ls_hs_config);
311 }
312
313 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
314 {
315 switch (info->mode) {
316 case PIPE_PRIM_PATCHES:
317 return info->count / info->vertices_per_patch;
318 case R600_PRIM_RECTANGLE_LIST:
319 return info->count / 3;
320 default:
321 return u_prims_for_vertices(info->mode, info->count);
322 }
323 }
324
325 static unsigned
326 si_get_init_multi_vgt_param(struct si_screen *sscreen,
327 union si_vgt_param_key *key)
328 {
329 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
330 unsigned max_primgroup_in_wave = 2;
331
332 /* SWITCH_ON_EOP(0) is always preferable. */
333 bool wd_switch_on_eop = false;
334 bool ia_switch_on_eop = false;
335 bool ia_switch_on_eoi = false;
336 bool partial_vs_wave = false;
337 bool partial_es_wave = false;
338
339 if (key->u.uses_tess) {
340 /* SWITCH_ON_EOI must be set if PrimID is used. */
341 if (key->u.tess_uses_prim_id)
342 ia_switch_on_eoi = true;
343
344 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
345 if ((sscreen->b.family == CHIP_TAHITI ||
346 sscreen->b.family == CHIP_PITCAIRN ||
347 sscreen->b.family == CHIP_BONAIRE) &&
348 key->u.uses_gs)
349 partial_vs_wave = true;
350
351 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
352 if (sscreen->has_distributed_tess) {
353 if (key->u.uses_gs) {
354 if (sscreen->b.chip_class <= VI)
355 partial_es_wave = true;
356
357 /* GPU hang workaround. */
358 if (sscreen->b.family == CHIP_TONGA ||
359 sscreen->b.family == CHIP_FIJI ||
360 sscreen->b.family == CHIP_POLARIS10 ||
361 sscreen->b.family == CHIP_POLARIS11 ||
362 sscreen->b.family == CHIP_POLARIS12)
363 partial_vs_wave = true;
364 } else {
365 partial_vs_wave = true;
366 }
367 }
368 }
369
370 /* This is a hardware requirement. */
371 if (key->u.line_stipple_enabled ||
372 (sscreen->b.debug_flags & DBG_SWITCH_ON_EOP)) {
373 ia_switch_on_eop = true;
374 wd_switch_on_eop = true;
375 }
376
377 if (sscreen->b.chip_class >= CIK) {
378 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
379 * 4 shader engines. Set 1 to pass the assertion below.
380 * The other cases are hardware requirements.
381 *
382 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
383 * for points, line strips, and tri strips.
384 */
385 if (sscreen->b.info.max_se < 4 ||
386 key->u.prim == PIPE_PRIM_POLYGON ||
387 key->u.prim == PIPE_PRIM_LINE_LOOP ||
388 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
389 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
390 (key->u.primitive_restart &&
391 (sscreen->b.family < CHIP_POLARIS10 ||
392 (key->u.prim != PIPE_PRIM_POINTS &&
393 key->u.prim != PIPE_PRIM_LINE_STRIP &&
394 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
395 key->u.count_from_stream_output)
396 wd_switch_on_eop = true;
397
398 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
399 * We don't know that for indirect drawing, so treat it as
400 * always problematic. */
401 if (sscreen->b.family == CHIP_HAWAII &&
402 key->u.uses_instancing)
403 wd_switch_on_eop = true;
404
405 /* Performance recommendation for 4 SE Gfx7-8 parts if
406 * instances are smaller than a primgroup.
407 * Assume indirect draws always use small instances.
408 * This is needed for good VS wave utilization.
409 */
410 if (sscreen->b.chip_class <= VI &&
411 sscreen->b.info.max_se == 4 &&
412 key->u.multi_instances_smaller_than_primgroup)
413 wd_switch_on_eop = true;
414
415 /* Required on CIK and later. */
416 if (sscreen->b.info.max_se > 2 && !wd_switch_on_eop)
417 ia_switch_on_eoi = true;
418
419 /* Required by Hawaii and, for some special cases, by VI. */
420 if (ia_switch_on_eoi &&
421 (sscreen->b.family == CHIP_HAWAII ||
422 (sscreen->b.chip_class == VI &&
423 (key->u.uses_gs || max_primgroup_in_wave != 2))))
424 partial_vs_wave = true;
425
426 /* Instancing bug on Bonaire. */
427 if (sscreen->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
428 key->u.uses_instancing)
429 partial_vs_wave = true;
430
431 /* If the WD switch is false, the IA switch must be false too. */
432 assert(wd_switch_on_eop || !ia_switch_on_eop);
433 }
434
435 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
436 if (sscreen->b.chip_class <= VI && ia_switch_on_eoi)
437 partial_es_wave = true;
438
439 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
440 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
441 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
442 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
443 S_028AA8_WD_SWITCH_ON_EOP(sscreen->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
444 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
445 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->b.chip_class == VI ?
446 max_primgroup_in_wave : 0) |
447 S_030960_EN_INST_OPT_BASIC(sscreen->b.chip_class >= GFX9) |
448 S_030960_EN_INST_OPT_ADV(sscreen->b.chip_class >= GFX9);
449 }
450
451 void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
452 {
453 for (int prim = 0; prim <= R600_PRIM_RECTANGLE_LIST; prim++)
454 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
455 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
456 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
457 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
458 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
459 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
460 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
461 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
462 union si_vgt_param_key key;
463
464 key.index = 0;
465 key.u.prim = prim;
466 key.u.uses_instancing = uses_instancing;
467 key.u.multi_instances_smaller_than_primgroup = multi_instances;
468 key.u.primitive_restart = primitive_restart;
469 key.u.count_from_stream_output = count_from_so;
470 key.u.line_stipple_enabled = line_stipple;
471 key.u.uses_tess = uses_tess;
472 key.u.tess_uses_prim_id = tess_uses_primid;
473 key.u.uses_gs = uses_gs;
474
475 sctx->ia_multi_vgt_param[key.index] =
476 si_get_init_multi_vgt_param(sctx->screen, &key);
477 }
478 }
479
480 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
481 const struct pipe_draw_info *info,
482 unsigned num_patches)
483 {
484 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
485 unsigned primgroup_size;
486 unsigned ia_multi_vgt_param;
487
488 if (sctx->tes_shader.cso) {
489 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
490 } else if (sctx->gs_shader.cso) {
491 primgroup_size = 64; /* recommended with a GS */
492 } else {
493 primgroup_size = 128; /* recommended without a GS and tess */
494 }
495
496 key.u.prim = info->mode;
497 key.u.uses_instancing = info->indirect || info->instance_count > 1;
498 key.u.multi_instances_smaller_than_primgroup =
499 info->indirect ||
500 (info->instance_count > 1 &&
501 (info->count_from_stream_output ||
502 si_num_prims_for_vertices(info) < primgroup_size));
503 key.u.primitive_restart = info->primitive_restart;
504 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
505
506 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
507 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
508
509 if (sctx->gs_shader.cso) {
510 /* GS requirement. */
511 if (sctx->b.chip_class <= VI &&
512 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
513 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
514
515 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
516 * The hw doc says all multi-SE chips are affected, but Vulkan
517 * only applies it to Hawaii. Do what Vulkan does.
518 */
519 if (sctx->b.family == CHIP_HAWAII &&
520 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
521 (info->indirect ||
522 (info->instance_count > 1 &&
523 (info->count_from_stream_output ||
524 si_num_prims_for_vertices(info) <= 1))))
525 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
526 }
527
528 return ia_multi_vgt_param;
529 }
530
531 /* rast_prim is the primitive type after GS. */
532 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
533 {
534 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
535 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
536 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
537
538 /* Skip this if not rendering lines. */
539 if (rast_prim != PIPE_PRIM_LINES &&
540 rast_prim != PIPE_PRIM_LINE_LOOP &&
541 rast_prim != PIPE_PRIM_LINE_STRIP &&
542 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
543 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
544 return;
545
546 if (rast_prim == sctx->last_rast_prim &&
547 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
548 return;
549
550 /* For lines, reset the stipple pattern at each primitive. Otherwise,
551 * reset the stipple pattern at each packet (line strips, line loops).
552 */
553 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
554 rs->pa_sc_line_stipple |
555 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
556
557 sctx->last_rast_prim = rast_prim;
558 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
559 }
560
561 static void si_emit_vs_state(struct si_context *sctx,
562 const struct pipe_draw_info *info)
563 {
564 sctx->current_vs_state &= C_VS_STATE_INDEXED;
565 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
566
567 if (sctx->current_vs_state != sctx->last_vs_state) {
568 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
569
570 radeon_set_sh_reg(cs,
571 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
572 SI_SGPR_VS_STATE_BITS * 4,
573 sctx->current_vs_state);
574
575 sctx->last_vs_state = sctx->current_vs_state;
576 }
577 }
578
579 static void si_emit_draw_registers(struct si_context *sctx,
580 const struct pipe_draw_info *info,
581 unsigned num_patches)
582 {
583 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
584 unsigned prim = si_conv_pipe_prim(info->mode);
585 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
586 unsigned ia_multi_vgt_param;
587
588 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
589
590 /* Draw state. */
591 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
592 if (sctx->b.chip_class >= GFX9)
593 radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
594 else if (sctx->b.chip_class >= CIK)
595 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
596 else
597 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
598
599 sctx->last_multi_vgt_param = ia_multi_vgt_param;
600 }
601 if (prim != sctx->last_prim) {
602 if (sctx->b.chip_class >= CIK)
603 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
604 else
605 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
606
607 sctx->last_prim = prim;
608 }
609
610 if (gs_out_prim != sctx->last_gs_out_prim) {
611 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
612 sctx->last_gs_out_prim = gs_out_prim;
613 }
614
615 /* Primitive restart. */
616 if (info->primitive_restart != sctx->last_primitive_restart_en) {
617 if (sctx->b.chip_class >= GFX9)
618 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
619 info->primitive_restart);
620 else
621 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
622 info->primitive_restart);
623
624 sctx->last_primitive_restart_en = info->primitive_restart;
625
626 }
627 if (info->primitive_restart &&
628 (info->restart_index != sctx->last_restart_index ||
629 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
630 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
631 info->restart_index);
632 sctx->last_restart_index = info->restart_index;
633 }
634 }
635
636 static void si_emit_draw_packets(struct si_context *sctx,
637 const struct pipe_draw_info *info,
638 struct pipe_resource *indexbuf,
639 unsigned index_size,
640 unsigned index_offset)
641 {
642 struct pipe_draw_indirect_info *indirect = info->indirect;
643 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
644 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
645 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
646 uint32_t index_max_size = 0;
647 uint64_t index_va = 0;
648
649 if (info->count_from_stream_output) {
650 struct r600_so_target *t =
651 (struct r600_so_target*)info->count_from_stream_output;
652 uint64_t va = t->buf_filled_size->gpu_address +
653 t->buf_filled_size_offset;
654
655 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
656 t->stride_in_dw);
657
658 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
659 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
660 COPY_DATA_DST_SEL(COPY_DATA_REG) |
661 COPY_DATA_WR_CONFIRM);
662 radeon_emit(cs, va); /* src address lo */
663 radeon_emit(cs, va >> 32); /* src address hi */
664 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
665 radeon_emit(cs, 0); /* unused */
666
667 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
668 t->buf_filled_size, RADEON_USAGE_READ,
669 RADEON_PRIO_SO_FILLED_SIZE);
670 }
671
672 /* draw packet */
673 if (index_size) {
674 if (index_size != sctx->last_index_size) {
675 unsigned index_type;
676
677 /* index type */
678 switch (index_size) {
679 case 1:
680 index_type = V_028A7C_VGT_INDEX_8;
681 break;
682 case 2:
683 index_type = V_028A7C_VGT_INDEX_16 |
684 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
685 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
686 break;
687 case 4:
688 index_type = V_028A7C_VGT_INDEX_32 |
689 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
690 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
691 break;
692 default:
693 assert(!"unreachable");
694 return;
695 }
696
697 if (sctx->b.chip_class >= GFX9) {
698 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
699 2, index_type);
700 } else {
701 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
702 radeon_emit(cs, index_type);
703 }
704
705 sctx->last_index_size = index_size;
706 }
707
708 index_max_size = (indexbuf->width0 - index_offset) /
709 index_size;
710 index_va = r600_resource(indexbuf)->gpu_address + index_offset;
711
712 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
713 (struct r600_resource *)indexbuf,
714 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
715 } else {
716 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
717 * so the state must be re-emitted before the next indexed draw.
718 */
719 if (sctx->b.chip_class >= CIK)
720 sctx->last_index_size = -1;
721 }
722
723 if (indirect) {
724 uint64_t indirect_va = r600_resource(indirect->buffer)->gpu_address;
725
726 assert(indirect_va % 8 == 0);
727
728 si_invalidate_draw_sh_constants(sctx);
729
730 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
731 radeon_emit(cs, 1);
732 radeon_emit(cs, indirect_va);
733 radeon_emit(cs, indirect_va >> 32);
734
735 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
736 (struct r600_resource *)indirect->buffer,
737 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
738
739 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
740 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
741
742 assert(indirect->offset % 4 == 0);
743
744 if (index_size) {
745 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
746 radeon_emit(cs, index_va);
747 radeon_emit(cs, index_va >> 32);
748
749 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
750 radeon_emit(cs, index_max_size);
751 }
752
753 if (!sctx->screen->has_draw_indirect_multi) {
754 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
755 : PKT3_DRAW_INDIRECT,
756 3, render_cond_bit));
757 radeon_emit(cs, indirect->offset);
758 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
759 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
760 radeon_emit(cs, di_src_sel);
761 } else {
762 uint64_t count_va = 0;
763
764 if (indirect->indirect_draw_count) {
765 struct r600_resource *params_buf =
766 (struct r600_resource *)indirect->indirect_draw_count;
767
768 radeon_add_to_buffer_list(
769 &sctx->b, &sctx->b.gfx, params_buf,
770 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
771
772 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
773 }
774
775 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
776 PKT3_DRAW_INDIRECT_MULTI,
777 8, render_cond_bit));
778 radeon_emit(cs, indirect->offset);
779 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
780 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
781 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
782 S_2C3_DRAW_INDEX_ENABLE(1) |
783 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
784 radeon_emit(cs, indirect->draw_count);
785 radeon_emit(cs, count_va);
786 radeon_emit(cs, count_va >> 32);
787 radeon_emit(cs, indirect->stride);
788 radeon_emit(cs, di_src_sel);
789 }
790 } else {
791 int base_vertex;
792
793 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
794 radeon_emit(cs, info->instance_count);
795
796 /* Base vertex and start instance. */
797 base_vertex = index_size ? info->index_bias : info->start;
798
799 if (base_vertex != sctx->last_base_vertex ||
800 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
801 info->start_instance != sctx->last_start_instance ||
802 info->drawid != sctx->last_drawid ||
803 sh_base_reg != sctx->last_sh_base_reg) {
804 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
805 radeon_emit(cs, base_vertex);
806 radeon_emit(cs, info->start_instance);
807 radeon_emit(cs, info->drawid);
808
809 sctx->last_base_vertex = base_vertex;
810 sctx->last_start_instance = info->start_instance;
811 sctx->last_drawid = info->drawid;
812 sctx->last_sh_base_reg = sh_base_reg;
813 }
814
815 if (index_size) {
816 index_va += info->start * index_size;
817
818 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
819 radeon_emit(cs, index_max_size);
820 radeon_emit(cs, index_va);
821 radeon_emit(cs, index_va >> 32);
822 radeon_emit(cs, info->count);
823 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
824 } else {
825 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
826 radeon_emit(cs, info->count);
827 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
828 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
829 }
830 }
831 }
832
833 static void si_emit_surface_sync(struct r600_common_context *rctx,
834 unsigned cp_coher_cntl)
835 {
836 struct radeon_winsys_cs *cs = rctx->gfx.cs;
837
838 if (rctx->chip_class >= GFX9) {
839 /* Flush caches and wait for the caches to assert idle. */
840 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
841 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
842 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
843 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
844 radeon_emit(cs, 0); /* CP_COHER_BASE */
845 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
846 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
847 } else {
848 /* ACQUIRE_MEM is only required on a compute ring. */
849 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
850 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
851 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
852 radeon_emit(cs, 0); /* CP_COHER_BASE */
853 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
854 }
855 }
856
857 void si_emit_cache_flush(struct si_context *sctx)
858 {
859 struct r600_common_context *rctx = &sctx->b;
860 struct radeon_winsys_cs *cs = rctx->gfx.cs;
861 uint32_t cp_coher_cntl = 0;
862 uint32_t flush_cb_db = rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
863 SI_CONTEXT_FLUSH_AND_INV_DB);
864
865 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB)
866 sctx->b.num_cb_cache_flushes++;
867 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB)
868 sctx->b.num_db_cache_flushes++;
869
870 /* SI has a bug that it always flushes ICACHE and KCACHE if either
871 * bit is set. An alternative way is to write SQC_CACHES, but that
872 * doesn't seem to work reliably. Since the bug doesn't affect
873 * correctness (it only does more work than necessary) and
874 * the performance impact is likely negligible, there is no plan
875 * to add a workaround for it.
876 */
877
878 if (rctx->flags & SI_CONTEXT_INV_ICACHE)
879 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
880 if (rctx->flags & SI_CONTEXT_INV_SMEM_L1)
881 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
882
883 if (rctx->chip_class <= VI) {
884 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
885 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
886 S_0085F0_CB0_DEST_BASE_ENA(1) |
887 S_0085F0_CB1_DEST_BASE_ENA(1) |
888 S_0085F0_CB2_DEST_BASE_ENA(1) |
889 S_0085F0_CB3_DEST_BASE_ENA(1) |
890 S_0085F0_CB4_DEST_BASE_ENA(1) |
891 S_0085F0_CB5_DEST_BASE_ENA(1) |
892 S_0085F0_CB6_DEST_BASE_ENA(1) |
893 S_0085F0_CB7_DEST_BASE_ENA(1);
894
895 /* Necessary for DCC */
896 if (rctx->chip_class == VI)
897 r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
898 0, EOP_DATA_SEL_DISCARD, NULL,
899 0, 0, R600_NOT_QUERY);
900 }
901 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB)
902 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
903 S_0085F0_DB_DEST_BASE_ENA(1);
904 }
905
906 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
907 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
908 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
909 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
910 }
911 if (rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
912 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
913 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
914 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
915 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
916 }
917
918 /* Wait for shader engines to go idle.
919 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
920 * for everything including CB/DB cache flushes.
921 */
922 if (!flush_cb_db) {
923 if (rctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
924 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
925 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
926 /* Only count explicit shader flushes, not implicit ones
927 * done by SURFACE_SYNC.
928 */
929 rctx->num_vs_flushes++;
930 rctx->num_ps_flushes++;
931 } else if (rctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
932 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
933 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
934 rctx->num_vs_flushes++;
935 }
936 }
937
938 if (rctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
939 sctx->compute_is_busy) {
940 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
941 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
942 rctx->num_cs_flushes++;
943 sctx->compute_is_busy = false;
944 }
945
946 /* VGT state synchronization. */
947 if (rctx->flags & SI_CONTEXT_VGT_FLUSH) {
948 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
949 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
950 }
951 if (rctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
952 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
953 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
954 }
955
956 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
957 * wait for idle on GFX9. We have to use a TS event.
958 */
959 if (sctx->b.chip_class >= GFX9 && flush_cb_db) {
960 uint64_t va;
961 unsigned tc_flags, cb_db_event;
962
963 /* Set the CB/DB flush event. */
964 switch (flush_cb_db) {
965 case SI_CONTEXT_FLUSH_AND_INV_CB:
966 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
967 break;
968 case SI_CONTEXT_FLUSH_AND_INV_DB:
969 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
970 break;
971 default:
972 /* both CB & DB */
973 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
974 }
975
976 /* These are the only allowed combinations. If you need to
977 * do multiple operations at once, do them separately.
978 * All operations that invalidate L2 also seem to invalidate
979 * metadata. Volatile (VOL) and WC flushes are not listed here.
980 *
981 * TC | TC_WB = writeback & invalidate L2 & L1
982 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
983 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
984 * TC | TC_NC = invalidate L2 for MTYPE == NC
985 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
986 * TCL1 = invalidate L1
987 */
988 tc_flags = 0;
989
990 if (rctx->flags & SI_CONTEXT_INV_L2_METADATA) {
991 tc_flags = EVENT_TC_ACTION_ENA |
992 EVENT_TC_MD_ACTION_ENA;
993 }
994
995 /* Ideally flush TC together with CB/DB. */
996 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
997 /* Writeback and invalidate everything in L2 & L1. */
998 tc_flags = EVENT_TC_ACTION_ENA |
999 EVENT_TC_WB_ACTION_ENA;
1000
1001 /* Clear the flags. */
1002 rctx->flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
1003 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
1004 SI_CONTEXT_INV_VMEM_L1);
1005 sctx->b.num_L2_invalidates++;
1006 }
1007
1008 /* Do the flush (enqueue the event and wait for it). */
1009 va = sctx->wait_mem_scratch->gpu_address;
1010 sctx->wait_mem_number++;
1011
1012 r600_gfx_write_event_eop(rctx, cb_db_event, tc_flags,
1013 EOP_DATA_SEL_VALUE_32BIT,
1014 sctx->wait_mem_scratch, va,
1015 sctx->wait_mem_number, R600_NOT_QUERY);
1016 r600_gfx_wait_fence(rctx, va, sctx->wait_mem_number, 0xffffffff);
1017 }
1018
1019 /* Make sure ME is idle (it executes most packets) before continuing.
1020 * This prevents read-after-write hazards between PFP and ME.
1021 */
1022 if (cp_coher_cntl ||
1023 (rctx->flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1024 SI_CONTEXT_INV_VMEM_L1 |
1025 SI_CONTEXT_INV_GLOBAL_L2 |
1026 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1027 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1028 radeon_emit(cs, 0);
1029 }
1030
1031 /* SI-CI-VI only:
1032 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1033 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1034 *
1035 * cp_coher_cntl should contain all necessary flags except TC flags
1036 * at this point.
1037 *
1038 * SI-CIK don't support L2 write-back.
1039 */
1040 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2 ||
1041 (rctx->chip_class <= CIK &&
1042 (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1043 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
1044 * WB must be set on VI+ when TC_ACTION is set.
1045 */
1046 si_emit_surface_sync(rctx, cp_coher_cntl |
1047 S_0085F0_TC_ACTION_ENA(1) |
1048 S_0085F0_TCL1_ACTION_ENA(1) |
1049 S_0301F0_TC_WB_ACTION_ENA(rctx->chip_class >= VI));
1050 cp_coher_cntl = 0;
1051 sctx->b.num_L2_invalidates++;
1052 } else {
1053 /* L1 invalidation and L2 writeback must be done separately,
1054 * because both operations can't be done together.
1055 */
1056 if (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
1057 /* WB = write-back
1058 * NC = apply to non-coherent MTYPEs
1059 * (i.e. MTYPE <= 1, which is what we use everywhere)
1060 *
1061 * WB doesn't work without NC.
1062 */
1063 si_emit_surface_sync(rctx, cp_coher_cntl |
1064 S_0301F0_TC_WB_ACTION_ENA(1) |
1065 S_0301F0_TC_NC_ACTION_ENA(1));
1066 cp_coher_cntl = 0;
1067 sctx->b.num_L2_writebacks++;
1068 }
1069 if (rctx->flags & SI_CONTEXT_INV_VMEM_L1) {
1070 /* Invalidate per-CU VMEM L1. */
1071 si_emit_surface_sync(rctx, cp_coher_cntl |
1072 S_0085F0_TCL1_ACTION_ENA(1));
1073 cp_coher_cntl = 0;
1074 }
1075 }
1076
1077 /* If TC flushes haven't cleared this... */
1078 if (cp_coher_cntl)
1079 si_emit_surface_sync(rctx, cp_coher_cntl);
1080
1081 if (rctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
1082 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1083 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1084 EVENT_INDEX(0));
1085 } else if (rctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
1086 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1087 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1088 EVENT_INDEX(0));
1089 }
1090
1091 rctx->flags = 0;
1092 }
1093
1094 static void si_get_draw_start_count(struct si_context *sctx,
1095 const struct pipe_draw_info *info,
1096 unsigned *start, unsigned *count)
1097 {
1098 struct pipe_draw_indirect_info *indirect = info->indirect;
1099
1100 if (indirect) {
1101 unsigned indirect_count;
1102 struct pipe_transfer *transfer;
1103 unsigned begin, end;
1104 unsigned map_size;
1105 unsigned *data;
1106
1107 if (indirect->indirect_draw_count) {
1108 data = pipe_buffer_map_range(&sctx->b.b,
1109 indirect->indirect_draw_count,
1110 indirect->indirect_draw_count_offset,
1111 sizeof(unsigned),
1112 PIPE_TRANSFER_READ, &transfer);
1113
1114 indirect_count = *data;
1115
1116 pipe_buffer_unmap(&sctx->b.b, transfer);
1117 } else {
1118 indirect_count = indirect->draw_count;
1119 }
1120
1121 if (!indirect_count) {
1122 *start = *count = 0;
1123 return;
1124 }
1125
1126 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1127 data = pipe_buffer_map_range(&sctx->b.b, indirect->buffer,
1128 indirect->offset, map_size,
1129 PIPE_TRANSFER_READ, &transfer);
1130
1131 begin = UINT_MAX;
1132 end = 0;
1133
1134 for (unsigned i = 0; i < indirect_count; ++i) {
1135 unsigned count = data[0];
1136 unsigned start = data[2];
1137
1138 if (count > 0) {
1139 begin = MIN2(begin, start);
1140 end = MAX2(end, start + count);
1141 }
1142
1143 data += indirect->stride / sizeof(unsigned);
1144 }
1145
1146 pipe_buffer_unmap(&sctx->b.b, transfer);
1147
1148 if (begin < end) {
1149 *start = begin;
1150 *count = end - begin;
1151 } else {
1152 *start = *count = 0;
1153 }
1154 } else {
1155 *start = info->start;
1156 *count = info->count;
1157 }
1158 }
1159
1160 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1161 unsigned skip_atom_mask)
1162 {
1163 /* Emit state atoms. */
1164 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1165 while (mask) {
1166 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
1167
1168 atom->emit(&sctx->b, atom);
1169 }
1170 sctx->dirty_atoms &= skip_atom_mask;
1171
1172 /* Emit states. */
1173 mask = sctx->dirty_states;
1174 while (mask) {
1175 unsigned i = u_bit_scan(&mask);
1176 struct si_pm4_state *state = sctx->queued.array[i];
1177
1178 if (!state || sctx->emitted.array[i] == state)
1179 continue;
1180
1181 si_pm4_emit(sctx, state);
1182 sctx->emitted.array[i] = state;
1183 }
1184 sctx->dirty_states = 0;
1185
1186 /* Emit draw states. */
1187 unsigned num_patches = 0;
1188
1189 si_emit_rasterizer_prim_state(sctx);
1190 if (sctx->tes_shader.cso)
1191 si_emit_derived_tess_state(sctx, info, &num_patches);
1192 si_emit_vs_state(sctx, info);
1193 si_emit_draw_registers(sctx, info, num_patches);
1194 }
1195
1196 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1197 {
1198 struct si_context *sctx = (struct si_context *)ctx;
1199 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1200 struct pipe_resource *indexbuf = info->index.resource;
1201 unsigned dirty_tex_counter;
1202 enum pipe_prim_type rast_prim;
1203 unsigned index_size = info->index_size;
1204 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1205
1206 if (likely(!info->indirect)) {
1207 /* SI-CI treat instance_count==0 as instance_count==1. There is
1208 * no workaround for indirect draws, but we can at least skip
1209 * direct draws.
1210 */
1211 if (unlikely(!info->instance_count))
1212 return;
1213
1214 /* Handle count == 0. */
1215 if (unlikely(!info->count &&
1216 (index_size || !info->count_from_stream_output)))
1217 return;
1218 }
1219
1220 if (unlikely(!sctx->vs_shader.cso)) {
1221 assert(0);
1222 return;
1223 }
1224 if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
1225 assert(0);
1226 return;
1227 }
1228 if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
1229 assert(0);
1230 return;
1231 }
1232
1233 /* Recompute and re-emit the texture resource states if needed. */
1234 dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_counter);
1235 if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_counter)) {
1236 sctx->b.last_dirty_tex_counter = dirty_tex_counter;
1237 sctx->framebuffer.dirty_cbufs |=
1238 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1239 sctx->framebuffer.dirty_zsbuf = true;
1240 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
1241 si_update_all_texture_descriptors(sctx);
1242 }
1243
1244 si_decompress_graphics_textures(sctx);
1245
1246 /* Set the rasterization primitive type.
1247 *
1248 * This must be done after si_decompress_textures, which can call
1249 * draw_vbo recursively, and before si_update_shaders, which uses
1250 * current_rast_prim for this draw_vbo call. */
1251 if (sctx->gs_shader.cso)
1252 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1253 else if (sctx->tes_shader.cso)
1254 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1255 else
1256 rast_prim = info->mode;
1257
1258 if (rast_prim != sctx->current_rast_prim) {
1259 sctx->current_rast_prim = rast_prim;
1260 sctx->do_update_shaders = true;
1261 }
1262
1263 if (sctx->tes_shader.cso &&
1264 (sctx->b.family == CHIP_VEGA10 || sctx->b.family == CHIP_RAVEN)) {
1265 /* Determine whether the LS VGPR fix should be applied.
1266 *
1267 * It is only required when num input CPs > num output CPs,
1268 * which cannot happen with the fixed function TCS. We should
1269 * also update this bit when switching from TCS to fixed
1270 * function TCS.
1271 */
1272 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1273 bool ls_vgpr_fix =
1274 tcs &&
1275 info->vertices_per_patch >
1276 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1277
1278 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1279 sctx->ls_vgpr_fix = ls_vgpr_fix;
1280 sctx->do_update_shaders = true;
1281 }
1282 }
1283
1284 if (sctx->gs_shader.cso) {
1285 /* Determine whether the GS triangle strip adjacency fix should
1286 * be applied. Rotate every other triangle if
1287 * - triangle strips with adjacency are fed to the GS and
1288 * - primitive restart is disabled (the rotation doesn't help
1289 * when the restart occurs after an odd number of triangles).
1290 */
1291 bool gs_tri_strip_adj_fix =
1292 !sctx->tes_shader.cso &&
1293 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1294 !info->primitive_restart;
1295
1296 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1297 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1298 sctx->do_update_shaders = true;
1299 }
1300 }
1301
1302 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1303 return;
1304
1305 if (index_size) {
1306 /* Translate or upload, if needed. */
1307 /* 8-bit indices are supported on VI. */
1308 if (sctx->b.chip_class <= CIK && index_size == 1) {
1309 unsigned start, count, start_offset, size, offset;
1310 void *ptr;
1311
1312 si_get_draw_start_count(sctx, info, &start, &count);
1313 start_offset = start * 2;
1314 size = count * 2;
1315
1316 indexbuf = NULL;
1317 u_upload_alloc(ctx->stream_uploader, start_offset,
1318 size,
1319 si_optimal_tcc_alignment(sctx, size),
1320 &offset, &indexbuf, &ptr);
1321 if (!indexbuf)
1322 return;
1323
1324 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, info, 0, 0,
1325 index_offset + start,
1326 count, ptr);
1327
1328 /* info->start will be added by the drawing code */
1329 index_offset = offset - start_offset;
1330 index_size = 2;
1331 } else if (info->has_user_indices) {
1332 unsigned start_offset;
1333
1334 assert(!info->indirect);
1335 start_offset = info->start * index_size;
1336
1337 indexbuf = NULL;
1338 u_upload_data(ctx->stream_uploader, start_offset,
1339 info->count * index_size,
1340 sctx->screen->b.info.tcc_cache_line_size,
1341 (char*)info->index.user + start_offset,
1342 &index_offset, &indexbuf);
1343 if (!indexbuf)
1344 return;
1345
1346 /* info->start will be added by the drawing code */
1347 index_offset -= start_offset;
1348 } else if (sctx->b.chip_class <= CIK &&
1349 r600_resource(indexbuf)->TC_L2_dirty) {
1350 /* VI reads index buffers through TC L2, so it doesn't
1351 * need this. */
1352 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1353 r600_resource(indexbuf)->TC_L2_dirty = false;
1354 }
1355 }
1356
1357 if (info->indirect) {
1358 struct pipe_draw_indirect_info *indirect = info->indirect;
1359
1360 /* Add the buffer size for memory checking in need_cs_space. */
1361 r600_context_add_resource_size(ctx, indirect->buffer);
1362
1363 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1364 if (sctx->b.chip_class <= VI) {
1365 if (r600_resource(indirect->buffer)->TC_L2_dirty) {
1366 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1367 r600_resource(indirect->buffer)->TC_L2_dirty = false;
1368 }
1369
1370 if (indirect->indirect_draw_count &&
1371 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1372 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1373 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1374 }
1375 }
1376 }
1377
1378 si_need_cs_space(sctx);
1379
1380 if (unlikely(sctx->b.log))
1381 si_log_draw_state(sctx, sctx->b.log);
1382
1383 /* Since we've called r600_context_add_resource_size for vertex buffers,
1384 * this must be called after si_need_cs_space, because we must let
1385 * need_cs_space flush before we add buffers to the buffer list.
1386 */
1387 if (!si_upload_vertex_buffer_descriptors(sctx))
1388 return;
1389
1390 /* GFX9 scissor bug workaround. This must be done before VPORT scissor
1391 * registers are changed. There is also a more efficient but more
1392 * involved alternative workaround.
1393 */
1394 if (sctx->b.chip_class == GFX9 &&
1395 si_is_atom_dirty(sctx, &sctx->b.scissors.atom)) {
1396 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
1397 si_emit_cache_flush(sctx);
1398 }
1399
1400 /* Use optimal packet order based on whether we need to sync the pipeline. */
1401 if (unlikely(sctx->b.flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1402 SI_CONTEXT_FLUSH_AND_INV_DB |
1403 SI_CONTEXT_PS_PARTIAL_FLUSH |
1404 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1405 /* If we have to wait for idle, set all states first, so that all
1406 * SET packets are processed in parallel with previous draw calls.
1407 * Then upload descriptors, set shader pointers, and draw, and
1408 * prefetch at the end. This ensures that the time the CUs
1409 * are idle is very short. (there are only SET_SH packets between
1410 * the wait and the draw)
1411 */
1412 struct r600_atom *shader_pointers = &sctx->shader_pointers.atom;
1413 unsigned masked_atoms = 1u << shader_pointers->id;
1414
1415 if (unlikely(sctx->b.flags & R600_CONTEXT_FLUSH_FOR_RENDER_COND))
1416 masked_atoms |= 1u << sctx->b.render_cond_atom.id;
1417
1418 /* Emit all states except shader pointers and render condition. */
1419 si_emit_all_states(sctx, info, masked_atoms);
1420 si_emit_cache_flush(sctx);
1421
1422 /* <-- CUs are idle here. */
1423 if (!si_upload_graphics_shader_descriptors(sctx))
1424 return;
1425
1426 /* Set shader pointers after descriptors are uploaded. */
1427 if (si_is_atom_dirty(sctx, shader_pointers))
1428 shader_pointers->emit(&sctx->b, NULL);
1429 if (si_is_atom_dirty(sctx, &sctx->b.render_cond_atom))
1430 sctx->b.render_cond_atom.emit(&sctx->b, NULL);
1431 sctx->dirty_atoms = 0;
1432
1433 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1434 /* <-- CUs are busy here. */
1435
1436 /* Start prefetches after the draw has been started. Both will run
1437 * in parallel, but starting the draw first is more important.
1438 */
1439 if (sctx->b.chip_class >= CIK && sctx->prefetch_L2_mask)
1440 cik_emit_prefetch_L2(sctx);
1441 } else {
1442 /* If we don't wait for idle, start prefetches first, then set
1443 * states, and draw at the end.
1444 */
1445 if (sctx->b.flags)
1446 si_emit_cache_flush(sctx);
1447
1448 if (sctx->b.chip_class >= CIK && sctx->prefetch_L2_mask)
1449 cik_emit_prefetch_L2(sctx);
1450
1451 if (!si_upload_graphics_shader_descriptors(sctx))
1452 return;
1453
1454 si_emit_all_states(sctx, info, 0);
1455 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1456 }
1457
1458 if (unlikely(sctx->current_saved_cs))
1459 si_trace_emit(sctx);
1460
1461 /* Workaround for a VGT hang when streamout is enabled.
1462 * It must be done after drawing. */
1463 if ((sctx->b.family == CHIP_HAWAII ||
1464 sctx->b.family == CHIP_TONGA ||
1465 sctx->b.family == CHIP_FIJI) &&
1466 r600_get_strmout_en(&sctx->b)) {
1467 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1468 }
1469
1470 if (unlikely(sctx->decompression_enabled)) {
1471 sctx->b.num_decompress_calls++;
1472 } else {
1473 sctx->b.num_draw_calls++;
1474 if (sctx->framebuffer.state.nr_cbufs > 1)
1475 sctx->b.num_mrt_draw_calls++;
1476 if (info->primitive_restart)
1477 sctx->b.num_prim_restart_calls++;
1478 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1479 sctx->b.num_spill_draw_calls++;
1480 }
1481 if (index_size && indexbuf != info->index.resource)
1482 pipe_resource_reference(&indexbuf, NULL);
1483 }
1484
1485 void si_trace_emit(struct si_context *sctx)
1486 {
1487 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1488 uint64_t va = sctx->current_saved_cs->trace_buf->gpu_address;
1489 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
1490
1491 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1492 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1493 S_370_WR_CONFIRM(1) |
1494 S_370_ENGINE_SEL(V_370_ME));
1495 radeon_emit(cs, va);
1496 radeon_emit(cs, va >> 32);
1497 radeon_emit(cs, trace_id);
1498 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1499 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
1500
1501 if (sctx->b.log)
1502 u_log_flush(sctx->b.log);
1503 }