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radeonsi/gfx10: emit GE_CNTL instead of IA_MULTI_VGT_PARAM for legacy mode
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32 #include "util/u_suballoc.h"
33
34 #include "ac_debug.h"
35
36 /* special primitive types */
37 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
38
39 static unsigned si_conv_pipe_prim(unsigned mode)
40 {
41 static const unsigned prim_conv[] = {
42 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
43 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
44 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
45 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
46 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
47 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
48 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
49 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
50 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
51 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
52 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
53 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
54 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
55 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
56 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
57 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
58 };
59 assert(mode < ARRAY_SIZE(prim_conv));
60 return prim_conv[mode];
61 }
62
63 /**
64 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
65 * LS.LDS_SIZE is shared by all 3 shader stages.
66 *
67 * The information about LDS and other non-compile-time parameters is then
68 * written to userdata SGPRs.
69 */
70 static void si_emit_derived_tess_state(struct si_context *sctx,
71 const struct pipe_draw_info *info,
72 unsigned *num_patches)
73 {
74 struct radeon_cmdbuf *cs = sctx->gfx_cs;
75 struct si_shader *ls_current;
76 struct si_shader_selector *ls;
77 /* The TES pointer will only be used for sctx->last_tcs.
78 * It would be wrong to think that TCS = TES. */
79 struct si_shader_selector *tcs =
80 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
81 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
82 bool has_primid_instancing_bug = sctx->chip_class == GFX6 &&
83 sctx->screen->info.max_se == 1;
84 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
85 unsigned num_tcs_input_cp = info->vertices_per_patch;
86 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
87 unsigned num_tcs_patch_outputs;
88 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
89 unsigned input_patch_size, output_patch_size, output_patch0_offset;
90 unsigned perpatch_output_offset, lds_size;
91 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
92 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
93
94 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
95 if (sctx->chip_class >= GFX9) {
96 if (sctx->tcs_shader.cso)
97 ls_current = sctx->tcs_shader.current;
98 else
99 ls_current = sctx->fixed_func_tcs_shader.current;
100
101 ls = ls_current->key.part.tcs.ls;
102 } else {
103 ls_current = sctx->vs_shader.current;
104 ls = sctx->vs_shader.cso;
105 }
106
107 if (sctx->last_ls == ls_current &&
108 sctx->last_tcs == tcs &&
109 sctx->last_tes_sh_base == tes_sh_base &&
110 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
111 (!has_primid_instancing_bug ||
112 (sctx->last_tess_uses_primid == tess_uses_primid))) {
113 *num_patches = sctx->last_num_patches;
114 return;
115 }
116
117 sctx->last_ls = ls_current;
118 sctx->last_tcs = tcs;
119 sctx->last_tes_sh_base = tes_sh_base;
120 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
121 sctx->last_tess_uses_primid = tess_uses_primid;
122
123 /* This calculates how shader inputs and outputs among VS, TCS, and TES
124 * are laid out in LDS. */
125 num_tcs_inputs = util_last_bit64(ls->outputs_written);
126
127 if (sctx->tcs_shader.cso) {
128 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
129 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
130 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
131 } else {
132 /* No TCS. Route varyings from LS to TES. */
133 num_tcs_outputs = num_tcs_inputs;
134 num_tcs_output_cp = num_tcs_input_cp;
135 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
136 }
137
138 input_vertex_size = ls->lshs_vertex_stride;
139 output_vertex_size = num_tcs_outputs * 16;
140
141 input_patch_size = num_tcs_input_cp * input_vertex_size;
142
143 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
144 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
145
146 /* Ensure that we only need one wave per SIMD so we don't need to check
147 * resource usage. Also ensures that the number of tcs in and out
148 * vertices per threadgroup are at most 256.
149 */
150 unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
151 *num_patches = 256 / max_verts_per_patch;
152
153 /* Make sure that the data fits in LDS. This assumes the shaders only
154 * use LDS for the inputs and outputs.
155 *
156 * While GFX7 can use 64K per threadgroup, there is a hang on Stoney
157 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
158 * uses 32K at most on all GCN chips.
159 */
160 hardware_lds_size = 32768;
161 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
162 output_patch_size));
163
164 /* Make sure the output data fits in the offchip buffer */
165 *num_patches = MIN2(*num_patches,
166 (sctx->screen->tess_offchip_block_dw_size * 4) /
167 output_patch_size);
168
169 /* Not necessary for correctness, but improves performance.
170 * The hardware can do more, but the radeonsi shader constant is
171 * limited to 6 bits.
172 */
173 *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */
174
175 /* When distributed tessellation is unsupported, switch between SEs
176 * at a higher frequency to compensate for it.
177 */
178 if (!sctx->screen->has_distributed_tess && sctx->screen->info.max_se > 1)
179 *num_patches = MIN2(*num_patches, 16); /* recommended */
180
181 /* Make sure that vector lanes are reasonably occupied. It probably
182 * doesn't matter much because this is LS-HS, and TES is likely to
183 * occupy significantly more CUs.
184 */
185 unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
186 if (temp_verts_per_tg > 64 && temp_verts_per_tg % 64 < 48)
187 *num_patches = (temp_verts_per_tg & ~63) / max_verts_per_patch;
188
189 if (sctx->chip_class == GFX6) {
190 /* GFX6 bug workaround, related to power management. Limit LS-HS
191 * threadgroups to only one wave.
192 */
193 unsigned one_wave = 64 / max_verts_per_patch;
194 *num_patches = MIN2(*num_patches, one_wave);
195 }
196
197 /* The VGT HS block increments the patch ID unconditionally
198 * within a single threadgroup. This results in incorrect
199 * patch IDs when instanced draws are used.
200 *
201 * The intended solution is to restrict threadgroups to
202 * a single instance by setting SWITCH_ON_EOI, which
203 * should cause IA to split instances up. However, this
204 * doesn't work correctly on GFX6 when there is no other
205 * SE to switch to.
206 */
207 if (has_primid_instancing_bug && tess_uses_primid)
208 *num_patches = 1;
209
210 sctx->last_num_patches = *num_patches;
211
212 output_patch0_offset = input_patch_size * *num_patches;
213 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
214
215 /* Compute userdata SGPRs. */
216 assert(((input_vertex_size / 4) & ~0xff) == 0);
217 assert(((output_vertex_size / 4) & ~0xff) == 0);
218 assert(((input_patch_size / 4) & ~0x1fff) == 0);
219 assert(((output_patch_size / 4) & ~0x1fff) == 0);
220 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
221 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
222 assert(num_tcs_input_cp <= 32);
223 assert(num_tcs_output_cp <= 32);
224
225 uint64_t ring_va = si_resource(sctx->tess_rings)->gpu_address;
226 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
227
228 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
229 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
230 tcs_out_layout = (output_patch_size / 4) |
231 (num_tcs_input_cp << 13) |
232 ring_va;
233 tcs_out_offsets = (output_patch0_offset / 16) |
234 ((perpatch_output_offset / 16) << 16);
235 offchip_layout = *num_patches |
236 (num_tcs_output_cp << 6) |
237 (pervertex_output_patch_size * *num_patches << 12);
238
239 /* Compute the LDS size. */
240 lds_size = output_patch0_offset + output_patch_size * *num_patches;
241
242 if (sctx->chip_class >= GFX7) {
243 assert(lds_size <= 65536);
244 lds_size = align(lds_size, 512) / 512;
245 } else {
246 assert(lds_size <= 32768);
247 lds_size = align(lds_size, 256) / 256;
248 }
249
250 /* Set SI_SGPR_VS_STATE_BITS. */
251 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
252 C_VS_STATE_LS_OUT_VERTEX_SIZE;
253 sctx->current_vs_state |= tcs_in_layout;
254
255 /* We should be able to support in-shader LDS use with LLVM >= 9
256 * by just adding the lds_sizes together, but it has never
257 * been tested. */
258 assert(ls_current->config.lds_size == 0);
259
260 if (sctx->chip_class >= GFX9) {
261 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
262 S_00B42C_LDS_SIZE_GFX9(lds_size);
263
264 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
265
266 /* Set userdata SGPRs for merged LS-HS. */
267 radeon_set_sh_reg_seq(cs,
268 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
269 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
270 radeon_emit(cs, offchip_layout);
271 radeon_emit(cs, tcs_out_offsets);
272 radeon_emit(cs, tcs_out_layout);
273 } else {
274 unsigned ls_rsrc2 = ls_current->config.rsrc2;
275
276 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
277 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
278
279 /* Due to a hw bug, RSRC2_LS must be written twice with another
280 * LS register written in between. */
281 if (sctx->chip_class == GFX7 && sctx->family != CHIP_HAWAII)
282 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
283 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
284 radeon_emit(cs, ls_current->config.rsrc1);
285 radeon_emit(cs, ls_rsrc2);
286
287 /* Set userdata SGPRs for TCS. */
288 radeon_set_sh_reg_seq(cs,
289 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
290 radeon_emit(cs, offchip_layout);
291 radeon_emit(cs, tcs_out_offsets);
292 radeon_emit(cs, tcs_out_layout);
293 radeon_emit(cs, tcs_in_layout);
294 }
295
296 /* Set userdata SGPRs for TES. */
297 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
298 radeon_emit(cs, offchip_layout);
299 radeon_emit(cs, ring_va);
300
301 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
302 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
303 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
304
305 if (sctx->last_ls_hs_config != ls_hs_config) {
306 if (sctx->chip_class >= GFX7) {
307 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
308 ls_hs_config);
309 } else {
310 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
311 ls_hs_config);
312 }
313 sctx->last_ls_hs_config = ls_hs_config;
314 sctx->context_roll = true;
315 }
316 }
317
318 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info,
319 enum pipe_prim_type prim)
320 {
321 switch (prim) {
322 case PIPE_PRIM_PATCHES:
323 return info->count / info->vertices_per_patch;
324 case PIPE_PRIM_POLYGON:
325 return info->count >= 3;
326 case SI_PRIM_RECTANGLE_LIST:
327 return info->count / 3;
328 default:
329 return u_decomposed_prims_for_vertices(prim, info->count);
330 }
331 }
332
333 static unsigned
334 si_get_init_multi_vgt_param(struct si_screen *sscreen,
335 union si_vgt_param_key *key)
336 {
337 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
338 unsigned max_primgroup_in_wave = 2;
339
340 /* SWITCH_ON_EOP(0) is always preferable. */
341 bool wd_switch_on_eop = false;
342 bool ia_switch_on_eop = false;
343 bool ia_switch_on_eoi = false;
344 bool partial_vs_wave = false;
345 bool partial_es_wave = false;
346
347 if (key->u.uses_tess) {
348 /* SWITCH_ON_EOI must be set if PrimID is used. */
349 if (key->u.tess_uses_prim_id)
350 ia_switch_on_eoi = true;
351
352 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
353 if ((sscreen->info.family == CHIP_TAHITI ||
354 sscreen->info.family == CHIP_PITCAIRN ||
355 sscreen->info.family == CHIP_BONAIRE) &&
356 key->u.uses_gs)
357 partial_vs_wave = true;
358
359 /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
360 if (sscreen->has_distributed_tess) {
361 if (key->u.uses_gs) {
362 if (sscreen->info.chip_class == GFX8)
363 partial_es_wave = true;
364 } else {
365 partial_vs_wave = true;
366 }
367 }
368 }
369
370 /* This is a hardware requirement. */
371 if (key->u.line_stipple_enabled ||
372 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
373 ia_switch_on_eop = true;
374 wd_switch_on_eop = true;
375 }
376
377 if (sscreen->info.chip_class >= GFX7) {
378 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
379 * 4 shader engines. Set 1 to pass the assertion below.
380 * The other cases are hardware requirements.
381 *
382 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
383 * for points, line strips, and tri strips.
384 */
385 if (sscreen->info.max_se <= 2 ||
386 key->u.prim == PIPE_PRIM_POLYGON ||
387 key->u.prim == PIPE_PRIM_LINE_LOOP ||
388 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
389 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
390 (key->u.primitive_restart &&
391 (sscreen->info.family < CHIP_POLARIS10 ||
392 (key->u.prim != PIPE_PRIM_POINTS &&
393 key->u.prim != PIPE_PRIM_LINE_STRIP &&
394 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
395 key->u.count_from_stream_output)
396 wd_switch_on_eop = true;
397
398 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
399 * We don't know that for indirect drawing, so treat it as
400 * always problematic. */
401 if (sscreen->info.family == CHIP_HAWAII &&
402 key->u.uses_instancing)
403 wd_switch_on_eop = true;
404
405 /* Performance recommendation for 4 SE Gfx7-8 parts if
406 * instances are smaller than a primgroup.
407 * Assume indirect draws always use small instances.
408 * This is needed for good VS wave utilization.
409 */
410 if (sscreen->info.chip_class <= GFX8 &&
411 sscreen->info.max_se == 4 &&
412 key->u.multi_instances_smaller_than_primgroup)
413 wd_switch_on_eop = true;
414
415 /* Required on GFX7 and later. */
416 if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
417 ia_switch_on_eoi = true;
418
419 /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
420 * to work around a GS hang.
421 */
422 if (key->u.uses_gs &&
423 (sscreen->info.family == CHIP_TONGA ||
424 sscreen->info.family == CHIP_FIJI ||
425 sscreen->info.family == CHIP_POLARIS10 ||
426 sscreen->info.family == CHIP_POLARIS11 ||
427 sscreen->info.family == CHIP_POLARIS12 ||
428 sscreen->info.family == CHIP_VEGAM))
429 partial_vs_wave = true;
430
431 /* Required by Hawaii and, for some special cases, by GFX8. */
432 if (ia_switch_on_eoi &&
433 (sscreen->info.family == CHIP_HAWAII ||
434 (sscreen->info.chip_class == GFX8 &&
435 (key->u.uses_gs || max_primgroup_in_wave != 2))))
436 partial_vs_wave = true;
437
438 /* Instancing bug on Bonaire. */
439 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
440 key->u.uses_instancing)
441 partial_vs_wave = true;
442
443 /* This only applies to Polaris10 and later 4 SE chips.
444 * wd_switch_on_eop is already true on all other chips.
445 */
446 if (!wd_switch_on_eop && key->u.primitive_restart)
447 partial_vs_wave = true;
448
449 /* If the WD switch is false, the IA switch must be false too. */
450 assert(wd_switch_on_eop || !ia_switch_on_eop);
451 }
452
453 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
454 if (sscreen->info.chip_class <= GFX8 && ia_switch_on_eoi)
455 partial_es_wave = true;
456
457 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
458 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
459 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
460 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
461 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= GFX7 ? wd_switch_on_eop : 0) |
462 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
463 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == GFX8 ?
464 max_primgroup_in_wave : 0) |
465 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
466 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
467 }
468
469 static void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
470 {
471 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
472 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
473 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
474 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
475 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
476 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
477 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
478 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
479 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
480 union si_vgt_param_key key;
481
482 key.index = 0;
483 key.u.prim = prim;
484 key.u.uses_instancing = uses_instancing;
485 key.u.multi_instances_smaller_than_primgroup = multi_instances;
486 key.u.primitive_restart = primitive_restart;
487 key.u.count_from_stream_output = count_from_so;
488 key.u.line_stipple_enabled = line_stipple;
489 key.u.uses_tess = uses_tess;
490 key.u.tess_uses_prim_id = tess_uses_primid;
491 key.u.uses_gs = uses_gs;
492
493 sctx->ia_multi_vgt_param[key.index] =
494 si_get_init_multi_vgt_param(sctx->screen, &key);
495 }
496 }
497
498 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
499 const struct pipe_draw_info *info,
500 enum pipe_prim_type prim,
501 unsigned num_patches,
502 unsigned instance_count,
503 bool primitive_restart)
504 {
505 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
506 unsigned primgroup_size;
507 unsigned ia_multi_vgt_param;
508
509 if (sctx->tes_shader.cso) {
510 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
511 } else if (sctx->gs_shader.cso) {
512 primgroup_size = 64; /* recommended with a GS */
513 } else {
514 primgroup_size = 128; /* recommended without a GS and tess */
515 }
516
517 key.u.prim = prim;
518 key.u.uses_instancing = info->indirect || instance_count > 1;
519 key.u.multi_instances_smaller_than_primgroup =
520 info->indirect ||
521 (instance_count > 1 &&
522 (info->count_from_stream_output ||
523 si_num_prims_for_vertices(info, prim) < primgroup_size));
524 key.u.primitive_restart = primitive_restart;
525 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
526
527 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
528 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
529
530 if (sctx->gs_shader.cso) {
531 /* GS requirement. */
532 if (sctx->chip_class <= GFX8 &&
533 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
534 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
535
536 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
537 * The hw doc says all multi-SE chips are affected, but Vulkan
538 * only applies it to Hawaii. Do what Vulkan does.
539 */
540 if (sctx->family == CHIP_HAWAII &&
541 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
542 (info->indirect ||
543 (instance_count > 1 &&
544 (info->count_from_stream_output ||
545 si_num_prims_for_vertices(info, prim) <= 1))))
546 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
547 }
548
549 return ia_multi_vgt_param;
550 }
551
552 /* rast_prim is the primitive type after GS. */
553 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
554 {
555 struct radeon_cmdbuf *cs = sctx->gfx_cs;
556 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
557 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
558
559 /* Skip this if not rendering lines. */
560 if (!util_prim_is_lines(rast_prim))
561 return;
562
563 if (rast_prim == sctx->last_rast_prim &&
564 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
565 return;
566
567 /* For lines, reset the stipple pattern at each primitive. Otherwise,
568 * reset the stipple pattern at each packet (line strips, line loops).
569 */
570 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
571 rs->pa_sc_line_stipple |
572 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
573
574 sctx->last_rast_prim = rast_prim;
575 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
576 sctx->context_roll = true;
577 }
578
579 static void si_emit_vs_state(struct si_context *sctx,
580 const struct pipe_draw_info *info)
581 {
582 sctx->current_vs_state &= C_VS_STATE_INDEXED;
583 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
584
585 if (sctx->num_vs_blit_sgprs) {
586 /* Re-emit the state after we leave u_blitter. */
587 sctx->last_vs_state = ~0;
588 return;
589 }
590
591 if (sctx->current_vs_state != sctx->last_vs_state) {
592 struct radeon_cmdbuf *cs = sctx->gfx_cs;
593
594 /* For the API vertex shader (VS_STATE_INDEXED). */
595 radeon_set_sh_reg(cs,
596 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
597 SI_SGPR_VS_STATE_BITS * 4,
598 sctx->current_vs_state);
599
600 /* For vertex color clamping, which is done in the last stage
601 * before the rasterizer. */
602 if (sctx->gs_shader.cso || sctx->tes_shader.cso) {
603 /* GS copy shader or TES if GS is missing. */
604 radeon_set_sh_reg(cs,
605 R_00B130_SPI_SHADER_USER_DATA_VS_0 +
606 SI_SGPR_VS_STATE_BITS * 4,
607 sctx->current_vs_state);
608 }
609
610 sctx->last_vs_state = sctx->current_vs_state;
611 }
612 }
613
614 static inline bool si_prim_restart_index_changed(struct si_context *sctx,
615 bool primitive_restart,
616 unsigned restart_index)
617 {
618 return primitive_restart &&
619 (restart_index != sctx->last_restart_index ||
620 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
621 }
622
623 static void si_emit_ia_multi_vgt_param(struct si_context *sctx,
624 const struct pipe_draw_info *info,
625 enum pipe_prim_type prim,
626 unsigned num_patches,
627 unsigned instance_count,
628 bool primitive_restart)
629 {
630 struct radeon_cmdbuf *cs = sctx->gfx_cs;
631 unsigned ia_multi_vgt_param;
632
633 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, prim, num_patches,
634 instance_count, primitive_restart);
635
636 /* Draw state. */
637 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
638 if (sctx->chip_class >= GFX9)
639 radeon_set_uconfig_reg_idx(cs, sctx->screen,
640 R_030960_IA_MULTI_VGT_PARAM, 4,
641 ia_multi_vgt_param);
642 else if (sctx->chip_class >= GFX7)
643 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
644 else
645 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
646
647 sctx->last_multi_vgt_param = ia_multi_vgt_param;
648 }
649 }
650
651 /* GFX10 removed IA_MULTI_VGT_PARAM in exchange for GE_CNTL.
652 * We overload last_multi_vgt_param.
653 */
654 static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches)
655 {
656 if (sctx->ngg)
657 return; /* set during PM4 emit */
658
659 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
660 unsigned primgroup_size;
661 unsigned vertgroup_size;
662
663 if (sctx->tes_shader.cso) {
664 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
665 vertgroup_size = 0;
666 } else if (sctx->gs_shader.cso) {
667 unsigned vgt_gs_onchip_cntl = sctx->gs_shader.current->ctx_reg.gs.vgt_gs_onchip_cntl;
668 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
669 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
670 } else {
671 primgroup_size = 128; /* recommended without a GS and tess */
672 vertgroup_size = 0;
673 }
674
675 unsigned ge_cntl =
676 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
677 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
678 S_03096C_PACKET_TO_ONE_PA(key.u.line_stipple_enabled) |
679 S_03096C_BREAK_WAVE_AT_EOI(key.u.uses_tess && key.u.tess_uses_prim_id);
680
681 if (ge_cntl != sctx->last_multi_vgt_param) {
682 radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, ge_cntl);
683 sctx->last_multi_vgt_param = ge_cntl;
684 }
685 }
686
687 static void si_emit_draw_registers(struct si_context *sctx,
688 const struct pipe_draw_info *info,
689 enum pipe_prim_type prim,
690 unsigned num_patches,
691 unsigned instance_count,
692 bool primitive_restart)
693 {
694 struct radeon_cmdbuf *cs = sctx->gfx_cs;
695 unsigned vgt_prim = si_conv_pipe_prim(info->mode);
696
697 if (sctx->chip_class >= GFX10)
698 gfx10_emit_ge_cntl(sctx, num_patches);
699 else
700 si_emit_ia_multi_vgt_param(sctx, info, prim, num_patches,
701 instance_count, primitive_restart);
702
703 if (vgt_prim != sctx->last_prim) {
704 if (sctx->chip_class >= GFX7)
705 radeon_set_uconfig_reg_idx(cs, sctx->screen,
706 R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
707 else
708 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);
709
710 sctx->last_prim = vgt_prim;
711 }
712
713 /* Primitive restart. */
714 if (primitive_restart != sctx->last_primitive_restart_en) {
715 if (sctx->chip_class >= GFX9)
716 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
717 primitive_restart);
718 else
719 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
720 primitive_restart);
721
722 sctx->last_primitive_restart_en = primitive_restart;
723
724 }
725 if (si_prim_restart_index_changed(sctx, primitive_restart, info->restart_index)) {
726 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
727 info->restart_index);
728 sctx->last_restart_index = info->restart_index;
729 sctx->context_roll = true;
730 }
731 }
732
733 static void si_emit_draw_packets(struct si_context *sctx,
734 const struct pipe_draw_info *info,
735 struct pipe_resource *indexbuf,
736 unsigned index_size,
737 unsigned index_offset,
738 unsigned instance_count,
739 bool dispatch_prim_discard_cs,
740 unsigned original_index_size)
741 {
742 struct pipe_draw_indirect_info *indirect = info->indirect;
743 struct radeon_cmdbuf *cs = sctx->gfx_cs;
744 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
745 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
746 uint32_t index_max_size = 0;
747 uint64_t index_va = 0;
748
749 if (info->count_from_stream_output) {
750 struct si_streamout_target *t =
751 (struct si_streamout_target*)info->count_from_stream_output;
752
753 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
754 t->stride_in_dw);
755 si_cp_copy_data(sctx, sctx->gfx_cs,
756 COPY_DATA_REG, NULL,
757 R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2,
758 COPY_DATA_SRC_MEM, t->buf_filled_size,
759 t->buf_filled_size_offset);
760 }
761
762 /* draw packet */
763 if (index_size) {
764 if (index_size != sctx->last_index_size) {
765 unsigned index_type;
766
767 /* index type */
768 switch (index_size) {
769 case 1:
770 index_type = V_028A7C_VGT_INDEX_8;
771 break;
772 case 2:
773 index_type = V_028A7C_VGT_INDEX_16 |
774 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
775 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
776 break;
777 case 4:
778 index_type = V_028A7C_VGT_INDEX_32 |
779 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
780 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
781 break;
782 default:
783 assert(!"unreachable");
784 return;
785 }
786
787 if (sctx->chip_class >= GFX9) {
788 radeon_set_uconfig_reg_idx(cs, sctx->screen,
789 R_03090C_VGT_INDEX_TYPE, 2,
790 index_type);
791 } else {
792 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
793 radeon_emit(cs, index_type);
794 }
795
796 sctx->last_index_size = index_size;
797 }
798
799 if (original_index_size) {
800 index_max_size = (indexbuf->width0 - index_offset) /
801 original_index_size;
802 index_va = si_resource(indexbuf)->gpu_address + index_offset;
803
804 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
805 si_resource(indexbuf),
806 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
807 }
808 } else {
809 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
810 * so the state must be re-emitted before the next indexed draw.
811 */
812 if (sctx->chip_class >= GFX7)
813 sctx->last_index_size = -1;
814 }
815
816 if (indirect) {
817 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address;
818
819 assert(indirect_va % 8 == 0);
820
821 si_invalidate_draw_sh_constants(sctx);
822
823 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
824 radeon_emit(cs, 1);
825 radeon_emit(cs, indirect_va);
826 radeon_emit(cs, indirect_va >> 32);
827
828 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
829 si_resource(indirect->buffer),
830 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
831
832 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
833 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
834
835 assert(indirect->offset % 4 == 0);
836
837 if (index_size) {
838 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
839 radeon_emit(cs, index_va);
840 radeon_emit(cs, index_va >> 32);
841
842 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
843 radeon_emit(cs, index_max_size);
844 }
845
846 if (!sctx->screen->has_draw_indirect_multi) {
847 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
848 : PKT3_DRAW_INDIRECT,
849 3, render_cond_bit));
850 radeon_emit(cs, indirect->offset);
851 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
852 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
853 radeon_emit(cs, di_src_sel);
854 } else {
855 uint64_t count_va = 0;
856
857 if (indirect->indirect_draw_count) {
858 struct si_resource *params_buf =
859 si_resource(indirect->indirect_draw_count);
860
861 radeon_add_to_buffer_list(
862 sctx, sctx->gfx_cs, params_buf,
863 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
864
865 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
866 }
867
868 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
869 PKT3_DRAW_INDIRECT_MULTI,
870 8, render_cond_bit));
871 radeon_emit(cs, indirect->offset);
872 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
873 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
874 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
875 S_2C3_DRAW_INDEX_ENABLE(1) |
876 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
877 radeon_emit(cs, indirect->draw_count);
878 radeon_emit(cs, count_va);
879 radeon_emit(cs, count_va >> 32);
880 radeon_emit(cs, indirect->stride);
881 radeon_emit(cs, di_src_sel);
882 }
883 } else {
884 int base_vertex;
885
886 if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
887 sctx->last_instance_count != instance_count) {
888 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
889 radeon_emit(cs, instance_count);
890 sctx->last_instance_count = instance_count;
891 }
892
893 /* Base vertex and start instance. */
894 base_vertex = original_index_size ? info->index_bias : info->start;
895
896 if (sctx->num_vs_blit_sgprs) {
897 /* Re-emit draw constants after we leave u_blitter. */
898 si_invalidate_draw_sh_constants(sctx);
899
900 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
901 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
902 sctx->num_vs_blit_sgprs);
903 radeon_emit_array(cs, sctx->vs_blit_sh_data,
904 sctx->num_vs_blit_sgprs);
905 } else if (base_vertex != sctx->last_base_vertex ||
906 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
907 info->start_instance != sctx->last_start_instance ||
908 info->drawid != sctx->last_drawid ||
909 sh_base_reg != sctx->last_sh_base_reg) {
910 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
911 radeon_emit(cs, base_vertex);
912 radeon_emit(cs, info->start_instance);
913 radeon_emit(cs, info->drawid);
914
915 sctx->last_base_vertex = base_vertex;
916 sctx->last_start_instance = info->start_instance;
917 sctx->last_drawid = info->drawid;
918 sctx->last_sh_base_reg = sh_base_reg;
919 }
920
921 if (index_size) {
922 if (dispatch_prim_discard_cs) {
923 index_va += info->start * original_index_size;
924 index_max_size = MIN2(index_max_size, info->count);
925
926 si_dispatch_prim_discard_cs_and_draw(sctx, info,
927 original_index_size,
928 base_vertex,
929 index_va, index_max_size);
930 return;
931 }
932
933 index_va += info->start * index_size;
934
935 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
936 radeon_emit(cs, index_max_size);
937 radeon_emit(cs, index_va);
938 radeon_emit(cs, index_va >> 32);
939 radeon_emit(cs, info->count);
940 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
941 } else {
942 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
943 radeon_emit(cs, info->count);
944 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
945 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
946 }
947 }
948 }
949
950 void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs,
951 unsigned cp_coher_cntl)
952 {
953 bool compute_ib = !sctx->has_graphics ||
954 cs == sctx->prim_discard_compute_cs;
955
956 if (sctx->chip_class >= GFX9 || compute_ib) {
957 /* Flush caches and wait for the caches to assert idle. */
958 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
959 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
960 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
961 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
962 radeon_emit(cs, 0); /* CP_COHER_BASE */
963 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
964 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
965 } else {
966 /* ACQUIRE_MEM is only required on a compute ring. */
967 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
968 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
969 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
970 radeon_emit(cs, 0); /* CP_COHER_BASE */
971 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
972 }
973
974 /* ACQUIRE_MEM has an implicit context roll if the current context
975 * is busy. */
976 if (!compute_ib)
977 sctx->context_roll = true;
978 }
979
980 void si_prim_discard_signal_next_compute_ib_start(struct si_context *sctx)
981 {
982 if (!si_compute_prim_discard_enabled(sctx))
983 return;
984
985 if (!sctx->barrier_buf) {
986 u_suballocator_alloc(sctx->allocator_zeroed_memory, 4, 4,
987 &sctx->barrier_buf_offset,
988 (struct pipe_resource**)&sctx->barrier_buf);
989 }
990
991 /* Emit a placeholder to signal the next compute IB to start.
992 * See si_compute_prim_discard.c for explanation.
993 */
994 uint32_t signal = 1;
995 si_cp_write_data(sctx, sctx->barrier_buf, sctx->barrier_buf_offset,
996 4, V_370_MEM, V_370_ME, &signal);
997
998 sctx->last_pkt3_write_data =
999 &sctx->gfx_cs->current.buf[sctx->gfx_cs->current.cdw - 5];
1000
1001 /* Only the last occurence of WRITE_DATA will be executed.
1002 * The packet will be enabled in si_flush_gfx_cs.
1003 */
1004 *sctx->last_pkt3_write_data = PKT3(PKT3_NOP, 3, 0);
1005 }
1006
1007 void gfx10_emit_cache_flush(struct si_context *ctx)
1008 {
1009 struct radeon_cmdbuf *cs = ctx->gfx_cs;
1010 uint32_t gcr_cntl = 0;
1011 unsigned cb_db_event = 0;
1012 unsigned flags = ctx->flags;
1013
1014 if (!ctx->has_graphics) {
1015 /* Only process compute flags. */
1016 flags &= SI_CONTEXT_INV_ICACHE |
1017 SI_CONTEXT_INV_SCACHE |
1018 SI_CONTEXT_INV_VCACHE |
1019 SI_CONTEXT_INV_L2 |
1020 SI_CONTEXT_WB_L2 |
1021 SI_CONTEXT_INV_L2_METADATA |
1022 SI_CONTEXT_CS_PARTIAL_FLUSH;
1023 }
1024
1025 /* We don't need these. */
1026 assert(!(flags & (SI_CONTEXT_VGT_FLUSH |
1027 SI_CONTEXT_VGT_STREAMOUT_SYNC |
1028 SI_CONTEXT_FLUSH_AND_INV_DB_META)));
1029
1030 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1031 ctx->num_cb_cache_flushes++;
1032 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1033 ctx->num_db_cache_flushes++;
1034
1035 if (flags & SI_CONTEXT_INV_ICACHE)
1036 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
1037 if (flags & SI_CONTEXT_INV_SCACHE) {
1038 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
1039 * to FORWARD when both L1 and L2 are written out (WB or INV).
1040 */
1041 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
1042 }
1043 if (flags & SI_CONTEXT_INV_VCACHE)
1044 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
1045 if (flags & SI_CONTEXT_INV_L2) {
1046 /* Writeback and invalidate everything in L2. */
1047 gcr_cntl |= S_586_GL2_INV(1) | S_586_GLM_INV(1);
1048 ctx->num_L2_invalidates++;
1049 } else if (flags & SI_CONTEXT_WB_L2) {
1050 /* Writeback but do not invalidate. */
1051 gcr_cntl |= S_586_GL2_WB(1);
1052 }
1053 if (flags & SI_CONTEXT_INV_L2_METADATA)
1054 gcr_cntl |= S_586_GLM_INV(1);
1055
1056 if (flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1057 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1058 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1059 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1060 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
1061 EVENT_INDEX(0));
1062 }
1063 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1064 /* Flush HTILE. Will wait for idle later. */
1065 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1066 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
1067 EVENT_INDEX(0));
1068 }
1069
1070 /* First flush CB/DB, then L1/L2. */
1071 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
1072
1073 if ((flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) ==
1074 (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1075 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1076 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1077 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1078 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1079 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1080 } else {
1081 assert(0);
1082 }
1083 } else {
1084 /* Wait for graphics shaders to go idle if requested. */
1085 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1086 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1087 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1088 /* Only count explicit shader flushes, not implicit ones. */
1089 ctx->num_vs_flushes++;
1090 ctx->num_ps_flushes++;
1091 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1092 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1093 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1094 ctx->num_vs_flushes++;
1095 }
1096 }
1097
1098 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH && ctx->compute_is_busy) {
1099 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1100 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
1101 ctx->num_cs_flushes++;
1102 ctx->compute_is_busy = false;
1103 }
1104
1105 if (cb_db_event) {
1106 /* CB/DB flush and invalidate (or possibly just a wait for a
1107 * meta flush) via RELEASE_MEM.
1108 *
1109 * Combine this with other cache flushes when possible; this
1110 * requires affected shaders to be idle, so do it after the
1111 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1112 * implied).
1113 */
1114 uint64_t va;
1115
1116 /* Do the flush (enqueue the event and wait for it). */
1117 va = ctx->wait_mem_scratch->gpu_address;
1118 ctx->wait_mem_number++;
1119
1120 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1121 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
1122 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
1123 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
1124 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
1125 assert(G_586_GL2_US(gcr_cntl) == 0);
1126 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
1127 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
1128 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
1129 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
1130 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
1131
1132 gcr_cntl &= C_586_GLM_WB &
1133 C_586_GLM_INV &
1134 C_586_GLV_INV &
1135 C_586_GL1_INV &
1136 C_586_GL2_INV &
1137 C_586_GL2_WB; /* keep SEQ */
1138
1139 si_cp_release_mem(ctx, cs, cb_db_event,
1140 S_490_GLM_WB(glm_wb) |
1141 S_490_GLM_INV(glm_inv) |
1142 S_490_GLV_INV(glv_inv) |
1143 S_490_GL1_INV(gl1_inv) |
1144 S_490_GL2_INV(gl2_inv) |
1145 S_490_GL2_WB(gl2_wb) |
1146 S_490_SEQ(gcr_seq),
1147 EOP_DST_SEL_MEM,
1148 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1149 EOP_DATA_SEL_VALUE_32BIT,
1150 ctx->wait_mem_scratch, va,
1151 ctx->wait_mem_number, SI_NOT_QUERY);
1152 si_cp_wait_mem(ctx, ctx->gfx_cs, va, ctx->wait_mem_number, 0xffffffff,
1153 WAIT_REG_MEM_EQUAL);
1154 }
1155
1156 /* Ignore fields that only modify the behavior of other fields. */
1157 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1158 /* Flush caches and wait for the caches to assert idle.
1159 * The cache flush is executed in the ME, but the PFP waits
1160 * for completion.
1161 */
1162 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1163 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1164 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1165 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1166 radeon_emit(cs, 0); /* CP_COHER_BASE */
1167 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1168 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1169 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1170 } else if (cb_db_event ||
1171 (flags & (SI_CONTEXT_VS_PARTIAL_FLUSH |
1172 SI_CONTEXT_PS_PARTIAL_FLUSH |
1173 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1174 /* We need to ensure that PFP waits as well. */
1175 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1176 radeon_emit(cs, 0);
1177 }
1178
1179 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1180 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1181 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1182 EVENT_INDEX(0));
1183 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1184 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1185 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1186 EVENT_INDEX(0));
1187 }
1188
1189 ctx->flags = 0;
1190 }
1191
1192 void si_emit_cache_flush(struct si_context *sctx)
1193 {
1194 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1195 uint32_t flags = sctx->flags;
1196
1197 if (!sctx->has_graphics) {
1198 /* Only process compute flags. */
1199 flags &= SI_CONTEXT_INV_ICACHE |
1200 SI_CONTEXT_INV_SCACHE |
1201 SI_CONTEXT_INV_VCACHE |
1202 SI_CONTEXT_INV_L2 |
1203 SI_CONTEXT_WB_L2 |
1204 SI_CONTEXT_INV_L2_METADATA |
1205 SI_CONTEXT_CS_PARTIAL_FLUSH;
1206 }
1207
1208 uint32_t cp_coher_cntl = 0;
1209 const uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1210 SI_CONTEXT_FLUSH_AND_INV_DB);
1211 const bool is_barrier = flush_cb_db ||
1212 /* INV_ICACHE == beginning of gfx IB. Checking
1213 * INV_ICACHE fixes corruption for DeusExMD with
1214 * compute-based culling, but I don't know why.
1215 */
1216 flags & (SI_CONTEXT_INV_ICACHE |
1217 SI_CONTEXT_PS_PARTIAL_FLUSH |
1218 SI_CONTEXT_VS_PARTIAL_FLUSH) ||
1219 (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1220 sctx->compute_is_busy);
1221
1222 assert(sctx->chip_class <= GFX9);
1223
1224 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1225 sctx->num_cb_cache_flushes++;
1226 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1227 sctx->num_db_cache_flushes++;
1228
1229 /* GFX6 has a bug that it always flushes ICACHE and KCACHE if either
1230 * bit is set. An alternative way is to write SQC_CACHES, but that
1231 * doesn't seem to work reliably. Since the bug doesn't affect
1232 * correctness (it only does more work than necessary) and
1233 * the performance impact is likely negligible, there is no plan
1234 * to add a workaround for it.
1235 */
1236
1237 if (flags & SI_CONTEXT_INV_ICACHE)
1238 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1239 if (flags & SI_CONTEXT_INV_SCACHE)
1240 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1241
1242 if (sctx->chip_class <= GFX8) {
1243 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1244 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1245 S_0085F0_CB0_DEST_BASE_ENA(1) |
1246 S_0085F0_CB1_DEST_BASE_ENA(1) |
1247 S_0085F0_CB2_DEST_BASE_ENA(1) |
1248 S_0085F0_CB3_DEST_BASE_ENA(1) |
1249 S_0085F0_CB4_DEST_BASE_ENA(1) |
1250 S_0085F0_CB5_DEST_BASE_ENA(1) |
1251 S_0085F0_CB6_DEST_BASE_ENA(1) |
1252 S_0085F0_CB7_DEST_BASE_ENA(1);
1253
1254 /* Necessary for DCC */
1255 if (sctx->chip_class == GFX8)
1256 si_cp_release_mem(sctx, cs,
1257 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1258 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
1259 EOP_DATA_SEL_DISCARD, NULL,
1260 0, 0, SI_NOT_QUERY);
1261 }
1262 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1263 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1264 S_0085F0_DB_DEST_BASE_ENA(1);
1265 }
1266
1267 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1268 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
1269 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1270 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1271 }
1272 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
1273 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
1274 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
1275 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1276 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1277 }
1278
1279 /* Wait for shader engines to go idle.
1280 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
1281 * for everything including CB/DB cache flushes.
1282 */
1283 if (!flush_cb_db) {
1284 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1285 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1286 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1287 /* Only count explicit shader flushes, not implicit ones
1288 * done by SURFACE_SYNC.
1289 */
1290 sctx->num_vs_flushes++;
1291 sctx->num_ps_flushes++;
1292 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1293 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1294 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1295 sctx->num_vs_flushes++;
1296 }
1297 }
1298
1299 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1300 sctx->compute_is_busy) {
1301 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1302 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1303 sctx->num_cs_flushes++;
1304 sctx->compute_is_busy = false;
1305 }
1306
1307 /* VGT state synchronization. */
1308 if (flags & SI_CONTEXT_VGT_FLUSH) {
1309 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1310 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1311 }
1312 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
1313 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1314 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1315 }
1316
1317 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
1318 * wait for idle on GFX9. We have to use a TS event.
1319 */
1320 if (sctx->chip_class >= GFX9 && flush_cb_db) {
1321 uint64_t va;
1322 unsigned tc_flags, cb_db_event;
1323
1324 /* Set the CB/DB flush event. */
1325 switch (flush_cb_db) {
1326 case SI_CONTEXT_FLUSH_AND_INV_CB:
1327 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1328 break;
1329 case SI_CONTEXT_FLUSH_AND_INV_DB:
1330 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1331 break;
1332 default:
1333 /* both CB & DB */
1334 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1335 }
1336
1337 /* These are the only allowed combinations. If you need to
1338 * do multiple operations at once, do them separately.
1339 * All operations that invalidate L2 also seem to invalidate
1340 * metadata. Volatile (VOL) and WC flushes are not listed here.
1341 *
1342 * TC | TC_WB = writeback & invalidate L2 & L1
1343 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1344 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1345 * TC | TC_NC = invalidate L2 for MTYPE == NC
1346 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1347 * TCL1 = invalidate L1
1348 */
1349 tc_flags = 0;
1350
1351 if (flags & SI_CONTEXT_INV_L2_METADATA) {
1352 tc_flags = EVENT_TC_ACTION_ENA |
1353 EVENT_TC_MD_ACTION_ENA;
1354 }
1355
1356 /* Ideally flush TC together with CB/DB. */
1357 if (flags & SI_CONTEXT_INV_L2) {
1358 /* Writeback and invalidate everything in L2 & L1. */
1359 tc_flags = EVENT_TC_ACTION_ENA |
1360 EVENT_TC_WB_ACTION_ENA;
1361
1362 /* Clear the flags. */
1363 flags &= ~(SI_CONTEXT_INV_L2 |
1364 SI_CONTEXT_WB_L2 |
1365 SI_CONTEXT_INV_VCACHE);
1366 sctx->num_L2_invalidates++;
1367 }
1368
1369 /* Do the flush (enqueue the event and wait for it). */
1370 va = sctx->wait_mem_scratch->gpu_address;
1371 sctx->wait_mem_number++;
1372
1373 si_cp_release_mem(sctx, cs, cb_db_event, tc_flags,
1374 EOP_DST_SEL_MEM,
1375 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1376 EOP_DATA_SEL_VALUE_32BIT,
1377 sctx->wait_mem_scratch, va,
1378 sctx->wait_mem_number, SI_NOT_QUERY);
1379 si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff,
1380 WAIT_REG_MEM_EQUAL);
1381 }
1382
1383 /* Make sure ME is idle (it executes most packets) before continuing.
1384 * This prevents read-after-write hazards between PFP and ME.
1385 */
1386 if (sctx->has_graphics &&
1387 (cp_coher_cntl ||
1388 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1389 SI_CONTEXT_INV_VCACHE |
1390 SI_CONTEXT_INV_L2 |
1391 SI_CONTEXT_WB_L2)))) {
1392 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1393 radeon_emit(cs, 0);
1394 }
1395
1396 /* GFX6-GFX8 only:
1397 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1398 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1399 *
1400 * cp_coher_cntl should contain all necessary flags except TC flags
1401 * at this point.
1402 *
1403 * GFX6-GFX7 don't support L2 write-back.
1404 */
1405 if (flags & SI_CONTEXT_INV_L2 ||
1406 (sctx->chip_class <= GFX7 &&
1407 (flags & SI_CONTEXT_WB_L2))) {
1408 /* Invalidate L1 & L2. (L1 is always invalidated on GFX6)
1409 * WB must be set on GFX8+ when TC_ACTION is set.
1410 */
1411 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1412 S_0085F0_TC_ACTION_ENA(1) |
1413 S_0085F0_TCL1_ACTION_ENA(1) |
1414 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= GFX8));
1415 cp_coher_cntl = 0;
1416 sctx->num_L2_invalidates++;
1417 } else {
1418 /* L1 invalidation and L2 writeback must be done separately,
1419 * because both operations can't be done together.
1420 */
1421 if (flags & SI_CONTEXT_WB_L2) {
1422 /* WB = write-back
1423 * NC = apply to non-coherent MTYPEs
1424 * (i.e. MTYPE <= 1, which is what we use everywhere)
1425 *
1426 * WB doesn't work without NC.
1427 */
1428 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1429 S_0301F0_TC_WB_ACTION_ENA(1) |
1430 S_0301F0_TC_NC_ACTION_ENA(1));
1431 cp_coher_cntl = 0;
1432 sctx->num_L2_writebacks++;
1433 }
1434 if (flags & SI_CONTEXT_INV_VCACHE) {
1435 /* Invalidate per-CU VMEM L1. */
1436 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1437 S_0085F0_TCL1_ACTION_ENA(1));
1438 cp_coher_cntl = 0;
1439 }
1440 }
1441
1442 /* If TC flushes haven't cleared this... */
1443 if (cp_coher_cntl)
1444 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl);
1445
1446 if (is_barrier)
1447 si_prim_discard_signal_next_compute_ib_start(sctx);
1448
1449 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1450 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1451 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1452 EVENT_INDEX(0));
1453 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1454 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1455 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1456 EVENT_INDEX(0));
1457 }
1458
1459 sctx->flags = 0;
1460 }
1461
1462 static void si_get_draw_start_count(struct si_context *sctx,
1463 const struct pipe_draw_info *info,
1464 unsigned *start, unsigned *count)
1465 {
1466 struct pipe_draw_indirect_info *indirect = info->indirect;
1467
1468 if (indirect) {
1469 unsigned indirect_count;
1470 struct pipe_transfer *transfer;
1471 unsigned begin, end;
1472 unsigned map_size;
1473 unsigned *data;
1474
1475 if (indirect->indirect_draw_count) {
1476 data = pipe_buffer_map_range(&sctx->b,
1477 indirect->indirect_draw_count,
1478 indirect->indirect_draw_count_offset,
1479 sizeof(unsigned),
1480 PIPE_TRANSFER_READ, &transfer);
1481
1482 indirect_count = *data;
1483
1484 pipe_buffer_unmap(&sctx->b, transfer);
1485 } else {
1486 indirect_count = indirect->draw_count;
1487 }
1488
1489 if (!indirect_count) {
1490 *start = *count = 0;
1491 return;
1492 }
1493
1494 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1495 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1496 indirect->offset, map_size,
1497 PIPE_TRANSFER_READ, &transfer);
1498
1499 begin = UINT_MAX;
1500 end = 0;
1501
1502 for (unsigned i = 0; i < indirect_count; ++i) {
1503 unsigned count = data[0];
1504 unsigned start = data[2];
1505
1506 if (count > 0) {
1507 begin = MIN2(begin, start);
1508 end = MAX2(end, start + count);
1509 }
1510
1511 data += indirect->stride / sizeof(unsigned);
1512 }
1513
1514 pipe_buffer_unmap(&sctx->b, transfer);
1515
1516 if (begin < end) {
1517 *start = begin;
1518 *count = end - begin;
1519 } else {
1520 *start = *count = 0;
1521 }
1522 } else {
1523 *start = info->start;
1524 *count = info->count;
1525 }
1526 }
1527
1528 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1529 enum pipe_prim_type prim, unsigned instance_count,
1530 bool primitive_restart, unsigned skip_atom_mask)
1531 {
1532 unsigned num_patches = 0;
1533
1534 si_emit_rasterizer_prim_state(sctx);
1535 if (sctx->tes_shader.cso)
1536 si_emit_derived_tess_state(sctx, info, &num_patches);
1537
1538 /* Emit state atoms. */
1539 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1540 while (mask)
1541 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1542
1543 sctx->dirty_atoms &= skip_atom_mask;
1544
1545 /* Emit states. */
1546 mask = sctx->dirty_states;
1547 while (mask) {
1548 unsigned i = u_bit_scan(&mask);
1549 struct si_pm4_state *state = sctx->queued.array[i];
1550
1551 if (!state || sctx->emitted.array[i] == state)
1552 continue;
1553
1554 si_pm4_emit(sctx, state);
1555 sctx->emitted.array[i] = state;
1556 }
1557 sctx->dirty_states = 0;
1558
1559 /* Emit draw states. */
1560 si_emit_vs_state(sctx, info);
1561 si_emit_draw_registers(sctx, info, prim, num_patches, instance_count,
1562 primitive_restart);
1563 }
1564
1565 static bool
1566 si_all_vs_resources_read_only(struct si_context *sctx,
1567 struct pipe_resource *indexbuf)
1568 {
1569 struct radeon_winsys *ws = sctx->ws;
1570 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1571
1572 /* Index buffer. */
1573 if (indexbuf &&
1574 ws->cs_is_buffer_referenced(cs, si_resource(indexbuf)->buf,
1575 RADEON_USAGE_WRITE))
1576 goto has_write_reference;
1577
1578 /* Vertex buffers. */
1579 struct si_vertex_elements *velems = sctx->vertex_elements;
1580 unsigned num_velems = velems->count;
1581
1582 for (unsigned i = 0; i < num_velems; i++) {
1583 if (!((1 << i) & velems->first_vb_use_mask))
1584 continue;
1585
1586 unsigned vb_index = velems->vertex_buffer_index[i];
1587 struct pipe_resource *res = sctx->vertex_buffer[vb_index].buffer.resource;
1588 if (!res)
1589 continue;
1590
1591 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1592 RADEON_USAGE_WRITE))
1593 goto has_write_reference;
1594 }
1595
1596 /* Constant and shader buffers. */
1597 struct si_descriptors *buffers =
1598 &sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_VERTEX)];
1599 for (unsigned i = 0; i < buffers->num_active_slots; i++) {
1600 unsigned index = buffers->first_active_slot + i;
1601 struct pipe_resource *res =
1602 sctx->const_and_shader_buffers[PIPE_SHADER_VERTEX].buffers[index];
1603 if (!res)
1604 continue;
1605
1606 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1607 RADEON_USAGE_WRITE))
1608 goto has_write_reference;
1609 }
1610
1611 /* Samplers. */
1612 struct si_shader_selector *vs = sctx->vs_shader.cso;
1613 if (vs->info.samplers_declared) {
1614 unsigned num_samplers = util_last_bit(vs->info.samplers_declared);
1615
1616 for (unsigned i = 0; i < num_samplers; i++) {
1617 struct pipe_sampler_view *view = sctx->samplers[PIPE_SHADER_VERTEX].views[i];
1618 if (!view)
1619 continue;
1620
1621 if (ws->cs_is_buffer_referenced(cs,
1622 si_resource(view->texture)->buf,
1623 RADEON_USAGE_WRITE))
1624 goto has_write_reference;
1625 }
1626 }
1627
1628 /* Images. */
1629 if (vs->info.images_declared) {
1630 unsigned num_images = util_last_bit(vs->info.images_declared);
1631
1632 for (unsigned i = 0; i < num_images; i++) {
1633 struct pipe_resource *res = sctx->images[PIPE_SHADER_VERTEX].views[i].resource;
1634 if (!res)
1635 continue;
1636
1637 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1638 RADEON_USAGE_WRITE))
1639 goto has_write_reference;
1640 }
1641 }
1642
1643 return true;
1644
1645 has_write_reference:
1646 /* If the current gfx IB has enough packets, flush it to remove write
1647 * references to buffers.
1648 */
1649 if (cs->prev_dw + cs->current.cdw > 2048) {
1650 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1651 assert(si_all_vs_resources_read_only(sctx, indexbuf));
1652 return true;
1653 }
1654 return false;
1655 }
1656
1657 static ALWAYS_INLINE bool pd_msg(const char *s)
1658 {
1659 if (SI_PRIM_DISCARD_DEBUG)
1660 printf("PD failed: %s\n", s);
1661 return false;
1662 }
1663
1664 static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1665 {
1666 struct si_context *sctx = (struct si_context *)ctx;
1667 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1668 struct pipe_resource *indexbuf = info->index.resource;
1669 unsigned dirty_tex_counter, dirty_buf_counter;
1670 enum pipe_prim_type rast_prim, prim = info->mode;
1671 unsigned index_size = info->index_size;
1672 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1673 unsigned instance_count = info->instance_count;
1674 bool primitive_restart = info->primitive_restart &&
1675 (!sctx->screen->options.prim_restart_tri_strips_only ||
1676 (prim != PIPE_PRIM_TRIANGLE_STRIP &&
1677 prim != PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY));
1678
1679 if (likely(!info->indirect)) {
1680 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
1681 * no workaround for indirect draws, but we can at least skip
1682 * direct draws.
1683 */
1684 if (unlikely(!instance_count))
1685 return;
1686
1687 /* Handle count == 0. */
1688 if (unlikely(!info->count &&
1689 (index_size || !info->count_from_stream_output)))
1690 return;
1691 }
1692
1693 if (unlikely(!sctx->vs_shader.cso ||
1694 !rs ||
1695 (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
1696 (!!sctx->tes_shader.cso != (prim == PIPE_PRIM_PATCHES)))) {
1697 assert(0);
1698 return;
1699 }
1700
1701 /* Recompute and re-emit the texture resource states if needed. */
1702 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1703 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1704 sctx->last_dirty_tex_counter = dirty_tex_counter;
1705 sctx->framebuffer.dirty_cbufs |=
1706 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1707 sctx->framebuffer.dirty_zsbuf = true;
1708 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1709 si_update_all_texture_descriptors(sctx);
1710 }
1711
1712 dirty_buf_counter = p_atomic_read(&sctx->screen->dirty_buf_counter);
1713 if (unlikely(dirty_buf_counter != sctx->last_dirty_buf_counter)) {
1714 sctx->last_dirty_buf_counter = dirty_buf_counter;
1715 /* Rebind all buffers unconditionally. */
1716 si_rebind_buffer(sctx, NULL);
1717 }
1718
1719 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1720
1721 /* Set the rasterization primitive type.
1722 *
1723 * This must be done after si_decompress_textures, which can call
1724 * draw_vbo recursively, and before si_update_shaders, which uses
1725 * current_rast_prim for this draw_vbo call. */
1726 if (sctx->gs_shader.cso)
1727 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1728 else if (sctx->tes_shader.cso) {
1729 if (sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1730 rast_prim = PIPE_PRIM_POINTS;
1731 else
1732 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1733 } else
1734 rast_prim = prim;
1735
1736 if (rast_prim != sctx->current_rast_prim) {
1737 if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
1738 util_prim_is_points_or_lines(rast_prim))
1739 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1740
1741 sctx->current_rast_prim = rast_prim;
1742 sctx->do_update_shaders = true;
1743 }
1744
1745 if (sctx->tes_shader.cso &&
1746 sctx->screen->has_ls_vgpr_init_bug) {
1747 /* Determine whether the LS VGPR fix should be applied.
1748 *
1749 * It is only required when num input CPs > num output CPs,
1750 * which cannot happen with the fixed function TCS. We should
1751 * also update this bit when switching from TCS to fixed
1752 * function TCS.
1753 */
1754 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1755 bool ls_vgpr_fix =
1756 tcs &&
1757 info->vertices_per_patch >
1758 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1759
1760 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1761 sctx->ls_vgpr_fix = ls_vgpr_fix;
1762 sctx->do_update_shaders = true;
1763 }
1764 }
1765
1766 if (sctx->gs_shader.cso) {
1767 /* Determine whether the GS triangle strip adjacency fix should
1768 * be applied. Rotate every other triangle if
1769 * - triangle strips with adjacency are fed to the GS and
1770 * - primitive restart is disabled (the rotation doesn't help
1771 * when the restart occurs after an odd number of triangles).
1772 */
1773 bool gs_tri_strip_adj_fix =
1774 !sctx->tes_shader.cso &&
1775 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1776 !primitive_restart;
1777
1778 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1779 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1780 sctx->do_update_shaders = true;
1781 }
1782 }
1783
1784 if (index_size) {
1785 /* Translate or upload, if needed. */
1786 /* 8-bit indices are supported on GFX8. */
1787 if (sctx->chip_class <= GFX7 && index_size == 1) {
1788 unsigned start, count, start_offset, size, offset;
1789 void *ptr;
1790
1791 si_get_draw_start_count(sctx, info, &start, &count);
1792 start_offset = start * 2;
1793 size = count * 2;
1794
1795 indexbuf = NULL;
1796 u_upload_alloc(ctx->stream_uploader, start_offset,
1797 size,
1798 si_optimal_tcc_alignment(sctx, size),
1799 &offset, &indexbuf, &ptr);
1800 if (!indexbuf)
1801 return;
1802
1803 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1804 index_offset + start,
1805 count, ptr);
1806
1807 /* info->start will be added by the drawing code */
1808 index_offset = offset - start_offset;
1809 index_size = 2;
1810 } else if (info->has_user_indices) {
1811 unsigned start_offset;
1812
1813 assert(!info->indirect);
1814 start_offset = info->start * index_size;
1815
1816 indexbuf = NULL;
1817 u_upload_data(ctx->stream_uploader, start_offset,
1818 info->count * index_size,
1819 sctx->screen->info.tcc_cache_line_size,
1820 (char*)info->index.user + start_offset,
1821 &index_offset, &indexbuf);
1822 if (!indexbuf)
1823 return;
1824
1825 /* info->start will be added by the drawing code */
1826 index_offset -= start_offset;
1827 } else if (sctx->chip_class <= GFX7 &&
1828 si_resource(indexbuf)->TC_L2_dirty) {
1829 /* GFX8 reads index buffers through TC L2, so it doesn't
1830 * need this. */
1831 sctx->flags |= SI_CONTEXT_WB_L2;
1832 si_resource(indexbuf)->TC_L2_dirty = false;
1833 }
1834 }
1835
1836 bool dispatch_prim_discard_cs = false;
1837 bool prim_discard_cs_instancing = false;
1838 unsigned original_index_size = index_size;
1839 unsigned direct_count = 0;
1840
1841 if (info->indirect) {
1842 struct pipe_draw_indirect_info *indirect = info->indirect;
1843
1844 /* Add the buffer size for memory checking in need_cs_space. */
1845 si_context_add_resource_size(sctx, indirect->buffer);
1846
1847 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1848 if (sctx->chip_class <= GFX8) {
1849 if (si_resource(indirect->buffer)->TC_L2_dirty) {
1850 sctx->flags |= SI_CONTEXT_WB_L2;
1851 si_resource(indirect->buffer)->TC_L2_dirty = false;
1852 }
1853
1854 if (indirect->indirect_draw_count &&
1855 si_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1856 sctx->flags |= SI_CONTEXT_WB_L2;
1857 si_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1858 }
1859 }
1860 } else {
1861 /* Multiply by 3 for strips and fans to get an approximate vertex
1862 * count as triangles. */
1863 direct_count = info->count * instance_count *
1864 (prim == PIPE_PRIM_TRIANGLES ? 1 : 3);
1865 }
1866
1867 /* Determine if we can use the primitive discard compute shader. */
1868 if (si_compute_prim_discard_enabled(sctx) &&
1869 (direct_count > sctx->prim_discard_vertex_count_threshold ?
1870 (sctx->compute_num_verts_rejected += direct_count, true) : /* Add, then return true. */
1871 (sctx->compute_num_verts_ineligible += direct_count, false)) && /* Add, then return false. */
1872 (!info->count_from_stream_output || pd_msg("draw_opaque")) &&
1873 (primitive_restart ?
1874 /* Supported prim types with primitive restart: */
1875 (prim == PIPE_PRIM_TRIANGLE_STRIP || pd_msg("bad prim type with primitive restart")) &&
1876 /* Disallow instancing with primitive restart: */
1877 (instance_count == 1 || pd_msg("instance_count > 1 with primitive restart")) :
1878 /* Supported prim types without primitive restart + allow instancing: */
1879 (1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1880 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1881 (1 << PIPE_PRIM_TRIANGLE_FAN)) &&
1882 /* Instancing is limited to 16-bit indices, because InstanceID is packed into VertexID. */
1883 /* TODO: DrawArraysInstanced doesn't sometimes work, so it's disabled. */
1884 (instance_count == 1 ||
1885 (instance_count <= USHRT_MAX && index_size && index_size <= 2) ||
1886 pd_msg("instance_count too large or index_size == 4 or DrawArraysInstanced"))) &&
1887 (info->drawid == 0 || !sctx->vs_shader.cso->info.uses_drawid || pd_msg("draw_id > 0")) &&
1888 (!sctx->render_cond || pd_msg("render condition")) &&
1889 /* Forced enablement ignores pipeline statistics queries. */
1890 (sctx->screen->debug_flags & (DBG(PD) | DBG(ALWAYS_PD)) ||
1891 (!sctx->num_pipeline_stat_queries && !sctx->streamout.prims_gen_query_enabled) ||
1892 pd_msg("pipestat or primgen query")) &&
1893 (!sctx->vertex_elements->instance_divisor_is_fetched || pd_msg("loads instance divisors")) &&
1894 (!sctx->tes_shader.cso || pd_msg("uses tess")) &&
1895 (!sctx->gs_shader.cso || pd_msg("uses GS")) &&
1896 (!sctx->ps_shader.cso->info.uses_primid || pd_msg("PS uses PrimID")) &&
1897 #if SI_PRIM_DISCARD_DEBUG /* same as cso->prim_discard_cs_allowed */
1898 (!sctx->vs_shader.cso->info.uses_bindless_images || pd_msg("uses bindless images")) &&
1899 (!sctx->vs_shader.cso->info.uses_bindless_samplers || pd_msg("uses bindless samplers")) &&
1900 (!sctx->vs_shader.cso->info.writes_memory || pd_msg("writes memory")) &&
1901 (!sctx->vs_shader.cso->info.writes_viewport_index || pd_msg("writes viewport index")) &&
1902 !sctx->vs_shader.cso->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
1903 !sctx->vs_shader.cso->so.num_outputs &&
1904 #else
1905 (sctx->vs_shader.cso->prim_discard_cs_allowed || pd_msg("VS shader uses unsupported features")) &&
1906 #endif
1907 /* Check that all buffers are used for read only, because compute
1908 * dispatches can run ahead. */
1909 (si_all_vs_resources_read_only(sctx, index_size ? indexbuf : NULL) || pd_msg("write reference"))) {
1910 switch (si_prepare_prim_discard_or_split_draw(sctx, info, primitive_restart)) {
1911 case SI_PRIM_DISCARD_ENABLED:
1912 original_index_size = index_size;
1913 prim_discard_cs_instancing = instance_count > 1;
1914 dispatch_prim_discard_cs = true;
1915
1916 /* The compute shader changes/lowers the following: */
1917 prim = PIPE_PRIM_TRIANGLES;
1918 index_size = 4;
1919 instance_count = 1;
1920 primitive_restart = false;
1921 sctx->compute_num_verts_rejected -= direct_count;
1922 sctx->compute_num_verts_accepted += direct_count;
1923 break;
1924 case SI_PRIM_DISCARD_DISABLED:
1925 break;
1926 case SI_PRIM_DISCARD_DRAW_SPLIT:
1927 sctx->compute_num_verts_rejected -= direct_count;
1928 goto return_cleanup;
1929 }
1930 }
1931
1932 if (prim_discard_cs_instancing != sctx->prim_discard_cs_instancing) {
1933 sctx->prim_discard_cs_instancing = prim_discard_cs_instancing;
1934 sctx->do_update_shaders = true;
1935 }
1936
1937 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1938 goto return_cleanup;
1939
1940 si_need_gfx_cs_space(sctx);
1941
1942 if (sctx->bo_list_add_all_gfx_resources)
1943 si_gfx_resources_add_all_to_bo_list(sctx);
1944
1945 /* Since we've called si_context_add_resource_size for vertex buffers,
1946 * this must be called after si_need_cs_space, because we must let
1947 * need_cs_space flush before we add buffers to the buffer list.
1948 */
1949 if (!si_upload_vertex_buffer_descriptors(sctx))
1950 goto return_cleanup;
1951
1952 /* Vega10/Raven scissor bug workaround. When any context register is
1953 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
1954 * registers must be written too.
1955 */
1956 bool has_gfx9_scissor_bug = sctx->screen->has_gfx9_scissor_bug;
1957 unsigned masked_atoms = 0;
1958
1959 if (has_gfx9_scissor_bug) {
1960 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
1961
1962 if (info->count_from_stream_output ||
1963 sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
1964 sctx->dirty_states & si_states_that_always_roll_context())
1965 sctx->context_roll = true;
1966 }
1967
1968 /* Use optimal packet order based on whether we need to sync the pipeline. */
1969 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1970 SI_CONTEXT_FLUSH_AND_INV_DB |
1971 SI_CONTEXT_PS_PARTIAL_FLUSH |
1972 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1973 /* If we have to wait for idle, set all states first, so that all
1974 * SET packets are processed in parallel with previous draw calls.
1975 * Then draw and prefetch at the end. This ensures that the time
1976 * the CUs are idle is very short.
1977 */
1978 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
1979 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
1980
1981 if (!si_upload_graphics_shader_descriptors(sctx))
1982 goto return_cleanup;
1983
1984 /* Emit all states except possibly render condition. */
1985 si_emit_all_states(sctx, info, prim, instance_count,
1986 primitive_restart, masked_atoms);
1987 sctx->emit_cache_flush(sctx);
1988 /* <-- CUs are idle here. */
1989
1990 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
1991 sctx->atoms.s.render_cond.emit(sctx);
1992
1993 if (has_gfx9_scissor_bug &&
1994 (sctx->context_roll ||
1995 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
1996 sctx->atoms.s.scissors.emit(sctx);
1997
1998 sctx->dirty_atoms = 0;
1999
2000 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
2001 instance_count, dispatch_prim_discard_cs,
2002 original_index_size);
2003 /* <-- CUs are busy here. */
2004
2005 /* Start prefetches after the draw has been started. Both will run
2006 * in parallel, but starting the draw first is more important.
2007 */
2008 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2009 cik_emit_prefetch_L2(sctx, false);
2010 } else {
2011 /* If we don't wait for idle, start prefetches first, then set
2012 * states, and draw at the end.
2013 */
2014 if (sctx->flags)
2015 sctx->emit_cache_flush(sctx);
2016
2017 /* Only prefetch the API VS and VBO descriptors. */
2018 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2019 cik_emit_prefetch_L2(sctx, true);
2020
2021 if (!si_upload_graphics_shader_descriptors(sctx))
2022 goto return_cleanup;
2023
2024 si_emit_all_states(sctx, info, prim, instance_count,
2025 primitive_restart, masked_atoms);
2026
2027 if (has_gfx9_scissor_bug &&
2028 (sctx->context_roll ||
2029 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
2030 sctx->atoms.s.scissors.emit(sctx);
2031
2032 sctx->dirty_atoms = 0;
2033
2034 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
2035 instance_count, dispatch_prim_discard_cs,
2036 original_index_size);
2037
2038 /* Prefetch the remaining shaders after the draw has been
2039 * started. */
2040 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2041 cik_emit_prefetch_L2(sctx, false);
2042 }
2043
2044 /* Clear the context roll flag after the draw call. */
2045 sctx->context_roll = false;
2046
2047 if (unlikely(sctx->current_saved_cs)) {
2048 si_trace_emit(sctx);
2049 si_log_draw_state(sctx, sctx->log);
2050 }
2051
2052 /* Workaround for a VGT hang when streamout is enabled.
2053 * It must be done after drawing. */
2054 if ((sctx->family == CHIP_HAWAII ||
2055 sctx->family == CHIP_TONGA ||
2056 sctx->family == CHIP_FIJI) &&
2057 si_get_strmout_en(sctx)) {
2058 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
2059 }
2060
2061 if (unlikely(sctx->decompression_enabled)) {
2062 sctx->num_decompress_calls++;
2063 } else {
2064 sctx->num_draw_calls++;
2065 if (sctx->framebuffer.state.nr_cbufs > 1)
2066 sctx->num_mrt_draw_calls++;
2067 if (primitive_restart)
2068 sctx->num_prim_restart_calls++;
2069 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
2070 sctx->num_spill_draw_calls++;
2071 }
2072
2073 return_cleanup:
2074 if (index_size && indexbuf != info->index.resource)
2075 pipe_resource_reference(&indexbuf, NULL);
2076 }
2077
2078 static void
2079 si_draw_rectangle(struct blitter_context *blitter,
2080 void *vertex_elements_cso,
2081 blitter_get_vs_func get_vs,
2082 int x1, int y1, int x2, int y2,
2083 float depth, unsigned num_instances,
2084 enum blitter_attrib_type type,
2085 const union blitter_attrib *attrib)
2086 {
2087 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
2088 struct si_context *sctx = (struct si_context*)pipe;
2089
2090 /* Pack position coordinates as signed int16. */
2091 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
2092 ((uint32_t)(y1 & 0xffff) << 16);
2093 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
2094 ((uint32_t)(y2 & 0xffff) << 16);
2095 sctx->vs_blit_sh_data[2] = fui(depth);
2096
2097 switch (type) {
2098 case UTIL_BLITTER_ATTRIB_COLOR:
2099 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
2100 sizeof(float)*4);
2101 break;
2102 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
2103 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
2104 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
2105 sizeof(attrib->texcoord));
2106 break;
2107 case UTIL_BLITTER_ATTRIB_NONE:;
2108 }
2109
2110 pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
2111
2112 struct pipe_draw_info info = {};
2113 info.mode = SI_PRIM_RECTANGLE_LIST;
2114 info.count = 3;
2115 info.instance_count = num_instances;
2116
2117 /* Don't set per-stage shader pointers for VS. */
2118 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
2119 sctx->vertex_buffer_pointer_dirty = false;
2120
2121 si_draw_vbo(pipe, &info);
2122 }
2123
2124 void si_trace_emit(struct si_context *sctx)
2125 {
2126 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2127 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
2128
2129 si_cp_write_data(sctx, sctx->current_saved_cs->trace_buf,
2130 0, 4, V_370_MEM, V_370_ME, &trace_id);
2131
2132 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2133 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
2134
2135 if (sctx->log)
2136 u_log_flush(sctx->log);
2137 }
2138
2139 void si_init_draw_functions(struct si_context *sctx)
2140 {
2141 sctx->b.draw_vbo = si_draw_vbo;
2142
2143 sctx->blitter->draw_rectangle = si_draw_rectangle;
2144
2145 si_init_ia_multi_vgt_param_table(sctx);
2146 }