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radeonsi: set number of userdata SGPRs of GS copy shader to 4
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "radeon/r600_cs.h"
30 #include "sid.h"
31
32 #include "util/u_format.h"
33 #include "util/u_index_modify.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36 #include "util/u_upload_mgr.h"
37
38 /*
39 * Shaders
40 */
41
42 static void si_shader_es(struct pipe_context *ctx, struct si_shader *shader)
43 {
44 struct si_context *sctx = (struct si_context *)ctx;
45 struct si_pm4_state *pm4;
46 unsigned num_sgprs, num_user_sgprs;
47 unsigned vgpr_comp_cnt;
48 uint64_t va;
49
50 si_pm4_delete_state(sctx, es, shader->pm4);
51 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
52
53 if (pm4 == NULL)
54 return;
55
56 va = shader->bo->gpu_address;
57 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
58
59 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
60
61 num_user_sgprs = SI_VS_NUM_USER_SGPR;
62 num_sgprs = shader->num_sgprs;
63 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
64 if ((num_user_sgprs + 1) > num_sgprs) {
65 /* Last 2 reserved SGPRs are used for VCC */
66 num_sgprs = num_user_sgprs + 1 + 2;
67 }
68 assert(num_sgprs <= 104);
69
70 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
71 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
72 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
73 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
74 S_00B328_SGPRS((num_sgprs - 1) / 8) |
75 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt));
76 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
77 S_00B32C_USER_SGPR(num_user_sgprs));
78 }
79
80 static void si_shader_gs(struct pipe_context *ctx, struct si_shader *shader)
81 {
82 struct si_context *sctx = (struct si_context *)ctx;
83 unsigned gs_vert_itemsize = shader->noutput * (16 >> 2);
84 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
85 unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
86 unsigned cut_mode;
87 struct si_pm4_state *pm4;
88 unsigned num_sgprs, num_user_sgprs;
89 uint64_t va;
90
91 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
92 assert(gsvs_itemsize < (1 << 15));
93
94 si_pm4_delete_state(sctx, gs, shader->pm4);
95 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
96
97 if (pm4 == NULL)
98 return;
99
100 if (gs_max_vert_out <= 128) {
101 cut_mode = V_028A40_GS_CUT_128;
102 } else if (gs_max_vert_out <= 256) {
103 cut_mode = V_028A40_GS_CUT_256;
104 } else if (gs_max_vert_out <= 512) {
105 cut_mode = V_028A40_GS_CUT_512;
106 } else {
107 assert(gs_max_vert_out <= 1024);
108 cut_mode = V_028A40_GS_CUT_1024;
109 }
110
111 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
112 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
113 S_028A40_CUT_MODE(cut_mode)|
114 S_028A40_ES_WRITE_OPTIMIZE(1) |
115 S_028A40_GS_WRITE_OPTIMIZE(1));
116
117 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
118 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize);
119 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize);
120
121 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
122 util_bitcount64(shader->selector->gs_used_inputs) * (16 >> 2));
123 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
124
125 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
126
127 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
128
129 va = shader->bo->gpu_address;
130 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
131 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
132 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
133
134 num_user_sgprs = SI_GS_NUM_USER_SGPR;
135 num_sgprs = shader->num_sgprs;
136 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
137 if ((num_user_sgprs + 2) > num_sgprs) {
138 /* Last 2 reserved SGPRs are used for VCC */
139 num_sgprs = num_user_sgprs + 2 + 2;
140 }
141 assert(num_sgprs <= 104);
142
143 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
144 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
145 S_00B228_SGPRS((num_sgprs - 1) / 8));
146 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
147 S_00B22C_USER_SGPR(num_user_sgprs));
148 }
149
150 static void si_shader_vs(struct pipe_context *ctx, struct si_shader *shader)
151 {
152 struct si_context *sctx = (struct si_context *)ctx;
153 struct si_pm4_state *pm4;
154 unsigned num_sgprs, num_user_sgprs;
155 unsigned nparams, i, vgpr_comp_cnt;
156 uint64_t va;
157
158 si_pm4_delete_state(sctx, vs, shader->pm4);
159 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
160
161 if (pm4 == NULL)
162 return;
163
164 va = shader->bo->gpu_address;
165 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
166
167 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
168
169 if (shader->is_gs_copy_shader)
170 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
171 else
172 num_user_sgprs = SI_VS_NUM_USER_SGPR;
173
174 num_sgprs = shader->num_sgprs;
175 if (num_user_sgprs > num_sgprs) {
176 /* Last 2 reserved SGPRs are used for VCC */
177 num_sgprs = num_user_sgprs + 2;
178 }
179 assert(num_sgprs <= 104);
180
181 /* Certain attributes (position, psize, etc.) don't count as params.
182 * VS is required to export at least one param and r600_shader_from_tgsi()
183 * takes care of adding a dummy export.
184 */
185 for (nparams = 0, i = 0 ; i < shader->noutput; i++) {
186 switch (shader->output[i].name) {
187 case TGSI_SEMANTIC_CLIPVERTEX:
188 case TGSI_SEMANTIC_POSITION:
189 case TGSI_SEMANTIC_PSIZE:
190 break;
191 default:
192 nparams++;
193 }
194 }
195 if (nparams < 1)
196 nparams = 1;
197
198 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
199 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
200
201 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
202 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
203 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
204 V_02870C_SPI_SHADER_4COMP :
205 V_02870C_SPI_SHADER_NONE) |
206 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
207 V_02870C_SPI_SHADER_4COMP :
208 V_02870C_SPI_SHADER_NONE) |
209 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
210 V_02870C_SPI_SHADER_4COMP :
211 V_02870C_SPI_SHADER_NONE));
212
213 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
214 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
215 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
216 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
217 S_00B128_SGPRS((num_sgprs - 1) / 8) |
218 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
219 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
220 S_00B12C_USER_SGPR(num_user_sgprs) |
221 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
222 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
223 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
224 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
225 S_00B12C_SO_EN(!!shader->selector->so.num_outputs));
226 }
227
228 static void si_shader_ps(struct pipe_context *ctx, struct si_shader *shader)
229 {
230 struct si_context *sctx = (struct si_context *)ctx;
231 struct si_pm4_state *pm4;
232 unsigned i, spi_ps_in_control;
233 unsigned num_sgprs, num_user_sgprs;
234 unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
235 uint64_t va;
236
237 si_pm4_delete_state(sctx, ps, shader->pm4);
238 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
239
240 if (pm4 == NULL)
241 return;
242
243 for (i = 0; i < shader->ninput; i++) {
244 switch (shader->input[i].name) {
245 case TGSI_SEMANTIC_POSITION:
246 if (shader->input[i].centroid) {
247 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
248 * Possible vaules:
249 * 0 -> Position = pixel center (default)
250 * 1 -> Position = pixel centroid
251 * 2 -> Position = iterated sample number XXX:
252 * What does this mean?
253 */
254 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
255 }
256 /* Fall through */
257 case TGSI_SEMANTIC_FACE:
258 continue;
259 }
260 }
261
262 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
263 S_0286D8_BC_OPTIMIZE_DISABLE(1);
264
265 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
266 spi_ps_input_ena = shader->spi_ps_input_ena;
267 /* we need to enable at least one of them, otherwise we hang the GPU */
268 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
269 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
270 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
271 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
272 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
273 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
274 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
275 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
276
277 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
278 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
279 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
280
281 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
282 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
283 shader->spi_shader_col_format);
284 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
285
286 va = shader->bo->gpu_address;
287 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
288 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
289 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
290
291 num_user_sgprs = SI_PS_NUM_USER_SGPR;
292 num_sgprs = shader->num_sgprs;
293 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
294 if ((num_user_sgprs + 1) > num_sgprs) {
295 /* Last 2 reserved SGPRs are used for VCC */
296 num_sgprs = num_user_sgprs + 1 + 2;
297 }
298 assert(num_sgprs <= 104);
299
300 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
301 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
302 S_00B028_SGPRS((num_sgprs - 1) / 8));
303 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
304 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
305 S_00B02C_USER_SGPR(num_user_sgprs));
306 }
307
308 /*
309 * Drawing
310 */
311
312 static unsigned si_conv_pipe_prim(unsigned pprim)
313 {
314 static const unsigned prim_conv[] = {
315 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
316 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
317 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
318 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
319 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
320 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
321 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
322 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
323 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
324 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
325 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
326 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
327 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
328 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
329 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
330 };
331 unsigned result = prim_conv[pprim];
332 if (result == ~0) {
333 R600_ERR("unsupported primitive type %d\n", pprim);
334 }
335 return result;
336 }
337
338 static unsigned si_conv_prim_to_gs_out(unsigned mode)
339 {
340 static const int prim_conv[] = {
341 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
342 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
343 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
344 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
345 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
346 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
347 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
348 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
349 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
350 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
351 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
352 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
353 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
354 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
355 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
356 };
357 assert(mode < Elements(prim_conv));
358
359 return prim_conv[mode];
360 }
361
362 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
363 const struct pipe_draw_info *info)
364 {
365 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
366 unsigned prim = info->mode;
367 unsigned primgroup_size = 128; /* recommended without a GS */
368
369 /* SWITCH_ON_EOP(0) is always preferable. */
370 bool wd_switch_on_eop = false;
371 bool ia_switch_on_eop = false;
372 bool partial_vs_wave = false;
373
374 if (sctx->gs_shader)
375 primgroup_size = 64; /* recommended with a GS */
376
377 /* This is a hardware requirement. */
378 if ((rs && rs->line_stipple_enable) ||
379 (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
380 ia_switch_on_eop = true;
381 wd_switch_on_eop = true;
382 }
383
384 if (sctx->b.streamout.streamout_enabled ||
385 sctx->b.streamout.prims_gen_query_enabled)
386 partial_vs_wave = true;
387
388 if (sctx->b.chip_class >= CIK) {
389 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
390 * 4 shader engines. Set 1 to pass the assertion below.
391 * The other cases are hardware requirements. */
392 if (sctx->b.screen->info.max_se < 4 ||
393 prim == PIPE_PRIM_POLYGON ||
394 prim == PIPE_PRIM_LINE_LOOP ||
395 prim == PIPE_PRIM_TRIANGLE_FAN ||
396 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
397 info->primitive_restart)
398 wd_switch_on_eop = true;
399
400 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
401 * We don't know that for indirect drawing, so treat it as
402 * always problematic. */
403 if (sctx->b.family == CHIP_HAWAII &&
404 (info->indirect || info->instance_count > 1))
405 wd_switch_on_eop = true;
406
407 /* If the WD switch is false, the IA switch must be false too. */
408 assert(wd_switch_on_eop || !ia_switch_on_eop);
409 }
410
411 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
412 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
413 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
414 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0);
415 }
416
417 static bool si_update_draw_info_state(struct si_context *sctx,
418 const struct pipe_draw_info *info,
419 const struct pipe_index_buffer *ib)
420 {
421 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
422 struct si_shader *vs = si_get_vs_state(sctx);
423 unsigned prim = si_conv_pipe_prim(info->mode);
424 unsigned gs_out_prim =
425 si_conv_prim_to_gs_out(sctx->gs_shader ?
426 sctx->gs_shader->gs_output_prim :
427 info->mode);
428 unsigned ls_mask = 0;
429 unsigned ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info);
430
431 if (pm4 == NULL)
432 return false;
433
434 if (prim == ~0) {
435 FREE(pm4);
436 return false;
437 }
438
439 if (sctx->b.chip_class >= CIK) {
440 si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
441 ib->index_size == 4 ? 0xFC000000 : 0xFC00);
442
443 si_pm4_cmd_begin(pm4, PKT3_DRAW_PREAMBLE);
444 si_pm4_cmd_add(pm4, prim); /* VGT_PRIMITIVE_TYPE */
445 si_pm4_cmd_add(pm4, ia_multi_vgt_param); /* IA_MULTI_VGT_PARAM */
446 si_pm4_cmd_add(pm4, 0); /* VGT_LS_HS_CONFIG */
447 si_pm4_cmd_end(pm4, false);
448 } else {
449 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
450 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
451 }
452
453 si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
454 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
455 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
456
457 if (prim == V_008958_DI_PT_LINELIST)
458 ls_mask = 1;
459 else if (prim == V_008958_DI_PT_LINESTRIP)
460 ls_mask = 2;
461 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
462 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
463 sctx->pa_sc_line_stipple);
464
465 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
466 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
467 S_028814_PROVOKING_VTX_LAST(1) | sctx->pa_su_sc_mode_cntl);
468 } else {
469 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, sctx->pa_su_sc_mode_cntl);
470 }
471 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
472 S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
473 S_02881C_USE_VTX_EDGE_FLAG(vs->vs_out_edgeflag) |
474 S_02881C_USE_VTX_RENDER_TARGET_INDX(vs->vs_out_layer) |
475 S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs->clip_dist_write & 0x0F) != 0) |
476 S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs->clip_dist_write & 0xF0) != 0) |
477 S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write) |
478 (sctx->queued.named.rasterizer->clip_plane_enable &
479 vs->clip_dist_write));
480 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL,
481 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
482 (vs->clip_dist_write ? 0 :
483 sctx->queued.named.rasterizer->clip_plane_enable & 0x3F));
484
485 si_pm4_set_state(sctx, draw_info, pm4);
486 return true;
487 }
488
489 static void si_update_spi_map(struct si_context *sctx)
490 {
491 struct si_shader *ps = sctx->ps_shader->current;
492 struct si_shader *vs = si_get_vs_state(sctx);
493 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
494 unsigned i, j, tmp;
495
496 for (i = 0; i < ps->ninput; i++) {
497 unsigned name = ps->input[i].name;
498 unsigned param_offset = ps->input[i].param_offset;
499
500 if (name == TGSI_SEMANTIC_POSITION)
501 /* Read from preloaded VGPRs, not parameters */
502 continue;
503
504 bcolor:
505 tmp = 0;
506
507 if (ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
508 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
509 sctx->ps_shader->current->key.ps.flatshade)) {
510 tmp |= S_028644_FLAT_SHADE(1);
511 }
512
513 if (name == TGSI_SEMANTIC_GENERIC &&
514 sctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
515 tmp |= S_028644_PT_SPRITE_TEX(1);
516 }
517
518 for (j = 0; j < vs->noutput; j++) {
519 if (name == vs->output[j].name &&
520 ps->input[i].sid == vs->output[j].sid) {
521 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
522 break;
523 }
524 }
525
526 if (j == vs->noutput) {
527 /* No corresponding output found, load defaults into input */
528 tmp |= S_028644_OFFSET(0x20);
529 }
530
531 si_pm4_set_reg(pm4,
532 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
533 tmp);
534
535 if (name == TGSI_SEMANTIC_COLOR &&
536 sctx->ps_shader->current->key.ps.color_two_side) {
537 name = TGSI_SEMANTIC_BCOLOR;
538 param_offset++;
539 goto bcolor;
540 }
541 }
542
543 si_pm4_set_state(sctx, spi, pm4);
544 }
545
546 /* Initialize state related to ESGS / GSVS ring buffers */
547 static void si_init_gs_rings(struct si_context *sctx)
548 {
549 unsigned esgs_ring_size = 128 * 1024;
550 unsigned gsvs_ring_size = 64 * 1024 * 1024;
551
552 assert(!sctx->gs_rings);
553 sctx->gs_rings = si_pm4_alloc_state(sctx);
554
555 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
556 PIPE_USAGE_DEFAULT, esgs_ring_size);
557
558 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
559 PIPE_USAGE_DEFAULT, gsvs_ring_size);
560
561 if (sctx->b.chip_class >= CIK) {
562 si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
563 esgs_ring_size / 256);
564 si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
565 gsvs_ring_size / 256);
566 } else {
567 si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
568 esgs_ring_size / 256);
569 si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
570 gsvs_ring_size / 256);
571 }
572
573 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
574 sctx->esgs_ring, 0, esgs_ring_size,
575 true, true, 4, 64);
576 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
577 sctx->esgs_ring, 0, esgs_ring_size,
578 false, false, 0, 0);
579 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
580 sctx->gsvs_ring, 0, gsvs_ring_size,
581 false, false, 0, 0);
582 }
583
584 static void si_update_derived_state(struct si_context *sctx)
585 {
586 struct pipe_context * ctx = (struct pipe_context*)sctx;
587
588 if (!sctx->blitter->running) {
589 /* Flush depth textures which need to be flushed. */
590 for (int i = 0; i < SI_NUM_SHADERS; i++) {
591 if (sctx->samplers[i].depth_texture_mask) {
592 si_flush_depth_textures(sctx, &sctx->samplers[i]);
593 }
594 if (sctx->samplers[i].compressed_colortex_mask) {
595 si_decompress_color_textures(sctx, &sctx->samplers[i]);
596 }
597 }
598 }
599
600 if (sctx->gs_shader) {
601 si_shader_select(ctx, sctx->gs_shader);
602
603 if (!sctx->gs_shader->current->pm4) {
604 si_shader_gs(ctx, sctx->gs_shader->current);
605 si_shader_vs(ctx, sctx->gs_shader->current->gs_copy_shader);
606 }
607
608 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
609 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
610
611 sctx->b.streamout.stride_in_dw = sctx->gs_shader->so.stride;
612
613 si_shader_select(ctx, sctx->vs_shader);
614
615 if (!sctx->vs_shader->current->pm4)
616 si_shader_es(ctx, sctx->vs_shader->current);
617
618 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
619
620 if (!sctx->gs_rings)
621 si_init_gs_rings(sctx);
622 if (sctx->emitted.named.gs_rings != sctx->gs_rings)
623 sctx->b.flags |= R600_CONTEXT_VGT_FLUSH;
624 si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
625
626 si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
627 sctx->gsvs_ring,
628 sctx->gs_shader->gs_max_out_vertices *
629 sctx->gs_shader->current->noutput * 16,
630 64, true, true, 4, 16);
631
632 if (!sctx->gs_on) {
633 sctx->gs_on = si_pm4_alloc_state(sctx);
634
635 si_pm4_set_reg(sctx->gs_on, R_028B54_VGT_SHADER_STAGES_EN,
636 S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
637 S_028B54_GS_EN(1) |
638 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER));
639 }
640 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_on);
641 } else {
642 si_shader_select(ctx, sctx->vs_shader);
643
644 if (!sctx->vs_shader->current->pm4)
645 si_shader_vs(ctx, sctx->vs_shader->current);
646
647 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
648
649 sctx->b.streamout.stride_in_dw = sctx->vs_shader->so.stride;
650
651 if (!sctx->gs_off) {
652 sctx->gs_off = si_pm4_alloc_state(sctx);
653
654 si_pm4_set_reg(sctx->gs_off, R_028A40_VGT_GS_MODE, 0);
655 si_pm4_set_reg(sctx->gs_off, R_028B54_VGT_SHADER_STAGES_EN, 0);
656 }
657 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_off);
658 si_pm4_bind_state(sctx, gs_rings, NULL);
659 si_pm4_bind_state(sctx, gs, NULL);
660 si_pm4_bind_state(sctx, es, NULL);
661 }
662
663 si_shader_select(ctx, sctx->ps_shader);
664
665 if (!sctx->ps_shader->current->pm4)
666 si_shader_ps(ctx, sctx->ps_shader->current);
667
668 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
669
670 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs)) {
671 /* XXX: Emitting the PS state even when only the VS changed
672 * fixes random failures with piglit glsl-max-varyings.
673 * Not sure why...
674 */
675 sctx->emitted.named.ps = NULL;
676 si_update_spi_map(sctx);
677 }
678
679 if (sctx->ps_db_shader_control != sctx->ps_shader->current->db_shader_control) {
680 sctx->ps_db_shader_control = sctx->ps_shader->current->db_shader_control;
681 sctx->db_render_state.dirty = true;
682 }
683 }
684
685 static void si_state_draw(struct si_context *sctx,
686 const struct pipe_draw_info *info,
687 const struct pipe_index_buffer *ib)
688 {
689 unsigned sh_base_reg = (sctx->gs_shader ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
690 R_00B130_SPI_SHADER_USER_DATA_VS_0);
691 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
692
693 if (pm4 == NULL)
694 return;
695
696 if (info->count_from_stream_output) {
697 struct r600_so_target *t =
698 (struct r600_so_target*)info->count_from_stream_output;
699 uint64_t va = t->buf_filled_size->gpu_address +
700 t->buf_filled_size_offset;
701
702 si_pm4_set_reg(pm4, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
703 t->stride_in_dw);
704
705 si_pm4_cmd_begin(pm4, PKT3_COPY_DATA);
706 si_pm4_cmd_add(pm4,
707 COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
708 COPY_DATA_DST_SEL(COPY_DATA_REG) |
709 COPY_DATA_WR_CONFIRM);
710 si_pm4_cmd_add(pm4, va); /* src address lo */
711 si_pm4_cmd_add(pm4, va >> 32UL); /* src address hi */
712 si_pm4_cmd_add(pm4, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
713 si_pm4_cmd_add(pm4, 0); /* unused */
714 si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ,
715 RADEON_PRIO_MIN);
716 si_pm4_cmd_end(pm4, true);
717 }
718
719 /* draw packet */
720 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
721 if (ib->index_size == 4) {
722 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (SI_BIG_ENDIAN ?
723 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
724 } else {
725 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (SI_BIG_ENDIAN ?
726 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
727 }
728 si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
729
730 if (!info->indirect) {
731 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
732 si_pm4_cmd_add(pm4, info->instance_count);
733 si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
734
735 si_pm4_set_reg(pm4, sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
736 info->indexed ? info->index_bias : info->start);
737 si_pm4_set_reg(pm4, sh_base_reg + SI_SGPR_START_INSTANCE * 4,
738 info->start_instance);
739 } else {
740 si_pm4_add_bo(pm4, (struct r600_resource *)info->indirect,
741 RADEON_USAGE_READ, RADEON_PRIO_MIN);
742 }
743
744 if (info->indexed) {
745 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
746 sctx->index_buffer.index_size;
747 uint64_t va = r600_resource(ib->buffer)->gpu_address + ib->offset;
748
749 si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ,
750 RADEON_PRIO_MIN);
751
752 if (info->indirect) {
753 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
754 si_cmd_draw_index_indirect(pm4, indirect_va, va, max_size,
755 info->indirect_offset,
756 sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
757 sh_base_reg + SI_SGPR_START_INSTANCE * 4,
758 sctx->b.predicate_drawing);
759 } else {
760 va += info->start * ib->index_size;
761 si_cmd_draw_index_2(pm4, max_size, va, info->count,
762 V_0287F0_DI_SRC_SEL_DMA,
763 sctx->b.predicate_drawing);
764 }
765 } else {
766 if (info->indirect) {
767 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
768 si_cmd_draw_indirect(pm4, indirect_va, info->indirect_offset,
769 sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
770 sh_base_reg + SI_SGPR_START_INSTANCE * 4,
771 sctx->b.predicate_drawing);
772 } else {
773 si_cmd_draw_index_auto(pm4, info->count,
774 V_0287F0_DI_SRC_SEL_AUTO_INDEX |
775 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output),
776 sctx->b.predicate_drawing);
777 }
778 }
779
780 si_pm4_set_state(sctx, draw, pm4);
781 }
782
783 void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom)
784 {
785 struct radeon_winsys_cs *cs = sctx->rings.gfx.cs;
786 uint32_t cp_coher_cntl = 0;
787 uint32_t compute =
788 PKT3_SHADER_TYPE_S(!!(sctx->flags & R600_CONTEXT_FLAG_COMPUTE));
789
790 /* XXX SI flushes both ICACHE and KCACHE if either flag is set.
791 * XXX CIK shouldn't have this issue. Test CIK before separating the flags
792 * XXX to ensure there is no regression. Also find out if there is another
793 * XXX way to flush either ICACHE or KCACHE but not both for SI. */
794 if (sctx->flags & (R600_CONTEXT_INV_SHADER_CACHE |
795 R600_CONTEXT_INV_CONST_CACHE)) {
796 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1) |
797 S_0085F0_SH_KCACHE_ACTION_ENA(1);
798 }
799 if (sctx->flags & (R600_CONTEXT_INV_TEX_CACHE |
800 R600_CONTEXT_STREAMOUT_FLUSH)) {
801 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1) |
802 S_0085F0_TCL1_ACTION_ENA(1);
803 }
804 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB) {
805 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
806 S_0085F0_CB0_DEST_BASE_ENA(1) |
807 S_0085F0_CB1_DEST_BASE_ENA(1) |
808 S_0085F0_CB2_DEST_BASE_ENA(1) |
809 S_0085F0_CB3_DEST_BASE_ENA(1) |
810 S_0085F0_CB4_DEST_BASE_ENA(1) |
811 S_0085F0_CB5_DEST_BASE_ENA(1) |
812 S_0085F0_CB6_DEST_BASE_ENA(1) |
813 S_0085F0_CB7_DEST_BASE_ENA(1);
814 }
815 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB) {
816 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
817 S_0085F0_DB_DEST_BASE_ENA(1);
818 }
819
820 if (cp_coher_cntl) {
821 if (sctx->chip_class >= CIK) {
822 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) | compute);
823 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
824 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
825 radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */
826 radeon_emit(cs, 0); /* CP_COHER_BASE */
827 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
828 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
829 } else {
830 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0) | compute);
831 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
832 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
833 radeon_emit(cs, 0); /* CP_COHER_BASE */
834 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
835 }
836 }
837
838 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META) {
839 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
840 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
841 }
842 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB_META) {
843 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
844 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
845 }
846 if (sctx->flags & R600_CONTEXT_FLUSH_WITH_INV_L2) {
847 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
848 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH) | EVENT_INDEX(7) |
849 EVENT_WRITE_INV_L2);
850 }
851
852 if (sctx->flags & (R600_CONTEXT_WAIT_3D_IDLE |
853 R600_CONTEXT_PS_PARTIAL_FLUSH)) {
854 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
855 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
856 } else if (sctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
857 /* Needed if streamout buffers are going to be used as a source. */
858 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
859 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
860 }
861
862 if (sctx->flags & R600_CONTEXT_CS_PARTIAL_FLUSH) {
863 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
864 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
865 }
866
867 if (sctx->flags & R600_CONTEXT_VGT_FLUSH) {
868 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
869 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
870 }
871 if (sctx->flags & R600_CONTEXT_VGT_STREAMOUT_SYNC) {
872 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
873 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
874 }
875
876 sctx->flags = 0;
877 }
878
879 const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 21 }; /* number of CS dwords */
880
881 static void si_get_draw_start_count(struct si_context *sctx,
882 const struct pipe_draw_info *info,
883 unsigned *start, unsigned *count)
884 {
885 if (info->indirect) {
886 struct r600_resource *indirect =
887 (struct r600_resource*)info->indirect;
888 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
889 indirect, PIPE_TRANSFER_READ);
890 data += info->indirect_offset/sizeof(int);
891 *start = data[2];
892 *count = data[0];
893 } else {
894 *start = info->start;
895 *count = info->count;
896 }
897 }
898
899 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
900 {
901 struct si_context *sctx = (struct si_context *)ctx;
902 struct pipe_index_buffer ib = {};
903 uint32_t i;
904
905 if (!info->count && !info->indirect &&
906 (info->indexed || !info->count_from_stream_output))
907 return;
908
909 if (!sctx->ps_shader || !sctx->vs_shader)
910 return;
911
912 si_update_derived_state(sctx);
913
914 if (sctx->vertex_buffers_dirty) {
915 si_update_vertex_buffers(sctx);
916 sctx->vertex_buffers_dirty = false;
917 }
918
919 if (info->indexed) {
920 /* Initialize the index buffer struct. */
921 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
922 ib.user_buffer = sctx->index_buffer.user_buffer;
923 ib.index_size = sctx->index_buffer.index_size;
924 ib.offset = sctx->index_buffer.offset;
925
926 /* Translate or upload, if needed. */
927 if (ib.index_size == 1) {
928 struct pipe_resource *out_buffer = NULL;
929 unsigned out_offset, start, count, start_offset;
930 void *ptr;
931
932 si_get_draw_start_count(sctx, info, &start, &count);
933 start_offset = start * ib.index_size;
934
935 u_upload_alloc(sctx->b.uploader, start_offset, count * 2,
936 &out_offset, &out_buffer, &ptr);
937
938 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
939 ib.offset + start_offset,
940 count, ptr);
941
942 pipe_resource_reference(&ib.buffer, NULL);
943 ib.user_buffer = NULL;
944 ib.buffer = out_buffer;
945 /* info->start will be added by the drawing code */
946 ib.offset = out_offset - start_offset;
947 ib.index_size = 2;
948 } else if (ib.user_buffer && !ib.buffer) {
949 unsigned start, count, start_offset;
950
951 si_get_draw_start_count(sctx, info, &start, &count);
952 start_offset = start * ib.index_size;
953
954 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
955 (char*)ib.user_buffer + start_offset,
956 &ib.offset, &ib.buffer);
957 /* info->start will be added by the drawing code */
958 ib.offset -= start_offset;
959 }
960 }
961
962 if (!si_update_draw_info_state(sctx, info, &ib))
963 return;
964
965 si_state_draw(sctx, info, &ib);
966
967 sctx->pm4_dirty_cdwords += si_pm4_dirty_dw(sctx);
968
969 /* Check flush flags. */
970 if (sctx->b.flags)
971 sctx->atoms.s.cache_flush->dirty = true;
972
973 si_need_cs_space(sctx, 0, TRUE);
974
975 /* Emit states. */
976 for (i = 0; i < SI_NUM_ATOMS(sctx); i++) {
977 if (sctx->atoms.array[i]->dirty) {
978 sctx->atoms.array[i]->emit(&sctx->b, sctx->atoms.array[i]);
979 sctx->atoms.array[i]->dirty = false;
980 }
981 }
982
983 si_pm4_emit_dirty(sctx);
984 sctx->pm4_dirty_cdwords = 0;
985
986 #if SI_TRACE_CS
987 if (sctx->screen->b.trace_bo) {
988 si_trace_emit(sctx);
989 }
990 #endif
991
992 /* Workaround for a VGT hang when streamout is enabled.
993 * It must be done after drawing. */
994 if (sctx->b.family == CHIP_HAWAII &&
995 (sctx->b.streamout.streamout_enabled ||
996 sctx->b.streamout.prims_gen_query_enabled)) {
997 sctx->b.flags |= R600_CONTEXT_VGT_STREAMOUT_SYNC;
998 }
999
1000 /* Set the depth buffer as dirty. */
1001 if (sctx->framebuffer.state.zsbuf) {
1002 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1003 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1004
1005 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1006 }
1007 if (sctx->framebuffer.compressed_cb_mask) {
1008 struct pipe_surface *surf;
1009 struct r600_texture *rtex;
1010 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1011
1012 do {
1013 unsigned i = u_bit_scan(&mask);
1014 surf = sctx->framebuffer.state.cbufs[i];
1015 rtex = (struct r600_texture*)surf->texture;
1016
1017 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1018 } while (mask);
1019 }
1020
1021 pipe_resource_reference(&ib.buffer, NULL);
1022 sctx->b.num_draw_calls++;
1023 }
1024
1025 #if SI_TRACE_CS
1026 void si_trace_emit(struct si_context *sctx)
1027 {
1028 struct si_screen *sscreen = sctx->screen;
1029 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
1030 uint64_t va;
1031
1032 va = sscreen->b.trace_bo->gpu_address;
1033 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, sscreen->b.trace_bo,
1034 RADEON_USAGE_READWRITE, RADEON_PRIO_MIN);
1035 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1036 radeon_emit(cs, PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_MEM_SYNC) |
1037 PKT3_WRITE_DATA_WR_CONFIRM |
1038 PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME));
1039 radeon_emit(cs, va & 0xFFFFFFFFUL);
1040 radeon_emit(cs, (va >> 32UL) & 0xFFFFFFFFUL);
1041 radeon_emit(cs, cs->cdw);
1042 radeon_emit(cs, sscreen->b.cs_count);
1043 }
1044 #endif