2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "radeon/r600_cs.h"
29 #include "util/u_index_modify.h"
30 #include "util/u_log.h"
31 #include "util/u_upload_mgr.h"
32 #include "util/u_prim.h"
36 /* special primitive types */
37 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
39 static unsigned si_conv_pipe_prim(unsigned mode
)
41 static const unsigned prim_conv
[] = {
42 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
43 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
44 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
45 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
46 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
47 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
48 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
49 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
50 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
51 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
52 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
53 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
54 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
55 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
56 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
57 [SI_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
59 assert(mode
< ARRAY_SIZE(prim_conv
));
60 return prim_conv
[mode
];
63 static unsigned si_conv_prim_to_gs_out(unsigned mode
)
65 static const int prim_conv
[] = {
66 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
67 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
68 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
69 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
70 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
71 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
72 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
73 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
74 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
75 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
76 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
77 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
78 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
79 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
80 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
81 [SI_PRIM_RECTANGLE_LIST
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
83 assert(mode
< ARRAY_SIZE(prim_conv
));
85 return prim_conv
[mode
];
89 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
90 * LS.LDS_SIZE is shared by all 3 shader stages.
92 * The information about LDS and other non-compile-time parameters is then
93 * written to userdata SGPRs.
95 static void si_emit_derived_tess_state(struct si_context
*sctx
,
96 const struct pipe_draw_info
*info
,
97 unsigned *num_patches
)
99 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
100 struct si_shader
*ls_current
;
101 struct si_shader_selector
*ls
;
102 /* The TES pointer will only be used for sctx->last_tcs.
103 * It would be wrong to think that TCS = TES. */
104 struct si_shader_selector
*tcs
=
105 sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.cso
: sctx
->tes_shader
.cso
;
106 unsigned tess_uses_primid
= sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
;
107 bool has_primid_instancing_bug
= sctx
->b
.chip_class
== SI
&&
108 sctx
->b
.screen
->info
.max_se
== 1;
109 unsigned tes_sh_base
= sctx
->shader_pointers
.sh_base
[PIPE_SHADER_TESS_EVAL
];
110 unsigned num_tcs_input_cp
= info
->vertices_per_patch
;
111 unsigned num_tcs_output_cp
, num_tcs_inputs
, num_tcs_outputs
;
112 unsigned num_tcs_patch_outputs
;
113 unsigned input_vertex_size
, output_vertex_size
, pervertex_output_patch_size
;
114 unsigned input_patch_size
, output_patch_size
, output_patch0_offset
;
115 unsigned perpatch_output_offset
, lds_size
;
116 unsigned tcs_in_layout
, tcs_out_layout
, tcs_out_offsets
;
117 unsigned offchip_layout
, hardware_lds_size
, ls_hs_config
;
119 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
120 if (sctx
->b
.chip_class
>= GFX9
) {
121 if (sctx
->tcs_shader
.cso
)
122 ls_current
= sctx
->tcs_shader
.current
;
124 ls_current
= sctx
->fixed_func_tcs_shader
.current
;
126 ls
= ls_current
->key
.part
.tcs
.ls
;
128 ls_current
= sctx
->vs_shader
.current
;
129 ls
= sctx
->vs_shader
.cso
;
132 if (sctx
->last_ls
== ls_current
&&
133 sctx
->last_tcs
== tcs
&&
134 sctx
->last_tes_sh_base
== tes_sh_base
&&
135 sctx
->last_num_tcs_input_cp
== num_tcs_input_cp
&&
136 (!has_primid_instancing_bug
||
137 (sctx
->last_tess_uses_primid
== tess_uses_primid
))) {
138 *num_patches
= sctx
->last_num_patches
;
142 sctx
->last_ls
= ls_current
;
143 sctx
->last_tcs
= tcs
;
144 sctx
->last_tes_sh_base
= tes_sh_base
;
145 sctx
->last_num_tcs_input_cp
= num_tcs_input_cp
;
146 sctx
->last_tess_uses_primid
= tess_uses_primid
;
148 /* This calculates how shader inputs and outputs among VS, TCS, and TES
149 * are laid out in LDS. */
150 num_tcs_inputs
= util_last_bit64(ls
->outputs_written
);
152 if (sctx
->tcs_shader
.cso
) {
153 num_tcs_outputs
= util_last_bit64(tcs
->outputs_written
);
154 num_tcs_output_cp
= tcs
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
155 num_tcs_patch_outputs
= util_last_bit64(tcs
->patch_outputs_written
);
157 /* No TCS. Route varyings from LS to TES. */
158 num_tcs_outputs
= num_tcs_inputs
;
159 num_tcs_output_cp
= num_tcs_input_cp
;
160 num_tcs_patch_outputs
= 2; /* TESSINNER + TESSOUTER */
163 input_vertex_size
= num_tcs_inputs
* 16;
164 output_vertex_size
= num_tcs_outputs
* 16;
166 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
168 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
169 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
171 /* Ensure that we only need one wave per SIMD so we don't need to check
172 * resource usage. Also ensures that the number of tcs in and out
173 * vertices per threadgroup are at most 256.
175 *num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
177 /* Make sure that the data fits in LDS. This assumes the shaders only
178 * use LDS for the inputs and outputs.
180 * While CIK can use 64K per threadgroup, there is a hang on Stoney
181 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
182 * uses 32K at most on all GCN chips.
184 hardware_lds_size
= 32768;
185 *num_patches
= MIN2(*num_patches
, hardware_lds_size
/ (input_patch_size
+
188 /* Make sure the output data fits in the offchip buffer */
189 *num_patches
= MIN2(*num_patches
,
190 (sctx
->screen
->tess_offchip_block_dw_size
* 4) /
193 /* Not necessary for correctness, but improves performance. The
194 * specific value is taken from the proprietary driver.
196 *num_patches
= MIN2(*num_patches
, 40);
198 if (sctx
->b
.chip_class
== SI
) {
199 /* SI bug workaround, related to power management. Limit LS-HS
200 * threadgroups to only one wave.
202 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
203 *num_patches
= MIN2(*num_patches
, one_wave
);
206 /* The VGT HS block increments the patch ID unconditionally
207 * within a single threadgroup. This results in incorrect
208 * patch IDs when instanced draws are used.
210 * The intended solution is to restrict threadgroups to
211 * a single instance by setting SWITCH_ON_EOI, which
212 * should cause IA to split instances up. However, this
213 * doesn't work correctly on SI when there is no other
216 if (has_primid_instancing_bug
&& tess_uses_primid
)
219 sctx
->last_num_patches
= *num_patches
;
221 output_patch0_offset
= input_patch_size
* *num_patches
;
222 perpatch_output_offset
= output_patch0_offset
+ pervertex_output_patch_size
;
224 /* Compute userdata SGPRs. */
225 assert(((input_vertex_size
/ 4) & ~0xff) == 0);
226 assert(((output_vertex_size
/ 4) & ~0xff) == 0);
227 assert(((input_patch_size
/ 4) & ~0x1fff) == 0);
228 assert(((output_patch_size
/ 4) & ~0x1fff) == 0);
229 assert(((output_patch0_offset
/ 16) & ~0xffff) == 0);
230 assert(((perpatch_output_offset
/ 16) & ~0xffff) == 0);
231 assert(num_tcs_input_cp
<= 32);
232 assert(num_tcs_output_cp
<= 32);
234 uint64_t ring_va
= r600_resource(sctx
->tess_rings
)->gpu_address
;
235 assert((ring_va
& u_bit_consecutive(0, 19)) == 0);
237 tcs_in_layout
= S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size
/ 4) |
238 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size
/ 4);
239 tcs_out_layout
= (output_patch_size
/ 4) |
240 (num_tcs_input_cp
<< 13) |
242 tcs_out_offsets
= (output_patch0_offset
/ 16) |
243 ((perpatch_output_offset
/ 16) << 16);
244 offchip_layout
= *num_patches
|
245 (num_tcs_output_cp
<< 6) |
246 (pervertex_output_patch_size
* *num_patches
<< 12);
248 /* Compute the LDS size. */
249 lds_size
= output_patch0_offset
+ output_patch_size
* *num_patches
;
251 if (sctx
->b
.chip_class
>= CIK
) {
252 assert(lds_size
<= 65536);
253 lds_size
= align(lds_size
, 512) / 512;
255 assert(lds_size
<= 32768);
256 lds_size
= align(lds_size
, 256) / 256;
259 /* Set SI_SGPR_VS_STATE_BITS. */
260 sctx
->current_vs_state
&= C_VS_STATE_LS_OUT_PATCH_SIZE
&
261 C_VS_STATE_LS_OUT_VERTEX_SIZE
;
262 sctx
->current_vs_state
|= tcs_in_layout
;
264 if (sctx
->b
.chip_class
>= GFX9
) {
265 unsigned hs_rsrc2
= ls_current
->config
.rsrc2
|
266 S_00B42C_LDS_SIZE(lds_size
);
268 radeon_set_sh_reg(cs
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
, hs_rsrc2
);
270 /* Set userdata SGPRs for merged LS-HS. */
271 radeon_set_sh_reg_seq(cs
,
272 R_00B430_SPI_SHADER_USER_DATA_LS_0
+
273 GFX9_SGPR_TCS_OFFCHIP_LAYOUT
* 4, 3);
274 radeon_emit(cs
, offchip_layout
);
275 radeon_emit(cs
, tcs_out_offsets
);
276 radeon_emit(cs
, tcs_out_layout
);
278 unsigned ls_rsrc2
= ls_current
->config
.rsrc2
;
280 si_multiwave_lds_size_workaround(sctx
->screen
, &lds_size
);
281 ls_rsrc2
|= S_00B52C_LDS_SIZE(lds_size
);
283 /* Due to a hw bug, RSRC2_LS must be written twice with another
284 * LS register written in between. */
285 if (sctx
->b
.chip_class
== CIK
&& sctx
->b
.family
!= CHIP_HAWAII
)
286 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, ls_rsrc2
);
287 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
288 radeon_emit(cs
, ls_current
->config
.rsrc1
);
289 radeon_emit(cs
, ls_rsrc2
);
291 /* Set userdata SGPRs for TCS. */
292 radeon_set_sh_reg_seq(cs
,
293 R_00B430_SPI_SHADER_USER_DATA_HS_0
+ GFX6_SGPR_TCS_OFFCHIP_LAYOUT
* 4, 4);
294 radeon_emit(cs
, offchip_layout
);
295 radeon_emit(cs
, tcs_out_offsets
);
296 radeon_emit(cs
, tcs_out_layout
);
297 radeon_emit(cs
, tcs_in_layout
);
300 /* Set userdata SGPRs for TES. */
301 radeon_set_sh_reg_seq(cs
, tes_sh_base
+ SI_SGPR_TES_OFFCHIP_LAYOUT
* 4, 2);
302 radeon_emit(cs
, offchip_layout
);
303 radeon_emit(cs
, ring_va
);
305 ls_hs_config
= S_028B58_NUM_PATCHES(*num_patches
) |
306 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
307 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
309 if (sctx
->b
.chip_class
>= CIK
)
310 radeon_set_context_reg_idx(cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
313 radeon_set_context_reg(cs
, R_028B58_VGT_LS_HS_CONFIG
,
317 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info
*info
)
319 switch (info
->mode
) {
320 case PIPE_PRIM_PATCHES
:
321 return info
->count
/ info
->vertices_per_patch
;
322 case SI_PRIM_RECTANGLE_LIST
:
323 return info
->count
/ 3;
325 return u_prims_for_vertices(info
->mode
, info
->count
);
330 si_get_init_multi_vgt_param(struct si_screen
*sscreen
,
331 union si_vgt_param_key
*key
)
333 STATIC_ASSERT(sizeof(union si_vgt_param_key
) == 4);
334 unsigned max_primgroup_in_wave
= 2;
336 /* SWITCH_ON_EOP(0) is always preferable. */
337 bool wd_switch_on_eop
= false;
338 bool ia_switch_on_eop
= false;
339 bool ia_switch_on_eoi
= false;
340 bool partial_vs_wave
= false;
341 bool partial_es_wave
= false;
343 if (key
->u
.uses_tess
) {
344 /* SWITCH_ON_EOI must be set if PrimID is used. */
345 if (key
->u
.tess_uses_prim_id
)
346 ia_switch_on_eoi
= true;
348 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
349 if ((sscreen
->info
.family
== CHIP_TAHITI
||
350 sscreen
->info
.family
== CHIP_PITCAIRN
||
351 sscreen
->info
.family
== CHIP_BONAIRE
) &&
353 partial_vs_wave
= true;
355 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
356 if (sscreen
->has_distributed_tess
) {
357 if (key
->u
.uses_gs
) {
358 if (sscreen
->info
.chip_class
<= VI
)
359 partial_es_wave
= true;
361 /* GPU hang workaround. */
362 if (sscreen
->info
.family
== CHIP_TONGA
||
363 sscreen
->info
.family
== CHIP_FIJI
||
364 sscreen
->info
.family
== CHIP_POLARIS10
||
365 sscreen
->info
.family
== CHIP_POLARIS11
||
366 sscreen
->info
.family
== CHIP_POLARIS12
)
367 partial_vs_wave
= true;
369 partial_vs_wave
= true;
374 /* This is a hardware requirement. */
375 if (key
->u
.line_stipple_enabled
||
376 (sscreen
->debug_flags
& DBG(SWITCH_ON_EOP
))) {
377 ia_switch_on_eop
= true;
378 wd_switch_on_eop
= true;
381 if (sscreen
->info
.chip_class
>= CIK
) {
382 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
383 * 4 shader engines. Set 1 to pass the assertion below.
384 * The other cases are hardware requirements.
386 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
387 * for points, line strips, and tri strips.
389 if (sscreen
->info
.max_se
< 4 ||
390 key
->u
.prim
== PIPE_PRIM_POLYGON
||
391 key
->u
.prim
== PIPE_PRIM_LINE_LOOP
||
392 key
->u
.prim
== PIPE_PRIM_TRIANGLE_FAN
||
393 key
->u
.prim
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
||
394 (key
->u
.primitive_restart
&&
395 (sscreen
->info
.family
< CHIP_POLARIS10
||
396 (key
->u
.prim
!= PIPE_PRIM_POINTS
&&
397 key
->u
.prim
!= PIPE_PRIM_LINE_STRIP
&&
398 key
->u
.prim
!= PIPE_PRIM_TRIANGLE_STRIP
))) ||
399 key
->u
.count_from_stream_output
)
400 wd_switch_on_eop
= true;
402 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
403 * We don't know that for indirect drawing, so treat it as
404 * always problematic. */
405 if (sscreen
->info
.family
== CHIP_HAWAII
&&
406 key
->u
.uses_instancing
)
407 wd_switch_on_eop
= true;
409 /* Performance recommendation for 4 SE Gfx7-8 parts if
410 * instances are smaller than a primgroup.
411 * Assume indirect draws always use small instances.
412 * This is needed for good VS wave utilization.
414 if (sscreen
->info
.chip_class
<= VI
&&
415 sscreen
->info
.max_se
== 4 &&
416 key
->u
.multi_instances_smaller_than_primgroup
)
417 wd_switch_on_eop
= true;
419 /* Required on CIK and later. */
420 if (sscreen
->info
.max_se
> 2 && !wd_switch_on_eop
)
421 ia_switch_on_eoi
= true;
423 /* Required by Hawaii and, for some special cases, by VI. */
424 if (ia_switch_on_eoi
&&
425 (sscreen
->info
.family
== CHIP_HAWAII
||
426 (sscreen
->info
.chip_class
== VI
&&
427 (key
->u
.uses_gs
|| max_primgroup_in_wave
!= 2))))
428 partial_vs_wave
= true;
430 /* Instancing bug on Bonaire. */
431 if (sscreen
->info
.family
== CHIP_BONAIRE
&& ia_switch_on_eoi
&&
432 key
->u
.uses_instancing
)
433 partial_vs_wave
= true;
435 /* If the WD switch is false, the IA switch must be false too. */
436 assert(wd_switch_on_eop
|| !ia_switch_on_eop
);
439 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
440 if (sscreen
->info
.chip_class
<= VI
&& ia_switch_on_eoi
)
441 partial_es_wave
= true;
443 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
444 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi
) |
445 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
446 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave
) |
447 S_028AA8_WD_SWITCH_ON_EOP(sscreen
->info
.chip_class
>= CIK
? wd_switch_on_eop
: 0) |
448 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
449 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen
->info
.chip_class
== VI
?
450 max_primgroup_in_wave
: 0) |
451 S_030960_EN_INST_OPT_BASIC(sscreen
->info
.chip_class
>= GFX9
) |
452 S_030960_EN_INST_OPT_ADV(sscreen
->info
.chip_class
>= GFX9
);
455 void si_init_ia_multi_vgt_param_table(struct si_context
*sctx
)
457 for (int prim
= 0; prim
<= SI_PRIM_RECTANGLE_LIST
; prim
++)
458 for (int uses_instancing
= 0; uses_instancing
< 2; uses_instancing
++)
459 for (int multi_instances
= 0; multi_instances
< 2; multi_instances
++)
460 for (int primitive_restart
= 0; primitive_restart
< 2; primitive_restart
++)
461 for (int count_from_so
= 0; count_from_so
< 2; count_from_so
++)
462 for (int line_stipple
= 0; line_stipple
< 2; line_stipple
++)
463 for (int uses_tess
= 0; uses_tess
< 2; uses_tess
++)
464 for (int tess_uses_primid
= 0; tess_uses_primid
< 2; tess_uses_primid
++)
465 for (int uses_gs
= 0; uses_gs
< 2; uses_gs
++) {
466 union si_vgt_param_key key
;
470 key
.u
.uses_instancing
= uses_instancing
;
471 key
.u
.multi_instances_smaller_than_primgroup
= multi_instances
;
472 key
.u
.primitive_restart
= primitive_restart
;
473 key
.u
.count_from_stream_output
= count_from_so
;
474 key
.u
.line_stipple_enabled
= line_stipple
;
475 key
.u
.uses_tess
= uses_tess
;
476 key
.u
.tess_uses_prim_id
= tess_uses_primid
;
477 key
.u
.uses_gs
= uses_gs
;
479 sctx
->ia_multi_vgt_param
[key
.index
] =
480 si_get_init_multi_vgt_param(sctx
->screen
, &key
);
484 static unsigned si_get_ia_multi_vgt_param(struct si_context
*sctx
,
485 const struct pipe_draw_info
*info
,
486 unsigned num_patches
)
488 union si_vgt_param_key key
= sctx
->ia_multi_vgt_param_key
;
489 unsigned primgroup_size
;
490 unsigned ia_multi_vgt_param
;
492 if (sctx
->tes_shader
.cso
) {
493 primgroup_size
= num_patches
; /* must be a multiple of NUM_PATCHES */
494 } else if (sctx
->gs_shader
.cso
) {
495 primgroup_size
= 64; /* recommended with a GS */
497 primgroup_size
= 128; /* recommended without a GS and tess */
500 key
.u
.prim
= info
->mode
;
501 key
.u
.uses_instancing
= info
->indirect
|| info
->instance_count
> 1;
502 key
.u
.multi_instances_smaller_than_primgroup
=
504 (info
->instance_count
> 1 &&
505 (info
->count_from_stream_output
||
506 si_num_prims_for_vertices(info
) < primgroup_size
));
507 key
.u
.primitive_restart
= info
->primitive_restart
;
508 key
.u
.count_from_stream_output
= info
->count_from_stream_output
!= NULL
;
510 ia_multi_vgt_param
= sctx
->ia_multi_vgt_param
[key
.index
] |
511 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1);
513 if (sctx
->gs_shader
.cso
) {
514 /* GS requirement. */
515 if (sctx
->b
.chip_class
<= VI
&&
516 SI_GS_PER_ES
/ primgroup_size
>= sctx
->screen
->gs_table_depth
- 3)
517 ia_multi_vgt_param
|= S_028AA8_PARTIAL_ES_WAVE_ON(1);
519 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
520 * The hw doc says all multi-SE chips are affected, but Vulkan
521 * only applies it to Hawaii. Do what Vulkan does.
523 if (sctx
->b
.family
== CHIP_HAWAII
&&
524 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param
) &&
526 (info
->instance_count
> 1 &&
527 (info
->count_from_stream_output
||
528 si_num_prims_for_vertices(info
) <= 1))))
529 sctx
->b
.flags
|= SI_CONTEXT_VGT_FLUSH
;
532 return ia_multi_vgt_param
;
535 /* rast_prim is the primitive type after GS. */
536 static void si_emit_rasterizer_prim_state(struct si_context
*sctx
)
538 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
539 enum pipe_prim_type rast_prim
= sctx
->current_rast_prim
;
540 struct si_state_rasterizer
*rs
= sctx
->emitted
.named
.rasterizer
;
542 /* Skip this if not rendering lines. */
543 if (rast_prim
!= PIPE_PRIM_LINES
&&
544 rast_prim
!= PIPE_PRIM_LINE_LOOP
&&
545 rast_prim
!= PIPE_PRIM_LINE_STRIP
&&
546 rast_prim
!= PIPE_PRIM_LINES_ADJACENCY
&&
547 rast_prim
!= PIPE_PRIM_LINE_STRIP_ADJACENCY
)
550 if (rast_prim
== sctx
->last_rast_prim
&&
551 rs
->pa_sc_line_stipple
== sctx
->last_sc_line_stipple
)
554 /* For lines, reset the stipple pattern at each primitive. Otherwise,
555 * reset the stipple pattern at each packet (line strips, line loops).
557 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
558 rs
->pa_sc_line_stipple
|
559 S_028A0C_AUTO_RESET_CNTL(rast_prim
== PIPE_PRIM_LINES
? 1 : 2));
561 sctx
->last_rast_prim
= rast_prim
;
562 sctx
->last_sc_line_stipple
= rs
->pa_sc_line_stipple
;
565 static void si_emit_vs_state(struct si_context
*sctx
,
566 const struct pipe_draw_info
*info
)
568 sctx
->current_vs_state
&= C_VS_STATE_INDEXED
;
569 sctx
->current_vs_state
|= S_VS_STATE_INDEXED(!!info
->index_size
);
571 if (sctx
->num_vs_blit_sgprs
) {
572 /* Re-emit the state after we leave u_blitter. */
573 sctx
->last_vs_state
= ~0;
577 if (sctx
->current_vs_state
!= sctx
->last_vs_state
) {
578 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
580 radeon_set_sh_reg(cs
,
581 sctx
->shader_pointers
.sh_base
[PIPE_SHADER_VERTEX
] +
582 SI_SGPR_VS_STATE_BITS
* 4,
583 sctx
->current_vs_state
);
585 sctx
->last_vs_state
= sctx
->current_vs_state
;
589 static void si_emit_draw_registers(struct si_context
*sctx
,
590 const struct pipe_draw_info
*info
,
591 unsigned num_patches
)
593 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
594 unsigned prim
= si_conv_pipe_prim(info
->mode
);
595 unsigned gs_out_prim
= si_conv_prim_to_gs_out(sctx
->current_rast_prim
);
596 unsigned ia_multi_vgt_param
;
598 ia_multi_vgt_param
= si_get_ia_multi_vgt_param(sctx
, info
, num_patches
);
601 if (ia_multi_vgt_param
!= sctx
->last_multi_vgt_param
) {
602 if (sctx
->b
.chip_class
>= GFX9
)
603 radeon_set_uconfig_reg_idx(cs
, R_030960_IA_MULTI_VGT_PARAM
, 4, ia_multi_vgt_param
);
604 else if (sctx
->b
.chip_class
>= CIK
)
605 radeon_set_context_reg_idx(cs
, R_028AA8_IA_MULTI_VGT_PARAM
, 1, ia_multi_vgt_param
);
607 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
, ia_multi_vgt_param
);
609 sctx
->last_multi_vgt_param
= ia_multi_vgt_param
;
611 if (prim
!= sctx
->last_prim
) {
612 if (sctx
->b
.chip_class
>= CIK
)
613 radeon_set_uconfig_reg_idx(cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
615 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
617 sctx
->last_prim
= prim
;
620 if (gs_out_prim
!= sctx
->last_gs_out_prim
) {
621 radeon_set_context_reg(cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out_prim
);
622 sctx
->last_gs_out_prim
= gs_out_prim
;
625 /* Primitive restart. */
626 if (info
->primitive_restart
!= sctx
->last_primitive_restart_en
) {
627 if (sctx
->b
.chip_class
>= GFX9
)
628 radeon_set_uconfig_reg(cs
, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
629 info
->primitive_restart
);
631 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
632 info
->primitive_restart
);
634 sctx
->last_primitive_restart_en
= info
->primitive_restart
;
637 if (info
->primitive_restart
&&
638 (info
->restart_index
!= sctx
->last_restart_index
||
639 sctx
->last_restart_index
== SI_RESTART_INDEX_UNKNOWN
)) {
640 radeon_set_context_reg(cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
641 info
->restart_index
);
642 sctx
->last_restart_index
= info
->restart_index
;
646 static void si_emit_draw_packets(struct si_context
*sctx
,
647 const struct pipe_draw_info
*info
,
648 struct pipe_resource
*indexbuf
,
650 unsigned index_offset
)
652 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
653 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
654 unsigned sh_base_reg
= sctx
->shader_pointers
.sh_base
[PIPE_SHADER_VERTEX
];
655 bool render_cond_bit
= sctx
->b
.render_cond
&& !sctx
->b
.render_cond_force_off
;
656 uint32_t index_max_size
= 0;
657 uint64_t index_va
= 0;
659 if (info
->count_from_stream_output
) {
660 struct si_streamout_target
*t
=
661 (struct si_streamout_target
*)info
->count_from_stream_output
;
662 uint64_t va
= t
->buf_filled_size
->gpu_address
+
663 t
->buf_filled_size_offset
;
665 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
668 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
669 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
670 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
671 COPY_DATA_WR_CONFIRM
);
672 radeon_emit(cs
, va
); /* src address lo */
673 radeon_emit(cs
, va
>> 32); /* src address hi */
674 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
675 radeon_emit(cs
, 0); /* unused */
677 radeon_add_to_buffer_list(&sctx
->b
, sctx
->b
.gfx_cs
,
678 t
->buf_filled_size
, RADEON_USAGE_READ
,
679 RADEON_PRIO_SO_FILLED_SIZE
);
684 if (index_size
!= sctx
->last_index_size
) {
688 switch (index_size
) {
690 index_type
= V_028A7C_VGT_INDEX_8
;
693 index_type
= V_028A7C_VGT_INDEX_16
|
694 (SI_BIG_ENDIAN
&& sctx
->b
.chip_class
<= CIK
?
695 V_028A7C_VGT_DMA_SWAP_16_BIT
: 0);
698 index_type
= V_028A7C_VGT_INDEX_32
|
699 (SI_BIG_ENDIAN
&& sctx
->b
.chip_class
<= CIK
?
700 V_028A7C_VGT_DMA_SWAP_32_BIT
: 0);
703 assert(!"unreachable");
707 if (sctx
->b
.chip_class
>= GFX9
) {
708 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
711 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
712 radeon_emit(cs
, index_type
);
715 sctx
->last_index_size
= index_size
;
718 index_max_size
= (indexbuf
->width0
- index_offset
) /
720 index_va
= r600_resource(indexbuf
)->gpu_address
+ index_offset
;
722 radeon_add_to_buffer_list(&sctx
->b
, sctx
->b
.gfx_cs
,
723 (struct r600_resource
*)indexbuf
,
724 RADEON_USAGE_READ
, RADEON_PRIO_INDEX_BUFFER
);
726 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
727 * so the state must be re-emitted before the next indexed draw.
729 if (sctx
->b
.chip_class
>= CIK
)
730 sctx
->last_index_size
= -1;
734 uint64_t indirect_va
= r600_resource(indirect
->buffer
)->gpu_address
;
736 assert(indirect_va
% 8 == 0);
738 si_invalidate_draw_sh_constants(sctx
);
740 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
742 radeon_emit(cs
, indirect_va
);
743 radeon_emit(cs
, indirect_va
>> 32);
745 radeon_add_to_buffer_list(&sctx
->b
, sctx
->b
.gfx_cs
,
746 (struct r600_resource
*)indirect
->buffer
,
747 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
749 unsigned di_src_sel
= index_size
? V_0287F0_DI_SRC_SEL_DMA
750 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
752 assert(indirect
->offset
% 4 == 0);
755 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
756 radeon_emit(cs
, index_va
);
757 radeon_emit(cs
, index_va
>> 32);
759 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
760 radeon_emit(cs
, index_max_size
);
763 if (!sctx
->screen
->has_draw_indirect_multi
) {
764 radeon_emit(cs
, PKT3(index_size
? PKT3_DRAW_INDEX_INDIRECT
765 : PKT3_DRAW_INDIRECT
,
766 3, render_cond_bit
));
767 radeon_emit(cs
, indirect
->offset
);
768 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
769 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
770 radeon_emit(cs
, di_src_sel
);
772 uint64_t count_va
= 0;
774 if (indirect
->indirect_draw_count
) {
775 struct r600_resource
*params_buf
=
776 (struct r600_resource
*)indirect
->indirect_draw_count
;
778 radeon_add_to_buffer_list(
779 &sctx
->b
, sctx
->b
.gfx_cs
, params_buf
,
780 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
782 count_va
= params_buf
->gpu_address
+ indirect
->indirect_draw_count_offset
;
785 radeon_emit(cs
, PKT3(index_size
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
786 PKT3_DRAW_INDIRECT_MULTI
,
787 8, render_cond_bit
));
788 radeon_emit(cs
, indirect
->offset
);
789 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
790 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
791 radeon_emit(cs
, ((sh_base_reg
+ SI_SGPR_DRAWID
* 4 - SI_SH_REG_OFFSET
) >> 2) |
792 S_2C3_DRAW_INDEX_ENABLE(1) |
793 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect
->indirect_draw_count
));
794 radeon_emit(cs
, indirect
->draw_count
);
795 radeon_emit(cs
, count_va
);
796 radeon_emit(cs
, count_va
>> 32);
797 radeon_emit(cs
, indirect
->stride
);
798 radeon_emit(cs
, di_src_sel
);
803 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
804 radeon_emit(cs
, info
->instance_count
);
806 /* Base vertex and start instance. */
807 base_vertex
= index_size
? info
->index_bias
: info
->start
;
809 if (sctx
->num_vs_blit_sgprs
) {
810 /* Re-emit draw constants after we leave u_blitter. */
811 si_invalidate_draw_sh_constants(sctx
);
813 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
814 radeon_set_sh_reg_seq(cs
, sh_base_reg
+ SI_SGPR_VS_BLIT_DATA
* 4,
815 sctx
->num_vs_blit_sgprs
);
816 radeon_emit_array(cs
, sctx
->vs_blit_sh_data
,
817 sctx
->num_vs_blit_sgprs
);
818 } else if (base_vertex
!= sctx
->last_base_vertex
||
819 sctx
->last_base_vertex
== SI_BASE_VERTEX_UNKNOWN
||
820 info
->start_instance
!= sctx
->last_start_instance
||
821 info
->drawid
!= sctx
->last_drawid
||
822 sh_base_reg
!= sctx
->last_sh_base_reg
) {
823 radeon_set_sh_reg_seq(cs
, sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4, 3);
824 radeon_emit(cs
, base_vertex
);
825 radeon_emit(cs
, info
->start_instance
);
826 radeon_emit(cs
, info
->drawid
);
828 sctx
->last_base_vertex
= base_vertex
;
829 sctx
->last_start_instance
= info
->start_instance
;
830 sctx
->last_drawid
= info
->drawid
;
831 sctx
->last_sh_base_reg
= sh_base_reg
;
835 index_va
+= info
->start
* index_size
;
837 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, render_cond_bit
));
838 radeon_emit(cs
, index_max_size
);
839 radeon_emit(cs
, index_va
);
840 radeon_emit(cs
, index_va
>> 32);
841 radeon_emit(cs
, info
->count
);
842 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
844 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
845 radeon_emit(cs
, info
->count
);
846 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
847 S_0287F0_USE_OPAQUE(!!info
->count_from_stream_output
));
852 static void si_emit_surface_sync(struct si_context
*sctx
,
853 unsigned cp_coher_cntl
)
855 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
857 if (sctx
->b
.chip_class
>= GFX9
) {
858 /* Flush caches and wait for the caches to assert idle. */
859 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 5, 0));
860 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
861 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
862 radeon_emit(cs
, 0xffffff); /* CP_COHER_SIZE_HI */
863 radeon_emit(cs
, 0); /* CP_COHER_BASE */
864 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
865 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
867 /* ACQUIRE_MEM is only required on a compute ring. */
868 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, 0));
869 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
870 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
871 radeon_emit(cs
, 0); /* CP_COHER_BASE */
872 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
876 void si_emit_cache_flush(struct si_context
*sctx
)
878 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
879 uint32_t flags
= sctx
->b
.flags
;
880 uint32_t cp_coher_cntl
= 0;
881 uint32_t flush_cb_db
= flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
|
882 SI_CONTEXT_FLUSH_AND_INV_DB
);
884 if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
)
885 sctx
->b
.num_cb_cache_flushes
++;
886 if (flags
& SI_CONTEXT_FLUSH_AND_INV_DB
)
887 sctx
->b
.num_db_cache_flushes
++;
889 /* SI has a bug that it always flushes ICACHE and KCACHE if either
890 * bit is set. An alternative way is to write SQC_CACHES, but that
891 * doesn't seem to work reliably. Since the bug doesn't affect
892 * correctness (it only does more work than necessary) and
893 * the performance impact is likely negligible, there is no plan
894 * to add a workaround for it.
897 if (flags
& SI_CONTEXT_INV_ICACHE
)
898 cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1);
899 if (flags
& SI_CONTEXT_INV_SMEM_L1
)
900 cp_coher_cntl
|= S_0085F0_SH_KCACHE_ACTION_ENA(1);
902 if (sctx
->b
.chip_class
<= VI
) {
903 if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
904 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
905 S_0085F0_CB0_DEST_BASE_ENA(1) |
906 S_0085F0_CB1_DEST_BASE_ENA(1) |
907 S_0085F0_CB2_DEST_BASE_ENA(1) |
908 S_0085F0_CB3_DEST_BASE_ENA(1) |
909 S_0085F0_CB4_DEST_BASE_ENA(1) |
910 S_0085F0_CB5_DEST_BASE_ENA(1) |
911 S_0085F0_CB6_DEST_BASE_ENA(1) |
912 S_0085F0_CB7_DEST_BASE_ENA(1);
914 /* Necessary for DCC */
915 if (sctx
->b
.chip_class
== VI
)
916 si_gfx_write_event_eop(sctx
, V_028A90_FLUSH_AND_INV_CB_DATA_TS
,
917 0, EOP_DATA_SEL_DISCARD
, NULL
,
920 if (flags
& SI_CONTEXT_FLUSH_AND_INV_DB
)
921 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
922 S_0085F0_DB_DEST_BASE_ENA(1);
925 if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
926 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
927 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
928 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
930 if (flags
& (SI_CONTEXT_FLUSH_AND_INV_DB
|
931 SI_CONTEXT_FLUSH_AND_INV_DB_META
)) {
932 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
933 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
934 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
937 /* Wait for shader engines to go idle.
938 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
939 * for everything including CB/DB cache flushes.
942 if (flags
& SI_CONTEXT_PS_PARTIAL_FLUSH
) {
943 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
944 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
945 /* Only count explicit shader flushes, not implicit ones
946 * done by SURFACE_SYNC.
948 sctx
->b
.num_vs_flushes
++;
949 sctx
->b
.num_ps_flushes
++;
950 } else if (flags
& SI_CONTEXT_VS_PARTIAL_FLUSH
) {
951 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
952 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
953 sctx
->b
.num_vs_flushes
++;
957 if (flags
& SI_CONTEXT_CS_PARTIAL_FLUSH
&&
958 sctx
->compute_is_busy
) {
959 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
960 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
| EVENT_INDEX(4)));
961 sctx
->b
.num_cs_flushes
++;
962 sctx
->compute_is_busy
= false;
965 /* VGT state synchronization. */
966 if (flags
& SI_CONTEXT_VGT_FLUSH
) {
967 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
968 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
970 if (flags
& SI_CONTEXT_VGT_STREAMOUT_SYNC
) {
971 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
972 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC
) | EVENT_INDEX(0));
975 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
976 * wait for idle on GFX9. We have to use a TS event.
978 if (sctx
->b
.chip_class
>= GFX9
&& flush_cb_db
) {
980 unsigned tc_flags
, cb_db_event
;
982 /* Set the CB/DB flush event. */
983 switch (flush_cb_db
) {
984 case SI_CONTEXT_FLUSH_AND_INV_CB
:
985 cb_db_event
= V_028A90_FLUSH_AND_INV_CB_DATA_TS
;
987 case SI_CONTEXT_FLUSH_AND_INV_DB
:
988 cb_db_event
= V_028A90_FLUSH_AND_INV_DB_DATA_TS
;
992 cb_db_event
= V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
;
995 /* These are the only allowed combinations. If you need to
996 * do multiple operations at once, do them separately.
997 * All operations that invalidate L2 also seem to invalidate
998 * metadata. Volatile (VOL) and WC flushes are not listed here.
1000 * TC | TC_WB = writeback & invalidate L2 & L1
1001 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1002 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1003 * TC | TC_NC = invalidate L2 for MTYPE == NC
1004 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1005 * TCL1 = invalidate L1
1009 if (flags
& SI_CONTEXT_INV_L2_METADATA
) {
1010 tc_flags
= EVENT_TC_ACTION_ENA
|
1011 EVENT_TC_MD_ACTION_ENA
;
1014 /* Ideally flush TC together with CB/DB. */
1015 if (flags
& SI_CONTEXT_INV_GLOBAL_L2
) {
1016 /* Writeback and invalidate everything in L2 & L1. */
1017 tc_flags
= EVENT_TC_ACTION_ENA
|
1018 EVENT_TC_WB_ACTION_ENA
;
1020 /* Clear the flags. */
1021 flags
&= ~(SI_CONTEXT_INV_GLOBAL_L2
|
1022 SI_CONTEXT_WRITEBACK_GLOBAL_L2
|
1023 SI_CONTEXT_INV_VMEM_L1
);
1024 sctx
->b
.num_L2_invalidates
++;
1027 /* Do the flush (enqueue the event and wait for it). */
1028 va
= sctx
->wait_mem_scratch
->gpu_address
;
1029 sctx
->wait_mem_number
++;
1031 si_gfx_write_event_eop(sctx
, cb_db_event
, tc_flags
,
1032 EOP_DATA_SEL_VALUE_32BIT
,
1033 sctx
->wait_mem_scratch
, va
,
1034 sctx
->wait_mem_number
, SI_NOT_QUERY
);
1035 si_gfx_wait_fence(sctx
, va
, sctx
->wait_mem_number
, 0xffffffff);
1038 /* Make sure ME is idle (it executes most packets) before continuing.
1039 * This prevents read-after-write hazards between PFP and ME.
1041 if (cp_coher_cntl
||
1042 (flags
& (SI_CONTEXT_CS_PARTIAL_FLUSH
|
1043 SI_CONTEXT_INV_VMEM_L1
|
1044 SI_CONTEXT_INV_GLOBAL_L2
|
1045 SI_CONTEXT_WRITEBACK_GLOBAL_L2
))) {
1046 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1051 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1052 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1054 * cp_coher_cntl should contain all necessary flags except TC flags
1057 * SI-CIK don't support L2 write-back.
1059 if (flags
& SI_CONTEXT_INV_GLOBAL_L2
||
1060 (sctx
->b
.chip_class
<= CIK
&&
1061 (flags
& SI_CONTEXT_WRITEBACK_GLOBAL_L2
))) {
1062 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
1063 * WB must be set on VI+ when TC_ACTION is set.
1065 si_emit_surface_sync(sctx
, cp_coher_cntl
|
1066 S_0085F0_TC_ACTION_ENA(1) |
1067 S_0085F0_TCL1_ACTION_ENA(1) |
1068 S_0301F0_TC_WB_ACTION_ENA(sctx
->b
.chip_class
>= VI
));
1070 sctx
->b
.num_L2_invalidates
++;
1072 /* L1 invalidation and L2 writeback must be done separately,
1073 * because both operations can't be done together.
1075 if (flags
& SI_CONTEXT_WRITEBACK_GLOBAL_L2
) {
1077 * NC = apply to non-coherent MTYPEs
1078 * (i.e. MTYPE <= 1, which is what we use everywhere)
1080 * WB doesn't work without NC.
1082 si_emit_surface_sync(sctx
, cp_coher_cntl
|
1083 S_0301F0_TC_WB_ACTION_ENA(1) |
1084 S_0301F0_TC_NC_ACTION_ENA(1));
1086 sctx
->b
.num_L2_writebacks
++;
1088 if (flags
& SI_CONTEXT_INV_VMEM_L1
) {
1089 /* Invalidate per-CU VMEM L1. */
1090 si_emit_surface_sync(sctx
, cp_coher_cntl
|
1091 S_0085F0_TCL1_ACTION_ENA(1));
1096 /* If TC flushes haven't cleared this... */
1098 si_emit_surface_sync(sctx
, cp_coher_cntl
);
1100 if (flags
& SI_CONTEXT_START_PIPELINE_STATS
) {
1101 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1102 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
1104 } else if (flags
& SI_CONTEXT_STOP_PIPELINE_STATS
) {
1105 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1106 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP
) |
1113 static void si_get_draw_start_count(struct si_context
*sctx
,
1114 const struct pipe_draw_info
*info
,
1115 unsigned *start
, unsigned *count
)
1117 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
1120 unsigned indirect_count
;
1121 struct pipe_transfer
*transfer
;
1122 unsigned begin
, end
;
1126 if (indirect
->indirect_draw_count
) {
1127 data
= pipe_buffer_map_range(&sctx
->b
.b
,
1128 indirect
->indirect_draw_count
,
1129 indirect
->indirect_draw_count_offset
,
1131 PIPE_TRANSFER_READ
, &transfer
);
1133 indirect_count
= *data
;
1135 pipe_buffer_unmap(&sctx
->b
.b
, transfer
);
1137 indirect_count
= indirect
->draw_count
;
1140 if (!indirect_count
) {
1141 *start
= *count
= 0;
1145 map_size
= (indirect_count
- 1) * indirect
->stride
+ 3 * sizeof(unsigned);
1146 data
= pipe_buffer_map_range(&sctx
->b
.b
, indirect
->buffer
,
1147 indirect
->offset
, map_size
,
1148 PIPE_TRANSFER_READ
, &transfer
);
1153 for (unsigned i
= 0; i
< indirect_count
; ++i
) {
1154 unsigned count
= data
[0];
1155 unsigned start
= data
[2];
1158 begin
= MIN2(begin
, start
);
1159 end
= MAX2(end
, start
+ count
);
1162 data
+= indirect
->stride
/ sizeof(unsigned);
1165 pipe_buffer_unmap(&sctx
->b
.b
, transfer
);
1169 *count
= end
- begin
;
1171 *start
= *count
= 0;
1174 *start
= info
->start
;
1175 *count
= info
->count
;
1179 static void si_emit_all_states(struct si_context
*sctx
, const struct pipe_draw_info
*info
,
1180 unsigned skip_atom_mask
)
1182 /* Emit state atoms. */
1183 unsigned mask
= sctx
->dirty_atoms
& ~skip_atom_mask
;
1185 struct r600_atom
*atom
= sctx
->atoms
.array
[u_bit_scan(&mask
)];
1187 atom
->emit(sctx
, atom
);
1189 sctx
->dirty_atoms
&= skip_atom_mask
;
1192 mask
= sctx
->dirty_states
;
1194 unsigned i
= u_bit_scan(&mask
);
1195 struct si_pm4_state
*state
= sctx
->queued
.array
[i
];
1197 if (!state
|| sctx
->emitted
.array
[i
] == state
)
1200 si_pm4_emit(sctx
, state
);
1201 sctx
->emitted
.array
[i
] = state
;
1203 sctx
->dirty_states
= 0;
1205 /* Emit draw states. */
1206 unsigned num_patches
= 0;
1208 si_emit_rasterizer_prim_state(sctx
);
1209 if (sctx
->tes_shader
.cso
)
1210 si_emit_derived_tess_state(sctx
, info
, &num_patches
);
1211 si_emit_vs_state(sctx
, info
);
1212 si_emit_draw_registers(sctx
, info
, num_patches
);
1215 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
1217 struct si_context
*sctx
= (struct si_context
*)ctx
;
1218 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1219 struct pipe_resource
*indexbuf
= info
->index
.resource
;
1220 unsigned dirty_tex_counter
;
1221 enum pipe_prim_type rast_prim
;
1222 unsigned index_size
= info
->index_size
;
1223 unsigned index_offset
= info
->indirect
? info
->start
* index_size
: 0;
1225 if (likely(!info
->indirect
)) {
1226 /* SI-CI treat instance_count==0 as instance_count==1. There is
1227 * no workaround for indirect draws, but we can at least skip
1230 if (unlikely(!info
->instance_count
))
1233 /* Handle count == 0. */
1234 if (unlikely(!info
->count
&&
1235 (index_size
|| !info
->count_from_stream_output
)))
1239 if (unlikely(!sctx
->vs_shader
.cso
)) {
1243 if (unlikely(!sctx
->ps_shader
.cso
&& (!rs
|| !rs
->rasterizer_discard
))) {
1247 if (unlikely(!!sctx
->tes_shader
.cso
!= (info
->mode
== PIPE_PRIM_PATCHES
))) {
1252 /* Recompute and re-emit the texture resource states if needed. */
1253 dirty_tex_counter
= p_atomic_read(&sctx
->b
.screen
->dirty_tex_counter
);
1254 if (unlikely(dirty_tex_counter
!= sctx
->b
.last_dirty_tex_counter
)) {
1255 sctx
->b
.last_dirty_tex_counter
= dirty_tex_counter
;
1256 sctx
->framebuffer
.dirty_cbufs
|=
1257 ((1 << sctx
->framebuffer
.state
.nr_cbufs
) - 1);
1258 sctx
->framebuffer
.dirty_zsbuf
= true;
1259 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
);
1260 si_update_all_texture_descriptors(sctx
);
1263 si_decompress_textures(sctx
, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS
));
1265 /* Set the rasterization primitive type.
1267 * This must be done after si_decompress_textures, which can call
1268 * draw_vbo recursively, and before si_update_shaders, which uses
1269 * current_rast_prim for this draw_vbo call. */
1270 if (sctx
->gs_shader
.cso
)
1271 rast_prim
= sctx
->gs_shader
.cso
->gs_output_prim
;
1272 else if (sctx
->tes_shader
.cso
) {
1273 if (sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
1274 rast_prim
= PIPE_PRIM_POINTS
;
1276 rast_prim
= sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1278 rast_prim
= info
->mode
;
1280 if (rast_prim
!= sctx
->current_rast_prim
) {
1281 bool old_is_poly
= sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES
;
1282 bool new_is_poly
= rast_prim
>= PIPE_PRIM_TRIANGLES
;
1283 if (old_is_poly
!= new_is_poly
) {
1284 sctx
->scissors
.dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1285 si_mark_atom_dirty(sctx
, &sctx
->scissors
.atom
);
1288 sctx
->current_rast_prim
= rast_prim
;
1289 sctx
->do_update_shaders
= true;
1292 if (sctx
->tes_shader
.cso
&&
1293 sctx
->screen
->has_ls_vgpr_init_bug
) {
1294 /* Determine whether the LS VGPR fix should be applied.
1296 * It is only required when num input CPs > num output CPs,
1297 * which cannot happen with the fixed function TCS. We should
1298 * also update this bit when switching from TCS to fixed
1301 struct si_shader_selector
*tcs
= sctx
->tcs_shader
.cso
;
1304 info
->vertices_per_patch
>
1305 tcs
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
1307 if (ls_vgpr_fix
!= sctx
->ls_vgpr_fix
) {
1308 sctx
->ls_vgpr_fix
= ls_vgpr_fix
;
1309 sctx
->do_update_shaders
= true;
1313 if (sctx
->gs_shader
.cso
) {
1314 /* Determine whether the GS triangle strip adjacency fix should
1315 * be applied. Rotate every other triangle if
1316 * - triangle strips with adjacency are fed to the GS and
1317 * - primitive restart is disabled (the rotation doesn't help
1318 * when the restart occurs after an odd number of triangles).
1320 bool gs_tri_strip_adj_fix
=
1321 !sctx
->tes_shader
.cso
&&
1322 info
->mode
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
&&
1323 !info
->primitive_restart
;
1325 if (gs_tri_strip_adj_fix
!= sctx
->gs_tri_strip_adj_fix
) {
1326 sctx
->gs_tri_strip_adj_fix
= gs_tri_strip_adj_fix
;
1327 sctx
->do_update_shaders
= true;
1331 if (sctx
->do_update_shaders
&& !si_update_shaders(sctx
))
1335 /* Translate or upload, if needed. */
1336 /* 8-bit indices are supported on VI. */
1337 if (sctx
->b
.chip_class
<= CIK
&& index_size
== 1) {
1338 unsigned start
, count
, start_offset
, size
, offset
;
1341 si_get_draw_start_count(sctx
, info
, &start
, &count
);
1342 start_offset
= start
* 2;
1346 u_upload_alloc(ctx
->stream_uploader
, start_offset
,
1348 si_optimal_tcc_alignment(sctx
, size
),
1349 &offset
, &indexbuf
, &ptr
);
1353 util_shorten_ubyte_elts_to_userptr(&sctx
->b
.b
, info
, 0, 0,
1354 index_offset
+ start
,
1357 /* info->start will be added by the drawing code */
1358 index_offset
= offset
- start_offset
;
1360 } else if (info
->has_user_indices
) {
1361 unsigned start_offset
;
1363 assert(!info
->indirect
);
1364 start_offset
= info
->start
* index_size
;
1367 u_upload_data(ctx
->stream_uploader
, start_offset
,
1368 info
->count
* index_size
,
1369 sctx
->screen
->info
.tcc_cache_line_size
,
1370 (char*)info
->index
.user
+ start_offset
,
1371 &index_offset
, &indexbuf
);
1375 /* info->start will be added by the drawing code */
1376 index_offset
-= start_offset
;
1377 } else if (sctx
->b
.chip_class
<= CIK
&&
1378 r600_resource(indexbuf
)->TC_L2_dirty
) {
1379 /* VI reads index buffers through TC L2, so it doesn't
1381 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1382 r600_resource(indexbuf
)->TC_L2_dirty
= false;
1386 if (info
->indirect
) {
1387 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
1389 /* Add the buffer size for memory checking in need_cs_space. */
1390 si_context_add_resource_size(ctx
, indirect
->buffer
);
1392 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1393 if (sctx
->b
.chip_class
<= VI
) {
1394 if (r600_resource(indirect
->buffer
)->TC_L2_dirty
) {
1395 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1396 r600_resource(indirect
->buffer
)->TC_L2_dirty
= false;
1399 if (indirect
->indirect_draw_count
&&
1400 r600_resource(indirect
->indirect_draw_count
)->TC_L2_dirty
) {
1401 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1402 r600_resource(indirect
->indirect_draw_count
)->TC_L2_dirty
= false;
1407 si_need_gfx_cs_space(sctx
);
1409 /* Since we've called r600_context_add_resource_size for vertex buffers,
1410 * this must be called after si_need_cs_space, because we must let
1411 * need_cs_space flush before we add buffers to the buffer list.
1413 if (!si_upload_vertex_buffer_descriptors(sctx
))
1416 /* Vega10/Raven scissor bug workaround. This must be done before VPORT
1417 * scissor registers are changed. There is also a more efficient but
1418 * more involved alternative workaround.
1420 if ((sctx
->b
.family
== CHIP_VEGA10
|| sctx
->b
.family
== CHIP_RAVEN
) &&
1421 si_is_atom_dirty(sctx
, &sctx
->scissors
.atom
)) {
1422 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
;
1423 si_emit_cache_flush(sctx
);
1426 /* Use optimal packet order based on whether we need to sync the pipeline. */
1427 if (unlikely(sctx
->b
.flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
|
1428 SI_CONTEXT_FLUSH_AND_INV_DB
|
1429 SI_CONTEXT_PS_PARTIAL_FLUSH
|
1430 SI_CONTEXT_CS_PARTIAL_FLUSH
))) {
1431 /* If we have to wait for idle, set all states first, so that all
1432 * SET packets are processed in parallel with previous draw calls.
1433 * Then upload descriptors, set shader pointers, and draw, and
1434 * prefetch at the end. This ensures that the time the CUs
1435 * are idle is very short. (there are only SET_SH packets between
1436 * the wait and the draw)
1438 struct r600_atom
*shader_pointers
= &sctx
->shader_pointers
.atom
;
1439 unsigned masked_atoms
= 1u << shader_pointers
->id
;
1441 if (unlikely(sctx
->b
.flags
& SI_CONTEXT_FLUSH_FOR_RENDER_COND
))
1442 masked_atoms
|= 1u << sctx
->b
.render_cond_atom
.id
;
1444 /* Emit all states except shader pointers and render condition. */
1445 si_emit_all_states(sctx
, info
, masked_atoms
);
1446 si_emit_cache_flush(sctx
);
1448 /* <-- CUs are idle here. */
1449 if (!si_upload_graphics_shader_descriptors(sctx
))
1452 /* Set shader pointers after descriptors are uploaded. */
1453 if (si_is_atom_dirty(sctx
, shader_pointers
))
1454 shader_pointers
->emit(sctx
, NULL
);
1455 if (si_is_atom_dirty(sctx
, &sctx
->b
.render_cond_atom
))
1456 sctx
->b
.render_cond_atom
.emit(sctx
, NULL
);
1457 sctx
->dirty_atoms
= 0;
1459 si_emit_draw_packets(sctx
, info
, indexbuf
, index_size
, index_offset
);
1460 /* <-- CUs are busy here. */
1462 /* Start prefetches after the draw has been started. Both will run
1463 * in parallel, but starting the draw first is more important.
1465 if (sctx
->b
.chip_class
>= CIK
&& sctx
->prefetch_L2_mask
)
1466 cik_emit_prefetch_L2(sctx
);
1468 /* If we don't wait for idle, start prefetches first, then set
1469 * states, and draw at the end.
1472 si_emit_cache_flush(sctx
);
1474 if (sctx
->b
.chip_class
>= CIK
&& sctx
->prefetch_L2_mask
)
1475 cik_emit_prefetch_L2(sctx
);
1477 if (!si_upload_graphics_shader_descriptors(sctx
))
1480 si_emit_all_states(sctx
, info
, 0);
1481 si_emit_draw_packets(sctx
, info
, indexbuf
, index_size
, index_offset
);
1484 if (unlikely(sctx
->current_saved_cs
)) {
1485 si_trace_emit(sctx
);
1486 si_log_draw_state(sctx
, sctx
->b
.log
);
1489 /* Workaround for a VGT hang when streamout is enabled.
1490 * It must be done after drawing. */
1491 if ((sctx
->b
.family
== CHIP_HAWAII
||
1492 sctx
->b
.family
== CHIP_TONGA
||
1493 sctx
->b
.family
== CHIP_FIJI
) &&
1494 si_get_strmout_en(sctx
)) {
1495 sctx
->b
.flags
|= SI_CONTEXT_VGT_STREAMOUT_SYNC
;
1498 if (unlikely(sctx
->decompression_enabled
)) {
1499 sctx
->b
.num_decompress_calls
++;
1501 sctx
->b
.num_draw_calls
++;
1502 if (sctx
->framebuffer
.state
.nr_cbufs
> 1)
1503 sctx
->b
.num_mrt_draw_calls
++;
1504 if (info
->primitive_restart
)
1505 sctx
->b
.num_prim_restart_calls
++;
1506 if (G_0286E8_WAVESIZE(sctx
->spi_tmpring_size
))
1507 sctx
->b
.num_spill_draw_calls
++;
1509 if (index_size
&& indexbuf
!= info
->index
.resource
)
1510 pipe_resource_reference(&indexbuf
, NULL
);
1513 void si_draw_rectangle(struct blitter_context
*blitter
,
1514 void *vertex_elements_cso
,
1515 blitter_get_vs_func get_vs
,
1516 int x1
, int y1
, int x2
, int y2
,
1517 float depth
, unsigned num_instances
,
1518 enum blitter_attrib_type type
,
1519 const union blitter_attrib
*attrib
)
1521 struct pipe_context
*pipe
= util_blitter_get_pipe(blitter
);
1522 struct si_context
*sctx
= (struct si_context
*)pipe
;
1524 /* Pack position coordinates as signed int16. */
1525 sctx
->vs_blit_sh_data
[0] = (uint32_t)(x1
& 0xffff) |
1526 ((uint32_t)(y1
& 0xffff) << 16);
1527 sctx
->vs_blit_sh_data
[1] = (uint32_t)(x2
& 0xffff) |
1528 ((uint32_t)(y2
& 0xffff) << 16);
1529 sctx
->vs_blit_sh_data
[2] = fui(depth
);
1532 case UTIL_BLITTER_ATTRIB_COLOR
:
1533 memcpy(&sctx
->vs_blit_sh_data
[3], attrib
->color
,
1536 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY
:
1537 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW
:
1538 memcpy(&sctx
->vs_blit_sh_data
[3], &attrib
->texcoord
,
1539 sizeof(attrib
->texcoord
));
1541 case UTIL_BLITTER_ATTRIB_NONE
:;
1544 pipe
->bind_vs_state(pipe
, si_get_blit_vs(sctx
, type
, num_instances
));
1546 struct pipe_draw_info info
= {};
1547 info
.mode
= SI_PRIM_RECTANGLE_LIST
;
1549 info
.instance_count
= num_instances
;
1551 /* Don't set per-stage shader pointers for VS. */
1552 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(VERTEX
);
1553 sctx
->vertex_buffer_pointer_dirty
= false;
1555 si_draw_vbo(pipe
, &info
);
1558 void si_trace_emit(struct si_context
*sctx
)
1560 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx_cs
;
1561 uint64_t va
= sctx
->current_saved_cs
->trace_buf
->gpu_address
;
1562 uint32_t trace_id
= ++sctx
->current_saved_cs
->trace_id
;
1564 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
1565 radeon_emit(cs
, S_370_DST_SEL(V_370_MEMORY_SYNC
) |
1566 S_370_WR_CONFIRM(1) |
1567 S_370_ENGINE_SEL(V_370_ME
));
1568 radeon_emit(cs
, va
);
1569 radeon_emit(cs
, va
>> 32);
1570 radeon_emit(cs
, trace_id
);
1571 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1572 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(trace_id
));
1575 u_log_flush(sctx
->b
.log
);