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radeonsi: disable the patch ID workaround on SI when the patch ID isn't used (v2)
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "radeon/r600_cs.h"
29 #include "sid.h"
30 #include "gfx9d.h"
31
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
35
36 #include "ac_debug.h"
37
38 static unsigned si_conv_pipe_prim(unsigned mode)
39 {
40 static const unsigned prim_conv[] = {
41 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
42 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
43 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
44 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
45 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
46 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
47 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
48 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
49 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
50 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
51 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
55 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
56 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
57 };
58 assert(mode < ARRAY_SIZE(prim_conv));
59 return prim_conv[mode];
60 }
61
62 static unsigned si_conv_prim_to_gs_out(unsigned mode)
63 {
64 static const int prim_conv[] = {
65 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
66 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
67 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
68 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
69 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
73 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
74 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
75 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
76 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
77 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
78 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
79 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
80 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
81 };
82 assert(mode < ARRAY_SIZE(prim_conv));
83
84 return prim_conv[mode];
85 }
86
87 /**
88 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
89 * LS.LDS_SIZE is shared by all 3 shader stages.
90 *
91 * The information about LDS and other non-compile-time parameters is then
92 * written to userdata SGPRs.
93 */
94 static void si_emit_derived_tess_state(struct si_context *sctx,
95 const struct pipe_draw_info *info,
96 unsigned *num_patches)
97 {
98 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
99 struct si_shader *ls_current;
100 struct si_shader_selector *ls;
101 /* The TES pointer will only be used for sctx->last_tcs.
102 * It would be wrong to think that TCS = TES. */
103 struct si_shader_selector *tcs =
104 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
105 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
106 bool has_primid_instancing_bug = sctx->b.chip_class == SI &&
107 sctx->b.screen->info.max_se == 1;
108 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
109 unsigned num_tcs_input_cp = info->vertices_per_patch;
110 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
111 unsigned num_tcs_patch_outputs;
112 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
113 unsigned input_patch_size, output_patch_size, output_patch0_offset;
114 unsigned perpatch_output_offset, lds_size;
115 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
116 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
117
118 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
119 if (sctx->b.chip_class >= GFX9) {
120 if (sctx->tcs_shader.cso)
121 ls_current = sctx->tcs_shader.current;
122 else
123 ls_current = sctx->fixed_func_tcs_shader.current;
124
125 ls = ls_current->key.part.tcs.ls;
126 } else {
127 ls_current = sctx->vs_shader.current;
128 ls = sctx->vs_shader.cso;
129 }
130
131 if (sctx->last_ls == ls_current &&
132 sctx->last_tcs == tcs &&
133 sctx->last_tes_sh_base == tes_sh_base &&
134 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
135 (!has_primid_instancing_bug ||
136 (sctx->last_tess_uses_primid == tess_uses_primid))) {
137 *num_patches = sctx->last_num_patches;
138 return;
139 }
140
141 sctx->last_ls = ls_current;
142 sctx->last_tcs = tcs;
143 sctx->last_tes_sh_base = tes_sh_base;
144 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
145 sctx->last_tess_uses_primid = tess_uses_primid;
146
147 /* This calculates how shader inputs and outputs among VS, TCS, and TES
148 * are laid out in LDS. */
149 num_tcs_inputs = util_last_bit64(ls->outputs_written);
150
151 if (sctx->tcs_shader.cso) {
152 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
153 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
154 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
155 } else {
156 /* No TCS. Route varyings from LS to TES. */
157 num_tcs_outputs = num_tcs_inputs;
158 num_tcs_output_cp = num_tcs_input_cp;
159 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
160 }
161
162 input_vertex_size = num_tcs_inputs * 16;
163 output_vertex_size = num_tcs_outputs * 16;
164
165 input_patch_size = num_tcs_input_cp * input_vertex_size;
166
167 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
168 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
169
170 /* Ensure that we only need one wave per SIMD so we don't need to check
171 * resource usage. Also ensures that the number of tcs in and out
172 * vertices per threadgroup are at most 256.
173 */
174 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
175
176 /* Make sure that the data fits in LDS. This assumes the shaders only
177 * use LDS for the inputs and outputs.
178 *
179 * While CIK can use 64K per threadgroup, there is a hang on Stoney
180 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
181 * uses 32K at most on all GCN chips.
182 */
183 hardware_lds_size = 32768;
184 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
185 output_patch_size));
186
187 /* Make sure the output data fits in the offchip buffer */
188 *num_patches = MIN2(*num_patches,
189 (sctx->screen->tess_offchip_block_dw_size * 4) /
190 output_patch_size);
191
192 /* Not necessary for correctness, but improves performance. The
193 * specific value is taken from the proprietary driver.
194 */
195 *num_patches = MIN2(*num_patches, 40);
196
197 if (sctx->b.chip_class == SI) {
198 /* SI bug workaround, related to power management. Limit LS-HS
199 * threadgroups to only one wave.
200 */
201 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
202 *num_patches = MIN2(*num_patches, one_wave);
203 }
204
205 /* The VGT HS block increments the patch ID unconditionally
206 * within a single threadgroup. This results in incorrect
207 * patch IDs when instanced draws are used.
208 *
209 * The intended solution is to restrict threadgroups to
210 * a single instance by setting SWITCH_ON_EOI, which
211 * should cause IA to split instances up. However, this
212 * doesn't work correctly on SI when there is no other
213 * SE to switch to.
214 */
215 if (has_primid_instancing_bug)
216 *num_patches = 1;
217
218 sctx->last_num_patches = *num_patches;
219
220 output_patch0_offset = input_patch_size * *num_patches;
221 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
222
223 /* Compute userdata SGPRs. */
224 assert(((input_vertex_size / 4) & ~0xff) == 0);
225 assert(((output_vertex_size / 4) & ~0xff) == 0);
226 assert(((input_patch_size / 4) & ~0x1fff) == 0);
227 assert(((output_patch_size / 4) & ~0x1fff) == 0);
228 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
229 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
230 assert(num_tcs_input_cp <= 32);
231 assert(num_tcs_output_cp <= 32);
232
233 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
234 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
235 tcs_out_layout = (output_patch_size / 4) |
236 ((output_vertex_size / 4) << 13);
237 tcs_out_offsets = (output_patch0_offset / 16) |
238 ((perpatch_output_offset / 16) << 16);
239 offchip_layout = *num_patches |
240 (num_tcs_output_cp << 6) |
241 (pervertex_output_patch_size * *num_patches << 12);
242
243 /* Compute the LDS size. */
244 lds_size = output_patch0_offset + output_patch_size * *num_patches;
245
246 if (sctx->b.chip_class >= CIK) {
247 assert(lds_size <= 65536);
248 lds_size = align(lds_size, 512) / 512;
249 } else {
250 assert(lds_size <= 32768);
251 lds_size = align(lds_size, 256) / 256;
252 }
253
254 /* Set SI_SGPR_VS_STATE_BITS. */
255 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
256 C_VS_STATE_LS_OUT_VERTEX_SIZE;
257 sctx->current_vs_state |= tcs_in_layout;
258
259 if (sctx->b.chip_class >= GFX9) {
260 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
261 S_00B42C_LDS_SIZE(lds_size);
262
263 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
264
265 /* Set userdata SGPRs for merged LS-HS. */
266 radeon_set_sh_reg_seq(cs,
267 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
268 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
269 radeon_emit(cs, offchip_layout);
270 radeon_emit(cs, tcs_out_offsets);
271 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
272 } else {
273 unsigned ls_rsrc2 = ls_current->config.rsrc2;
274
275 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
276 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
277
278 /* Due to a hw bug, RSRC2_LS must be written twice with another
279 * LS register written in between. */
280 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
281 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
282 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
283 radeon_emit(cs, ls_current->config.rsrc1);
284 radeon_emit(cs, ls_rsrc2);
285
286 /* Set userdata SGPRs for TCS. */
287 radeon_set_sh_reg_seq(cs,
288 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
289 radeon_emit(cs, offchip_layout);
290 radeon_emit(cs, tcs_out_offsets);
291 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
292 radeon_emit(cs, tcs_in_layout);
293 }
294
295 /* Set userdata SGPRs for TES. */
296 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
297 radeon_emit(cs, offchip_layout);
298 radeon_emit(cs, r600_resource(sctx->tess_offchip_ring)->gpu_address >> 16);
299
300 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
301 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
302 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
303
304 if (sctx->b.chip_class >= CIK)
305 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
306 ls_hs_config);
307 else
308 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
309 ls_hs_config);
310 }
311
312 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
313 {
314 switch (info->mode) {
315 case PIPE_PRIM_PATCHES:
316 return info->count / info->vertices_per_patch;
317 case R600_PRIM_RECTANGLE_LIST:
318 return info->count / 3;
319 default:
320 return u_prims_for_vertices(info->mode, info->count);
321 }
322 }
323
324 static unsigned
325 si_get_init_multi_vgt_param(struct si_screen *sscreen,
326 union si_vgt_param_key *key)
327 {
328 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
329 unsigned max_primgroup_in_wave = 2;
330
331 /* SWITCH_ON_EOP(0) is always preferable. */
332 bool wd_switch_on_eop = false;
333 bool ia_switch_on_eop = false;
334 bool ia_switch_on_eoi = false;
335 bool partial_vs_wave = false;
336 bool partial_es_wave = false;
337
338 if (key->u.uses_tess) {
339 /* SWITCH_ON_EOI must be set if PrimID is used. */
340 if (key->u.tess_uses_prim_id)
341 ia_switch_on_eoi = true;
342
343 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
344 if ((sscreen->b.family == CHIP_TAHITI ||
345 sscreen->b.family == CHIP_PITCAIRN ||
346 sscreen->b.family == CHIP_BONAIRE) &&
347 key->u.uses_gs)
348 partial_vs_wave = true;
349
350 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
351 if (sscreen->has_distributed_tess) {
352 if (key->u.uses_gs) {
353 if (sscreen->b.chip_class <= VI)
354 partial_es_wave = true;
355
356 /* GPU hang workaround. */
357 if (sscreen->b.family == CHIP_TONGA ||
358 sscreen->b.family == CHIP_FIJI ||
359 sscreen->b.family == CHIP_POLARIS10 ||
360 sscreen->b.family == CHIP_POLARIS11 ||
361 sscreen->b.family == CHIP_POLARIS12)
362 partial_vs_wave = true;
363 } else {
364 partial_vs_wave = true;
365 }
366 }
367 }
368
369 /* This is a hardware requirement. */
370 if (key->u.line_stipple_enabled ||
371 (sscreen->b.debug_flags & DBG_SWITCH_ON_EOP)) {
372 ia_switch_on_eop = true;
373 wd_switch_on_eop = true;
374 }
375
376 if (sscreen->b.chip_class >= CIK) {
377 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
378 * 4 shader engines. Set 1 to pass the assertion below.
379 * The other cases are hardware requirements.
380 *
381 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
382 * for points, line strips, and tri strips.
383 */
384 if (sscreen->b.info.max_se < 4 ||
385 key->u.prim == PIPE_PRIM_POLYGON ||
386 key->u.prim == PIPE_PRIM_LINE_LOOP ||
387 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
388 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
389 (key->u.primitive_restart &&
390 (sscreen->b.family < CHIP_POLARIS10 ||
391 (key->u.prim != PIPE_PRIM_POINTS &&
392 key->u.prim != PIPE_PRIM_LINE_STRIP &&
393 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
394 key->u.count_from_stream_output)
395 wd_switch_on_eop = true;
396
397 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
398 * We don't know that for indirect drawing, so treat it as
399 * always problematic. */
400 if (sscreen->b.family == CHIP_HAWAII &&
401 key->u.uses_instancing)
402 wd_switch_on_eop = true;
403
404 /* Performance recommendation for 4 SE Gfx7-8 parts if
405 * instances are smaller than a primgroup.
406 * Assume indirect draws always use small instances.
407 * This is needed for good VS wave utilization.
408 */
409 if (sscreen->b.chip_class <= VI &&
410 sscreen->b.info.max_se == 4 &&
411 key->u.multi_instances_smaller_than_primgroup)
412 wd_switch_on_eop = true;
413
414 /* Required on CIK and later. */
415 if (sscreen->b.info.max_se > 2 && !wd_switch_on_eop)
416 ia_switch_on_eoi = true;
417
418 /* Required by Hawaii and, for some special cases, by VI. */
419 if (ia_switch_on_eoi &&
420 (sscreen->b.family == CHIP_HAWAII ||
421 (sscreen->b.chip_class == VI &&
422 (key->u.uses_gs || max_primgroup_in_wave != 2))))
423 partial_vs_wave = true;
424
425 /* Instancing bug on Bonaire. */
426 if (sscreen->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
427 key->u.uses_instancing)
428 partial_vs_wave = true;
429
430 /* If the WD switch is false, the IA switch must be false too. */
431 assert(wd_switch_on_eop || !ia_switch_on_eop);
432 }
433
434 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
435 if (sscreen->b.chip_class <= VI && ia_switch_on_eoi)
436 partial_es_wave = true;
437
438 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
439 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
440 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
441 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
442 S_028AA8_WD_SWITCH_ON_EOP(sscreen->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
443 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
444 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->b.chip_class == VI ?
445 max_primgroup_in_wave : 0) |
446 S_030960_EN_INST_OPT_BASIC(sscreen->b.chip_class >= GFX9) |
447 S_030960_EN_INST_OPT_ADV(sscreen->b.chip_class >= GFX9);
448 }
449
450 void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
451 {
452 for (int prim = 0; prim <= R600_PRIM_RECTANGLE_LIST; prim++)
453 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
454 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
455 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
456 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
457 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
458 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
459 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
460 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
461 union si_vgt_param_key key;
462
463 key.index = 0;
464 key.u.prim = prim;
465 key.u.uses_instancing = uses_instancing;
466 key.u.multi_instances_smaller_than_primgroup = multi_instances;
467 key.u.primitive_restart = primitive_restart;
468 key.u.count_from_stream_output = count_from_so;
469 key.u.line_stipple_enabled = line_stipple;
470 key.u.uses_tess = uses_tess;
471 key.u.tess_uses_prim_id = tess_uses_primid;
472 key.u.uses_gs = uses_gs;
473
474 sctx->ia_multi_vgt_param[key.index] =
475 si_get_init_multi_vgt_param(sctx->screen, &key);
476 }
477 }
478
479 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
480 const struct pipe_draw_info *info,
481 unsigned num_patches)
482 {
483 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
484 unsigned primgroup_size;
485 unsigned ia_multi_vgt_param;
486
487 if (sctx->tes_shader.cso) {
488 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
489 } else if (sctx->gs_shader.cso) {
490 primgroup_size = 64; /* recommended with a GS */
491 } else {
492 primgroup_size = 128; /* recommended without a GS and tess */
493 }
494
495 key.u.prim = info->mode;
496 key.u.uses_instancing = info->indirect || info->instance_count > 1;
497 key.u.multi_instances_smaller_than_primgroup =
498 info->indirect ||
499 (info->instance_count > 1 &&
500 (info->count_from_stream_output ||
501 si_num_prims_for_vertices(info) < primgroup_size));
502 key.u.primitive_restart = info->primitive_restart;
503 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
504
505 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
506 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
507
508 if (sctx->gs_shader.cso) {
509 /* GS requirement. */
510 if (sctx->b.chip_class <= VI &&
511 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
512 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
513
514 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
515 * The hw doc says all multi-SE chips are affected, but Vulkan
516 * only applies it to Hawaii. Do what Vulkan does.
517 */
518 if (sctx->b.family == CHIP_HAWAII &&
519 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
520 (info->indirect ||
521 (info->instance_count > 1 &&
522 (info->count_from_stream_output ||
523 si_num_prims_for_vertices(info) <= 1))))
524 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
525 }
526
527 return ia_multi_vgt_param;
528 }
529
530 /* rast_prim is the primitive type after GS. */
531 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
532 {
533 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
534 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
535 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
536
537 /* Skip this if not rendering lines. */
538 if (rast_prim != PIPE_PRIM_LINES &&
539 rast_prim != PIPE_PRIM_LINE_LOOP &&
540 rast_prim != PIPE_PRIM_LINE_STRIP &&
541 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
542 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
543 return;
544
545 if (rast_prim == sctx->last_rast_prim &&
546 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
547 return;
548
549 /* For lines, reset the stipple pattern at each primitive. Otherwise,
550 * reset the stipple pattern at each packet (line strips, line loops).
551 */
552 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
553 rs->pa_sc_line_stipple |
554 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
555
556 sctx->last_rast_prim = rast_prim;
557 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
558 }
559
560 static void si_emit_vs_state(struct si_context *sctx,
561 const struct pipe_draw_info *info)
562 {
563 sctx->current_vs_state &= C_VS_STATE_INDEXED;
564 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
565
566 if (sctx->current_vs_state != sctx->last_vs_state) {
567 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
568
569 radeon_set_sh_reg(cs,
570 sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX] +
571 SI_SGPR_VS_STATE_BITS * 4,
572 sctx->current_vs_state);
573
574 sctx->last_vs_state = sctx->current_vs_state;
575 }
576 }
577
578 static void si_emit_draw_registers(struct si_context *sctx,
579 const struct pipe_draw_info *info,
580 unsigned num_patches)
581 {
582 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
583 unsigned prim = si_conv_pipe_prim(info->mode);
584 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
585 unsigned ia_multi_vgt_param;
586
587 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
588
589 /* Draw state. */
590 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
591 if (sctx->b.chip_class >= GFX9)
592 radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
593 else if (sctx->b.chip_class >= CIK)
594 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
595 else
596 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
597
598 sctx->last_multi_vgt_param = ia_multi_vgt_param;
599 }
600 if (prim != sctx->last_prim) {
601 if (sctx->b.chip_class >= CIK)
602 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
603 else
604 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
605
606 sctx->last_prim = prim;
607 }
608
609 if (gs_out_prim != sctx->last_gs_out_prim) {
610 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
611 sctx->last_gs_out_prim = gs_out_prim;
612 }
613
614 /* Primitive restart. */
615 if (info->primitive_restart != sctx->last_primitive_restart_en) {
616 if (sctx->b.chip_class >= GFX9)
617 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
618 info->primitive_restart);
619 else
620 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
621 info->primitive_restart);
622
623 sctx->last_primitive_restart_en = info->primitive_restart;
624
625 }
626 if (info->primitive_restart &&
627 (info->restart_index != sctx->last_restart_index ||
628 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
629 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
630 info->restart_index);
631 sctx->last_restart_index = info->restart_index;
632 }
633 }
634
635 static void si_emit_draw_packets(struct si_context *sctx,
636 const struct pipe_draw_info *info,
637 struct pipe_resource *indexbuf,
638 unsigned index_size,
639 unsigned index_offset)
640 {
641 struct pipe_draw_indirect_info *indirect = info->indirect;
642 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
643 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
644 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
645 uint32_t index_max_size = 0;
646 uint64_t index_va = 0;
647
648 if (info->count_from_stream_output) {
649 struct r600_so_target *t =
650 (struct r600_so_target*)info->count_from_stream_output;
651 uint64_t va = t->buf_filled_size->gpu_address +
652 t->buf_filled_size_offset;
653
654 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
655 t->stride_in_dw);
656
657 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
658 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
659 COPY_DATA_DST_SEL(COPY_DATA_REG) |
660 COPY_DATA_WR_CONFIRM);
661 radeon_emit(cs, va); /* src address lo */
662 radeon_emit(cs, va >> 32); /* src address hi */
663 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
664 radeon_emit(cs, 0); /* unused */
665
666 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
667 t->buf_filled_size, RADEON_USAGE_READ,
668 RADEON_PRIO_SO_FILLED_SIZE);
669 }
670
671 /* draw packet */
672 if (index_size) {
673 if (index_size != sctx->last_index_size) {
674 unsigned index_type;
675
676 /* index type */
677 switch (index_size) {
678 case 1:
679 index_type = V_028A7C_VGT_INDEX_8;
680 break;
681 case 2:
682 index_type = V_028A7C_VGT_INDEX_16 |
683 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
684 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
685 break;
686 case 4:
687 index_type = V_028A7C_VGT_INDEX_32 |
688 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
689 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
690 break;
691 default:
692 assert(!"unreachable");
693 return;
694 }
695
696 if (sctx->b.chip_class >= GFX9) {
697 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
698 2, index_type);
699 } else {
700 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
701 radeon_emit(cs, index_type);
702 }
703
704 sctx->last_index_size = index_size;
705 }
706
707 index_max_size = (indexbuf->width0 - index_offset) /
708 index_size;
709 index_va = r600_resource(indexbuf)->gpu_address + index_offset;
710
711 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
712 (struct r600_resource *)indexbuf,
713 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
714 } else {
715 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
716 * so the state must be re-emitted before the next indexed draw.
717 */
718 if (sctx->b.chip_class >= CIK)
719 sctx->last_index_size = -1;
720 }
721
722 if (indirect) {
723 uint64_t indirect_va = r600_resource(indirect->buffer)->gpu_address;
724
725 assert(indirect_va % 8 == 0);
726
727 si_invalidate_draw_sh_constants(sctx);
728
729 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
730 radeon_emit(cs, 1);
731 radeon_emit(cs, indirect_va);
732 radeon_emit(cs, indirect_va >> 32);
733
734 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
735 (struct r600_resource *)indirect->buffer,
736 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
737
738 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
739 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
740
741 assert(indirect->offset % 4 == 0);
742
743 if (index_size) {
744 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
745 radeon_emit(cs, index_va);
746 radeon_emit(cs, index_va >> 32);
747
748 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
749 radeon_emit(cs, index_max_size);
750 }
751
752 if (!sctx->screen->has_draw_indirect_multi) {
753 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
754 : PKT3_DRAW_INDIRECT,
755 3, render_cond_bit));
756 radeon_emit(cs, indirect->offset);
757 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
758 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
759 radeon_emit(cs, di_src_sel);
760 } else {
761 uint64_t count_va = 0;
762
763 if (indirect->indirect_draw_count) {
764 struct r600_resource *params_buf =
765 (struct r600_resource *)indirect->indirect_draw_count;
766
767 radeon_add_to_buffer_list(
768 &sctx->b, &sctx->b.gfx, params_buf,
769 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
770
771 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
772 }
773
774 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
775 PKT3_DRAW_INDIRECT_MULTI,
776 8, render_cond_bit));
777 radeon_emit(cs, indirect->offset);
778 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
779 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
780 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
781 S_2C3_DRAW_INDEX_ENABLE(1) |
782 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
783 radeon_emit(cs, indirect->draw_count);
784 radeon_emit(cs, count_va);
785 radeon_emit(cs, count_va >> 32);
786 radeon_emit(cs, indirect->stride);
787 radeon_emit(cs, di_src_sel);
788 }
789 } else {
790 int base_vertex;
791
792 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
793 radeon_emit(cs, info->instance_count);
794
795 /* Base vertex and start instance. */
796 base_vertex = index_size ? info->index_bias : info->start;
797
798 if (base_vertex != sctx->last_base_vertex ||
799 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
800 info->start_instance != sctx->last_start_instance ||
801 info->drawid != sctx->last_drawid ||
802 sh_base_reg != sctx->last_sh_base_reg) {
803 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
804 radeon_emit(cs, base_vertex);
805 radeon_emit(cs, info->start_instance);
806 radeon_emit(cs, info->drawid);
807
808 sctx->last_base_vertex = base_vertex;
809 sctx->last_start_instance = info->start_instance;
810 sctx->last_drawid = info->drawid;
811 sctx->last_sh_base_reg = sh_base_reg;
812 }
813
814 if (index_size) {
815 index_va += info->start * index_size;
816
817 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
818 radeon_emit(cs, index_max_size);
819 radeon_emit(cs, index_va);
820 radeon_emit(cs, index_va >> 32);
821 radeon_emit(cs, info->count);
822 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
823 } else {
824 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
825 radeon_emit(cs, info->count);
826 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
827 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
828 }
829 }
830 }
831
832 static void si_emit_surface_sync(struct r600_common_context *rctx,
833 unsigned cp_coher_cntl)
834 {
835 struct radeon_winsys_cs *cs = rctx->gfx.cs;
836
837 if (rctx->chip_class >= GFX9) {
838 /* Flush caches and wait for the caches to assert idle. */
839 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
840 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
841 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
842 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
843 radeon_emit(cs, 0); /* CP_COHER_BASE */
844 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
845 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
846 } else {
847 /* ACQUIRE_MEM is only required on a compute ring. */
848 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
849 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
850 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
851 radeon_emit(cs, 0); /* CP_COHER_BASE */
852 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
853 }
854 }
855
856 void si_emit_cache_flush(struct si_context *sctx)
857 {
858 struct r600_common_context *rctx = &sctx->b;
859 struct radeon_winsys_cs *cs = rctx->gfx.cs;
860 uint32_t cp_coher_cntl = 0;
861 uint32_t flush_cb_db = rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
862 SI_CONTEXT_FLUSH_AND_INV_DB);
863
864 if (rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
865 SI_CONTEXT_FLUSH_AND_INV_DB))
866 sctx->b.num_fb_cache_flushes++;
867
868 /* SI has a bug that it always flushes ICACHE and KCACHE if either
869 * bit is set. An alternative way is to write SQC_CACHES, but that
870 * doesn't seem to work reliably. Since the bug doesn't affect
871 * correctness (it only does more work than necessary) and
872 * the performance impact is likely negligible, there is no plan
873 * to add a workaround for it.
874 */
875
876 if (rctx->flags & SI_CONTEXT_INV_ICACHE)
877 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
878 if (rctx->flags & SI_CONTEXT_INV_SMEM_L1)
879 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
880
881 if (rctx->chip_class <= VI) {
882 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
883 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
884 S_0085F0_CB0_DEST_BASE_ENA(1) |
885 S_0085F0_CB1_DEST_BASE_ENA(1) |
886 S_0085F0_CB2_DEST_BASE_ENA(1) |
887 S_0085F0_CB3_DEST_BASE_ENA(1) |
888 S_0085F0_CB4_DEST_BASE_ENA(1) |
889 S_0085F0_CB5_DEST_BASE_ENA(1) |
890 S_0085F0_CB6_DEST_BASE_ENA(1) |
891 S_0085F0_CB7_DEST_BASE_ENA(1);
892
893 /* Necessary for DCC */
894 if (rctx->chip_class == VI)
895 r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
896 0, 0, NULL, 0, 0, 0);
897 }
898 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB)
899 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
900 S_0085F0_DB_DEST_BASE_ENA(1);
901 }
902
903 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
904 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
905 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
906 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
907 }
908 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
909 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
910 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
911 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
912 }
913
914 /* Wait for shader engines to go idle.
915 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
916 * for everything including CB/DB cache flushes.
917 */
918 if (!flush_cb_db) {
919 if (rctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
920 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
921 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
922 /* Only count explicit shader flushes, not implicit ones
923 * done by SURFACE_SYNC.
924 */
925 rctx->num_vs_flushes++;
926 rctx->num_ps_flushes++;
927 } else if (rctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
928 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
929 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
930 rctx->num_vs_flushes++;
931 }
932 }
933
934 if (rctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
935 sctx->compute_is_busy) {
936 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
937 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
938 rctx->num_cs_flushes++;
939 sctx->compute_is_busy = false;
940 }
941
942 /* VGT state synchronization. */
943 if (rctx->flags & SI_CONTEXT_VGT_FLUSH) {
944 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
945 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
946 }
947 if (rctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
948 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
949 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
950 }
951
952 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
953 * wait for idle on GFX9. We have to use a TS event.
954 */
955 if (sctx->b.chip_class >= GFX9 && flush_cb_db) {
956 struct r600_resource *rbuf = NULL;
957 uint64_t va;
958 unsigned offset = 0, tc_flags, cb_db_event;
959
960 /* Set the CB/DB flush event. */
961 switch (flush_cb_db) {
962 case SI_CONTEXT_FLUSH_AND_INV_CB:
963 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
964 break;
965 case SI_CONTEXT_FLUSH_AND_INV_DB:
966 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
967 break;
968 default:
969 /* both CB & DB */
970 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
971 }
972
973 /* TC | TC_WB = invalidate L2 data
974 * TC_MD | TC_WB = invalidate L2 metadata
975 * TC | TC_WB | TC_MD = invalidate L2 data & metadata
976 *
977 * The metadata cache must always be invalidated for coherency
978 * between CB/DB and shaders. (metadata = HTILE, CMASK, DCC)
979 *
980 * TC must be invalidated on GFX9 only if the CB/DB surface is
981 * not pipe-aligned. If the surface is RB-aligned, it might not
982 * strictly be pipe-aligned since RB alignment takes precendence.
983 */
984 tc_flags = EVENT_TC_WB_ACTION_ENA |
985 EVENT_TC_MD_ACTION_ENA;
986
987 /* Ideally flush TC together with CB/DB. */
988 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
989 tc_flags |= EVENT_TC_ACTION_ENA |
990 EVENT_TCL1_ACTION_ENA;
991
992 /* Clear the flags. */
993 rctx->flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
994 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
995 SI_CONTEXT_INV_VMEM_L1);
996 }
997
998 /* Allocate memory for the fence. */
999 u_suballocator_alloc(rctx->allocator_zeroed_memory, 4, 4,
1000 &offset, (struct pipe_resource**)&rbuf);
1001 va = rbuf->gpu_address + offset;
1002
1003 r600_gfx_write_event_eop(rctx, cb_db_event, tc_flags, 1,
1004 rbuf, va, 0, 1);
1005 r600_gfx_wait_fence(rctx, va, 1, 0xffffffff);
1006 }
1007
1008 /* Make sure ME is idle (it executes most packets) before continuing.
1009 * This prevents read-after-write hazards between PFP and ME.
1010 */
1011 if (cp_coher_cntl ||
1012 (rctx->flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1013 SI_CONTEXT_INV_VMEM_L1 |
1014 SI_CONTEXT_INV_GLOBAL_L2 |
1015 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1016 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1017 radeon_emit(cs, 0);
1018 }
1019
1020 /* SI-CI-VI only:
1021 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1022 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1023 *
1024 * cp_coher_cntl should contain all necessary flags except TC flags
1025 * at this point.
1026 *
1027 * SI-CIK don't support L2 write-back.
1028 */
1029 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2 ||
1030 (rctx->chip_class <= CIK &&
1031 (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1032 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
1033 * WB must be set on VI+ when TC_ACTION is set.
1034 */
1035 si_emit_surface_sync(rctx, cp_coher_cntl |
1036 S_0085F0_TC_ACTION_ENA(1) |
1037 S_0085F0_TCL1_ACTION_ENA(1) |
1038 S_0301F0_TC_WB_ACTION_ENA(rctx->chip_class >= VI));
1039 cp_coher_cntl = 0;
1040 sctx->b.num_L2_invalidates++;
1041 } else {
1042 /* L1 invalidation and L2 writeback must be done separately,
1043 * because both operations can't be done together.
1044 */
1045 if (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
1046 /* WB = write-back
1047 * NC = apply to non-coherent MTYPEs
1048 * (i.e. MTYPE <= 1, which is what we use everywhere)
1049 *
1050 * WB doesn't work without NC.
1051 */
1052 si_emit_surface_sync(rctx, cp_coher_cntl |
1053 S_0301F0_TC_WB_ACTION_ENA(1) |
1054 S_0301F0_TC_NC_ACTION_ENA(1));
1055 cp_coher_cntl = 0;
1056 sctx->b.num_L2_writebacks++;
1057 }
1058 if (rctx->flags & SI_CONTEXT_INV_VMEM_L1) {
1059 /* Invalidate per-CU VMEM L1. */
1060 si_emit_surface_sync(rctx, cp_coher_cntl |
1061 S_0085F0_TCL1_ACTION_ENA(1));
1062 cp_coher_cntl = 0;
1063 }
1064 }
1065
1066 /* If TC flushes haven't cleared this... */
1067 if (cp_coher_cntl)
1068 si_emit_surface_sync(rctx, cp_coher_cntl);
1069
1070 if (rctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
1071 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1072 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1073 EVENT_INDEX(0));
1074 } else if (rctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
1075 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1076 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1077 EVENT_INDEX(0));
1078 }
1079
1080 rctx->flags = 0;
1081 }
1082
1083 static void si_get_draw_start_count(struct si_context *sctx,
1084 const struct pipe_draw_info *info,
1085 unsigned *start, unsigned *count)
1086 {
1087 struct pipe_draw_indirect_info *indirect = info->indirect;
1088
1089 if (indirect) {
1090 unsigned indirect_count;
1091 struct pipe_transfer *transfer;
1092 unsigned begin, end;
1093 unsigned map_size;
1094 unsigned *data;
1095
1096 if (indirect->indirect_draw_count) {
1097 data = pipe_buffer_map_range(&sctx->b.b,
1098 indirect->indirect_draw_count,
1099 indirect->indirect_draw_count_offset,
1100 sizeof(unsigned),
1101 PIPE_TRANSFER_READ, &transfer);
1102
1103 indirect_count = *data;
1104
1105 pipe_buffer_unmap(&sctx->b.b, transfer);
1106 } else {
1107 indirect_count = indirect->draw_count;
1108 }
1109
1110 if (!indirect_count) {
1111 *start = *count = 0;
1112 return;
1113 }
1114
1115 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1116 data = pipe_buffer_map_range(&sctx->b.b, indirect->buffer,
1117 indirect->offset, map_size,
1118 PIPE_TRANSFER_READ, &transfer);
1119
1120 begin = UINT_MAX;
1121 end = 0;
1122
1123 for (unsigned i = 0; i < indirect_count; ++i) {
1124 unsigned count = data[0];
1125 unsigned start = data[2];
1126
1127 if (count > 0) {
1128 begin = MIN2(begin, start);
1129 end = MAX2(end, start + count);
1130 }
1131
1132 data += indirect->stride / sizeof(unsigned);
1133 }
1134
1135 pipe_buffer_unmap(&sctx->b.b, transfer);
1136
1137 if (begin < end) {
1138 *start = begin;
1139 *count = end - begin;
1140 } else {
1141 *start = *count = 0;
1142 }
1143 } else {
1144 *start = info->start;
1145 *count = info->count;
1146 }
1147 }
1148
1149 void si_ce_pre_draw_synchronization(struct si_context *sctx)
1150 {
1151 if (sctx->ce_need_synchronization) {
1152 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
1153 radeon_emit(sctx->ce_ib, 1);
1154
1155 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
1156 radeon_emit(sctx->b.gfx.cs, 1);
1157 }
1158 }
1159
1160 void si_ce_post_draw_synchronization(struct si_context *sctx)
1161 {
1162 if (sctx->ce_need_synchronization) {
1163 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
1164 radeon_emit(sctx->b.gfx.cs, 0);
1165
1166 sctx->ce_need_synchronization = false;
1167 }
1168 }
1169
1170 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1171 {
1172 struct si_context *sctx = (struct si_context *)ctx;
1173 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1174 struct pipe_resource *indexbuf = info->index.resource;
1175 unsigned mask, dirty_tex_counter;
1176 enum pipe_prim_type rast_prim;
1177 unsigned num_patches = 0;
1178 unsigned index_size = info->index_size;
1179 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1180
1181 if (likely(!info->indirect)) {
1182 /* SI-CI treat instance_count==0 as instance_count==1. There is
1183 * no workaround for indirect draws, but we can at least skip
1184 * direct draws.
1185 */
1186 if (unlikely(!info->instance_count))
1187 return;
1188
1189 /* Handle count == 0. */
1190 if (unlikely(!info->count &&
1191 (index_size || !info->count_from_stream_output)))
1192 return;
1193 }
1194
1195 if (unlikely(!sctx->vs_shader.cso)) {
1196 assert(0);
1197 return;
1198 }
1199 if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
1200 assert(0);
1201 return;
1202 }
1203 if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
1204 assert(0);
1205 return;
1206 }
1207
1208 /* Recompute and re-emit the texture resource states if needed. */
1209 dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_counter);
1210 if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_counter)) {
1211 sctx->b.last_dirty_tex_counter = dirty_tex_counter;
1212 sctx->framebuffer.dirty_cbufs |=
1213 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1214 sctx->framebuffer.dirty_zsbuf = true;
1215 sctx->framebuffer.do_update_surf_dirtiness = true;
1216 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
1217 si_update_all_texture_descriptors(sctx);
1218 }
1219
1220 si_decompress_graphics_textures(sctx);
1221
1222 /* Set the rasterization primitive type.
1223 *
1224 * This must be done after si_decompress_textures, which can call
1225 * draw_vbo recursively, and before si_update_shaders, which uses
1226 * current_rast_prim for this draw_vbo call. */
1227 if (sctx->gs_shader.cso)
1228 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1229 else if (sctx->tes_shader.cso)
1230 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1231 else
1232 rast_prim = info->mode;
1233
1234 if (rast_prim != sctx->current_rast_prim) {
1235 sctx->current_rast_prim = rast_prim;
1236 sctx->do_update_shaders = true;
1237 }
1238
1239 if (sctx->gs_shader.cso) {
1240 /* Determine whether the GS triangle strip adjacency fix should
1241 * be applied. Rotate every other triangle if
1242 * - triangle strips with adjacency are fed to the GS and
1243 * - primitive restart is disabled (the rotation doesn't help
1244 * when the restart occurs after an odd number of triangles).
1245 */
1246 bool gs_tri_strip_adj_fix =
1247 !sctx->tes_shader.cso &&
1248 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1249 !info->primitive_restart;
1250
1251 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1252 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1253 sctx->do_update_shaders = true;
1254 }
1255 }
1256
1257 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1258 return;
1259
1260 if (!si_upload_graphics_shader_descriptors(sctx))
1261 return;
1262
1263 if (index_size) {
1264 /* Translate or upload, if needed. */
1265 /* 8-bit indices are supported on VI. */
1266 if (sctx->b.chip_class <= CIK && index_size == 1) {
1267 unsigned start, count, start_offset, size, offset;
1268 void *ptr;
1269
1270 si_get_draw_start_count(sctx, info, &start, &count);
1271 start_offset = start * 2;
1272 size = count * 2;
1273
1274 indexbuf = NULL;
1275 u_upload_alloc(ctx->stream_uploader, start_offset,
1276 size,
1277 si_optimal_tcc_alignment(sctx, size),
1278 &offset, &indexbuf, &ptr);
1279 if (!indexbuf)
1280 return;
1281
1282 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, info, 0, 0,
1283 index_offset + start,
1284 count, ptr);
1285
1286 /* info->start will be added by the drawing code */
1287 index_offset = offset - start_offset;
1288 index_size = 2;
1289 } else if (info->has_user_indices) {
1290 unsigned start_offset;
1291
1292 assert(!info->indirect);
1293 start_offset = info->start * index_size;
1294
1295 indexbuf = NULL;
1296 u_upload_data(ctx->stream_uploader, start_offset,
1297 info->count * index_size,
1298 sctx->screen->b.info.tcc_cache_line_size,
1299 (char*)info->index.user + start_offset,
1300 &index_offset, &indexbuf);
1301 if (!indexbuf)
1302 return;
1303
1304 /* info->start will be added by the drawing code */
1305 index_offset -= start_offset;
1306 } else if (sctx->b.chip_class <= CIK &&
1307 r600_resource(indexbuf)->TC_L2_dirty) {
1308 /* VI reads index buffers through TC L2, so it doesn't
1309 * need this. */
1310 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1311 r600_resource(indexbuf)->TC_L2_dirty = false;
1312 }
1313 }
1314
1315 if (info->indirect) {
1316 struct pipe_draw_indirect_info *indirect = info->indirect;
1317
1318 /* Add the buffer size for memory checking in need_cs_space. */
1319 r600_context_add_resource_size(ctx, indirect->buffer);
1320
1321 if (r600_resource(indirect->buffer)->TC_L2_dirty) {
1322 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1323 r600_resource(indirect->buffer)->TC_L2_dirty = false;
1324 }
1325
1326 if (indirect->indirect_draw_count &&
1327 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1328 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1329 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1330 }
1331 }
1332
1333 si_need_cs_space(sctx);
1334
1335 /* Since we've called r600_context_add_resource_size for vertex buffers,
1336 * this must be called after si_need_cs_space, because we must let
1337 * need_cs_space flush before we add buffers to the buffer list.
1338 */
1339 if (!si_upload_vertex_buffer_descriptors(sctx))
1340 return;
1341
1342 /* GFX9 scissor bug workaround. There is also a more efficient but
1343 * more involved alternative workaround. */
1344 if (sctx->b.chip_class == GFX9 &&
1345 si_is_atom_dirty(sctx, &sctx->b.scissors.atom))
1346 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
1347
1348 /* Flush caches before the first state atom, which does L2 prefetches. */
1349 if (sctx->b.flags)
1350 si_emit_cache_flush(sctx);
1351
1352 /* Emit state atoms. */
1353 mask = sctx->dirty_atoms;
1354 while (mask) {
1355 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
1356
1357 atom->emit(&sctx->b, atom);
1358 }
1359 sctx->dirty_atoms = 0;
1360
1361 /* Emit states. */
1362 mask = sctx->dirty_states;
1363 while (mask) {
1364 unsigned i = u_bit_scan(&mask);
1365 struct si_pm4_state *state = sctx->queued.array[i];
1366
1367 if (!state || sctx->emitted.array[i] == state)
1368 continue;
1369
1370 si_pm4_emit(sctx, state);
1371 sctx->emitted.array[i] = state;
1372 }
1373 sctx->dirty_states = 0;
1374
1375 si_emit_rasterizer_prim_state(sctx);
1376 if (sctx->tes_shader.cso)
1377 si_emit_derived_tess_state(sctx, info, &num_patches);
1378 si_emit_vs_state(sctx, info);
1379 si_emit_draw_registers(sctx, info, num_patches);
1380
1381 si_ce_pre_draw_synchronization(sctx);
1382 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1383 si_ce_post_draw_synchronization(sctx);
1384
1385 if (sctx->trace_buf)
1386 si_trace_emit(sctx);
1387
1388 /* Workaround for a VGT hang when streamout is enabled.
1389 * It must be done after drawing. */
1390 if ((sctx->b.family == CHIP_HAWAII ||
1391 sctx->b.family == CHIP_TONGA ||
1392 sctx->b.family == CHIP_FIJI) &&
1393 r600_get_strmout_en(&sctx->b)) {
1394 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1395 }
1396
1397 if (sctx->framebuffer.do_update_surf_dirtiness) {
1398 /* Set the depth buffer as dirty. */
1399 if (sctx->framebuffer.state.zsbuf) {
1400 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1401 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1402
1403 if (!rtex->tc_compatible_htile)
1404 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1405
1406 if (rtex->surface.flags & RADEON_SURF_SBUFFER &&
1407 (!rtex->tc_compatible_htile || !rtex->can_sample_s))
1408 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
1409 }
1410 if (sctx->framebuffer.compressed_cb_mask) {
1411 struct pipe_surface *surf;
1412 struct r600_texture *rtex;
1413 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1414
1415 do {
1416 unsigned i = u_bit_scan(&mask);
1417 surf = sctx->framebuffer.state.cbufs[i];
1418 rtex = (struct r600_texture*)surf->texture;
1419
1420 if (rtex->fmask.size)
1421 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1422 if (rtex->dcc_gather_statistics)
1423 rtex->separate_dcc_dirty = true;
1424 } while (mask);
1425 }
1426 sctx->framebuffer.do_update_surf_dirtiness = false;
1427 }
1428
1429 sctx->b.num_draw_calls++;
1430 if (info->primitive_restart)
1431 sctx->b.num_prim_restart_calls++;
1432 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1433 sctx->b.num_spill_draw_calls++;
1434 if (index_size && indexbuf != info->index.resource)
1435 pipe_resource_reference(&indexbuf, NULL);
1436 }
1437
1438 void si_trace_emit(struct si_context *sctx)
1439 {
1440 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1441
1442 sctx->trace_id++;
1443 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
1444 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
1445 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1446 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1447 S_370_WR_CONFIRM(1) |
1448 S_370_ENGINE_SEL(V_370_ME));
1449 radeon_emit(cs, sctx->trace_buf->gpu_address);
1450 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
1451 radeon_emit(cs, sctx->trace_id);
1452 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1453 radeon_emit(cs, AC_ENCODE_TRACE_POINT(sctx->trace_id));
1454 }