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radeonsi/gfx10: allow rectangle outputs from NGG primitive shader
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32 #include "util/u_suballoc.h"
33
34 #include "ac_debug.h"
35
36 /* special primitive types */
37 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
38
39 static unsigned si_conv_pipe_prim(unsigned mode)
40 {
41 static const unsigned prim_conv[] = {
42 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
43 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
44 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
45 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
46 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
47 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
48 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
49 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
50 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
51 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
52 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
53 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
54 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
55 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
56 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
57 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
58 };
59 assert(mode < ARRAY_SIZE(prim_conv));
60 return prim_conv[mode];
61 }
62
63 /**
64 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
65 * LS.LDS_SIZE is shared by all 3 shader stages.
66 *
67 * The information about LDS and other non-compile-time parameters is then
68 * written to userdata SGPRs.
69 */
70 static void si_emit_derived_tess_state(struct si_context *sctx,
71 const struct pipe_draw_info *info,
72 unsigned *num_patches)
73 {
74 struct radeon_cmdbuf *cs = sctx->gfx_cs;
75 struct si_shader *ls_current;
76 struct si_shader_selector *ls;
77 /* The TES pointer will only be used for sctx->last_tcs.
78 * It would be wrong to think that TCS = TES. */
79 struct si_shader_selector *tcs =
80 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
81 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
82 bool has_primid_instancing_bug = sctx->chip_class == GFX6 &&
83 sctx->screen->info.max_se == 1;
84 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
85 unsigned num_tcs_input_cp = info->vertices_per_patch;
86 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
87 unsigned num_tcs_patch_outputs;
88 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
89 unsigned input_patch_size, output_patch_size, output_patch0_offset;
90 unsigned perpatch_output_offset, lds_size;
91 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
92 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
93
94 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
95 if (sctx->chip_class >= GFX9) {
96 if (sctx->tcs_shader.cso)
97 ls_current = sctx->tcs_shader.current;
98 else
99 ls_current = sctx->fixed_func_tcs_shader.current;
100
101 ls = ls_current->key.part.tcs.ls;
102 } else {
103 ls_current = sctx->vs_shader.current;
104 ls = sctx->vs_shader.cso;
105 }
106
107 if (sctx->last_ls == ls_current &&
108 sctx->last_tcs == tcs &&
109 sctx->last_tes_sh_base == tes_sh_base &&
110 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
111 (!has_primid_instancing_bug ||
112 (sctx->last_tess_uses_primid == tess_uses_primid))) {
113 *num_patches = sctx->last_num_patches;
114 return;
115 }
116
117 sctx->last_ls = ls_current;
118 sctx->last_tcs = tcs;
119 sctx->last_tes_sh_base = tes_sh_base;
120 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
121 sctx->last_tess_uses_primid = tess_uses_primid;
122
123 /* This calculates how shader inputs and outputs among VS, TCS, and TES
124 * are laid out in LDS. */
125 num_tcs_inputs = util_last_bit64(ls->outputs_written);
126
127 if (sctx->tcs_shader.cso) {
128 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
129 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
130 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
131 } else {
132 /* No TCS. Route varyings from LS to TES. */
133 num_tcs_outputs = num_tcs_inputs;
134 num_tcs_output_cp = num_tcs_input_cp;
135 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
136 }
137
138 input_vertex_size = ls->lshs_vertex_stride;
139 output_vertex_size = num_tcs_outputs * 16;
140
141 input_patch_size = num_tcs_input_cp * input_vertex_size;
142
143 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
144 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
145
146 /* Ensure that we only need one wave per SIMD so we don't need to check
147 * resource usage. Also ensures that the number of tcs in and out
148 * vertices per threadgroup are at most 256.
149 */
150 unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
151 *num_patches = 256 / max_verts_per_patch;
152
153 /* Make sure that the data fits in LDS. This assumes the shaders only
154 * use LDS for the inputs and outputs.
155 *
156 * While GFX7 can use 64K per threadgroup, there is a hang on Stoney
157 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
158 * uses 32K at most on all GCN chips.
159 */
160 hardware_lds_size = 32768;
161 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
162 output_patch_size));
163
164 /* Make sure the output data fits in the offchip buffer */
165 *num_patches = MIN2(*num_patches,
166 (sctx->screen->tess_offchip_block_dw_size * 4) /
167 output_patch_size);
168
169 /* Not necessary for correctness, but improves performance.
170 * The hardware can do more, but the radeonsi shader constant is
171 * limited to 6 bits.
172 */
173 *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */
174
175 /* When distributed tessellation is unsupported, switch between SEs
176 * at a higher frequency to compensate for it.
177 */
178 if (!sctx->screen->has_distributed_tess && sctx->screen->info.max_se > 1)
179 *num_patches = MIN2(*num_patches, 16); /* recommended */
180
181 /* Make sure that vector lanes are reasonably occupied. It probably
182 * doesn't matter much because this is LS-HS, and TES is likely to
183 * occupy significantly more CUs.
184 */
185 unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
186 if (temp_verts_per_tg > 64 && temp_verts_per_tg % 64 < 48)
187 *num_patches = (temp_verts_per_tg & ~63) / max_verts_per_patch;
188
189 if (sctx->chip_class == GFX6) {
190 /* GFX6 bug workaround, related to power management. Limit LS-HS
191 * threadgroups to only one wave.
192 */
193 unsigned one_wave = 64 / max_verts_per_patch;
194 *num_patches = MIN2(*num_patches, one_wave);
195 }
196
197 /* The VGT HS block increments the patch ID unconditionally
198 * within a single threadgroup. This results in incorrect
199 * patch IDs when instanced draws are used.
200 *
201 * The intended solution is to restrict threadgroups to
202 * a single instance by setting SWITCH_ON_EOI, which
203 * should cause IA to split instances up. However, this
204 * doesn't work correctly on GFX6 when there is no other
205 * SE to switch to.
206 */
207 if (has_primid_instancing_bug && tess_uses_primid)
208 *num_patches = 1;
209
210 sctx->last_num_patches = *num_patches;
211
212 output_patch0_offset = input_patch_size * *num_patches;
213 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
214
215 /* Compute userdata SGPRs. */
216 assert(((input_vertex_size / 4) & ~0xff) == 0);
217 assert(((output_vertex_size / 4) & ~0xff) == 0);
218 assert(((input_patch_size / 4) & ~0x1fff) == 0);
219 assert(((output_patch_size / 4) & ~0x1fff) == 0);
220 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
221 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
222 assert(num_tcs_input_cp <= 32);
223 assert(num_tcs_output_cp <= 32);
224
225 uint64_t ring_va = si_resource(sctx->tess_rings)->gpu_address;
226 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
227
228 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
229 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
230 tcs_out_layout = (output_patch_size / 4) |
231 (num_tcs_input_cp << 13) |
232 ring_va;
233 tcs_out_offsets = (output_patch0_offset / 16) |
234 ((perpatch_output_offset / 16) << 16);
235 offchip_layout = *num_patches |
236 (num_tcs_output_cp << 6) |
237 (pervertex_output_patch_size * *num_patches << 12);
238
239 /* Compute the LDS size. */
240 lds_size = output_patch0_offset + output_patch_size * *num_patches;
241
242 if (sctx->chip_class >= GFX7) {
243 assert(lds_size <= 65536);
244 lds_size = align(lds_size, 512) / 512;
245 } else {
246 assert(lds_size <= 32768);
247 lds_size = align(lds_size, 256) / 256;
248 }
249
250 /* Set SI_SGPR_VS_STATE_BITS. */
251 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
252 C_VS_STATE_LS_OUT_VERTEX_SIZE;
253 sctx->current_vs_state |= tcs_in_layout;
254
255 /* We should be able to support in-shader LDS use with LLVM >= 9
256 * by just adding the lds_sizes together, but it has never
257 * been tested. */
258 assert(ls_current->config.lds_size == 0);
259
260 if (sctx->chip_class >= GFX9) {
261 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
262 S_00B42C_LDS_SIZE_GFX9(lds_size);
263
264 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
265
266 /* Set userdata SGPRs for merged LS-HS. */
267 radeon_set_sh_reg_seq(cs,
268 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
269 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
270 radeon_emit(cs, offchip_layout);
271 radeon_emit(cs, tcs_out_offsets);
272 radeon_emit(cs, tcs_out_layout);
273 } else {
274 unsigned ls_rsrc2 = ls_current->config.rsrc2;
275
276 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
277 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
278
279 /* Due to a hw bug, RSRC2_LS must be written twice with another
280 * LS register written in between. */
281 if (sctx->chip_class == GFX7 && sctx->family != CHIP_HAWAII)
282 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
283 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
284 radeon_emit(cs, ls_current->config.rsrc1);
285 radeon_emit(cs, ls_rsrc2);
286
287 /* Set userdata SGPRs for TCS. */
288 radeon_set_sh_reg_seq(cs,
289 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
290 radeon_emit(cs, offchip_layout);
291 radeon_emit(cs, tcs_out_offsets);
292 radeon_emit(cs, tcs_out_layout);
293 radeon_emit(cs, tcs_in_layout);
294 }
295
296 /* Set userdata SGPRs for TES. */
297 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
298 radeon_emit(cs, offchip_layout);
299 radeon_emit(cs, ring_va);
300
301 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
302 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
303 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
304
305 if (sctx->last_ls_hs_config != ls_hs_config) {
306 if (sctx->chip_class >= GFX7) {
307 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
308 ls_hs_config);
309 } else {
310 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
311 ls_hs_config);
312 }
313 sctx->last_ls_hs_config = ls_hs_config;
314 sctx->context_roll = true;
315 }
316 }
317
318 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info,
319 enum pipe_prim_type prim)
320 {
321 switch (prim) {
322 case PIPE_PRIM_PATCHES:
323 return info->count / info->vertices_per_patch;
324 case PIPE_PRIM_POLYGON:
325 return info->count >= 3;
326 case SI_PRIM_RECTANGLE_LIST:
327 return info->count / 3;
328 default:
329 return u_decomposed_prims_for_vertices(prim, info->count);
330 }
331 }
332
333 static unsigned
334 si_get_init_multi_vgt_param(struct si_screen *sscreen,
335 union si_vgt_param_key *key)
336 {
337 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
338 unsigned max_primgroup_in_wave = 2;
339
340 /* SWITCH_ON_EOP(0) is always preferable. */
341 bool wd_switch_on_eop = false;
342 bool ia_switch_on_eop = false;
343 bool ia_switch_on_eoi = false;
344 bool partial_vs_wave = false;
345 bool partial_es_wave = false;
346
347 if (key->u.uses_tess) {
348 /* SWITCH_ON_EOI must be set if PrimID is used. */
349 if (key->u.tess_uses_prim_id)
350 ia_switch_on_eoi = true;
351
352 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
353 if ((sscreen->info.family == CHIP_TAHITI ||
354 sscreen->info.family == CHIP_PITCAIRN ||
355 sscreen->info.family == CHIP_BONAIRE) &&
356 key->u.uses_gs)
357 partial_vs_wave = true;
358
359 /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
360 if (sscreen->has_distributed_tess) {
361 if (key->u.uses_gs) {
362 if (sscreen->info.chip_class == GFX8)
363 partial_es_wave = true;
364 } else {
365 partial_vs_wave = true;
366 }
367 }
368 }
369
370 /* This is a hardware requirement. */
371 if (key->u.line_stipple_enabled ||
372 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
373 ia_switch_on_eop = true;
374 wd_switch_on_eop = true;
375 }
376
377 if (sscreen->info.chip_class >= GFX7) {
378 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
379 * 4 shader engines. Set 1 to pass the assertion below.
380 * The other cases are hardware requirements.
381 *
382 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
383 * for points, line strips, and tri strips.
384 */
385 if (sscreen->info.max_se <= 2 ||
386 key->u.prim == PIPE_PRIM_POLYGON ||
387 key->u.prim == PIPE_PRIM_LINE_LOOP ||
388 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
389 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
390 (key->u.primitive_restart &&
391 (sscreen->info.family < CHIP_POLARIS10 ||
392 (key->u.prim != PIPE_PRIM_POINTS &&
393 key->u.prim != PIPE_PRIM_LINE_STRIP &&
394 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
395 key->u.count_from_stream_output)
396 wd_switch_on_eop = true;
397
398 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
399 * We don't know that for indirect drawing, so treat it as
400 * always problematic. */
401 if (sscreen->info.family == CHIP_HAWAII &&
402 key->u.uses_instancing)
403 wd_switch_on_eop = true;
404
405 /* Performance recommendation for 4 SE Gfx7-8 parts if
406 * instances are smaller than a primgroup.
407 * Assume indirect draws always use small instances.
408 * This is needed for good VS wave utilization.
409 */
410 if (sscreen->info.chip_class <= GFX8 &&
411 sscreen->info.max_se == 4 &&
412 key->u.multi_instances_smaller_than_primgroup)
413 wd_switch_on_eop = true;
414
415 /* Required on GFX7 and later. */
416 if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
417 ia_switch_on_eoi = true;
418
419 /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
420 * to work around a GS hang.
421 */
422 if (key->u.uses_gs &&
423 (sscreen->info.family == CHIP_TONGA ||
424 sscreen->info.family == CHIP_FIJI ||
425 sscreen->info.family == CHIP_POLARIS10 ||
426 sscreen->info.family == CHIP_POLARIS11 ||
427 sscreen->info.family == CHIP_POLARIS12 ||
428 sscreen->info.family == CHIP_VEGAM))
429 partial_vs_wave = true;
430
431 /* Required by Hawaii and, for some special cases, by GFX8. */
432 if (ia_switch_on_eoi &&
433 (sscreen->info.family == CHIP_HAWAII ||
434 (sscreen->info.chip_class == GFX8 &&
435 (key->u.uses_gs || max_primgroup_in_wave != 2))))
436 partial_vs_wave = true;
437
438 /* Instancing bug on Bonaire. */
439 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
440 key->u.uses_instancing)
441 partial_vs_wave = true;
442
443 /* This only applies to Polaris10 and later 4 SE chips.
444 * wd_switch_on_eop is already true on all other chips.
445 */
446 if (!wd_switch_on_eop && key->u.primitive_restart)
447 partial_vs_wave = true;
448
449 /* If the WD switch is false, the IA switch must be false too. */
450 assert(wd_switch_on_eop || !ia_switch_on_eop);
451 }
452
453 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
454 if (sscreen->info.chip_class <= GFX8 && ia_switch_on_eoi)
455 partial_es_wave = true;
456
457 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
458 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
459 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
460 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
461 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= GFX7 ? wd_switch_on_eop : 0) |
462 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
463 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == GFX8 ?
464 max_primgroup_in_wave : 0) |
465 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
466 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
467 }
468
469 static void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
470 {
471 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
472 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
473 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
474 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
475 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
476 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
477 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
478 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
479 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
480 union si_vgt_param_key key;
481
482 key.index = 0;
483 key.u.prim = prim;
484 key.u.uses_instancing = uses_instancing;
485 key.u.multi_instances_smaller_than_primgroup = multi_instances;
486 key.u.primitive_restart = primitive_restart;
487 key.u.count_from_stream_output = count_from_so;
488 key.u.line_stipple_enabled = line_stipple;
489 key.u.uses_tess = uses_tess;
490 key.u.tess_uses_prim_id = tess_uses_primid;
491 key.u.uses_gs = uses_gs;
492
493 sctx->ia_multi_vgt_param[key.index] =
494 si_get_init_multi_vgt_param(sctx->screen, &key);
495 }
496 }
497
498 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
499 const struct pipe_draw_info *info,
500 enum pipe_prim_type prim,
501 unsigned num_patches,
502 unsigned instance_count,
503 bool primitive_restart)
504 {
505 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
506 unsigned primgroup_size;
507 unsigned ia_multi_vgt_param;
508
509 if (sctx->tes_shader.cso) {
510 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
511 } else if (sctx->gs_shader.cso) {
512 primgroup_size = 64; /* recommended with a GS */
513 } else {
514 primgroup_size = 128; /* recommended without a GS and tess */
515 }
516
517 key.u.prim = prim;
518 key.u.uses_instancing = info->indirect || instance_count > 1;
519 key.u.multi_instances_smaller_than_primgroup =
520 info->indirect ||
521 (instance_count > 1 &&
522 (info->count_from_stream_output ||
523 si_num_prims_for_vertices(info, prim) < primgroup_size));
524 key.u.primitive_restart = primitive_restart;
525 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
526
527 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
528 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
529
530 if (sctx->gs_shader.cso) {
531 /* GS requirement. */
532 if (sctx->chip_class <= GFX8 &&
533 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
534 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
535
536 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
537 * The hw doc says all multi-SE chips are affected, but Vulkan
538 * only applies it to Hawaii. Do what Vulkan does.
539 */
540 if (sctx->family == CHIP_HAWAII &&
541 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
542 (info->indirect ||
543 (instance_count > 1 &&
544 (info->count_from_stream_output ||
545 si_num_prims_for_vertices(info, prim) <= 1))))
546 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
547 }
548
549 return ia_multi_vgt_param;
550 }
551
552 static unsigned si_conv_prim_to_gs_out(unsigned mode)
553 {
554 static const int prim_conv[] = {
555 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
556 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
557 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
558 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
559 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
560 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
561 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
562 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
563 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
564 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
565 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
566 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
567 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
568 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
569 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
570 [SI_PRIM_RECTANGLE_LIST] = V_028A6C_VGT_OUT_RECT_V0,
571 };
572 assert(mode < ARRAY_SIZE(prim_conv));
573
574 return prim_conv[mode];
575 }
576
577 /* rast_prim is the primitive type after GS. */
578 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
579 {
580 struct radeon_cmdbuf *cs = sctx->gfx_cs;
581 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
582 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
583
584 if (likely(rast_prim == sctx->last_rast_prim &&
585 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple))
586 return;
587
588 if (util_prim_is_lines(rast_prim)) {
589 /* For lines, reset the stipple pattern at each primitive. Otherwise,
590 * reset the stipple pattern at each packet (line strips, line loops).
591 */
592 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
593 rs->pa_sc_line_stipple |
594 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
595 sctx->context_roll = true;
596 }
597
598 if (rast_prim != sctx->last_rast_prim &&
599 (sctx->ngg || sctx->gs_shader.cso)) {
600 unsigned gs_out = si_conv_prim_to_gs_out(sctx->current_rast_prim);
601 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
602 sctx->context_roll = true;
603
604 if (sctx->chip_class >= GFX10) {
605 sctx->current_vs_state &= C_VS_STATE_OUTPRIM;
606 sctx->current_vs_state |= S_VS_STATE_OUTPRIM(gs_out);
607 }
608 }
609
610 sctx->last_rast_prim = rast_prim;
611 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
612 }
613
614 static void si_emit_vs_state(struct si_context *sctx,
615 const struct pipe_draw_info *info)
616 {
617 sctx->current_vs_state &= C_VS_STATE_INDEXED;
618 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
619
620 if (sctx->num_vs_blit_sgprs) {
621 /* Re-emit the state after we leave u_blitter. */
622 sctx->last_vs_state = ~0;
623 return;
624 }
625
626 if (sctx->current_vs_state != sctx->last_vs_state) {
627 struct radeon_cmdbuf *cs = sctx->gfx_cs;
628
629 /* For the API vertex shader (VS_STATE_INDEXED). */
630 radeon_set_sh_reg(cs,
631 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
632 SI_SGPR_VS_STATE_BITS * 4,
633 sctx->current_vs_state);
634
635 /* For vertex color clamping, which is done in the last stage
636 * before the rasterizer. */
637 if (sctx->gs_shader.cso || sctx->tes_shader.cso) {
638 /* GS copy shader or TES if GS is missing. */
639 radeon_set_sh_reg(cs,
640 R_00B130_SPI_SHADER_USER_DATA_VS_0 +
641 SI_SGPR_VS_STATE_BITS * 4,
642 sctx->current_vs_state);
643 }
644
645 sctx->last_vs_state = sctx->current_vs_state;
646 }
647 }
648
649 static inline bool si_prim_restart_index_changed(struct si_context *sctx,
650 bool primitive_restart,
651 unsigned restart_index)
652 {
653 return primitive_restart &&
654 (restart_index != sctx->last_restart_index ||
655 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
656 }
657
658 static void si_emit_ia_multi_vgt_param(struct si_context *sctx,
659 const struct pipe_draw_info *info,
660 enum pipe_prim_type prim,
661 unsigned num_patches,
662 unsigned instance_count,
663 bool primitive_restart)
664 {
665 struct radeon_cmdbuf *cs = sctx->gfx_cs;
666 unsigned ia_multi_vgt_param;
667
668 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, prim, num_patches,
669 instance_count, primitive_restart);
670
671 /* Draw state. */
672 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
673 if (sctx->chip_class >= GFX9)
674 radeon_set_uconfig_reg_idx(cs, sctx->screen,
675 R_030960_IA_MULTI_VGT_PARAM, 4,
676 ia_multi_vgt_param);
677 else if (sctx->chip_class >= GFX7)
678 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
679 else
680 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
681
682 sctx->last_multi_vgt_param = ia_multi_vgt_param;
683 }
684 }
685
686 /* GFX10 removed IA_MULTI_VGT_PARAM in exchange for GE_CNTL.
687 * We overload last_multi_vgt_param.
688 */
689 static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches)
690 {
691 if (sctx->ngg)
692 return; /* set during PM4 emit */
693
694 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
695 unsigned primgroup_size;
696 unsigned vertgroup_size;
697
698 if (sctx->tes_shader.cso) {
699 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
700 vertgroup_size = 0;
701 } else if (sctx->gs_shader.cso) {
702 unsigned vgt_gs_onchip_cntl = sctx->gs_shader.current->ctx_reg.gs.vgt_gs_onchip_cntl;
703 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
704 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
705 } else {
706 primgroup_size = 128; /* recommended without a GS and tess */
707 vertgroup_size = 0;
708 }
709
710 unsigned ge_cntl =
711 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
712 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
713 S_03096C_PACKET_TO_ONE_PA(key.u.line_stipple_enabled) |
714 S_03096C_BREAK_WAVE_AT_EOI(key.u.uses_tess && key.u.tess_uses_prim_id);
715
716 if (ge_cntl != sctx->last_multi_vgt_param) {
717 radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, ge_cntl);
718 sctx->last_multi_vgt_param = ge_cntl;
719 }
720 }
721
722 static void si_emit_draw_registers(struct si_context *sctx,
723 const struct pipe_draw_info *info,
724 enum pipe_prim_type prim,
725 unsigned num_patches,
726 unsigned instance_count,
727 bool primitive_restart)
728 {
729 struct radeon_cmdbuf *cs = sctx->gfx_cs;
730 unsigned vgt_prim = si_conv_pipe_prim(info->mode);
731
732 if (sctx->chip_class >= GFX10)
733 gfx10_emit_ge_cntl(sctx, num_patches);
734 else
735 si_emit_ia_multi_vgt_param(sctx, info, prim, num_patches,
736 instance_count, primitive_restart);
737
738 if (vgt_prim != sctx->last_prim) {
739 if (sctx->chip_class >= GFX7)
740 radeon_set_uconfig_reg_idx(cs, sctx->screen,
741 R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
742 else
743 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);
744
745 sctx->last_prim = vgt_prim;
746 }
747
748 /* Primitive restart. */
749 if (primitive_restart != sctx->last_primitive_restart_en) {
750 if (sctx->chip_class >= GFX9)
751 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
752 primitive_restart);
753 else
754 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
755 primitive_restart);
756
757 sctx->last_primitive_restart_en = primitive_restart;
758
759 }
760 if (si_prim_restart_index_changed(sctx, primitive_restart, info->restart_index)) {
761 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
762 info->restart_index);
763 sctx->last_restart_index = info->restart_index;
764 sctx->context_roll = true;
765 }
766 }
767
768 static void si_emit_draw_packets(struct si_context *sctx,
769 const struct pipe_draw_info *info,
770 struct pipe_resource *indexbuf,
771 unsigned index_size,
772 unsigned index_offset,
773 unsigned instance_count,
774 bool dispatch_prim_discard_cs,
775 unsigned original_index_size)
776 {
777 struct pipe_draw_indirect_info *indirect = info->indirect;
778 struct radeon_cmdbuf *cs = sctx->gfx_cs;
779 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
780 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
781 uint32_t index_max_size = 0;
782 uint64_t index_va = 0;
783
784 if (info->count_from_stream_output) {
785 struct si_streamout_target *t =
786 (struct si_streamout_target*)info->count_from_stream_output;
787
788 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
789 t->stride_in_dw);
790 si_cp_copy_data(sctx, sctx->gfx_cs,
791 COPY_DATA_REG, NULL,
792 R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2,
793 COPY_DATA_SRC_MEM, t->buf_filled_size,
794 t->buf_filled_size_offset);
795 }
796
797 /* draw packet */
798 if (index_size) {
799 if (index_size != sctx->last_index_size) {
800 unsigned index_type;
801
802 /* index type */
803 switch (index_size) {
804 case 1:
805 index_type = V_028A7C_VGT_INDEX_8;
806 break;
807 case 2:
808 index_type = V_028A7C_VGT_INDEX_16 |
809 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
810 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
811 break;
812 case 4:
813 index_type = V_028A7C_VGT_INDEX_32 |
814 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
815 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
816 break;
817 default:
818 assert(!"unreachable");
819 return;
820 }
821
822 if (sctx->chip_class >= GFX9) {
823 radeon_set_uconfig_reg_idx(cs, sctx->screen,
824 R_03090C_VGT_INDEX_TYPE, 2,
825 index_type);
826 } else {
827 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
828 radeon_emit(cs, index_type);
829 }
830
831 sctx->last_index_size = index_size;
832 }
833
834 if (original_index_size) {
835 index_max_size = (indexbuf->width0 - index_offset) /
836 original_index_size;
837 index_va = si_resource(indexbuf)->gpu_address + index_offset;
838
839 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
840 si_resource(indexbuf),
841 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
842 }
843 } else {
844 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
845 * so the state must be re-emitted before the next indexed draw.
846 */
847 if (sctx->chip_class >= GFX7)
848 sctx->last_index_size = -1;
849 }
850
851 if (indirect) {
852 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address;
853
854 assert(indirect_va % 8 == 0);
855
856 si_invalidate_draw_sh_constants(sctx);
857
858 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
859 radeon_emit(cs, 1);
860 radeon_emit(cs, indirect_va);
861 radeon_emit(cs, indirect_va >> 32);
862
863 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
864 si_resource(indirect->buffer),
865 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
866
867 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
868 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
869
870 assert(indirect->offset % 4 == 0);
871
872 if (index_size) {
873 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
874 radeon_emit(cs, index_va);
875 radeon_emit(cs, index_va >> 32);
876
877 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
878 radeon_emit(cs, index_max_size);
879 }
880
881 if (!sctx->screen->has_draw_indirect_multi) {
882 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
883 : PKT3_DRAW_INDIRECT,
884 3, render_cond_bit));
885 radeon_emit(cs, indirect->offset);
886 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
887 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
888 radeon_emit(cs, di_src_sel);
889 } else {
890 uint64_t count_va = 0;
891
892 if (indirect->indirect_draw_count) {
893 struct si_resource *params_buf =
894 si_resource(indirect->indirect_draw_count);
895
896 radeon_add_to_buffer_list(
897 sctx, sctx->gfx_cs, params_buf,
898 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
899
900 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
901 }
902
903 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
904 PKT3_DRAW_INDIRECT_MULTI,
905 8, render_cond_bit));
906 radeon_emit(cs, indirect->offset);
907 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
908 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
909 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
910 S_2C3_DRAW_INDEX_ENABLE(1) |
911 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
912 radeon_emit(cs, indirect->draw_count);
913 radeon_emit(cs, count_va);
914 radeon_emit(cs, count_va >> 32);
915 radeon_emit(cs, indirect->stride);
916 radeon_emit(cs, di_src_sel);
917 }
918 } else {
919 int base_vertex;
920
921 if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
922 sctx->last_instance_count != instance_count) {
923 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
924 radeon_emit(cs, instance_count);
925 sctx->last_instance_count = instance_count;
926 }
927
928 /* Base vertex and start instance. */
929 base_vertex = original_index_size ? info->index_bias : info->start;
930
931 if (sctx->num_vs_blit_sgprs) {
932 /* Re-emit draw constants after we leave u_blitter. */
933 si_invalidate_draw_sh_constants(sctx);
934
935 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
936 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
937 sctx->num_vs_blit_sgprs);
938 radeon_emit_array(cs, sctx->vs_blit_sh_data,
939 sctx->num_vs_blit_sgprs);
940 } else if (base_vertex != sctx->last_base_vertex ||
941 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
942 info->start_instance != sctx->last_start_instance ||
943 info->drawid != sctx->last_drawid ||
944 sh_base_reg != sctx->last_sh_base_reg) {
945 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
946 radeon_emit(cs, base_vertex);
947 radeon_emit(cs, info->start_instance);
948 radeon_emit(cs, info->drawid);
949
950 sctx->last_base_vertex = base_vertex;
951 sctx->last_start_instance = info->start_instance;
952 sctx->last_drawid = info->drawid;
953 sctx->last_sh_base_reg = sh_base_reg;
954 }
955
956 if (index_size) {
957 if (dispatch_prim_discard_cs) {
958 index_va += info->start * original_index_size;
959 index_max_size = MIN2(index_max_size, info->count);
960
961 si_dispatch_prim_discard_cs_and_draw(sctx, info,
962 original_index_size,
963 base_vertex,
964 index_va, index_max_size);
965 return;
966 }
967
968 index_va += info->start * index_size;
969
970 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
971 radeon_emit(cs, index_max_size);
972 radeon_emit(cs, index_va);
973 radeon_emit(cs, index_va >> 32);
974 radeon_emit(cs, info->count);
975 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
976 } else {
977 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
978 radeon_emit(cs, info->count);
979 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
980 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
981 }
982 }
983 }
984
985 void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs,
986 unsigned cp_coher_cntl)
987 {
988 bool compute_ib = !sctx->has_graphics ||
989 cs == sctx->prim_discard_compute_cs;
990
991 if (sctx->chip_class >= GFX9 || compute_ib) {
992 /* Flush caches and wait for the caches to assert idle. */
993 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
994 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
995 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
996 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
997 radeon_emit(cs, 0); /* CP_COHER_BASE */
998 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
999 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1000 } else {
1001 /* ACQUIRE_MEM is only required on a compute ring. */
1002 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
1003 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1004 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1005 radeon_emit(cs, 0); /* CP_COHER_BASE */
1006 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1007 }
1008
1009 /* ACQUIRE_MEM has an implicit context roll if the current context
1010 * is busy. */
1011 if (!compute_ib)
1012 sctx->context_roll = true;
1013 }
1014
1015 void si_prim_discard_signal_next_compute_ib_start(struct si_context *sctx)
1016 {
1017 if (!si_compute_prim_discard_enabled(sctx))
1018 return;
1019
1020 if (!sctx->barrier_buf) {
1021 u_suballocator_alloc(sctx->allocator_zeroed_memory, 4, 4,
1022 &sctx->barrier_buf_offset,
1023 (struct pipe_resource**)&sctx->barrier_buf);
1024 }
1025
1026 /* Emit a placeholder to signal the next compute IB to start.
1027 * See si_compute_prim_discard.c for explanation.
1028 */
1029 uint32_t signal = 1;
1030 si_cp_write_data(sctx, sctx->barrier_buf, sctx->barrier_buf_offset,
1031 4, V_370_MEM, V_370_ME, &signal);
1032
1033 sctx->last_pkt3_write_data =
1034 &sctx->gfx_cs->current.buf[sctx->gfx_cs->current.cdw - 5];
1035
1036 /* Only the last occurence of WRITE_DATA will be executed.
1037 * The packet will be enabled in si_flush_gfx_cs.
1038 */
1039 *sctx->last_pkt3_write_data = PKT3(PKT3_NOP, 3, 0);
1040 }
1041
1042 void gfx10_emit_cache_flush(struct si_context *ctx)
1043 {
1044 struct radeon_cmdbuf *cs = ctx->gfx_cs;
1045 uint32_t gcr_cntl = 0;
1046 unsigned cb_db_event = 0;
1047 unsigned flags = ctx->flags;
1048
1049 if (!ctx->has_graphics) {
1050 /* Only process compute flags. */
1051 flags &= SI_CONTEXT_INV_ICACHE |
1052 SI_CONTEXT_INV_SCACHE |
1053 SI_CONTEXT_INV_VCACHE |
1054 SI_CONTEXT_INV_L2 |
1055 SI_CONTEXT_WB_L2 |
1056 SI_CONTEXT_INV_L2_METADATA |
1057 SI_CONTEXT_CS_PARTIAL_FLUSH;
1058 }
1059
1060 /* We don't need these. */
1061 assert(!(flags & (SI_CONTEXT_VGT_FLUSH |
1062 SI_CONTEXT_VGT_STREAMOUT_SYNC |
1063 SI_CONTEXT_FLUSH_AND_INV_DB_META)));
1064
1065 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1066 ctx->num_cb_cache_flushes++;
1067 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1068 ctx->num_db_cache_flushes++;
1069
1070 if (flags & SI_CONTEXT_INV_ICACHE)
1071 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
1072 if (flags & SI_CONTEXT_INV_SCACHE) {
1073 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
1074 * to FORWARD when both L1 and L2 are written out (WB or INV).
1075 */
1076 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
1077 }
1078 if (flags & SI_CONTEXT_INV_VCACHE)
1079 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
1080 if (flags & SI_CONTEXT_INV_L2) {
1081 /* Writeback and invalidate everything in L2. */
1082 gcr_cntl |= S_586_GL2_INV(1) | S_586_GLM_INV(1);
1083 ctx->num_L2_invalidates++;
1084 } else if (flags & SI_CONTEXT_WB_L2) {
1085 /* Writeback but do not invalidate. */
1086 gcr_cntl |= S_586_GL2_WB(1);
1087 }
1088 if (flags & SI_CONTEXT_INV_L2_METADATA)
1089 gcr_cntl |= S_586_GLM_INV(1);
1090
1091 if (flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1092 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1093 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1094 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1095 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
1096 EVENT_INDEX(0));
1097 }
1098 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1099 /* Flush HTILE. Will wait for idle later. */
1100 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1101 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
1102 EVENT_INDEX(0));
1103 }
1104
1105 /* First flush CB/DB, then L1/L2. */
1106 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
1107
1108 if ((flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) ==
1109 (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1110 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1111 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1112 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1113 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1114 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1115 } else {
1116 assert(0);
1117 }
1118 } else {
1119 /* Wait for graphics shaders to go idle if requested. */
1120 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1121 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1122 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1123 /* Only count explicit shader flushes, not implicit ones. */
1124 ctx->num_vs_flushes++;
1125 ctx->num_ps_flushes++;
1126 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1127 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1128 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1129 ctx->num_vs_flushes++;
1130 }
1131 }
1132
1133 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH && ctx->compute_is_busy) {
1134 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1135 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
1136 ctx->num_cs_flushes++;
1137 ctx->compute_is_busy = false;
1138 }
1139
1140 if (cb_db_event) {
1141 /* CB/DB flush and invalidate (or possibly just a wait for a
1142 * meta flush) via RELEASE_MEM.
1143 *
1144 * Combine this with other cache flushes when possible; this
1145 * requires affected shaders to be idle, so do it after the
1146 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1147 * implied).
1148 */
1149 uint64_t va;
1150
1151 /* Do the flush (enqueue the event and wait for it). */
1152 va = ctx->wait_mem_scratch->gpu_address;
1153 ctx->wait_mem_number++;
1154
1155 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1156 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
1157 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
1158 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
1159 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
1160 assert(G_586_GL2_US(gcr_cntl) == 0);
1161 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
1162 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
1163 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
1164 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
1165 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
1166
1167 gcr_cntl &= C_586_GLM_WB &
1168 C_586_GLM_INV &
1169 C_586_GLV_INV &
1170 C_586_GL1_INV &
1171 C_586_GL2_INV &
1172 C_586_GL2_WB; /* keep SEQ */
1173
1174 si_cp_release_mem(ctx, cs, cb_db_event,
1175 S_490_GLM_WB(glm_wb) |
1176 S_490_GLM_INV(glm_inv) |
1177 S_490_GLV_INV(glv_inv) |
1178 S_490_GL1_INV(gl1_inv) |
1179 S_490_GL2_INV(gl2_inv) |
1180 S_490_GL2_WB(gl2_wb) |
1181 S_490_SEQ(gcr_seq),
1182 EOP_DST_SEL_MEM,
1183 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1184 EOP_DATA_SEL_VALUE_32BIT,
1185 ctx->wait_mem_scratch, va,
1186 ctx->wait_mem_number, SI_NOT_QUERY);
1187 si_cp_wait_mem(ctx, ctx->gfx_cs, va, ctx->wait_mem_number, 0xffffffff,
1188 WAIT_REG_MEM_EQUAL);
1189 }
1190
1191 /* Ignore fields that only modify the behavior of other fields. */
1192 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1193 /* Flush caches and wait for the caches to assert idle.
1194 * The cache flush is executed in the ME, but the PFP waits
1195 * for completion.
1196 */
1197 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1198 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1199 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1200 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1201 radeon_emit(cs, 0); /* CP_COHER_BASE */
1202 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1203 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1204 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1205 } else if (cb_db_event ||
1206 (flags & (SI_CONTEXT_VS_PARTIAL_FLUSH |
1207 SI_CONTEXT_PS_PARTIAL_FLUSH |
1208 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1209 /* We need to ensure that PFP waits as well. */
1210 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1211 radeon_emit(cs, 0);
1212 }
1213
1214 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1215 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1216 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1217 EVENT_INDEX(0));
1218 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1219 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1220 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1221 EVENT_INDEX(0));
1222 }
1223
1224 ctx->flags = 0;
1225 }
1226
1227 void si_emit_cache_flush(struct si_context *sctx)
1228 {
1229 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1230 uint32_t flags = sctx->flags;
1231
1232 if (!sctx->has_graphics) {
1233 /* Only process compute flags. */
1234 flags &= SI_CONTEXT_INV_ICACHE |
1235 SI_CONTEXT_INV_SCACHE |
1236 SI_CONTEXT_INV_VCACHE |
1237 SI_CONTEXT_INV_L2 |
1238 SI_CONTEXT_WB_L2 |
1239 SI_CONTEXT_INV_L2_METADATA |
1240 SI_CONTEXT_CS_PARTIAL_FLUSH;
1241 }
1242
1243 uint32_t cp_coher_cntl = 0;
1244 const uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1245 SI_CONTEXT_FLUSH_AND_INV_DB);
1246 const bool is_barrier = flush_cb_db ||
1247 /* INV_ICACHE == beginning of gfx IB. Checking
1248 * INV_ICACHE fixes corruption for DeusExMD with
1249 * compute-based culling, but I don't know why.
1250 */
1251 flags & (SI_CONTEXT_INV_ICACHE |
1252 SI_CONTEXT_PS_PARTIAL_FLUSH |
1253 SI_CONTEXT_VS_PARTIAL_FLUSH) ||
1254 (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1255 sctx->compute_is_busy);
1256
1257 assert(sctx->chip_class <= GFX9);
1258
1259 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1260 sctx->num_cb_cache_flushes++;
1261 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1262 sctx->num_db_cache_flushes++;
1263
1264 /* GFX6 has a bug that it always flushes ICACHE and KCACHE if either
1265 * bit is set. An alternative way is to write SQC_CACHES, but that
1266 * doesn't seem to work reliably. Since the bug doesn't affect
1267 * correctness (it only does more work than necessary) and
1268 * the performance impact is likely negligible, there is no plan
1269 * to add a workaround for it.
1270 */
1271
1272 if (flags & SI_CONTEXT_INV_ICACHE)
1273 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1274 if (flags & SI_CONTEXT_INV_SCACHE)
1275 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1276
1277 if (sctx->chip_class <= GFX8) {
1278 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1279 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1280 S_0085F0_CB0_DEST_BASE_ENA(1) |
1281 S_0085F0_CB1_DEST_BASE_ENA(1) |
1282 S_0085F0_CB2_DEST_BASE_ENA(1) |
1283 S_0085F0_CB3_DEST_BASE_ENA(1) |
1284 S_0085F0_CB4_DEST_BASE_ENA(1) |
1285 S_0085F0_CB5_DEST_BASE_ENA(1) |
1286 S_0085F0_CB6_DEST_BASE_ENA(1) |
1287 S_0085F0_CB7_DEST_BASE_ENA(1);
1288
1289 /* Necessary for DCC */
1290 if (sctx->chip_class == GFX8)
1291 si_cp_release_mem(sctx, cs,
1292 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1293 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
1294 EOP_DATA_SEL_DISCARD, NULL,
1295 0, 0, SI_NOT_QUERY);
1296 }
1297 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1298 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1299 S_0085F0_DB_DEST_BASE_ENA(1);
1300 }
1301
1302 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1303 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
1304 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1305 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1306 }
1307 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
1308 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
1309 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
1310 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1311 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1312 }
1313
1314 /* Wait for shader engines to go idle.
1315 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
1316 * for everything including CB/DB cache flushes.
1317 */
1318 if (!flush_cb_db) {
1319 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1320 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1321 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1322 /* Only count explicit shader flushes, not implicit ones
1323 * done by SURFACE_SYNC.
1324 */
1325 sctx->num_vs_flushes++;
1326 sctx->num_ps_flushes++;
1327 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1328 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1329 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1330 sctx->num_vs_flushes++;
1331 }
1332 }
1333
1334 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1335 sctx->compute_is_busy) {
1336 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1337 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1338 sctx->num_cs_flushes++;
1339 sctx->compute_is_busy = false;
1340 }
1341
1342 /* VGT state synchronization. */
1343 if (flags & SI_CONTEXT_VGT_FLUSH) {
1344 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1345 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1346 }
1347 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
1348 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1349 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1350 }
1351
1352 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
1353 * wait for idle on GFX9. We have to use a TS event.
1354 */
1355 if (sctx->chip_class >= GFX9 && flush_cb_db) {
1356 uint64_t va;
1357 unsigned tc_flags, cb_db_event;
1358
1359 /* Set the CB/DB flush event. */
1360 switch (flush_cb_db) {
1361 case SI_CONTEXT_FLUSH_AND_INV_CB:
1362 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1363 break;
1364 case SI_CONTEXT_FLUSH_AND_INV_DB:
1365 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1366 break;
1367 default:
1368 /* both CB & DB */
1369 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1370 }
1371
1372 /* These are the only allowed combinations. If you need to
1373 * do multiple operations at once, do them separately.
1374 * All operations that invalidate L2 also seem to invalidate
1375 * metadata. Volatile (VOL) and WC flushes are not listed here.
1376 *
1377 * TC | TC_WB = writeback & invalidate L2 & L1
1378 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1379 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1380 * TC | TC_NC = invalidate L2 for MTYPE == NC
1381 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1382 * TCL1 = invalidate L1
1383 */
1384 tc_flags = 0;
1385
1386 if (flags & SI_CONTEXT_INV_L2_METADATA) {
1387 tc_flags = EVENT_TC_ACTION_ENA |
1388 EVENT_TC_MD_ACTION_ENA;
1389 }
1390
1391 /* Ideally flush TC together with CB/DB. */
1392 if (flags & SI_CONTEXT_INV_L2) {
1393 /* Writeback and invalidate everything in L2 & L1. */
1394 tc_flags = EVENT_TC_ACTION_ENA |
1395 EVENT_TC_WB_ACTION_ENA;
1396
1397 /* Clear the flags. */
1398 flags &= ~(SI_CONTEXT_INV_L2 |
1399 SI_CONTEXT_WB_L2 |
1400 SI_CONTEXT_INV_VCACHE);
1401 sctx->num_L2_invalidates++;
1402 }
1403
1404 /* Do the flush (enqueue the event and wait for it). */
1405 va = sctx->wait_mem_scratch->gpu_address;
1406 sctx->wait_mem_number++;
1407
1408 si_cp_release_mem(sctx, cs, cb_db_event, tc_flags,
1409 EOP_DST_SEL_MEM,
1410 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1411 EOP_DATA_SEL_VALUE_32BIT,
1412 sctx->wait_mem_scratch, va,
1413 sctx->wait_mem_number, SI_NOT_QUERY);
1414 si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff,
1415 WAIT_REG_MEM_EQUAL);
1416 }
1417
1418 /* Make sure ME is idle (it executes most packets) before continuing.
1419 * This prevents read-after-write hazards between PFP and ME.
1420 */
1421 if (sctx->has_graphics &&
1422 (cp_coher_cntl ||
1423 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1424 SI_CONTEXT_INV_VCACHE |
1425 SI_CONTEXT_INV_L2 |
1426 SI_CONTEXT_WB_L2)))) {
1427 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1428 radeon_emit(cs, 0);
1429 }
1430
1431 /* GFX6-GFX8 only:
1432 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1433 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1434 *
1435 * cp_coher_cntl should contain all necessary flags except TC flags
1436 * at this point.
1437 *
1438 * GFX6-GFX7 don't support L2 write-back.
1439 */
1440 if (flags & SI_CONTEXT_INV_L2 ||
1441 (sctx->chip_class <= GFX7 &&
1442 (flags & SI_CONTEXT_WB_L2))) {
1443 /* Invalidate L1 & L2. (L1 is always invalidated on GFX6)
1444 * WB must be set on GFX8+ when TC_ACTION is set.
1445 */
1446 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1447 S_0085F0_TC_ACTION_ENA(1) |
1448 S_0085F0_TCL1_ACTION_ENA(1) |
1449 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= GFX8));
1450 cp_coher_cntl = 0;
1451 sctx->num_L2_invalidates++;
1452 } else {
1453 /* L1 invalidation and L2 writeback must be done separately,
1454 * because both operations can't be done together.
1455 */
1456 if (flags & SI_CONTEXT_WB_L2) {
1457 /* WB = write-back
1458 * NC = apply to non-coherent MTYPEs
1459 * (i.e. MTYPE <= 1, which is what we use everywhere)
1460 *
1461 * WB doesn't work without NC.
1462 */
1463 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1464 S_0301F0_TC_WB_ACTION_ENA(1) |
1465 S_0301F0_TC_NC_ACTION_ENA(1));
1466 cp_coher_cntl = 0;
1467 sctx->num_L2_writebacks++;
1468 }
1469 if (flags & SI_CONTEXT_INV_VCACHE) {
1470 /* Invalidate per-CU VMEM L1. */
1471 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1472 S_0085F0_TCL1_ACTION_ENA(1));
1473 cp_coher_cntl = 0;
1474 }
1475 }
1476
1477 /* If TC flushes haven't cleared this... */
1478 if (cp_coher_cntl)
1479 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl);
1480
1481 if (is_barrier)
1482 si_prim_discard_signal_next_compute_ib_start(sctx);
1483
1484 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1485 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1486 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1487 EVENT_INDEX(0));
1488 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1489 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1490 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1491 EVENT_INDEX(0));
1492 }
1493
1494 sctx->flags = 0;
1495 }
1496
1497 static void si_get_draw_start_count(struct si_context *sctx,
1498 const struct pipe_draw_info *info,
1499 unsigned *start, unsigned *count)
1500 {
1501 struct pipe_draw_indirect_info *indirect = info->indirect;
1502
1503 if (indirect) {
1504 unsigned indirect_count;
1505 struct pipe_transfer *transfer;
1506 unsigned begin, end;
1507 unsigned map_size;
1508 unsigned *data;
1509
1510 if (indirect->indirect_draw_count) {
1511 data = pipe_buffer_map_range(&sctx->b,
1512 indirect->indirect_draw_count,
1513 indirect->indirect_draw_count_offset,
1514 sizeof(unsigned),
1515 PIPE_TRANSFER_READ, &transfer);
1516
1517 indirect_count = *data;
1518
1519 pipe_buffer_unmap(&sctx->b, transfer);
1520 } else {
1521 indirect_count = indirect->draw_count;
1522 }
1523
1524 if (!indirect_count) {
1525 *start = *count = 0;
1526 return;
1527 }
1528
1529 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1530 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1531 indirect->offset, map_size,
1532 PIPE_TRANSFER_READ, &transfer);
1533
1534 begin = UINT_MAX;
1535 end = 0;
1536
1537 for (unsigned i = 0; i < indirect_count; ++i) {
1538 unsigned count = data[0];
1539 unsigned start = data[2];
1540
1541 if (count > 0) {
1542 begin = MIN2(begin, start);
1543 end = MAX2(end, start + count);
1544 }
1545
1546 data += indirect->stride / sizeof(unsigned);
1547 }
1548
1549 pipe_buffer_unmap(&sctx->b, transfer);
1550
1551 if (begin < end) {
1552 *start = begin;
1553 *count = end - begin;
1554 } else {
1555 *start = *count = 0;
1556 }
1557 } else {
1558 *start = info->start;
1559 *count = info->count;
1560 }
1561 }
1562
1563 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1564 enum pipe_prim_type prim, unsigned instance_count,
1565 bool primitive_restart, unsigned skip_atom_mask)
1566 {
1567 unsigned num_patches = 0;
1568
1569 si_emit_rasterizer_prim_state(sctx);
1570 if (sctx->tes_shader.cso)
1571 si_emit_derived_tess_state(sctx, info, &num_patches);
1572
1573 /* Emit state atoms. */
1574 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1575 while (mask)
1576 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1577
1578 sctx->dirty_atoms &= skip_atom_mask;
1579
1580 /* Emit states. */
1581 mask = sctx->dirty_states;
1582 while (mask) {
1583 unsigned i = u_bit_scan(&mask);
1584 struct si_pm4_state *state = sctx->queued.array[i];
1585
1586 if (!state || sctx->emitted.array[i] == state)
1587 continue;
1588
1589 si_pm4_emit(sctx, state);
1590 sctx->emitted.array[i] = state;
1591 }
1592 sctx->dirty_states = 0;
1593
1594 /* Emit draw states. */
1595 si_emit_vs_state(sctx, info);
1596 si_emit_draw_registers(sctx, info, prim, num_patches, instance_count,
1597 primitive_restart);
1598 }
1599
1600 static bool
1601 si_all_vs_resources_read_only(struct si_context *sctx,
1602 struct pipe_resource *indexbuf)
1603 {
1604 struct radeon_winsys *ws = sctx->ws;
1605 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1606
1607 /* Index buffer. */
1608 if (indexbuf &&
1609 ws->cs_is_buffer_referenced(cs, si_resource(indexbuf)->buf,
1610 RADEON_USAGE_WRITE))
1611 goto has_write_reference;
1612
1613 /* Vertex buffers. */
1614 struct si_vertex_elements *velems = sctx->vertex_elements;
1615 unsigned num_velems = velems->count;
1616
1617 for (unsigned i = 0; i < num_velems; i++) {
1618 if (!((1 << i) & velems->first_vb_use_mask))
1619 continue;
1620
1621 unsigned vb_index = velems->vertex_buffer_index[i];
1622 struct pipe_resource *res = sctx->vertex_buffer[vb_index].buffer.resource;
1623 if (!res)
1624 continue;
1625
1626 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1627 RADEON_USAGE_WRITE))
1628 goto has_write_reference;
1629 }
1630
1631 /* Constant and shader buffers. */
1632 struct si_descriptors *buffers =
1633 &sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_VERTEX)];
1634 for (unsigned i = 0; i < buffers->num_active_slots; i++) {
1635 unsigned index = buffers->first_active_slot + i;
1636 struct pipe_resource *res =
1637 sctx->const_and_shader_buffers[PIPE_SHADER_VERTEX].buffers[index];
1638 if (!res)
1639 continue;
1640
1641 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1642 RADEON_USAGE_WRITE))
1643 goto has_write_reference;
1644 }
1645
1646 /* Samplers. */
1647 struct si_shader_selector *vs = sctx->vs_shader.cso;
1648 if (vs->info.samplers_declared) {
1649 unsigned num_samplers = util_last_bit(vs->info.samplers_declared);
1650
1651 for (unsigned i = 0; i < num_samplers; i++) {
1652 struct pipe_sampler_view *view = sctx->samplers[PIPE_SHADER_VERTEX].views[i];
1653 if (!view)
1654 continue;
1655
1656 if (ws->cs_is_buffer_referenced(cs,
1657 si_resource(view->texture)->buf,
1658 RADEON_USAGE_WRITE))
1659 goto has_write_reference;
1660 }
1661 }
1662
1663 /* Images. */
1664 if (vs->info.images_declared) {
1665 unsigned num_images = util_last_bit(vs->info.images_declared);
1666
1667 for (unsigned i = 0; i < num_images; i++) {
1668 struct pipe_resource *res = sctx->images[PIPE_SHADER_VERTEX].views[i].resource;
1669 if (!res)
1670 continue;
1671
1672 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1673 RADEON_USAGE_WRITE))
1674 goto has_write_reference;
1675 }
1676 }
1677
1678 return true;
1679
1680 has_write_reference:
1681 /* If the current gfx IB has enough packets, flush it to remove write
1682 * references to buffers.
1683 */
1684 if (cs->prev_dw + cs->current.cdw > 2048) {
1685 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1686 assert(si_all_vs_resources_read_only(sctx, indexbuf));
1687 return true;
1688 }
1689 return false;
1690 }
1691
1692 static ALWAYS_INLINE bool pd_msg(const char *s)
1693 {
1694 if (SI_PRIM_DISCARD_DEBUG)
1695 printf("PD failed: %s\n", s);
1696 return false;
1697 }
1698
1699 static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1700 {
1701 struct si_context *sctx = (struct si_context *)ctx;
1702 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1703 struct pipe_resource *indexbuf = info->index.resource;
1704 unsigned dirty_tex_counter, dirty_buf_counter;
1705 enum pipe_prim_type rast_prim, prim = info->mode;
1706 unsigned index_size = info->index_size;
1707 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1708 unsigned instance_count = info->instance_count;
1709 bool primitive_restart = info->primitive_restart &&
1710 (!sctx->screen->options.prim_restart_tri_strips_only ||
1711 (prim != PIPE_PRIM_TRIANGLE_STRIP &&
1712 prim != PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY));
1713
1714 if (likely(!info->indirect)) {
1715 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
1716 * no workaround for indirect draws, but we can at least skip
1717 * direct draws.
1718 */
1719 if (unlikely(!instance_count))
1720 return;
1721
1722 /* Handle count == 0. */
1723 if (unlikely(!info->count &&
1724 (index_size || !info->count_from_stream_output)))
1725 return;
1726 }
1727
1728 if (unlikely(!sctx->vs_shader.cso ||
1729 !rs ||
1730 (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
1731 (!!sctx->tes_shader.cso != (prim == PIPE_PRIM_PATCHES)))) {
1732 assert(0);
1733 return;
1734 }
1735
1736 /* Recompute and re-emit the texture resource states if needed. */
1737 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1738 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1739 sctx->last_dirty_tex_counter = dirty_tex_counter;
1740 sctx->framebuffer.dirty_cbufs |=
1741 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1742 sctx->framebuffer.dirty_zsbuf = true;
1743 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1744 si_update_all_texture_descriptors(sctx);
1745 }
1746
1747 dirty_buf_counter = p_atomic_read(&sctx->screen->dirty_buf_counter);
1748 if (unlikely(dirty_buf_counter != sctx->last_dirty_buf_counter)) {
1749 sctx->last_dirty_buf_counter = dirty_buf_counter;
1750 /* Rebind all buffers unconditionally. */
1751 si_rebind_buffer(sctx, NULL);
1752 }
1753
1754 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1755
1756 /* Set the rasterization primitive type.
1757 *
1758 * This must be done after si_decompress_textures, which can call
1759 * draw_vbo recursively, and before si_update_shaders, which uses
1760 * current_rast_prim for this draw_vbo call. */
1761 if (sctx->gs_shader.cso)
1762 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1763 else if (sctx->tes_shader.cso) {
1764 if (sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1765 rast_prim = PIPE_PRIM_POINTS;
1766 else
1767 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1768 } else
1769 rast_prim = prim;
1770
1771 if (rast_prim != sctx->current_rast_prim) {
1772 if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
1773 util_prim_is_points_or_lines(rast_prim))
1774 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1775
1776 sctx->current_rast_prim = rast_prim;
1777 sctx->do_update_shaders = true;
1778 }
1779
1780 if (sctx->tes_shader.cso &&
1781 sctx->screen->has_ls_vgpr_init_bug) {
1782 /* Determine whether the LS VGPR fix should be applied.
1783 *
1784 * It is only required when num input CPs > num output CPs,
1785 * which cannot happen with the fixed function TCS. We should
1786 * also update this bit when switching from TCS to fixed
1787 * function TCS.
1788 */
1789 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1790 bool ls_vgpr_fix =
1791 tcs &&
1792 info->vertices_per_patch >
1793 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1794
1795 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1796 sctx->ls_vgpr_fix = ls_vgpr_fix;
1797 sctx->do_update_shaders = true;
1798 }
1799 }
1800
1801 if (sctx->gs_shader.cso) {
1802 /* Determine whether the GS triangle strip adjacency fix should
1803 * be applied. Rotate every other triangle if
1804 * - triangle strips with adjacency are fed to the GS and
1805 * - primitive restart is disabled (the rotation doesn't help
1806 * when the restart occurs after an odd number of triangles).
1807 */
1808 bool gs_tri_strip_adj_fix =
1809 !sctx->tes_shader.cso &&
1810 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1811 !primitive_restart;
1812
1813 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1814 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1815 sctx->do_update_shaders = true;
1816 }
1817 }
1818
1819 if (index_size) {
1820 /* Translate or upload, if needed. */
1821 /* 8-bit indices are supported on GFX8. */
1822 if (sctx->chip_class <= GFX7 && index_size == 1) {
1823 unsigned start, count, start_offset, size, offset;
1824 void *ptr;
1825
1826 si_get_draw_start_count(sctx, info, &start, &count);
1827 start_offset = start * 2;
1828 size = count * 2;
1829
1830 indexbuf = NULL;
1831 u_upload_alloc(ctx->stream_uploader, start_offset,
1832 size,
1833 si_optimal_tcc_alignment(sctx, size),
1834 &offset, &indexbuf, &ptr);
1835 if (!indexbuf)
1836 return;
1837
1838 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1839 index_offset + start,
1840 count, ptr);
1841
1842 /* info->start will be added by the drawing code */
1843 index_offset = offset - start_offset;
1844 index_size = 2;
1845 } else if (info->has_user_indices) {
1846 unsigned start_offset;
1847
1848 assert(!info->indirect);
1849 start_offset = info->start * index_size;
1850
1851 indexbuf = NULL;
1852 u_upload_data(ctx->stream_uploader, start_offset,
1853 info->count * index_size,
1854 sctx->screen->info.tcc_cache_line_size,
1855 (char*)info->index.user + start_offset,
1856 &index_offset, &indexbuf);
1857 if (!indexbuf)
1858 return;
1859
1860 /* info->start will be added by the drawing code */
1861 index_offset -= start_offset;
1862 } else if (sctx->chip_class <= GFX7 &&
1863 si_resource(indexbuf)->TC_L2_dirty) {
1864 /* GFX8 reads index buffers through TC L2, so it doesn't
1865 * need this. */
1866 sctx->flags |= SI_CONTEXT_WB_L2;
1867 si_resource(indexbuf)->TC_L2_dirty = false;
1868 }
1869 }
1870
1871 bool dispatch_prim_discard_cs = false;
1872 bool prim_discard_cs_instancing = false;
1873 unsigned original_index_size = index_size;
1874 unsigned direct_count = 0;
1875
1876 if (info->indirect) {
1877 struct pipe_draw_indirect_info *indirect = info->indirect;
1878
1879 /* Add the buffer size for memory checking in need_cs_space. */
1880 si_context_add_resource_size(sctx, indirect->buffer);
1881
1882 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1883 if (sctx->chip_class <= GFX8) {
1884 if (si_resource(indirect->buffer)->TC_L2_dirty) {
1885 sctx->flags |= SI_CONTEXT_WB_L2;
1886 si_resource(indirect->buffer)->TC_L2_dirty = false;
1887 }
1888
1889 if (indirect->indirect_draw_count &&
1890 si_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1891 sctx->flags |= SI_CONTEXT_WB_L2;
1892 si_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1893 }
1894 }
1895 } else {
1896 /* Multiply by 3 for strips and fans to get an approximate vertex
1897 * count as triangles. */
1898 direct_count = info->count * instance_count *
1899 (prim == PIPE_PRIM_TRIANGLES ? 1 : 3);
1900 }
1901
1902 /* Determine if we can use the primitive discard compute shader. */
1903 if (si_compute_prim_discard_enabled(sctx) &&
1904 (direct_count > sctx->prim_discard_vertex_count_threshold ?
1905 (sctx->compute_num_verts_rejected += direct_count, true) : /* Add, then return true. */
1906 (sctx->compute_num_verts_ineligible += direct_count, false)) && /* Add, then return false. */
1907 (!info->count_from_stream_output || pd_msg("draw_opaque")) &&
1908 (primitive_restart ?
1909 /* Supported prim types with primitive restart: */
1910 (prim == PIPE_PRIM_TRIANGLE_STRIP || pd_msg("bad prim type with primitive restart")) &&
1911 /* Disallow instancing with primitive restart: */
1912 (instance_count == 1 || pd_msg("instance_count > 1 with primitive restart")) :
1913 /* Supported prim types without primitive restart + allow instancing: */
1914 (1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1915 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1916 (1 << PIPE_PRIM_TRIANGLE_FAN)) &&
1917 /* Instancing is limited to 16-bit indices, because InstanceID is packed into VertexID. */
1918 /* TODO: DrawArraysInstanced doesn't sometimes work, so it's disabled. */
1919 (instance_count == 1 ||
1920 (instance_count <= USHRT_MAX && index_size && index_size <= 2) ||
1921 pd_msg("instance_count too large or index_size == 4 or DrawArraysInstanced"))) &&
1922 (info->drawid == 0 || !sctx->vs_shader.cso->info.uses_drawid || pd_msg("draw_id > 0")) &&
1923 (!sctx->render_cond || pd_msg("render condition")) &&
1924 /* Forced enablement ignores pipeline statistics queries. */
1925 (sctx->screen->debug_flags & (DBG(PD) | DBG(ALWAYS_PD)) ||
1926 (!sctx->num_pipeline_stat_queries && !sctx->streamout.prims_gen_query_enabled) ||
1927 pd_msg("pipestat or primgen query")) &&
1928 (!sctx->vertex_elements->instance_divisor_is_fetched || pd_msg("loads instance divisors")) &&
1929 (!sctx->tes_shader.cso || pd_msg("uses tess")) &&
1930 (!sctx->gs_shader.cso || pd_msg("uses GS")) &&
1931 (!sctx->ps_shader.cso->info.uses_primid || pd_msg("PS uses PrimID")) &&
1932 #if SI_PRIM_DISCARD_DEBUG /* same as cso->prim_discard_cs_allowed */
1933 (!sctx->vs_shader.cso->info.uses_bindless_images || pd_msg("uses bindless images")) &&
1934 (!sctx->vs_shader.cso->info.uses_bindless_samplers || pd_msg("uses bindless samplers")) &&
1935 (!sctx->vs_shader.cso->info.writes_memory || pd_msg("writes memory")) &&
1936 (!sctx->vs_shader.cso->info.writes_viewport_index || pd_msg("writes viewport index")) &&
1937 !sctx->vs_shader.cso->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
1938 !sctx->vs_shader.cso->so.num_outputs &&
1939 #else
1940 (sctx->vs_shader.cso->prim_discard_cs_allowed || pd_msg("VS shader uses unsupported features")) &&
1941 #endif
1942 /* Check that all buffers are used for read only, because compute
1943 * dispatches can run ahead. */
1944 (si_all_vs_resources_read_only(sctx, index_size ? indexbuf : NULL) || pd_msg("write reference"))) {
1945 switch (si_prepare_prim_discard_or_split_draw(sctx, info, primitive_restart)) {
1946 case SI_PRIM_DISCARD_ENABLED:
1947 original_index_size = index_size;
1948 prim_discard_cs_instancing = instance_count > 1;
1949 dispatch_prim_discard_cs = true;
1950
1951 /* The compute shader changes/lowers the following: */
1952 prim = PIPE_PRIM_TRIANGLES;
1953 index_size = 4;
1954 instance_count = 1;
1955 primitive_restart = false;
1956 sctx->compute_num_verts_rejected -= direct_count;
1957 sctx->compute_num_verts_accepted += direct_count;
1958 break;
1959 case SI_PRIM_DISCARD_DISABLED:
1960 break;
1961 case SI_PRIM_DISCARD_DRAW_SPLIT:
1962 sctx->compute_num_verts_rejected -= direct_count;
1963 goto return_cleanup;
1964 }
1965 }
1966
1967 if (prim_discard_cs_instancing != sctx->prim_discard_cs_instancing) {
1968 sctx->prim_discard_cs_instancing = prim_discard_cs_instancing;
1969 sctx->do_update_shaders = true;
1970 }
1971
1972 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1973 goto return_cleanup;
1974
1975 si_need_gfx_cs_space(sctx);
1976
1977 if (sctx->bo_list_add_all_gfx_resources)
1978 si_gfx_resources_add_all_to_bo_list(sctx);
1979
1980 /* Since we've called si_context_add_resource_size for vertex buffers,
1981 * this must be called after si_need_cs_space, because we must let
1982 * need_cs_space flush before we add buffers to the buffer list.
1983 */
1984 if (!si_upload_vertex_buffer_descriptors(sctx))
1985 goto return_cleanup;
1986
1987 /* Vega10/Raven scissor bug workaround. When any context register is
1988 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
1989 * registers must be written too.
1990 */
1991 bool has_gfx9_scissor_bug = sctx->screen->has_gfx9_scissor_bug;
1992 unsigned masked_atoms = 0;
1993
1994 if (has_gfx9_scissor_bug) {
1995 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
1996
1997 if (info->count_from_stream_output ||
1998 sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
1999 sctx->dirty_states & si_states_that_always_roll_context())
2000 sctx->context_roll = true;
2001 }
2002
2003 /* Use optimal packet order based on whether we need to sync the pipeline. */
2004 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
2005 SI_CONTEXT_FLUSH_AND_INV_DB |
2006 SI_CONTEXT_PS_PARTIAL_FLUSH |
2007 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
2008 /* If we have to wait for idle, set all states first, so that all
2009 * SET packets are processed in parallel with previous draw calls.
2010 * Then draw and prefetch at the end. This ensures that the time
2011 * the CUs are idle is very short.
2012 */
2013 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
2014 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
2015
2016 if (!si_upload_graphics_shader_descriptors(sctx))
2017 goto return_cleanup;
2018
2019 /* Emit all states except possibly render condition. */
2020 si_emit_all_states(sctx, info, prim, instance_count,
2021 primitive_restart, masked_atoms);
2022 sctx->emit_cache_flush(sctx);
2023 /* <-- CUs are idle here. */
2024
2025 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
2026 sctx->atoms.s.render_cond.emit(sctx);
2027
2028 if (has_gfx9_scissor_bug &&
2029 (sctx->context_roll ||
2030 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
2031 sctx->atoms.s.scissors.emit(sctx);
2032
2033 sctx->dirty_atoms = 0;
2034
2035 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
2036 instance_count, dispatch_prim_discard_cs,
2037 original_index_size);
2038 /* <-- CUs are busy here. */
2039
2040 /* Start prefetches after the draw has been started. Both will run
2041 * in parallel, but starting the draw first is more important.
2042 */
2043 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2044 cik_emit_prefetch_L2(sctx, false);
2045 } else {
2046 /* If we don't wait for idle, start prefetches first, then set
2047 * states, and draw at the end.
2048 */
2049 if (sctx->flags)
2050 sctx->emit_cache_flush(sctx);
2051
2052 /* Only prefetch the API VS and VBO descriptors. */
2053 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2054 cik_emit_prefetch_L2(sctx, true);
2055
2056 if (!si_upload_graphics_shader_descriptors(sctx))
2057 goto return_cleanup;
2058
2059 si_emit_all_states(sctx, info, prim, instance_count,
2060 primitive_restart, masked_atoms);
2061
2062 if (has_gfx9_scissor_bug &&
2063 (sctx->context_roll ||
2064 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
2065 sctx->atoms.s.scissors.emit(sctx);
2066
2067 sctx->dirty_atoms = 0;
2068
2069 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
2070 instance_count, dispatch_prim_discard_cs,
2071 original_index_size);
2072
2073 /* Prefetch the remaining shaders after the draw has been
2074 * started. */
2075 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2076 cik_emit_prefetch_L2(sctx, false);
2077 }
2078
2079 /* Clear the context roll flag after the draw call. */
2080 sctx->context_roll = false;
2081
2082 if (unlikely(sctx->current_saved_cs)) {
2083 si_trace_emit(sctx);
2084 si_log_draw_state(sctx, sctx->log);
2085 }
2086
2087 /* Workaround for a VGT hang when streamout is enabled.
2088 * It must be done after drawing. */
2089 if ((sctx->family == CHIP_HAWAII ||
2090 sctx->family == CHIP_TONGA ||
2091 sctx->family == CHIP_FIJI) &&
2092 si_get_strmout_en(sctx)) {
2093 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
2094 }
2095
2096 if (unlikely(sctx->decompression_enabled)) {
2097 sctx->num_decompress_calls++;
2098 } else {
2099 sctx->num_draw_calls++;
2100 if (sctx->framebuffer.state.nr_cbufs > 1)
2101 sctx->num_mrt_draw_calls++;
2102 if (primitive_restart)
2103 sctx->num_prim_restart_calls++;
2104 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
2105 sctx->num_spill_draw_calls++;
2106 }
2107
2108 return_cleanup:
2109 if (index_size && indexbuf != info->index.resource)
2110 pipe_resource_reference(&indexbuf, NULL);
2111 }
2112
2113 static void
2114 si_draw_rectangle(struct blitter_context *blitter,
2115 void *vertex_elements_cso,
2116 blitter_get_vs_func get_vs,
2117 int x1, int y1, int x2, int y2,
2118 float depth, unsigned num_instances,
2119 enum blitter_attrib_type type,
2120 const union blitter_attrib *attrib)
2121 {
2122 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
2123 struct si_context *sctx = (struct si_context*)pipe;
2124
2125 /* Pack position coordinates as signed int16. */
2126 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
2127 ((uint32_t)(y1 & 0xffff) << 16);
2128 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
2129 ((uint32_t)(y2 & 0xffff) << 16);
2130 sctx->vs_blit_sh_data[2] = fui(depth);
2131
2132 switch (type) {
2133 case UTIL_BLITTER_ATTRIB_COLOR:
2134 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
2135 sizeof(float)*4);
2136 break;
2137 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
2138 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
2139 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
2140 sizeof(attrib->texcoord));
2141 break;
2142 case UTIL_BLITTER_ATTRIB_NONE:;
2143 }
2144
2145 pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
2146
2147 struct pipe_draw_info info = {};
2148 info.mode = SI_PRIM_RECTANGLE_LIST;
2149 info.count = 3;
2150 info.instance_count = num_instances;
2151
2152 /* Don't set per-stage shader pointers for VS. */
2153 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
2154 sctx->vertex_buffer_pointer_dirty = false;
2155
2156 si_draw_vbo(pipe, &info);
2157 }
2158
2159 void si_trace_emit(struct si_context *sctx)
2160 {
2161 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2162 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
2163
2164 si_cp_write_data(sctx, sctx->current_saved_cs->trace_buf,
2165 0, 4, V_370_MEM, V_370_ME, &trace_id);
2166
2167 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2168 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
2169
2170 if (sctx->log)
2171 u_log_flush(sctx->log);
2172 }
2173
2174 void si_init_draw_functions(struct si_context *sctx)
2175 {
2176 sctx->b.draw_vbo = si_draw_vbo;
2177
2178 sctx->blitter->draw_rectangle = si_draw_rectangle;
2179
2180 si_init_ia_multi_vgt_param_table(sctx);
2181 }