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radeonsi: fix a hang with instancing on Hawaii
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "../radeon/r600_cs.h"
30 #include "sid.h"
31
32 #include "util/u_blitter.h"
33 #include "util/u_format.h"
34 #include "util/u_index_modify.h"
35 #include "util/u_memory.h"
36 #include "util/u_prim.h"
37 #include "util/u_upload_mgr.h"
38
39 /*
40 * Shaders
41 */
42
43 static void si_pipe_shader_es(struct pipe_context *ctx, struct si_pipe_shader *shader)
44 {
45 struct si_context *sctx = (struct si_context *)ctx;
46 struct si_pm4_state *pm4;
47 unsigned num_sgprs, num_user_sgprs;
48 unsigned vgpr_comp_cnt;
49 uint64_t va;
50
51 si_pm4_delete_state(sctx, es, shader->pm4);
52 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
53
54 if (pm4 == NULL)
55 return;
56
57 va = r600_resource_va(ctx->screen, (void *)shader->bo);
58 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
59
60 vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
61
62 num_user_sgprs = SI_VS_NUM_USER_SGPR;
63 num_sgprs = shader->num_sgprs;
64 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
65 if ((num_user_sgprs + 1) > num_sgprs) {
66 /* Last 2 reserved SGPRs are used for VCC */
67 num_sgprs = num_user_sgprs + 1 + 2;
68 }
69 assert(num_sgprs <= 104);
70
71 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
72 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
73 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
74 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
75 S_00B328_SGPRS((num_sgprs - 1) / 8) |
76 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt));
77 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
78 S_00B32C_USER_SGPR(num_user_sgprs));
79
80 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
81 }
82
83 static void si_pipe_shader_gs(struct pipe_context *ctx, struct si_pipe_shader *shader)
84 {
85 struct si_context *sctx = (struct si_context *)ctx;
86 unsigned gs_vert_itemsize = shader->shader.noutput * (16 >> 2);
87 unsigned gs_max_vert_out = shader->shader.gs_max_out_vertices;
88 unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
89 unsigned cut_mode;
90 struct si_pm4_state *pm4;
91 unsigned num_sgprs, num_user_sgprs;
92 uint64_t va;
93
94 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
95 assert(gsvs_itemsize < (1 << 15));
96
97 si_pm4_delete_state(sctx, gs, shader->pm4);
98 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
99
100 if (pm4 == NULL)
101 return;
102
103 if (gs_max_vert_out <= 128) {
104 cut_mode = V_028A40_GS_CUT_128;
105 } else if (gs_max_vert_out <= 256) {
106 cut_mode = V_028A40_GS_CUT_256;
107 } else if (gs_max_vert_out <= 512) {
108 cut_mode = V_028A40_GS_CUT_512;
109 } else {
110 assert(gs_max_vert_out <= 1024);
111 cut_mode = V_028A40_GS_CUT_1024;
112 }
113
114 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
115 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
116 S_028A40_CUT_MODE(cut_mode)|
117 S_028A40_ES_WRITE_OPTIMIZE(1) |
118 S_028A40_GS_WRITE_OPTIMIZE(1));
119
120 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
121 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize);
122 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize);
123
124 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
125 shader->shader.nparam * (16 >> 2));
126 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
127
128 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
129
130 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
131
132 va = r600_resource_va(ctx->screen, (void *)shader->bo);
133 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
134 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
135 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
136
137 num_user_sgprs = SI_GS_NUM_USER_SGPR;
138 num_sgprs = shader->num_sgprs;
139 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
140 if ((num_user_sgprs + 2) > num_sgprs) {
141 /* Last 2 reserved SGPRs are used for VCC */
142 num_sgprs = num_user_sgprs + 2 + 2;
143 }
144 assert(num_sgprs <= 104);
145
146 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
147 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
148 S_00B228_SGPRS((num_sgprs - 1) / 8));
149 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
150 S_00B22C_USER_SGPR(num_user_sgprs));
151
152 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
153 }
154
155 static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
156 {
157 struct si_context *sctx = (struct si_context *)ctx;
158 struct si_pm4_state *pm4;
159 unsigned num_sgprs, num_user_sgprs;
160 unsigned nparams, i, vgpr_comp_cnt;
161 uint64_t va;
162
163 si_pm4_delete_state(sctx, vs, shader->pm4);
164 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
165
166 if (pm4 == NULL)
167 return;
168
169 va = r600_resource_va(ctx->screen, (void *)shader->bo);
170 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
171
172 vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
173
174 num_user_sgprs = SI_VS_NUM_USER_SGPR;
175 num_sgprs = shader->num_sgprs;
176 if (num_user_sgprs > num_sgprs) {
177 /* Last 2 reserved SGPRs are used for VCC */
178 num_sgprs = num_user_sgprs + 2;
179 }
180 assert(num_sgprs <= 104);
181
182 /* Certain attributes (position, psize, etc.) don't count as params.
183 * VS is required to export at least one param and r600_shader_from_tgsi()
184 * takes care of adding a dummy export.
185 */
186 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
187 switch (shader->shader.output[i].name) {
188 case TGSI_SEMANTIC_CLIPVERTEX:
189 case TGSI_SEMANTIC_POSITION:
190 case TGSI_SEMANTIC_PSIZE:
191 break;
192 default:
193 nparams++;
194 }
195 }
196 if (nparams < 1)
197 nparams = 1;
198
199 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
200 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
201
202 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
203 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
204 S_02870C_POS1_EXPORT_FORMAT(shader->shader.nr_pos_exports > 1 ?
205 V_02870C_SPI_SHADER_4COMP :
206 V_02870C_SPI_SHADER_NONE) |
207 S_02870C_POS2_EXPORT_FORMAT(shader->shader.nr_pos_exports > 2 ?
208 V_02870C_SPI_SHADER_4COMP :
209 V_02870C_SPI_SHADER_NONE) |
210 S_02870C_POS3_EXPORT_FORMAT(shader->shader.nr_pos_exports > 3 ?
211 V_02870C_SPI_SHADER_4COMP :
212 V_02870C_SPI_SHADER_NONE));
213
214 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
215 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
216 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
217 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
218 S_00B128_SGPRS((num_sgprs - 1) / 8) |
219 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
220 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
221 S_00B12C_USER_SGPR(num_user_sgprs) |
222 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
223 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
224 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
225 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
226 S_00B12C_SO_EN(!!shader->selector->so.num_outputs));
227
228 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
229 }
230
231 static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
232 {
233 struct si_context *sctx = (struct si_context *)ctx;
234 struct si_pm4_state *pm4;
235 unsigned i, spi_ps_in_control, db_shader_control;
236 unsigned num_sgprs, num_user_sgprs;
237 unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
238 uint64_t va;
239
240 si_pm4_delete_state(sctx, ps, shader->pm4);
241 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
242
243 if (pm4 == NULL)
244 return;
245
246 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
247 S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer);
248
249 for (i = 0; i < shader->shader.ninput; i++) {
250 switch (shader->shader.input[i].name) {
251 case TGSI_SEMANTIC_POSITION:
252 if (shader->shader.input[i].centroid) {
253 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
254 * Possible vaules:
255 * 0 -> Position = pixel center (default)
256 * 1 -> Position = pixel centroid
257 * 2 -> Position = iterated sample number XXX:
258 * What does this mean?
259 */
260 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
261 }
262 /* Fall through */
263 case TGSI_SEMANTIC_FACE:
264 continue;
265 }
266 }
267
268 db_shader_control |= shader->db_shader_control;
269
270 if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
271 db_shader_control |= S_02880C_KILL_ENABLE(1);
272
273 if (sctx->b.chip_class >= CIK)
274 db_shader_control |=
275 S_02880C_CONSERVATIVE_Z_EXPORT(shader->shader.ps_conservative_z);
276
277 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.nparam) |
278 S_0286D8_BC_OPTIMIZE_DISABLE(1);
279
280 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
281 spi_ps_input_ena = shader->spi_ps_input_ena;
282 /* we need to enable at least one of them, otherwise we hang the GPU */
283 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
284 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
285 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
286 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
287 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
288 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
289 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
290 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
291
292 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
293 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
294 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
295
296 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
297 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
298 shader->spi_shader_col_format);
299 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
300
301 va = r600_resource_va(ctx->screen, (void *)shader->bo);
302 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
303 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
304 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
305
306 num_user_sgprs = SI_PS_NUM_USER_SGPR;
307 num_sgprs = shader->num_sgprs;
308 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
309 if ((num_user_sgprs + 1) > num_sgprs) {
310 /* Last 2 reserved SGPRs are used for VCC */
311 num_sgprs = num_user_sgprs + 1 + 2;
312 }
313 assert(num_sgprs <= 104);
314
315 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
316 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
317 S_00B028_SGPRS((num_sgprs - 1) / 8));
318 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
319 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
320 S_00B02C_USER_SGPR(num_user_sgprs));
321
322 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
323
324 shader->cb0_is_integer = sctx->framebuffer.cb0_is_integer;
325 shader->sprite_coord_enable = sctx->sprite_coord_enable;
326 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
327 }
328
329 /*
330 * Drawing
331 */
332
333 static unsigned si_conv_pipe_prim(unsigned pprim)
334 {
335 static const unsigned prim_conv[] = {
336 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
337 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
338 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
339 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
340 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
341 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
342 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
343 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
344 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
345 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
346 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
347 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
348 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
349 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ
350 };
351 unsigned result = prim_conv[pprim];
352 if (result == ~0) {
353 R600_ERR("unsupported primitive type %d\n", pprim);
354 }
355 return result;
356 }
357
358 static unsigned si_conv_prim_to_gs_out(unsigned mode)
359 {
360 static const int prim_conv[] = {
361 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
362 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
363 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
364 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
365 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
366 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
367 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
368 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
369 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
370 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
371 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
372 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
373 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
374 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
375 };
376 assert(mode < Elements(prim_conv));
377
378 return prim_conv[mode];
379 }
380
381 static bool si_update_draw_info_state(struct si_context *sctx,
382 const struct pipe_draw_info *info,
383 const struct pipe_index_buffer *ib)
384 {
385 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
386 struct si_shader *vs = si_get_vs_state(sctx);
387 unsigned prim = si_conv_pipe_prim(info->mode);
388 unsigned gs_out_prim =
389 si_conv_prim_to_gs_out(sctx->gs_shader ?
390 sctx->gs_shader->current->shader.gs_output_prim :
391 info->mode);
392 unsigned ls_mask = 0;
393
394 if (pm4 == NULL)
395 return false;
396
397 if (prim == ~0) {
398 FREE(pm4);
399 return false;
400 }
401
402 if (sctx->b.chip_class >= CIK) {
403 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
404 bool wd_switch_on_eop = prim == V_008958_DI_PT_POLYGON ||
405 prim == V_008958_DI_PT_LINELOOP ||
406 prim == V_008958_DI_PT_TRIFAN ||
407 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
408 info->primitive_restart ||
409 (rs ? rs->line_stipple_enable : false);
410 /* If the WD switch is false, the IA switch must be false too. */
411 bool ia_switch_on_eop = wd_switch_on_eop;
412 unsigned primgroup_size = 64;
413
414 /* Hawaii hangs if instancing is enabled and each instance
415 * is smaller than a prim group and WD_SWITCH_ON_EOP is 0.
416 * We don't know that for indirect drawing, so treat it as
417 * always problematic. */
418 if (sctx->b.family == CHIP_HAWAII &&
419 (info->indirect ||
420 (info->instance_count > 1 &&
421 u_prims_for_vertices(info->mode, info->count) < primgroup_size))) {
422 wd_switch_on_eop = true;
423 ia_switch_on_eop = true;
424 }
425
426 si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
427 ib->index_size == 4 ? 0xFC000000 : 0xFC00);
428
429 si_pm4_cmd_begin(pm4, PKT3_DRAW_PREAMBLE);
430 si_pm4_cmd_add(pm4, prim); /* VGT_PRIMITIVE_TYPE */
431 si_pm4_cmd_add(pm4, /* IA_MULTI_VGT_PARAM */
432 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
433 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
434 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
435 S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
436 si_pm4_cmd_add(pm4, 0); /* VGT_LS_HS_CONFIG */
437 si_pm4_cmd_end(pm4, false);
438 } else {
439 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
440 }
441
442 si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
443 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
444 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
445
446 if (prim == V_008958_DI_PT_LINELIST)
447 ls_mask = 1;
448 else if (prim == V_008958_DI_PT_LINESTRIP)
449 ls_mask = 2;
450 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
451 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
452 sctx->pa_sc_line_stipple);
453
454 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
455 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
456 S_028814_PROVOKING_VTX_LAST(1) | sctx->pa_su_sc_mode_cntl);
457 } else {
458 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, sctx->pa_su_sc_mode_cntl);
459 }
460 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
461 S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
462 S_02881C_USE_VTX_EDGE_FLAG(vs->vs_out_edgeflag) |
463 S_02881C_USE_VTX_RENDER_TARGET_INDX(vs->vs_out_layer) |
464 S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs->clip_dist_write & 0x0F) != 0) |
465 S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs->clip_dist_write & 0xF0) != 0) |
466 S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write) |
467 (sctx->queued.named.rasterizer->clip_plane_enable &
468 vs->clip_dist_write));
469 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL,
470 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
471 (vs->clip_dist_write ? 0 :
472 sctx->queued.named.rasterizer->clip_plane_enable & 0x3F));
473
474 si_pm4_set_state(sctx, draw_info, pm4);
475 return true;
476 }
477
478 static void si_update_spi_map(struct si_context *sctx)
479 {
480 struct si_shader *ps = &sctx->ps_shader->current->shader;
481 struct si_shader *vs = si_get_vs_state(sctx);
482 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
483 unsigned i, j, tmp;
484
485 for (i = 0; i < ps->ninput; i++) {
486 unsigned name = ps->input[i].name;
487 unsigned param_offset = ps->input[i].param_offset;
488
489 if (name == TGSI_SEMANTIC_POSITION)
490 /* Read from preloaded VGPRs, not parameters */
491 continue;
492
493 bcolor:
494 tmp = 0;
495
496 if (ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
497 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
498 sctx->ps_shader->current->key.ps.flatshade)) {
499 tmp |= S_028644_FLAT_SHADE(1);
500 }
501
502 if (name == TGSI_SEMANTIC_GENERIC &&
503 sctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
504 tmp |= S_028644_PT_SPRITE_TEX(1);
505 }
506
507 for (j = 0; j < vs->noutput; j++) {
508 if (name == vs->output[j].name &&
509 ps->input[i].sid == vs->output[j].sid) {
510 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
511 break;
512 }
513 }
514
515 if (j == vs->noutput) {
516 /* No corresponding output found, load defaults into input */
517 tmp |= S_028644_OFFSET(0x20);
518 }
519
520 si_pm4_set_reg(pm4,
521 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
522 tmp);
523
524 if (name == TGSI_SEMANTIC_COLOR &&
525 sctx->ps_shader->current->key.ps.color_two_side) {
526 name = TGSI_SEMANTIC_BCOLOR;
527 param_offset++;
528 goto bcolor;
529 }
530 }
531
532 si_pm4_set_state(sctx, spi, pm4);
533 }
534
535 /* Initialize state related to ESGS / GSVS ring buffers */
536 static void si_init_gs_rings(struct si_context *sctx)
537 {
538 unsigned size = 128 * 1024;
539
540 assert(!sctx->gs_rings);
541 sctx->gs_rings = si_pm4_alloc_state(sctx);
542
543 sctx->esgs_ring.buffer =
544 pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
545 PIPE_USAGE_DEFAULT, size);
546 sctx->esgs_ring.buffer_size = size;
547
548 size = 64 * 1024 * 1024;
549 sctx->gsvs_ring.buffer =
550 pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
551 PIPE_USAGE_DEFAULT, size);
552 sctx->gsvs_ring.buffer_size = size;
553
554 if (sctx->b.chip_class >= CIK) {
555 si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
556 sctx->esgs_ring.buffer_size / 256);
557 si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
558 sctx->gsvs_ring.buffer_size / 256);
559 } else {
560 si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
561 sctx->esgs_ring.buffer_size / 256);
562 si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
563 sctx->gsvs_ring.buffer_size / 256);
564 }
565
566 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
567 &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size,
568 true, true, 4, 64);
569 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
570 &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size,
571 false, false, 0, 0);
572 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
573 &sctx->gsvs_ring, 0, sctx->gsvs_ring.buffer_size,
574 false, false, 0, 0);
575 }
576
577 static void si_update_derived_state(struct si_context *sctx)
578 {
579 struct pipe_context * ctx = (struct pipe_context*)sctx;
580
581 if (!sctx->blitter->running) {
582 /* Flush depth textures which need to be flushed. */
583 for (int i = 0; i < SI_NUM_SHADERS; i++) {
584 if (sctx->samplers[i].depth_texture_mask) {
585 si_flush_depth_textures(sctx, &sctx->samplers[i]);
586 }
587 if (sctx->samplers[i].compressed_colortex_mask) {
588 si_decompress_color_textures(sctx, &sctx->samplers[i]);
589 }
590 }
591 }
592
593 if (sctx->gs_shader) {
594 si_shader_select(ctx, sctx->gs_shader);
595
596 if (!sctx->gs_shader->current->pm4) {
597 si_pipe_shader_gs(ctx, sctx->gs_shader->current);
598 si_pipe_shader_vs(ctx,
599 sctx->gs_shader->current->gs_copy_shader);
600 }
601
602 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
603 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
604
605 sctx->b.streamout.stride_in_dw = sctx->gs_shader->so.stride;
606
607 si_shader_select(ctx, sctx->vs_shader);
608
609 if (!sctx->vs_shader->current->pm4)
610 si_pipe_shader_es(ctx, sctx->vs_shader->current);
611
612 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
613
614 if (!sctx->gs_rings)
615 si_init_gs_rings(sctx);
616 if (sctx->emitted.named.gs_rings != sctx->gs_rings)
617 sctx->b.flags |= R600_CONTEXT_VGT_FLUSH;
618 si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
619
620 si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
621 &sctx->gsvs_ring,
622 sctx->gs_shader->current->shader.gs_max_out_vertices *
623 sctx->gs_shader->current->shader.noutput * 16,
624 64, true, true, 4, 16);
625
626 if (!sctx->gs_on) {
627 sctx->gs_on = si_pm4_alloc_state(sctx);
628
629 si_pm4_set_reg(sctx->gs_on, R_028B54_VGT_SHADER_STAGES_EN,
630 S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
631 S_028B54_GS_EN(1) |
632 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER));
633 }
634 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_on);
635 } else {
636 si_shader_select(ctx, sctx->vs_shader);
637
638 if (!sctx->vs_shader->current->pm4)
639 si_pipe_shader_vs(ctx, sctx->vs_shader->current);
640
641 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
642
643 sctx->b.streamout.stride_in_dw = sctx->vs_shader->so.stride;
644
645 if (!sctx->gs_off) {
646 sctx->gs_off = si_pm4_alloc_state(sctx);
647
648 si_pm4_set_reg(sctx->gs_off, R_028A40_VGT_GS_MODE, 0);
649 si_pm4_set_reg(sctx->gs_off, R_028B54_VGT_SHADER_STAGES_EN, 0);
650 }
651 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_off);
652 si_pm4_bind_state(sctx, gs_rings, NULL);
653 si_pm4_bind_state(sctx, gs, NULL);
654 si_pm4_bind_state(sctx, es, NULL);
655 }
656
657 si_shader_select(ctx, sctx->ps_shader);
658
659 if (!sctx->ps_shader->current->pm4 ||
660 sctx->ps_shader->current->cb0_is_integer != sctx->framebuffer.cb0_is_integer)
661 si_pipe_shader_ps(ctx, sctx->ps_shader->current);
662
663 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
664
665 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs)) {
666 /* XXX: Emitting the PS state even when only the VS changed
667 * fixes random failures with piglit glsl-max-varyings.
668 * Not sure why...
669 */
670 sctx->emitted.named.ps = NULL;
671 si_update_spi_map(sctx);
672 }
673 }
674
675 static void si_state_draw(struct si_context *sctx,
676 const struct pipe_draw_info *info,
677 const struct pipe_index_buffer *ib)
678 {
679 unsigned sh_base_reg = (sctx->gs_shader ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
680 R_00B130_SPI_SHADER_USER_DATA_VS_0);
681 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
682
683 if (pm4 == NULL)
684 return;
685
686 /* queries need some special values
687 * (this is non-zero if any query is active) */
688 if (sctx->b.num_occlusion_queries > 0) {
689 if (sctx->b.chip_class >= CIK) {
690 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
691 S_028004_PERFECT_ZPASS_COUNTS(1) |
692 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
693 S_028004_ZPASS_ENABLE(1) |
694 S_028004_SLICE_EVEN_ENABLE(1) |
695 S_028004_SLICE_ODD_ENABLE(1));
696 } else {
697 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
698 S_028004_PERFECT_ZPASS_COUNTS(1) |
699 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
700 }
701 }
702
703 if (info->count_from_stream_output) {
704 struct r600_so_target *t =
705 (struct r600_so_target*)info->count_from_stream_output;
706 uint64_t va = r600_resource_va(&sctx->screen->b.b,
707 &t->buf_filled_size->b.b);
708 va += t->buf_filled_size_offset;
709
710 si_pm4_set_reg(pm4, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
711 t->stride_in_dw);
712
713 si_pm4_cmd_begin(pm4, PKT3_COPY_DATA);
714 si_pm4_cmd_add(pm4,
715 COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
716 COPY_DATA_DST_SEL(COPY_DATA_REG) |
717 COPY_DATA_WR_CONFIRM);
718 si_pm4_cmd_add(pm4, va); /* src address lo */
719 si_pm4_cmd_add(pm4, va >> 32UL); /* src address hi */
720 si_pm4_cmd_add(pm4, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
721 si_pm4_cmd_add(pm4, 0); /* unused */
722 si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ,
723 RADEON_PRIO_MIN);
724 si_pm4_cmd_end(pm4, true);
725 }
726
727 /* draw packet */
728 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
729 if (ib->index_size == 4) {
730 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (SI_BIG_ENDIAN ?
731 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
732 } else {
733 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (SI_BIG_ENDIAN ?
734 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
735 }
736 si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
737
738 if (!info->indirect) {
739 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
740 si_pm4_cmd_add(pm4, info->instance_count);
741 si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
742
743 si_pm4_set_reg(pm4, sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
744 info->indexed ? info->index_bias : info->start);
745 si_pm4_set_reg(pm4, sh_base_reg + SI_SGPR_START_INSTANCE * 4,
746 info->start_instance);
747 } else {
748 si_pm4_add_bo(pm4, (struct r600_resource *)info->indirect,
749 RADEON_USAGE_READ, RADEON_PRIO_MIN);
750 }
751
752 if (info->indexed) {
753 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
754 sctx->index_buffer.index_size;
755 uint64_t va;
756 va = r600_resource_va(&sctx->screen->b.b, ib->buffer);
757 va += ib->offset;
758
759 si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ,
760 RADEON_PRIO_MIN);
761
762 if (info->indirect) {
763 uint64_t indirect_va = r600_resource_va(&sctx->screen->b.b,
764 info->indirect);
765 si_cmd_draw_index_indirect(pm4, indirect_va, va, max_size,
766 info->indirect_offset,
767 sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
768 sh_base_reg + SI_SGPR_START_INSTANCE * 4,
769 sctx->b.predicate_drawing);
770 } else {
771 va += info->start * ib->index_size;
772 si_cmd_draw_index_2(pm4, max_size, va, info->count,
773 V_0287F0_DI_SRC_SEL_DMA,
774 sctx->b.predicate_drawing);
775 }
776 } else {
777 if (info->indirect) {
778 uint64_t indirect_va = r600_resource_va(&sctx->screen->b.b,
779 info->indirect);
780 si_cmd_draw_indirect(pm4, indirect_va, info->indirect_offset,
781 sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
782 sh_base_reg + SI_SGPR_START_INSTANCE * 4,
783 sctx->b.predicate_drawing);
784 } else {
785 si_cmd_draw_index_auto(pm4, info->count,
786 V_0287F0_DI_SRC_SEL_AUTO_INDEX |
787 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output),
788 sctx->b.predicate_drawing);
789 }
790 }
791
792 si_pm4_set_state(sctx, draw, pm4);
793 }
794
795 void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom)
796 {
797 struct radeon_winsys_cs *cs = sctx->rings.gfx.cs;
798 uint32_t cp_coher_cntl = 0;
799
800 /* XXX SI flushes both ICACHE and KCACHE if either flag is set.
801 * XXX CIK shouldn't have this issue. Test CIK before separating the flags
802 * XXX to ensure there is no regression. Also find out if there is another
803 * XXX way to flush either ICACHE or KCACHE but not both for SI. */
804 if (sctx->flags & (R600_CONTEXT_INV_SHADER_CACHE |
805 R600_CONTEXT_INV_CONST_CACHE)) {
806 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1) |
807 S_0085F0_SH_KCACHE_ACTION_ENA(1);
808 }
809 if (sctx->flags & (R600_CONTEXT_INV_TEX_CACHE |
810 R600_CONTEXT_STREAMOUT_FLUSH)) {
811 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1) |
812 S_0085F0_TCL1_ACTION_ENA(1);
813 }
814 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB) {
815 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
816 S_0085F0_CB0_DEST_BASE_ENA(1) |
817 S_0085F0_CB1_DEST_BASE_ENA(1) |
818 S_0085F0_CB2_DEST_BASE_ENA(1) |
819 S_0085F0_CB3_DEST_BASE_ENA(1) |
820 S_0085F0_CB4_DEST_BASE_ENA(1) |
821 S_0085F0_CB5_DEST_BASE_ENA(1) |
822 S_0085F0_CB6_DEST_BASE_ENA(1) |
823 S_0085F0_CB7_DEST_BASE_ENA(1);
824 }
825 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB) {
826 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
827 S_0085F0_DB_DEST_BASE_ENA(1);
828 }
829
830 if (cp_coher_cntl) {
831 if (sctx->chip_class >= CIK) {
832 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
833 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
834 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
835 radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */
836 radeon_emit(cs, 0); /* CP_COHER_BASE */
837 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
838 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
839 } else {
840 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
841 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
842 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
843 radeon_emit(cs, 0); /* CP_COHER_BASE */
844 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
845 }
846 }
847
848 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META) {
849 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
850 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
851 }
852 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB_META) {
853 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
854 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
855 }
856
857 if (sctx->flags & (R600_CONTEXT_WAIT_3D_IDLE |
858 R600_CONTEXT_PS_PARTIAL_FLUSH)) {
859 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
860 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
861 } else if (sctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
862 /* Needed if streamout buffers are going to be used as a source. */
863 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
864 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
865 }
866
867 if (sctx->flags & R600_CONTEXT_VGT_FLUSH) {
868 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
869 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
870 }
871
872 sctx->flags = 0;
873 }
874
875 const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 13 }; /* number of CS dwords */
876
877 static void si_get_draw_start_count(struct si_context *sctx,
878 const struct pipe_draw_info *info,
879 unsigned *start, unsigned *count)
880 {
881 if (info->indirect) {
882 struct r600_resource *indirect =
883 (struct r600_resource*)info->indirect;
884 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
885 indirect, PIPE_TRANSFER_READ);
886 data += info->indirect_offset/sizeof(int);
887 *start = data[2];
888 *count = data[0];
889 } else {
890 *start = info->start;
891 *count = info->count;
892 }
893 }
894
895 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
896 {
897 struct si_context *sctx = (struct si_context *)ctx;
898 struct pipe_index_buffer ib = {};
899 uint32_t i;
900
901 if (!info->count && !info->indirect &&
902 (info->indexed || !info->count_from_stream_output))
903 return;
904
905 if (!sctx->ps_shader || !sctx->vs_shader)
906 return;
907
908 si_update_derived_state(sctx);
909
910 if (sctx->vertex_buffers_dirty) {
911 si_update_vertex_buffers(sctx);
912 sctx->vertex_buffers_dirty = false;
913 }
914
915 if (info->indexed) {
916 /* Initialize the index buffer struct. */
917 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
918 ib.user_buffer = sctx->index_buffer.user_buffer;
919 ib.index_size = sctx->index_buffer.index_size;
920 ib.offset = sctx->index_buffer.offset;
921
922 /* Translate or upload, if needed. */
923 if (ib.index_size == 1) {
924 struct pipe_resource *out_buffer = NULL;
925 unsigned out_offset, start, count, start_offset;
926 void *ptr;
927
928 si_get_draw_start_count(sctx, info, &start, &count);
929 start_offset = start * ib.index_size;
930
931 u_upload_alloc(sctx->b.uploader, start_offset, count * 2,
932 &out_offset, &out_buffer, &ptr);
933
934 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
935 ib.offset + start_offset,
936 count, ptr);
937
938 pipe_resource_reference(&ib.buffer, NULL);
939 ib.user_buffer = NULL;
940 ib.buffer = out_buffer;
941 /* info->start will be added by the drawing code */
942 ib.offset = out_offset - start_offset;
943 ib.index_size = 2;
944 } else if (ib.user_buffer && !ib.buffer) {
945 unsigned start, count, start_offset;
946
947 si_get_draw_start_count(sctx, info, &start, &count);
948 start_offset = start * ib.index_size;
949
950 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
951 (char*)ib.user_buffer + start_offset,
952 &ib.offset, &ib.buffer);
953 /* info->start will be added by the drawing code */
954 ib.offset -= start_offset;
955 }
956 }
957
958 if (!si_update_draw_info_state(sctx, info, &ib))
959 return;
960
961 si_state_draw(sctx, info, &ib);
962
963 sctx->pm4_dirty_cdwords += si_pm4_dirty_dw(sctx);
964
965 /* Check flush flags. */
966 if (sctx->b.flags)
967 sctx->atoms.s.cache_flush->dirty = true;
968
969 si_need_cs_space(sctx, 0, TRUE);
970
971 /* Emit states. */
972 for (i = 0; i < SI_NUM_ATOMS(sctx); i++) {
973 if (sctx->atoms.array[i]->dirty) {
974 sctx->atoms.array[i]->emit(&sctx->b, sctx->atoms.array[i]);
975 sctx->atoms.array[i]->dirty = false;
976 }
977 }
978
979 si_pm4_emit_dirty(sctx);
980 sctx->pm4_dirty_cdwords = 0;
981
982 #if SI_TRACE_CS
983 if (sctx->screen->b.trace_bo) {
984 si_trace_emit(sctx);
985 }
986 #endif
987
988 /* Set the depth buffer as dirty. */
989 if (sctx->framebuffer.state.zsbuf) {
990 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
991 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
992
993 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
994 }
995 if (sctx->framebuffer.compressed_cb_mask) {
996 struct pipe_surface *surf;
997 struct r600_texture *rtex;
998 unsigned mask = sctx->framebuffer.compressed_cb_mask;
999
1000 do {
1001 unsigned i = u_bit_scan(&mask);
1002 surf = sctx->framebuffer.state.cbufs[i];
1003 rtex = (struct r600_texture*)surf->texture;
1004
1005 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1006 } while (mask);
1007 }
1008
1009 pipe_resource_reference(&ib.buffer, NULL);
1010 sctx->b.num_draw_calls++;
1011 }