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radeonsi: move VGT_LS_HS_CONFIG to derived tess_state
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "radeon/r600_cs.h"
30 #include "sid.h"
31
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
35 #include "util/u_memory.h"
36
37 static unsigned si_conv_pipe_prim(unsigned mode)
38 {
39 static const unsigned prim_conv[] = {
40 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
41 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
42 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
43 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
44 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
45 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
46 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
47 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
48 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
49 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
50 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
51 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
52 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
53 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
54 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
55 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
56 };
57 assert(mode < ARRAY_SIZE(prim_conv));
58 return prim_conv[mode];
59 }
60
61 static unsigned si_conv_prim_to_gs_out(unsigned mode)
62 {
63 static const int prim_conv[] = {
64 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
65 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
66 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
67 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
68 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
69 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
73 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
74 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
75 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
76 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
77 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
78 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
79 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
80 };
81 assert(mode < ARRAY_SIZE(prim_conv));
82
83 return prim_conv[mode];
84 }
85
86 /**
87 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
88 * LS.LDS_SIZE is shared by all 3 shader stages.
89 *
90 * The information about LDS and other non-compile-time parameters is then
91 * written to userdata SGPRs.
92 */
93 static void si_emit_derived_tess_state(struct si_context *sctx,
94 const struct pipe_draw_info *info,
95 unsigned *num_patches)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_shader_ctx_state *ls = &sctx->vs_shader;
99 /* The TES pointer will only be used for sctx->last_tcs.
100 * It would be wrong to think that TCS = TES. */
101 struct si_shader_selector *tcs =
102 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
103 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
104 unsigned num_tcs_input_cp = info->vertices_per_patch;
105 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
106 unsigned num_tcs_patch_outputs;
107 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
108 unsigned input_patch_size, output_patch_size, output_patch0_offset;
109 unsigned perpatch_output_offset, lds_size, ls_rsrc2;
110 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
111 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
112
113 /* This calculates how shader inputs and outputs among VS, TCS, and TES
114 * are laid out in LDS. */
115 num_tcs_inputs = util_last_bit64(ls->cso->outputs_written);
116
117 if (sctx->tcs_shader.cso) {
118 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
119 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
120 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
121 } else {
122 /* No TCS. Route varyings from LS to TES. */
123 num_tcs_outputs = num_tcs_inputs;
124 num_tcs_output_cp = num_tcs_input_cp;
125 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
126 }
127
128 input_vertex_size = num_tcs_inputs * 16;
129 output_vertex_size = num_tcs_outputs * 16;
130
131 input_patch_size = num_tcs_input_cp * input_vertex_size;
132
133 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
134 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
135
136 /* Ensure that we only need one wave per SIMD so we don't need to check
137 * resource usage. Also ensures that the number of tcs in and out
138 * vertices per threadgroup are at most 256.
139 */
140 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
141
142 /* Make sure that the data fits in LDS. This assumes the shaders only
143 * use LDS for the inputs and outputs.
144 */
145 hardware_lds_size = sctx->b.chip_class >= CIK ? 65536 : 32768;
146 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
147 output_patch_size));
148
149 /* Make sure the output data fits in the offchip buffer */
150 *num_patches = MIN2(*num_patches,
151 (sctx->screen->tess_offchip_block_dw_size * 4) /
152 output_patch_size);
153
154 /* Not necessary for correctness, but improves performance. The
155 * specific value is taken from the proprietary driver.
156 */
157 *num_patches = MIN2(*num_patches, 40);
158
159 output_patch0_offset = input_patch_size * *num_patches;
160 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
161
162 lds_size = output_patch0_offset + output_patch_size * *num_patches;
163 ls_rsrc2 = ls->current->config.rsrc2;
164
165 if (sctx->b.chip_class >= CIK) {
166 assert(lds_size <= 65536);
167 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 512) / 512);
168 } else {
169 assert(lds_size <= 32768);
170 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 256) / 256);
171 }
172
173 if (sctx->last_ls == ls->current &&
174 sctx->last_tcs == tcs &&
175 sctx->last_tes_sh_base == tes_sh_base &&
176 sctx->last_num_tcs_input_cp == num_tcs_input_cp)
177 return;
178
179 sctx->last_ls = ls->current;
180 sctx->last_tcs = tcs;
181 sctx->last_tes_sh_base = tes_sh_base;
182 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
183
184 /* Due to a hw bug, RSRC2_LS must be written twice with another
185 * LS register written in between. */
186 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
187 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
188 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
189 radeon_emit(cs, ls->current->config.rsrc1);
190 radeon_emit(cs, ls_rsrc2);
191
192 /* Compute userdata SGPRs. */
193 assert(((input_vertex_size / 4) & ~0xff) == 0);
194 assert(((output_vertex_size / 4) & ~0xff) == 0);
195 assert(((input_patch_size / 4) & ~0x1fff) == 0);
196 assert(((output_patch_size / 4) & ~0x1fff) == 0);
197 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
198 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
199 assert(num_tcs_input_cp <= 32);
200 assert(num_tcs_output_cp <= 32);
201
202 tcs_in_layout = (input_patch_size / 4) |
203 ((input_vertex_size / 4) << 13);
204 tcs_out_layout = (output_patch_size / 4) |
205 ((output_vertex_size / 4) << 13);
206 tcs_out_offsets = (output_patch0_offset / 16) |
207 ((perpatch_output_offset / 16) << 16);
208 offchip_layout = (pervertex_output_patch_size * *num_patches << 16) |
209 (num_tcs_output_cp << 9) | *num_patches;
210
211 /* Set them for LS. */
212 radeon_set_sh_reg(cs,
213 R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4,
214 tcs_in_layout);
215
216 /* Set them for TCS. */
217 radeon_set_sh_reg_seq(cs,
218 R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
219 radeon_emit(cs, offchip_layout);
220 radeon_emit(cs, tcs_out_offsets);
221 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
222 radeon_emit(cs, tcs_in_layout);
223
224 /* Set them for TES. */
225 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 1);
226 radeon_emit(cs, offchip_layout);
227
228 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
229 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
230 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
231
232 if (sctx->b.chip_class >= CIK)
233 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
234 ls_hs_config);
235 else
236 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
237 ls_hs_config);
238 }
239
240 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
241 {
242 switch (info->mode) {
243 case PIPE_PRIM_PATCHES:
244 return info->count / info->vertices_per_patch;
245 case R600_PRIM_RECTANGLE_LIST:
246 return info->count / 3;
247 default:
248 return u_prims_for_vertices(info->mode, info->count);
249 }
250 }
251
252 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
253 const struct pipe_draw_info *info,
254 unsigned num_patches)
255 {
256 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
257 unsigned prim = info->mode;
258 unsigned primgroup_size = 128; /* recommended without a GS */
259 unsigned max_primgroup_in_wave = 2;
260
261 /* SWITCH_ON_EOP(0) is always preferable. */
262 bool wd_switch_on_eop = false;
263 bool ia_switch_on_eop = false;
264 bool ia_switch_on_eoi = false;
265 bool partial_vs_wave = false;
266 bool partial_es_wave = false;
267
268 if (sctx->gs_shader.cso)
269 primgroup_size = 64; /* recommended with a GS */
270
271 if (sctx->tes_shader.cso) {
272 /* primgroup_size must be set to a multiple of NUM_PATCHES */
273 primgroup_size = num_patches;
274
275 /* SWITCH_ON_EOI must be set if PrimID is used. */
276 if ((sctx->tcs_shader.cso && sctx->tcs_shader.cso->info.uses_primid) ||
277 sctx->tes_shader.cso->info.uses_primid)
278 ia_switch_on_eoi = true;
279
280 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
281 if ((sctx->b.family == CHIP_TAHITI ||
282 sctx->b.family == CHIP_PITCAIRN ||
283 sctx->b.family == CHIP_BONAIRE) &&
284 sctx->gs_shader.cso)
285 partial_vs_wave = true;
286
287 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
288 if (sctx->screen->has_distributed_tess) {
289 if (sctx->gs_shader.cso)
290 partial_es_wave = true;
291 else
292 partial_vs_wave = true;
293 }
294 }
295
296 /* This is a hardware requirement. */
297 if ((rs && rs->line_stipple_enable) ||
298 (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
299 ia_switch_on_eop = true;
300 wd_switch_on_eop = true;
301 }
302
303 if (sctx->b.chip_class >= CIK) {
304 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
305 * 4 shader engines. Set 1 to pass the assertion below.
306 * The other cases are hardware requirements.
307 *
308 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
309 * for points, line strips, and tri strips.
310 */
311 if (sctx->b.screen->info.max_se < 4 ||
312 prim == PIPE_PRIM_POLYGON ||
313 prim == PIPE_PRIM_LINE_LOOP ||
314 prim == PIPE_PRIM_TRIANGLE_FAN ||
315 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
316 (info->primitive_restart &&
317 (sctx->b.family < CHIP_POLARIS10 ||
318 (prim != PIPE_PRIM_POINTS &&
319 prim != PIPE_PRIM_LINE_STRIP &&
320 prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
321 info->count_from_stream_output)
322 wd_switch_on_eop = true;
323
324 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
325 * We don't know that for indirect drawing, so treat it as
326 * always problematic. */
327 if (sctx->b.family == CHIP_HAWAII &&
328 (info->indirect || info->instance_count > 1))
329 wd_switch_on_eop = true;
330
331 /* Performance recommendation for 4 SE Gfx7-8 parts if
332 * instances are smaller than a primgroup.
333 * Assume indirect draws always use small instances.
334 * This is needed for good VS wave utilization.
335 */
336 if (sctx->b.chip_class <= VI &&
337 sctx->b.screen->info.max_se >= 4 &&
338 (info->indirect ||
339 (info->instance_count > 1 &&
340 si_num_prims_for_vertices(info) < primgroup_size)))
341 wd_switch_on_eop = true;
342
343 /* Required on CIK and later. */
344 if (sctx->b.screen->info.max_se > 2 && !wd_switch_on_eop)
345 ia_switch_on_eoi = true;
346
347 /* Required by Hawaii and, for some special cases, by VI. */
348 if (ia_switch_on_eoi &&
349 (sctx->b.family == CHIP_HAWAII ||
350 (sctx->b.chip_class == VI &&
351 (sctx->gs_shader.cso || max_primgroup_in_wave != 2))))
352 partial_vs_wave = true;
353
354 /* Instancing bug on Bonaire. */
355 if (sctx->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
356 (info->indirect || info->instance_count > 1))
357 partial_vs_wave = true;
358
359 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
360 * The hw doc says all multi-SE chips are affected, but Vulkan
361 * only applies it to Hawaii. Do what Vulkan does.
362 */
363 if (sctx->b.family == CHIP_HAWAII &&
364 sctx->gs_shader.cso &&
365 ia_switch_on_eoi &&
366 (info->indirect ||
367 (info->instance_count > 1 &&
368 si_num_prims_for_vertices(info) <= 1)))
369 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
370
371
372 /* If the WD switch is false, the IA switch must be false too. */
373 assert(wd_switch_on_eop || !ia_switch_on_eop);
374 }
375
376 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
377 if (ia_switch_on_eoi)
378 partial_es_wave = true;
379
380 /* GS requirement. */
381 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
382 partial_es_wave = true;
383
384 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
385 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
386 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
387 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
388 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
389 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
390 S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx->b.chip_class >= VI ?
391 max_primgroup_in_wave : 0);
392 }
393
394 static void si_emit_scratch_reloc(struct si_context *sctx)
395 {
396 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
397
398 if (!sctx->emit_scratch_reloc)
399 return;
400
401 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
402 sctx->spi_tmpring_size);
403
404 if (sctx->scratch_buffer) {
405 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
406 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
407 RADEON_PRIO_SCRATCH_BUFFER);
408
409 }
410 sctx->emit_scratch_reloc = false;
411 }
412
413 /* rast_prim is the primitive type after GS. */
414 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
415 {
416 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
417 unsigned rast_prim = sctx->current_rast_prim;
418 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
419
420 /* Skip this if not rendering lines. */
421 if (rast_prim != PIPE_PRIM_LINES &&
422 rast_prim != PIPE_PRIM_LINE_LOOP &&
423 rast_prim != PIPE_PRIM_LINE_STRIP &&
424 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
425 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
426 return;
427
428 if (rast_prim == sctx->last_rast_prim &&
429 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
430 return;
431
432 /* For lines, reset the stipple pattern at each primitive. Otherwise,
433 * reset the stipple pattern at each packet (line strips, line loops).
434 */
435 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
436 rs->pa_sc_line_stipple |
437 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
438
439 sctx->last_rast_prim = rast_prim;
440 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
441 }
442
443 static void si_emit_draw_registers(struct si_context *sctx,
444 const struct pipe_draw_info *info)
445 {
446 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
447 unsigned prim = si_conv_pipe_prim(info->mode);
448 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
449 unsigned ia_multi_vgt_param, num_patches = 0;
450
451 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
452 * whether the "fractional odd" tessellation spacing is used.
453 */
454 if (sctx->b.family >= CHIP_POLARIS10) {
455 struct si_shader_selector *tes = sctx->tes_shader.cso;
456 unsigned vtx_reuse_depth = 30;
457
458 if (tes &&
459 tes->info.properties[TGSI_PROPERTY_TES_SPACING] ==
460 PIPE_TESS_SPACING_FRACTIONAL_ODD)
461 vtx_reuse_depth = 14;
462
463 if (vtx_reuse_depth != sctx->last_vtx_reuse_depth) {
464 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
465 vtx_reuse_depth);
466 sctx->last_vtx_reuse_depth = vtx_reuse_depth;
467 }
468 }
469
470 if (sctx->tes_shader.cso)
471 si_emit_derived_tess_state(sctx, info, &num_patches);
472
473 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
474
475 /* Draw state. */
476 if (prim != sctx->last_prim ||
477 ia_multi_vgt_param != sctx->last_multi_vgt_param) {
478 if (sctx->b.chip_class >= CIK) {
479 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
480 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
481 } else {
482 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
483 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
484 }
485
486 sctx->last_prim = prim;
487 sctx->last_multi_vgt_param = ia_multi_vgt_param;
488 }
489
490 if (gs_out_prim != sctx->last_gs_out_prim) {
491 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
492 sctx->last_gs_out_prim = gs_out_prim;
493 }
494
495 /* Primitive restart. */
496 if (info->primitive_restart != sctx->last_primitive_restart_en) {
497 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
498 sctx->last_primitive_restart_en = info->primitive_restart;
499
500 }
501 if (info->primitive_restart &&
502 (info->restart_index != sctx->last_restart_index ||
503 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
504 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
505 info->restart_index);
506 sctx->last_restart_index = info->restart_index;
507 }
508 }
509
510 static void si_emit_draw_packets(struct si_context *sctx,
511 const struct pipe_draw_info *info,
512 const struct pipe_index_buffer *ib)
513 {
514 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
515 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
516 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
517 uint32_t index_max_size = 0;
518 uint64_t index_va = 0;
519
520 if (info->count_from_stream_output) {
521 struct r600_so_target *t =
522 (struct r600_so_target*)info->count_from_stream_output;
523 uint64_t va = t->buf_filled_size->gpu_address +
524 t->buf_filled_size_offset;
525
526 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
527 t->stride_in_dw);
528
529 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
530 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
531 COPY_DATA_DST_SEL(COPY_DATA_REG) |
532 COPY_DATA_WR_CONFIRM);
533 radeon_emit(cs, va); /* src address lo */
534 radeon_emit(cs, va >> 32); /* src address hi */
535 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
536 radeon_emit(cs, 0); /* unused */
537
538 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
539 t->buf_filled_size, RADEON_USAGE_READ,
540 RADEON_PRIO_SO_FILLED_SIZE);
541 }
542
543 /* draw packet */
544 if (info->indexed) {
545 if (ib->index_size != sctx->last_index_size) {
546 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
547
548 /* index type */
549 switch (ib->index_size) {
550 case 1:
551 radeon_emit(cs, V_028A7C_VGT_INDEX_8);
552 break;
553 case 2:
554 radeon_emit(cs, V_028A7C_VGT_INDEX_16 |
555 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
556 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
557 break;
558 case 4:
559 radeon_emit(cs, V_028A7C_VGT_INDEX_32 |
560 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
561 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
562 break;
563 default:
564 assert(!"unreachable");
565 return;
566 }
567
568 sctx->last_index_size = ib->index_size;
569 }
570
571 index_max_size = (ib->buffer->width0 - ib->offset) /
572 ib->index_size;
573 index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
574
575 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
576 (struct r600_resource *)ib->buffer,
577 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
578 } else {
579 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
580 * so the state must be re-emitted before the next indexed draw.
581 */
582 if (sctx->b.chip_class >= CIK)
583 sctx->last_index_size = -1;
584 }
585
586 if (!info->indirect) {
587 int base_vertex;
588
589 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
590 radeon_emit(cs, info->instance_count);
591
592 /* Base vertex and start instance. */
593 base_vertex = info->indexed ? info->index_bias : info->start;
594
595 if (base_vertex != sctx->last_base_vertex ||
596 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
597 info->start_instance != sctx->last_start_instance ||
598 info->drawid != sctx->last_drawid ||
599 sh_base_reg != sctx->last_sh_base_reg) {
600 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
601 radeon_emit(cs, base_vertex);
602 radeon_emit(cs, info->start_instance);
603 radeon_emit(cs, info->drawid);
604
605 sctx->last_base_vertex = base_vertex;
606 sctx->last_start_instance = info->start_instance;
607 sctx->last_drawid = info->drawid;
608 sctx->last_sh_base_reg = sh_base_reg;
609 }
610 } else {
611 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
612
613 assert(indirect_va % 8 == 0);
614
615 si_invalidate_draw_sh_constants(sctx);
616
617 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
618 radeon_emit(cs, 1);
619 radeon_emit(cs, indirect_va);
620 radeon_emit(cs, indirect_va >> 32);
621
622 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
623 (struct r600_resource *)info->indirect,
624 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
625 }
626
627 if (info->indirect) {
628 unsigned di_src_sel = info->indexed ? V_0287F0_DI_SRC_SEL_DMA
629 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
630
631 assert(info->indirect_offset % 4 == 0);
632
633 if (info->indexed) {
634 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
635 radeon_emit(cs, index_va);
636 radeon_emit(cs, index_va >> 32);
637
638 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
639 radeon_emit(cs, index_max_size);
640 }
641
642 if (!sctx->screen->has_draw_indirect_multi) {
643 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT
644 : PKT3_DRAW_INDIRECT,
645 3, render_cond_bit));
646 radeon_emit(cs, info->indirect_offset);
647 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
648 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
649 radeon_emit(cs, di_src_sel);
650 } else {
651 uint64_t count_va = 0;
652
653 if (info->indirect_params) {
654 struct r600_resource *params_buf =
655 (struct r600_resource *)info->indirect_params;
656
657 radeon_add_to_buffer_list(
658 &sctx->b, &sctx->b.gfx, params_buf,
659 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
660
661 count_va = params_buf->gpu_address + info->indirect_params_offset;
662 }
663
664 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
665 PKT3_DRAW_INDIRECT_MULTI,
666 8, render_cond_bit));
667 radeon_emit(cs, info->indirect_offset);
668 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
669 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
670 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
671 S_2C3_DRAW_INDEX_ENABLE(1) |
672 S_2C3_COUNT_INDIRECT_ENABLE(!!info->indirect_params));
673 radeon_emit(cs, info->indirect_count);
674 radeon_emit(cs, count_va);
675 radeon_emit(cs, count_va >> 32);
676 radeon_emit(cs, info->indirect_stride);
677 radeon_emit(cs, di_src_sel);
678 }
679 } else {
680 if (info->indexed) {
681 index_va += info->start * ib->index_size;
682
683 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
684 radeon_emit(cs, index_max_size);
685 radeon_emit(cs, index_va);
686 radeon_emit(cs, (index_va >> 32UL) & 0xFF);
687 radeon_emit(cs, info->count);
688 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
689 } else {
690 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
691 radeon_emit(cs, info->count);
692 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
693 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
694 }
695 }
696 }
697
698 void si_emit_cache_flush(struct si_context *sctx)
699 {
700 struct r600_common_context *rctx = &sctx->b;
701 struct radeon_winsys_cs *cs = rctx->gfx.cs;
702 uint32_t cp_coher_cntl = 0;
703
704 /* SI has a bug that it always flushes ICACHE and KCACHE if either
705 * bit is set. An alternative way is to write SQC_CACHES, but that
706 * doesn't seem to work reliably. Since the bug doesn't affect
707 * correctness (it only does more work than necessary) and
708 * the performance impact is likely negligible, there is no plan
709 * to add a workaround for it.
710 */
711
712 if (rctx->flags & SI_CONTEXT_INV_ICACHE)
713 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
714 if (rctx->flags & SI_CONTEXT_INV_SMEM_L1)
715 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
716
717 if (rctx->flags & SI_CONTEXT_INV_VMEM_L1)
718 cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
719 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
720 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
721
722 if (rctx->chip_class >= VI)
723 cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1);
724 }
725
726 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
727 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
728 S_0085F0_CB0_DEST_BASE_ENA(1) |
729 S_0085F0_CB1_DEST_BASE_ENA(1) |
730 S_0085F0_CB2_DEST_BASE_ENA(1) |
731 S_0085F0_CB3_DEST_BASE_ENA(1) |
732 S_0085F0_CB4_DEST_BASE_ENA(1) |
733 S_0085F0_CB5_DEST_BASE_ENA(1) |
734 S_0085F0_CB6_DEST_BASE_ENA(1) |
735 S_0085F0_CB7_DEST_BASE_ENA(1);
736
737 /* Necessary for DCC */
738 if (rctx->chip_class >= VI) {
739 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
740 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) |
741 EVENT_INDEX(5));
742 radeon_emit(cs, 0);
743 radeon_emit(cs, 0);
744 radeon_emit(cs, 0);
745 radeon_emit(cs, 0);
746 }
747 }
748 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
749 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
750 S_0085F0_DB_DEST_BASE_ENA(1);
751 }
752
753 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) {
754 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
755 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
756 /* needed for wait for idle in SURFACE_SYNC */
757 assert(rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB);
758 }
759 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) {
760 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
761 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
762 /* needed for wait for idle in SURFACE_SYNC */
763 assert(rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB);
764 }
765
766 /* Wait for shader engines to go idle.
767 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
768 * for everything including CB/DB cache flushes.
769 */
770 if (!(rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
771 SI_CONTEXT_FLUSH_AND_INV_DB))) {
772 if (rctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
773 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
774 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
775 /* Only count explicit shader flushes, not implicit ones
776 * done by SURFACE_SYNC.
777 */
778 rctx->num_vs_flushes++;
779 rctx->num_ps_flushes++;
780 } else if (rctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
781 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
782 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
783 rctx->num_vs_flushes++;
784 }
785 }
786
787 if (rctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
788 sctx->compute_is_busy) {
789 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
790 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
791 rctx->num_cs_flushes++;
792 sctx->compute_is_busy = false;
793 }
794
795 /* VGT state synchronization. */
796 if (rctx->flags & SI_CONTEXT_VGT_FLUSH) {
797 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
798 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
799 }
800 if (rctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
801 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
802 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
803 }
804
805 /* Make sure ME is idle (it executes most packets) before continuing.
806 * This prevents read-after-write hazards between PFP and ME.
807 */
808 if (cp_coher_cntl || (rctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH)) {
809 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
810 radeon_emit(cs, 0);
811 }
812
813 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
814 * Therefore, it should be last. Done in PFP.
815 */
816 if (cp_coher_cntl) {
817 /* ACQUIRE_MEM is only required on a compute ring. */
818 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
819 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
820 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
821 radeon_emit(cs, 0); /* CP_COHER_BASE */
822 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
823 }
824
825 if (rctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
826 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
827 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
828 EVENT_INDEX(0));
829 } else if (rctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
830 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
831 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
832 EVENT_INDEX(0));
833 }
834
835 rctx->flags = 0;
836 }
837
838 static void si_get_draw_start_count(struct si_context *sctx,
839 const struct pipe_draw_info *info,
840 unsigned *start, unsigned *count)
841 {
842 if (info->indirect) {
843 struct r600_resource *indirect =
844 (struct r600_resource*)info->indirect;
845 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
846 indirect, PIPE_TRANSFER_READ);
847 data += info->indirect_offset/sizeof(int);
848 *start = data[2];
849 *count = data[0];
850 } else {
851 *start = info->start;
852 *count = info->count;
853 }
854 }
855
856 void si_ce_pre_draw_synchronization(struct si_context *sctx)
857 {
858 if (sctx->ce_need_synchronization) {
859 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
860 radeon_emit(sctx->ce_ib, 1);
861
862 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
863 radeon_emit(sctx->b.gfx.cs, 1);
864 }
865 }
866
867 void si_ce_post_draw_synchronization(struct si_context *sctx)
868 {
869 if (sctx->ce_need_synchronization) {
870 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
871 radeon_emit(sctx->b.gfx.cs, 0);
872
873 sctx->ce_need_synchronization = false;
874 }
875 }
876
877 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
878 {
879 struct si_context *sctx = (struct si_context *)ctx;
880 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
881 struct pipe_index_buffer ib = {};
882 unsigned mask, dirty_fb_counter, dirty_tex_counter, rast_prim;
883
884 if (likely(!info->indirect)) {
885 /* SI-CI treat instance_count==0 as instance_count==1. There is
886 * no workaround for indirect draws, but we can at least skip
887 * direct draws.
888 */
889 if (unlikely(!info->instance_count))
890 return;
891
892 /* Handle count == 0. */
893 if (unlikely(!info->count &&
894 (info->indexed || !info->count_from_stream_output)))
895 return;
896 }
897
898 if (unlikely(!sctx->vs_shader.cso)) {
899 assert(0);
900 return;
901 }
902 if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
903 assert(0);
904 return;
905 }
906 if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
907 assert(0);
908 return;
909 }
910
911 /* Re-emit the framebuffer state if needed. */
912 dirty_fb_counter = p_atomic_read(&sctx->b.screen->dirty_fb_counter);
913 if (unlikely(dirty_fb_counter != sctx->b.last_dirty_fb_counter)) {
914 sctx->b.last_dirty_fb_counter = dirty_fb_counter;
915 sctx->framebuffer.dirty_cbufs |=
916 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
917 sctx->framebuffer.dirty_zsbuf = true;
918 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
919 }
920
921 /* Invalidate & recompute texture descriptors if needed. */
922 dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_descriptor_counter);
923 if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_descriptor_counter)) {
924 sctx->b.last_dirty_tex_descriptor_counter = dirty_tex_counter;
925 si_update_all_texture_descriptors(sctx);
926 }
927
928 si_decompress_graphics_textures(sctx);
929
930 /* Set the rasterization primitive type.
931 *
932 * This must be done after si_decompress_textures, which can call
933 * draw_vbo recursively, and before si_update_shaders, which uses
934 * current_rast_prim for this draw_vbo call. */
935 if (sctx->gs_shader.cso)
936 rast_prim = sctx->gs_shader.cso->gs_output_prim;
937 else if (sctx->tes_shader.cso)
938 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
939 else
940 rast_prim = info->mode;
941
942 if (rast_prim != sctx->current_rast_prim) {
943 sctx->current_rast_prim = rast_prim;
944 sctx->do_update_shaders = true;
945 }
946
947 if (sctx->do_update_shaders && !si_update_shaders(sctx))
948 return;
949
950 if (!si_upload_graphics_shader_descriptors(sctx))
951 return;
952
953 if (info->indexed) {
954 /* Initialize the index buffer struct. */
955 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
956 ib.user_buffer = sctx->index_buffer.user_buffer;
957 ib.index_size = sctx->index_buffer.index_size;
958 ib.offset = sctx->index_buffer.offset;
959
960 /* Translate or upload, if needed. */
961 /* 8-bit indices are supported on VI. */
962 if (sctx->b.chip_class <= CIK && ib.index_size == 1) {
963 struct pipe_resource *out_buffer = NULL;
964 unsigned out_offset, start, count, start_offset;
965 void *ptr;
966
967 si_get_draw_start_count(sctx, info, &start, &count);
968 start_offset = start * ib.index_size;
969
970 u_upload_alloc(sctx->b.uploader, start_offset, count * 2, 256,
971 &out_offset, &out_buffer, &ptr);
972 if (!out_buffer) {
973 pipe_resource_reference(&ib.buffer, NULL);
974 return;
975 }
976
977 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
978 ib.offset + start_offset,
979 count, ptr);
980
981 pipe_resource_reference(&ib.buffer, NULL);
982 ib.user_buffer = NULL;
983 ib.buffer = out_buffer;
984 /* info->start will be added by the drawing code */
985 ib.offset = out_offset - start_offset;
986 ib.index_size = 2;
987 } else if (ib.user_buffer && !ib.buffer) {
988 unsigned start, count, start_offset;
989
990 si_get_draw_start_count(sctx, info, &start, &count);
991 start_offset = start * ib.index_size;
992
993 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
994 256, (char*)ib.user_buffer + start_offset,
995 &ib.offset, &ib.buffer);
996 if (!ib.buffer)
997 return;
998 /* info->start will be added by the drawing code */
999 ib.offset -= start_offset;
1000 }
1001 }
1002
1003 /* VI reads index buffers through TC L2. */
1004 if (info->indexed && sctx->b.chip_class <= CIK &&
1005 r600_resource(ib.buffer)->TC_L2_dirty) {
1006 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
1007 r600_resource(ib.buffer)->TC_L2_dirty = false;
1008 }
1009
1010 if (info->indirect && r600_resource(info->indirect)->TC_L2_dirty) {
1011 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
1012 r600_resource(info->indirect)->TC_L2_dirty = false;
1013 }
1014
1015 if (info->indirect_params &&
1016 r600_resource(info->indirect_params)->TC_L2_dirty) {
1017 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
1018 r600_resource(info->indirect_params)->TC_L2_dirty = false;
1019 }
1020
1021 /* Add buffer sizes for memory checking in need_cs_space. */
1022 if (sctx->emit_scratch_reloc && sctx->scratch_buffer)
1023 r600_context_add_resource_size(ctx, &sctx->scratch_buffer->b.b);
1024 if (info->indirect)
1025 r600_context_add_resource_size(ctx, info->indirect);
1026
1027 si_need_cs_space(sctx);
1028
1029 /* Since we've called r600_context_add_resource_size for vertex buffers,
1030 * this must be called after si_need_cs_space, because we must let
1031 * need_cs_space flush before we add buffers to the buffer list.
1032 */
1033 if (!si_upload_vertex_buffer_descriptors(sctx))
1034 return;
1035
1036 /* Flushed caches prior to emitting states. */
1037 if (sctx->b.flags)
1038 si_emit_cache_flush(sctx);
1039
1040 /* Emit states. */
1041 mask = sctx->dirty_atoms;
1042 while (mask) {
1043 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
1044
1045 atom->emit(&sctx->b, atom);
1046 }
1047 sctx->dirty_atoms = 0;
1048
1049 si_pm4_emit_dirty(sctx);
1050 si_emit_scratch_reloc(sctx);
1051 si_emit_rasterizer_prim_state(sctx);
1052 si_emit_draw_registers(sctx, info);
1053
1054 si_ce_pre_draw_synchronization(sctx);
1055
1056 si_emit_draw_packets(sctx, info, &ib);
1057
1058 si_ce_post_draw_synchronization(sctx);
1059
1060 if (sctx->trace_buf)
1061 si_trace_emit(sctx);
1062
1063 /* Workaround for a VGT hang when streamout is enabled.
1064 * It must be done after drawing. */
1065 if ((sctx->b.family == CHIP_HAWAII ||
1066 sctx->b.family == CHIP_TONGA ||
1067 sctx->b.family == CHIP_FIJI) &&
1068 r600_get_strmout_en(&sctx->b)) {
1069 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1070 }
1071
1072 /* Set the depth buffer as dirty. */
1073 if (sctx->framebuffer.state.zsbuf) {
1074 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1075 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1076
1077 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1078
1079 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1080 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
1081 }
1082 if (sctx->framebuffer.compressed_cb_mask) {
1083 struct pipe_surface *surf;
1084 struct r600_texture *rtex;
1085 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1086
1087 do {
1088 unsigned i = u_bit_scan(&mask);
1089 surf = sctx->framebuffer.state.cbufs[i];
1090 rtex = (struct r600_texture*)surf->texture;
1091
1092 if (rtex->fmask.size)
1093 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1094 if (rtex->dcc_gather_statistics)
1095 rtex->separate_dcc_dirty = true;
1096 } while (mask);
1097 }
1098
1099 pipe_resource_reference(&ib.buffer, NULL);
1100 sctx->b.num_draw_calls++;
1101 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1102 sctx->b.num_spill_draw_calls++;
1103 }
1104
1105 void si_trace_emit(struct si_context *sctx)
1106 {
1107 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1108
1109 sctx->trace_id++;
1110 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
1111 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
1112 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1113 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1114 S_370_WR_CONFIRM(1) |
1115 S_370_ENGINE_SEL(V_370_ME));
1116 radeon_emit(cs, sctx->trace_buf->gpu_address);
1117 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
1118 radeon_emit(cs, sctx->trace_id);
1119 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1120 radeon_emit(cs, SI_ENCODE_TRACE_POINT(sctx->trace_id));
1121 }