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radeonsi: move draw cmds to si_commands.c
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "radeonsi_pipe.h"
32 #include "radeonsi_shader.h"
33 #include "si_state.h"
34 #include "sid.h"
35
36 /*
37 * Shaders
38 */
39
40 static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
41 {
42 struct r600_context *rctx = (struct r600_context *)ctx;
43 struct si_pm4_state *pm4;
44 unsigned num_sgprs, num_user_sgprs;
45 unsigned nparams, i;
46 uint64_t va;
47
48 if (si_pipe_shader_create(ctx, shader))
49 return;
50
51 si_pm4_delete_state(rctx, vs, shader->pm4);
52 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
53
54 si_pm4_inval_shader_cache(pm4);
55
56 /* Certain attributes (position, psize, etc.) don't count as params.
57 * VS is required to export at least one param and r600_shader_from_tgsi()
58 * takes care of adding a dummy export.
59 */
60 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
61 if (shader->shader.output[i].name != TGSI_SEMANTIC_POSITION)
62 nparams++;
63 }
64 if (nparams < 1)
65 nparams = 1;
66
67 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
68 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
69
70 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
71 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
72 S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
73 S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
74 S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE));
75
76 va = r600_resource_va(ctx->screen, (void *)shader->bo);
77 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
78 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
79 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
80
81 num_user_sgprs = 8;
82 num_sgprs = shader->num_sgprs;
83 if (num_user_sgprs > num_sgprs)
84 num_sgprs = num_user_sgprs;
85 /* Last 2 reserved SGPRs are used for VCC */
86 num_sgprs += 2;
87 assert(num_sgprs <= 104);
88
89 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
90 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
91 S_00B128_SGPRS((num_sgprs - 1) / 8));
92 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
93 S_00B12C_USER_SGPR(num_user_sgprs));
94
95 si_pm4_bind_state(rctx, vs, shader->pm4);
96 }
97
98 static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
99 {
100 struct r600_context *rctx = (struct r600_context *)ctx;
101 struct si_pm4_state *pm4;
102 unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
103 unsigned num_sgprs, num_user_sgprs;
104 int ninterp = 0;
105 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
106 unsigned fragcoord_interp_mode = 0;
107 unsigned spi_baryc_cntl, spi_ps_input_ena;
108 uint64_t va;
109
110 if (si_pipe_shader_create(ctx, shader))
111 return;
112
113 si_pm4_delete_state(rctx, ps, shader->pm4);
114 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
115
116 si_pm4_inval_shader_cache(pm4);
117
118 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
119 for (i = 0; i < shader->shader.ninput; i++) {
120 if (shader->shader.input[i].name == TGSI_SEMANTIC_POSITION) {
121 if (shader->shader.input[i].centroid) {
122 /* fragcoord_interp_mode will be written to
123 * SPI_BARYC_CNTL.POS_FLOAT_LOCATION
124 * Possible vaules:
125 * 0 -> Position = pixel center (default)
126 * 1 -> Position = pixel centroid
127 * 2 -> Position = iterated sample number XXX:
128 * What does this mean?
129 */
130 fragcoord_interp_mode = 1;
131 }
132 continue;
133 }
134 ninterp++;
135 /* XXX: Flat shading hangs the GPU */
136 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
137 (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
138 rctx->queued.named.rasterizer->flatshade))
139 have_linear = TRUE;
140 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
141 have_linear = TRUE;
142 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
143 have_perspective = TRUE;
144 if (shader->shader.input[i].centroid)
145 have_centroid = TRUE;
146 }
147
148 for (i = 0; i < shader->shader.noutput; i++) {
149 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
150 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
151 if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
152 db_shader_control |= 0; // XXX OP_VAL or TEST_VAL?
153 }
154 if (shader->shader.uses_kill)
155 db_shader_control |= S_02880C_KILL_ENABLE(1);
156
157 exports_ps = 0;
158 num_cout = 0;
159 for (i = 0; i < shader->shader.noutput; i++) {
160 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
161 shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
162 exports_ps |= 1;
163 else if (shader->shader.output[i].name == TGSI_SEMANTIC_COLOR) {
164 if (shader->shader.fs_write_all)
165 num_cout = shader->shader.nr_cbufs;
166 else
167 num_cout++;
168 }
169 }
170 if (!exports_ps) {
171 /* always at least export 1 component per pixel */
172 exports_ps = 2;
173 }
174
175 spi_ps_in_control = S_0286D8_NUM_INTERP(ninterp);
176
177 spi_baryc_cntl = 0;
178 if (have_perspective)
179 spi_baryc_cntl |= have_centroid ?
180 S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1);
181 if (have_linear)
182 spi_baryc_cntl |= have_centroid ?
183 S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1);
184 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(fragcoord_interp_mode);
185
186 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
187 spi_ps_input_ena = shader->spi_ps_input_ena;
188 /* we need to enable at least one of them, otherwise we hang the GPU */
189 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
190 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
191 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
192 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
193 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
194 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
195 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
196 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
197
198 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
199 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
200 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
201
202 /* XXX: Depends on Z buffer format? */
203 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, 0);
204
205 va = r600_resource_va(ctx->screen, (void *)shader->bo);
206 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
207 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
208 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
209
210 num_user_sgprs = 6;
211 num_sgprs = shader->num_sgprs;
212 if (num_user_sgprs > num_sgprs)
213 num_sgprs = num_user_sgprs;
214 /* Last 2 reserved SGPRs are used for VCC */
215 num_sgprs += 2;
216 assert(num_sgprs <= 104);
217
218 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
219 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
220 S_00B028_SGPRS((num_sgprs - 1) / 8));
221 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
222 S_00B02C_USER_SGPR(num_user_sgprs));
223
224 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
225
226 shader->sprite_coord_enable = rctx->sprite_coord_enable;
227 si_pm4_bind_state(rctx, ps, shader->pm4);
228 }
229
230 /*
231 * Drawing
232 */
233
234 static unsigned si_conv_pipe_prim(unsigned pprim)
235 {
236 static const unsigned prim_conv[] = {
237 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
238 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
239 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
240 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
241 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
242 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
243 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
244 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
245 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
246 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
247 [PIPE_PRIM_LINES_ADJACENCY] = ~0,
248 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0,
249 [PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0,
250 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0
251 };
252 unsigned result = prim_conv[pprim];
253 if (result == ~0) {
254 R600_ERR("unsupported primitive type %d\n", pprim);
255 }
256 return result;
257 }
258
259 static bool si_update_draw_info_state(struct r600_context *rctx,
260 const struct pipe_draw_info *info)
261 {
262 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
263 unsigned prim = si_conv_pipe_prim(info->mode);
264 unsigned ls_mask = 0;
265
266 if (pm4 == NULL)
267 return false;
268
269 if (prim == ~0) {
270 FREE(pm4);
271 return false;
272 }
273
274 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
275 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
276 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
277 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET,
278 info->indexed ? info->index_bias : info->start);
279 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
280 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
281 #if 0
282 si_pm4_set_reg(pm4, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
283 si_pm4_set_reg(pm4, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance);
284 #endif
285
286 if (prim == V_008958_DI_PT_LINELIST)
287 ls_mask = 1;
288 else if (prim == V_008958_DI_PT_LINESTRIP)
289 ls_mask = 2;
290 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
291 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
292 rctx->pa_sc_line_stipple);
293
294 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
295 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
296 S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
297 } else {
298 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
299 }
300 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
301 prim == PIPE_PRIM_POINTS ? rctx->pa_cl_vs_out_cntl : 0
302 /*| (rctx->rasterizer->clip_plane_enable &
303 rctx->vs_shader->shader.clip_dist_write)*/);
304 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL, rctx->pa_cl_clip_cntl
305 /*| (rctx->vs_shader->shader.clip_dist_write ||
306 rctx->vs_shader->shader.vs_prohibit_ucps ?
307 0 : rctx->rasterizer->clip_plane_enable & 0x3F)*/);
308
309 si_pm4_set_state(rctx, draw_info, pm4);
310 return true;
311 }
312
313 static void si_update_alpha_ref(struct r600_context *rctx)
314 {
315 #if 0
316 unsigned alpha_ref;
317 struct r600_pipe_state rstate;
318
319 alpha_ref = rctx->alpha_ref;
320 rstate.nregs = 0;
321 if (rctx->export_16bpc)
322 alpha_ref &= ~0x1FFF;
323 si_pm4_set_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref);
324
325 si_pm4_set_state(rctx, TODO, pm4);
326 rctx->alpha_ref_dirty = false;
327 #endif
328 }
329
330 static void si_update_spi_map(struct r600_context *rctx)
331 {
332 struct si_shader *ps = &rctx->ps_shader->current->shader;
333 struct si_shader *vs = &rctx->vs_shader->current->shader;
334 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
335 unsigned i, j, tmp;
336
337 for (i = 0; i < ps->ninput; i++) {
338 tmp = 0;
339
340 #if 0
341 /* XXX: Flat shading hangs the GPU */
342 if (ps->input[i].name == TGSI_SEMANTIC_POSITION ||
343 ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
344 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
345 rctx->rasterizer && rctx->rasterizer->flatshade)) {
346 tmp |= S_028644_FLAT_SHADE(1);
347 }
348 #endif
349
350 if (ps->input[i].name == TGSI_SEMANTIC_GENERIC &&
351 rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
352 tmp |= S_028644_PT_SPRITE_TEX(1);
353 }
354
355 for (j = 0; j < vs->noutput; j++) {
356 if (ps->input[i].name == vs->output[j].name &&
357 ps->input[i].sid == vs->output[j].sid) {
358 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
359 break;
360 }
361 }
362
363 if (j == vs->noutput) {
364 /* No corresponding output found, load defaults into input */
365 tmp |= S_028644_OFFSET(0x20);
366 }
367
368 si_pm4_set_reg(pm4, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp);
369 }
370
371 si_pm4_set_state(rctx, spi, pm4);
372 }
373
374 static void si_update_derived_state(struct r600_context *rctx)
375 {
376 struct pipe_context * ctx = (struct pipe_context*)rctx;
377 unsigned ps_dirty = 0;
378
379 if (!rctx->blitter->running) {
380 if (rctx->have_depth_fb || rctx->have_depth_texture)
381 si_flush_depth_textures(rctx);
382 }
383
384 si_shader_select(ctx, rctx->ps_shader, &ps_dirty);
385
386 if (rctx->alpha_ref_dirty) {
387 si_update_alpha_ref(rctx);
388 }
389
390 if (!rctx->vs_shader->current->pm4) {
391 si_pipe_shader_vs(ctx, rctx->vs_shader->current);
392 }
393
394 if (!rctx->ps_shader->current->pm4) {
395 si_pipe_shader_ps(ctx, rctx->ps_shader->current);
396 ps_dirty = 0;
397 }
398 if (!rctx->ps_shader->current->bo) {
399 if (!rctx->dummy_pixel_shader->pm4)
400 si_pipe_shader_ps(ctx, rctx->dummy_pixel_shader);
401 else
402 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
403
404 ps_dirty = 0;
405 }
406
407 if (ps_dirty) {
408 si_pm4_bind_state(rctx, ps, rctx->ps_shader->current->pm4);
409 }
410
411 if (si_pm4_state_changed(rctx, ps) || si_pm4_state_changed(rctx, vs)) {
412 si_update_spi_map(rctx);
413 }
414 }
415
416 static void si_vertex_buffer_update(struct r600_context *rctx)
417 {
418 struct pipe_context *ctx = &rctx->context;
419 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
420 bool bound[PIPE_MAX_ATTRIBS] = {};
421 unsigned i, count;
422 uint64_t va;
423
424 si_pm4_inval_vertex_cache(pm4);
425
426 /* bind vertex buffer once */
427 count = rctx->vertex_elements->count;
428 assert(count <= 256 / 4);
429
430 si_pm4_sh_data_begin(pm4);
431 for (i = 0 ; i < count; i++) {
432 struct pipe_vertex_element *ve = &rctx->vertex_elements->elements[i];
433 struct pipe_vertex_buffer *vb;
434 struct si_resource *rbuffer;
435 unsigned offset;
436
437 if (ve->vertex_buffer_index >= rctx->nr_vertex_buffers)
438 continue;
439
440 vb = &rctx->vertex_buffer[ve->vertex_buffer_index];
441 rbuffer = (struct si_resource*)vb->buffer;
442 if (rbuffer == NULL)
443 continue;
444
445 offset = 0;
446 offset += vb->buffer_offset;
447 offset += ve->src_offset;
448
449 va = r600_resource_va(ctx->screen, (void*)rbuffer);
450 va += offset;
451
452 /* Fill in T# buffer resource description */
453 si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF);
454 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
455 S_008F04_STRIDE(vb->stride)));
456 si_pm4_sh_data_add(pm4, (vb->buffer->width0 - vb->buffer_offset) /
457 MAX2(vb->stride, 1));
458 si_pm4_sh_data_add(pm4, rctx->vertex_elements->rsrc_word3[i]);
459
460 if (!bound[ve->vertex_buffer_index]) {
461 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
462 bound[ve->vertex_buffer_index] = true;
463 }
464 }
465 si_pm4_sh_data_end(pm4, R_00B148_SPI_SHADER_USER_DATA_VS_6);
466 si_pm4_set_state(rctx, vertex_buffers, pm4);
467 }
468
469 static void si_state_draw(struct r600_context *rctx,
470 const struct pipe_draw_info *info,
471 const struct pipe_index_buffer *ib)
472 {
473 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
474
475 /* queries need some special values
476 * (this is non-zero if any query is active) */
477 if (rctx->num_cs_dw_queries_suspend) {
478 struct si_state_dsa *dsa = rctx->queued.named.dsa;
479
480 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
481 S_028004_PERFECT_ZPASS_COUNTS(1));
482 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
483 dsa->db_render_override |
484 S_02800C_NOOP_CULL_DISABLE(1));
485 }
486
487 /* draw packet */
488 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
489 if (ib->index_size == 4) {
490 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (R600_BIG_ENDIAN ?
491 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
492 } else {
493 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (R600_BIG_ENDIAN ?
494 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
495 }
496 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
497
498 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
499 si_pm4_cmd_add(pm4, info->instance_count);
500 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
501
502 if (info->indexed) {
503 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
504 rctx->index_buffer.index_size;
505 uint64_t va;
506 va = r600_resource_va(&rctx->screen->screen, ib->buffer);
507 va += ib->offset;
508
509 si_pm4_add_bo(pm4, (struct si_resource *)ib->buffer, RADEON_USAGE_READ);
510 si_cmd_draw_index_2(pm4, max_size, va, info->count,
511 V_0287F0_DI_SRC_SEL_DMA,
512 rctx->predicate_drawing);
513 } else {
514 uint32_t initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
515 initiator |= S_0287F0_USE_OPAQUE(!!info->count_from_stream_output);
516 si_cmd_draw_index_auto(pm4, info->count, initiator, rctx->predicate_drawing);
517 }
518 si_pm4_set_state(rctx, draw, pm4);
519 }
520
521 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
522 {
523 struct r600_context *rctx = (struct r600_context *)ctx;
524 struct pipe_index_buffer ib = {};
525 uint32_t cp_coher_cntl;
526
527 if ((!info->count && (info->indexed || !info->count_from_stream_output)) ||
528 (info->indexed && !rctx->index_buffer.buffer)) {
529 return;
530 }
531
532 if (!rctx->ps_shader || !rctx->vs_shader)
533 return;
534
535 si_update_derived_state(rctx);
536 si_vertex_buffer_update(rctx);
537
538 if (info->indexed) {
539 /* Initialize the index buffer struct. */
540 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
541 ib.index_size = rctx->index_buffer.index_size;
542 ib.offset = rctx->index_buffer.offset + info->start * ib.index_size;
543
544 /* Translate or upload, if needed. */
545 r600_translate_index_buffer(rctx, &ib, info->count);
546
547 if (ib.user_buffer) {
548 r600_upload_index_buffer(rctx, &ib, info->count);
549 }
550
551 } else if (info->count_from_stream_output) {
552 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info->count_from_stream_output);
553 }
554
555 rctx->vs_shader_so_strides = rctx->vs_shader->current->so_strides;
556
557 if (!si_update_draw_info_state(rctx, info))
558 return;
559
560 si_state_draw(rctx, info, &ib);
561
562 cp_coher_cntl = si_pm4_sync_flags(rctx);
563 if (cp_coher_cntl) {
564 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
565 si_cmd_surface_sync(pm4, cp_coher_cntl);
566 si_pm4_set_state(rctx, sync, pm4);
567 }
568
569 /* Emit states. */
570 rctx->pm4_dirty_cdwords += si_pm4_dirty_dw(rctx);
571
572 si_need_cs_space(rctx, 0, TRUE);
573
574 si_pm4_emit_dirty(rctx);
575 rctx->pm4_dirty_cdwords = 0;
576
577 #if 0
578 /* Enable stream out if needed. */
579 if (rctx->streamout_start) {
580 r600_context_streamout_begin(rctx);
581 rctx->streamout_start = FALSE;
582 }
583 #endif
584
585
586 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY;
587
588 if (rctx->framebuffer.zsbuf)
589 {
590 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
591 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
592 }
593
594 pipe_resource_reference(&ib.buffer, NULL);
595 }