projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: Allow TES distribution between shader engines.
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "radeon/r600_cs.h"
30 #include "sid.h"
31
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
35 #include "util/u_memory.h"
36
37 static unsigned si_conv_pipe_prim(unsigned mode)
38 {
39 static const unsigned prim_conv[] = {
40 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
41 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
42 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
43 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
44 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
45 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
46 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
47 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
48 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
49 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
50 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
51 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
52 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
53 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
54 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
55 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
56 };
57 assert(mode < ARRAY_SIZE(prim_conv));
58 return prim_conv[mode];
59 }
60
61 static unsigned si_conv_prim_to_gs_out(unsigned mode)
62 {
63 static const int prim_conv[] = {
64 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
65 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
66 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
67 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
68 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
69 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
73 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
74 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
75 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
76 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
77 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
78 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
79 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
80 };
81 assert(mode < ARRAY_SIZE(prim_conv));
82
83 return prim_conv[mode];
84 }
85
86 /**
87 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
88 * LS.LDS_SIZE is shared by all 3 shader stages.
89 *
90 * The information about LDS and other non-compile-time parameters is then
91 * written to userdata SGPRs.
92 */
93 static void si_emit_derived_tess_state(struct si_context *sctx,
94 const struct pipe_draw_info *info,
95 unsigned *num_patches)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_shader_ctx_state *ls = &sctx->vs_shader;
99 /* The TES pointer will only be used for sctx->last_tcs.
100 * It would be wrong to think that TCS = TES. */
101 struct si_shader_selector *tcs =
102 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
103 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
104 unsigned num_tcs_input_cp = info->vertices_per_patch;
105 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
106 unsigned num_tcs_patch_outputs;
107 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
108 unsigned input_patch_size, output_patch_size, output_patch0_offset;
109 unsigned perpatch_output_offset, lds_size, ls_rsrc2;
110 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
111 unsigned offchip_layout, hardware_lds_size;
112
113 /* This calculates how shader inputs and outputs among VS, TCS, and TES
114 * are laid out in LDS. */
115 num_tcs_inputs = util_last_bit64(ls->cso->outputs_written);
116
117 if (sctx->tcs_shader.cso) {
118 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
119 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
120 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
121 } else {
122 /* No TCS. Route varyings from LS to TES. */
123 num_tcs_outputs = num_tcs_inputs;
124 num_tcs_output_cp = num_tcs_input_cp;
125 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
126 }
127
128 input_vertex_size = num_tcs_inputs * 16;
129 output_vertex_size = num_tcs_outputs * 16;
130
131 input_patch_size = num_tcs_input_cp * input_vertex_size;
132
133 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
134 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
135
136 /* Ensure that we only need one wave per SIMD so we don't need to check
137 * resource usage. Also ensures that the number of tcs in and out
138 * vertices per threadgroup are at most 256.
139 */
140 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
141
142 /* Make sure that the data fits in LDS. This assumes the shaders only
143 * use LDS for the inputs and outputs.
144 */
145 hardware_lds_size = sctx->b.chip_class >= CIK ? 65536 : 32768;
146 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
147 output_patch_size));
148
149 /* Make sure the output data fits in the offchip buffer */
150 *num_patches = MIN2(*num_patches, SI_TESS_OFFCHIP_BLOCK_SIZE /
151 output_patch_size);
152
153 /* Not necessary for correctness, but improves performance. The
154 * specific value is taken from the proprietary driver.
155 */
156 *num_patches = MIN2(*num_patches, 40);
157
158 output_patch0_offset = input_patch_size * *num_patches;
159 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
160
161 lds_size = output_patch0_offset + output_patch_size * *num_patches;
162 ls_rsrc2 = ls->current->config.rsrc2;
163
164 if (sctx->b.chip_class >= CIK) {
165 assert(lds_size <= 65536);
166 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 512) / 512);
167 } else {
168 assert(lds_size <= 32768);
169 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 256) / 256);
170 }
171
172 if (sctx->last_ls == ls->current &&
173 sctx->last_tcs == tcs &&
174 sctx->last_tes_sh_base == tes_sh_base &&
175 sctx->last_num_tcs_input_cp == num_tcs_input_cp)
176 return;
177
178 sctx->last_ls = ls->current;
179 sctx->last_tcs = tcs;
180 sctx->last_tes_sh_base = tes_sh_base;
181 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
182
183 /* Due to a hw bug, RSRC2_LS must be written twice with another
184 * LS register written in between. */
185 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
186 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
187 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
188 radeon_emit(cs, ls->current->config.rsrc1);
189 radeon_emit(cs, ls_rsrc2);
190
191 /* Compute userdata SGPRs. */
192 assert(((input_vertex_size / 4) & ~0xff) == 0);
193 assert(((output_vertex_size / 4) & ~0xff) == 0);
194 assert(((input_patch_size / 4) & ~0x1fff) == 0);
195 assert(((output_patch_size / 4) & ~0x1fff) == 0);
196 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
197 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
198 assert(num_tcs_input_cp <= 32);
199 assert(num_tcs_output_cp <= 32);
200
201 tcs_in_layout = (input_patch_size / 4) |
202 ((input_vertex_size / 4) << 13);
203 tcs_out_layout = (output_patch_size / 4) |
204 ((output_vertex_size / 4) << 13);
205 tcs_out_offsets = (output_patch0_offset / 16) |
206 ((perpatch_output_offset / 16) << 16);
207 offchip_layout = (pervertex_output_patch_size * *num_patches << 16) |
208 (num_tcs_output_cp << 9) | *num_patches;
209
210 /* Set them for LS. */
211 radeon_set_sh_reg(cs,
212 R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4,
213 tcs_in_layout);
214
215 /* Set them for TCS. */
216 radeon_set_sh_reg_seq(cs,
217 R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
218 radeon_emit(cs, offchip_layout);
219 radeon_emit(cs, tcs_out_offsets);
220 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
221 radeon_emit(cs, tcs_in_layout);
222
223 /* Set them for TES. */
224 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 1);
225 radeon_emit(cs, offchip_layout);
226 }
227
228 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
229 {
230 switch (info->mode) {
231 case PIPE_PRIM_PATCHES:
232 return info->count / info->vertices_per_patch;
233 case R600_PRIM_RECTANGLE_LIST:
234 return info->count / 3;
235 default:
236 return u_prims_for_vertices(info->mode, info->count);
237 }
238 }
239
240 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
241 const struct pipe_draw_info *info,
242 unsigned num_patches)
243 {
244 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
245 unsigned prim = info->mode;
246 unsigned primgroup_size = 128; /* recommended without a GS */
247 unsigned max_primgroup_in_wave = 2;
248
249 /* SWITCH_ON_EOP(0) is always preferable. */
250 bool wd_switch_on_eop = false;
251 bool ia_switch_on_eop = false;
252 bool ia_switch_on_eoi = false;
253 bool partial_vs_wave = false;
254 bool partial_es_wave = false;
255
256 if (sctx->gs_shader.cso)
257 primgroup_size = 64; /* recommended with a GS */
258
259 if (sctx->tes_shader.cso) {
260 unsigned num_cp_out =
261 sctx->tcs_shader.cso ?
262 sctx->tcs_shader.cso->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
263 info->vertices_per_patch;
264 unsigned max_size = 256 / MAX2(info->vertices_per_patch, num_cp_out);
265
266 primgroup_size = MIN2(primgroup_size, max_size);
267
268 /* primgroup_size must be set to a multiple of NUM_PATCHES */
269 primgroup_size = (primgroup_size / num_patches) * num_patches;
270
271 /* SWITCH_ON_EOI must be set if PrimID is used. */
272 if ((sctx->tcs_shader.cso && sctx->tcs_shader.cso->info.uses_primid) ||
273 sctx->tes_shader.cso->info.uses_primid)
274 ia_switch_on_eoi = true;
275
276 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
277 if ((sctx->b.family == CHIP_TAHITI ||
278 sctx->b.family == CHIP_PITCAIRN ||
279 sctx->b.family == CHIP_BONAIRE) &&
280 sctx->gs_shader.cso)
281 partial_vs_wave = true;
282
283 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
284 if (sctx->b.chip_class >= VI) {
285 if (sctx->gs_shader.cso)
286 partial_es_wave = true;
287 else
288 partial_vs_wave = true;
289 }
290 }
291
292 /* This is a hardware requirement. */
293 if ((rs && rs->line_stipple_enable) ||
294 (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
295 ia_switch_on_eop = true;
296 wd_switch_on_eop = true;
297 }
298
299 if (sctx->b.chip_class >= CIK) {
300 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
301 * 4 shader engines. Set 1 to pass the assertion below.
302 * The other cases are hardware requirements. */
303 if (sctx->b.screen->info.max_se < 4 ||
304 prim == PIPE_PRIM_POLYGON ||
305 prim == PIPE_PRIM_LINE_LOOP ||
306 prim == PIPE_PRIM_TRIANGLE_FAN ||
307 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
308 info->primitive_restart ||
309 info->count_from_stream_output)
310 wd_switch_on_eop = true;
311
312 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
313 * We don't know that for indirect drawing, so treat it as
314 * always problematic. */
315 if (sctx->b.family == CHIP_HAWAII &&
316 (info->indirect || info->instance_count > 1))
317 wd_switch_on_eop = true;
318
319 /* Required on CIK and later. */
320 if (sctx->b.screen->info.max_se > 2 && !wd_switch_on_eop)
321 ia_switch_on_eoi = true;
322
323 /* Required by Hawaii and, for some special cases, by VI. */
324 if (ia_switch_on_eoi &&
325 (sctx->b.family == CHIP_HAWAII ||
326 (sctx->b.chip_class == VI &&
327 (sctx->gs_shader.cso || max_primgroup_in_wave != 2))))
328 partial_vs_wave = true;
329
330 /* Instancing bug on Bonaire. */
331 if (sctx->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
332 (info->indirect || info->instance_count > 1))
333 partial_vs_wave = true;
334
335 /* If the WD switch is false, the IA switch must be false too. */
336 assert(wd_switch_on_eop || !ia_switch_on_eop);
337 }
338
339 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
340 if (ia_switch_on_eoi)
341 partial_es_wave = true;
342
343 /* GS requirement. */
344 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
345 partial_es_wave = true;
346
347 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
348 * on multi-SE chips. */
349 if (sctx->b.screen->info.max_se >= 2 && ia_switch_on_eoi &&
350 (info->indirect ||
351 (info->instance_count > 1 &&
352 si_num_prims_for_vertices(info) <= 1)))
353 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
354
355 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
356 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
357 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
358 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
359 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
360 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
361 S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx->b.chip_class >= VI ?
362 max_primgroup_in_wave : 0);
363 }
364
365 static unsigned si_get_ls_hs_config(struct si_context *sctx,
366 const struct pipe_draw_info *info,
367 unsigned num_patches)
368 {
369 unsigned num_output_cp;
370
371 if (!sctx->tes_shader.cso)
372 return 0;
373
374 num_output_cp = sctx->tcs_shader.cso ?
375 sctx->tcs_shader.cso->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
376 info->vertices_per_patch;
377
378 return S_028B58_NUM_PATCHES(num_patches) |
379 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
380 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
381 }
382
383 static void si_emit_scratch_reloc(struct si_context *sctx)
384 {
385 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
386
387 if (!sctx->emit_scratch_reloc)
388 return;
389
390 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
391 sctx->spi_tmpring_size);
392
393 if (sctx->scratch_buffer) {
394 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
395 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
396 RADEON_PRIO_SCRATCH_BUFFER);
397
398 }
399 sctx->emit_scratch_reloc = false;
400 }
401
402 /* rast_prim is the primitive type after GS. */
403 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
404 {
405 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
406 unsigned rast_prim = sctx->current_rast_prim;
407 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
408
409 /* Skip this if not rendering lines. */
410 if (rast_prim != PIPE_PRIM_LINES &&
411 rast_prim != PIPE_PRIM_LINE_LOOP &&
412 rast_prim != PIPE_PRIM_LINE_STRIP &&
413 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
414 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
415 return;
416
417 if (rast_prim == sctx->last_rast_prim &&
418 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
419 return;
420
421 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
422 rs->pa_sc_line_stipple |
423 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 :
424 rast_prim == PIPE_PRIM_LINE_STRIP ? 2 : 0));
425
426 sctx->last_rast_prim = rast_prim;
427 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
428 }
429
430 static void si_emit_draw_registers(struct si_context *sctx,
431 const struct pipe_draw_info *info)
432 {
433 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
434 unsigned prim = si_conv_pipe_prim(info->mode);
435 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
436 unsigned ia_multi_vgt_param, ls_hs_config, num_patches = 0;
437
438 if (sctx->tes_shader.cso)
439 si_emit_derived_tess_state(sctx, info, &num_patches);
440
441 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
442 ls_hs_config = si_get_ls_hs_config(sctx, info, num_patches);
443
444 /* Draw state. */
445 if (prim != sctx->last_prim ||
446 ia_multi_vgt_param != sctx->last_multi_vgt_param ||
447 ls_hs_config != sctx->last_ls_hs_config) {
448 if (sctx->b.chip_class >= CIK) {
449 radeon_emit(cs, PKT3(PKT3_DRAW_PREAMBLE, 2, 0));
450 radeon_emit(cs, prim); /* VGT_PRIMITIVE_TYPE */
451 radeon_emit(cs, ia_multi_vgt_param); /* IA_MULTI_VGT_PARAM */
452 radeon_emit(cs, ls_hs_config); /* VGT_LS_HS_CONFIG */
453 } else {
454 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
455 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
456 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
457 }
458 sctx->last_prim = prim;
459 sctx->last_multi_vgt_param = ia_multi_vgt_param;
460 sctx->last_ls_hs_config = ls_hs_config;
461 }
462
463 if (gs_out_prim != sctx->last_gs_out_prim) {
464 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
465 sctx->last_gs_out_prim = gs_out_prim;
466 }
467
468 /* Primitive restart. */
469 if (info->primitive_restart != sctx->last_primitive_restart_en) {
470 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
471 sctx->last_primitive_restart_en = info->primitive_restart;
472
473 if (info->primitive_restart &&
474 (info->restart_index != sctx->last_restart_index ||
475 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
476 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
477 info->restart_index);
478 sctx->last_restart_index = info->restart_index;
479 }
480 }
481 }
482
483 static void si_emit_draw_packets(struct si_context *sctx,
484 const struct pipe_draw_info *info,
485 const struct pipe_index_buffer *ib)
486 {
487 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
488 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
489 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
490
491 if (info->count_from_stream_output) {
492 struct r600_so_target *t =
493 (struct r600_so_target*)info->count_from_stream_output;
494 uint64_t va = t->buf_filled_size->gpu_address +
495 t->buf_filled_size_offset;
496
497 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
498 t->stride_in_dw);
499
500 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
501 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
502 COPY_DATA_DST_SEL(COPY_DATA_REG) |
503 COPY_DATA_WR_CONFIRM);
504 radeon_emit(cs, va); /* src address lo */
505 radeon_emit(cs, va >> 32); /* src address hi */
506 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
507 radeon_emit(cs, 0); /* unused */
508
509 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
510 t->buf_filled_size, RADEON_USAGE_READ,
511 RADEON_PRIO_SO_FILLED_SIZE);
512 }
513
514 /* draw packet */
515 if (info->indexed) {
516 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
517
518 /* index type */
519 switch (ib->index_size) {
520 case 1:
521 radeon_emit(cs, V_028A7C_VGT_INDEX_8);
522 break;
523 case 2:
524 radeon_emit(cs, V_028A7C_VGT_INDEX_16 |
525 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
526 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
527 break;
528 case 4:
529 radeon_emit(cs, V_028A7C_VGT_INDEX_32 |
530 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
531 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
532 break;
533 default:
534 assert(!"unreachable");
535 return;
536 }
537 }
538
539 if (!info->indirect) {
540 int base_vertex;
541
542 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
543 radeon_emit(cs, info->instance_count);
544
545 /* Base vertex and start instance. */
546 base_vertex = info->indexed ? info->index_bias : info->start;
547
548 if (base_vertex != sctx->last_base_vertex ||
549 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
550 info->start_instance != sctx->last_start_instance ||
551 sh_base_reg != sctx->last_sh_base_reg) {
552 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
553 radeon_emit(cs, base_vertex);
554 radeon_emit(cs, info->start_instance);
555
556 sctx->last_base_vertex = base_vertex;
557 sctx->last_start_instance = info->start_instance;
558 sctx->last_sh_base_reg = sh_base_reg;
559 }
560 } else {
561 si_invalidate_draw_sh_constants(sctx);
562
563 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
564 (struct r600_resource *)info->indirect,
565 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
566 }
567
568 if (info->indexed) {
569 uint32_t index_max_size = (ib->buffer->width0 - ib->offset) /
570 ib->index_size;
571 uint64_t index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
572
573 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
574 (struct r600_resource *)ib->buffer,
575 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
576
577 if (info->indirect) {
578 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
579
580 assert(indirect_va % 8 == 0);
581 assert(index_va % 2 == 0);
582 assert(info->indirect_offset % 4 == 0);
583
584 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
585 radeon_emit(cs, 1);
586 radeon_emit(cs, indirect_va);
587 radeon_emit(cs, indirect_va >> 32);
588
589 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
590 radeon_emit(cs, index_va);
591 radeon_emit(cs, index_va >> 32);
592
593 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
594 radeon_emit(cs, index_max_size);
595
596 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT, 3, render_cond_bit));
597 radeon_emit(cs, info->indirect_offset);
598 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
599 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
600 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
601 } else {
602 index_va += info->start * ib->index_size;
603
604 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
605 radeon_emit(cs, index_max_size);
606 radeon_emit(cs, index_va);
607 radeon_emit(cs, (index_va >> 32UL) & 0xFF);
608 radeon_emit(cs, info->count);
609 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
610 }
611 } else {
612 if (info->indirect) {
613 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
614
615 assert(indirect_va % 8 == 0);
616 assert(info->indirect_offset % 4 == 0);
617
618 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
619 radeon_emit(cs, 1);
620 radeon_emit(cs, indirect_va);
621 radeon_emit(cs, indirect_va >> 32);
622
623 radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, render_cond_bit));
624 radeon_emit(cs, info->indirect_offset);
625 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
626 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
627 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
628 } else {
629 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
630 radeon_emit(cs, info->count);
631 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
632 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
633 }
634 }
635 }
636
637 void si_emit_cache_flush(struct si_context *si_ctx, struct r600_atom *atom)
638 {
639 struct r600_common_context *sctx = &si_ctx->b;
640 struct radeon_winsys_cs *cs = sctx->gfx.cs;
641 uint32_t cp_coher_cntl = 0;
642
643 /* SI has a bug that it always flushes ICACHE and KCACHE if either
644 * bit is set. An alternative way is to write SQC_CACHES, but that
645 * doesn't seem to work reliably. Since the bug doesn't affect
646 * correctness (it only does more work than necessary) and
647 * the performance impact is likely negligible, there is no plan
648 * to add a workaround for it.
649 */
650
651 if (sctx->flags & SI_CONTEXT_INV_ICACHE)
652 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
653 if (sctx->flags & SI_CONTEXT_INV_SMEM_L1)
654 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
655
656 if (sctx->flags & SI_CONTEXT_INV_VMEM_L1)
657 cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
658 if (sctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
659 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
660
661 if (sctx->chip_class >= VI)
662 cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1);
663 }
664
665 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
666 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
667 S_0085F0_CB0_DEST_BASE_ENA(1) |
668 S_0085F0_CB1_DEST_BASE_ENA(1) |
669 S_0085F0_CB2_DEST_BASE_ENA(1) |
670 S_0085F0_CB3_DEST_BASE_ENA(1) |
671 S_0085F0_CB4_DEST_BASE_ENA(1) |
672 S_0085F0_CB5_DEST_BASE_ENA(1) |
673 S_0085F0_CB6_DEST_BASE_ENA(1) |
674 S_0085F0_CB7_DEST_BASE_ENA(1);
675
676 /* Necessary for DCC */
677 if (sctx->chip_class >= VI) {
678 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
679 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) |
680 EVENT_INDEX(5));
681 radeon_emit(cs, 0);
682 radeon_emit(cs, 0);
683 radeon_emit(cs, 0);
684 radeon_emit(cs, 0);
685 }
686 }
687 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
688 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
689 S_0085F0_DB_DEST_BASE_ENA(1);
690 }
691
692 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) {
693 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
694 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
695 /* needed for wait for idle in SURFACE_SYNC */
696 assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB);
697 }
698 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) {
699 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
700 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
701 /* needed for wait for idle in SURFACE_SYNC */
702 assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB);
703 }
704
705 /* Wait for shader engines to go idle.
706 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
707 * for everything including CB/DB cache flushes.
708 */
709 if (!(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
710 SI_CONTEXT_FLUSH_AND_INV_DB))) {
711 if (sctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
712 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
713 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
714 } else if (sctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
715 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
716 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
717 }
718 }
719 if (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH) {
720 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
721 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
722 }
723
724 /* VGT state synchronization. */
725 if (sctx->flags & SI_CONTEXT_VGT_FLUSH) {
726 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
727 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
728 }
729 if (sctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
730 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
731 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
732 }
733
734 /* Make sure ME is idle (it executes most packets) before continuing.
735 * This prevents read-after-write hazards between PFP and ME.
736 */
737 if (cp_coher_cntl || (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH)) {
738 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
739 radeon_emit(cs, 0);
740 }
741
742 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
743 * Therefore, it should be last. Done in PFP.
744 */
745 if (cp_coher_cntl) {
746 /* ACQUIRE_MEM is only required on a compute ring. */
747 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
748 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
749 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
750 radeon_emit(cs, 0); /* CP_COHER_BASE */
751 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
752 }
753
754 if (sctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
755 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
756 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
757 EVENT_INDEX(0));
758 } else if (sctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
759 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
760 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
761 EVENT_INDEX(0));
762 }
763
764 sctx->flags = 0;
765 }
766
767 static void si_get_draw_start_count(struct si_context *sctx,
768 const struct pipe_draw_info *info,
769 unsigned *start, unsigned *count)
770 {
771 if (info->indirect) {
772 struct r600_resource *indirect =
773 (struct r600_resource*)info->indirect;
774 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
775 indirect, PIPE_TRANSFER_READ);
776 data += info->indirect_offset/sizeof(int);
777 *start = data[2];
778 *count = data[0];
779 } else {
780 *start = info->start;
781 *count = info->count;
782 }
783 }
784
785 void si_ce_pre_draw_synchronization(struct si_context *sctx)
786 {
787 if (sctx->ce_need_synchronization) {
788 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
789 radeon_emit(sctx->ce_ib, 1);
790
791 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
792 radeon_emit(sctx->b.gfx.cs, 1);
793 }
794 }
795
796 void si_ce_post_draw_synchronization(struct si_context *sctx)
797 {
798 if (sctx->ce_need_synchronization) {
799 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
800 radeon_emit(sctx->b.gfx.cs, 0);
801
802 sctx->ce_need_synchronization = false;
803 }
804 }
805
806 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
807 {
808 struct si_context *sctx = (struct si_context *)ctx;
809 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
810 struct pipe_index_buffer ib = {};
811 unsigned mask, dirty_fb_counter;
812
813 if (!info->count && !info->indirect &&
814 (info->indexed || !info->count_from_stream_output))
815 return;
816
817 if (!sctx->vs_shader.cso) {
818 assert(0);
819 return;
820 }
821 if (!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard)) {
822 assert(0);
823 return;
824 }
825 if (!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES)) {
826 assert(0);
827 return;
828 }
829
830 /* Re-emit the framebuffer state if needed. */
831 dirty_fb_counter = p_atomic_read(&sctx->b.screen->dirty_fb_counter);
832 if (dirty_fb_counter != sctx->b.last_dirty_fb_counter) {
833 sctx->b.last_dirty_fb_counter = dirty_fb_counter;
834 sctx->framebuffer.dirty_cbufs |=
835 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
836 sctx->framebuffer.dirty_zsbuf = true;
837 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
838 }
839
840 si_decompress_graphics_textures(sctx);
841
842 /* Set the rasterization primitive type.
843 *
844 * This must be done after si_decompress_textures, which can call
845 * draw_vbo recursively, and before si_update_shaders, which uses
846 * current_rast_prim for this draw_vbo call. */
847 if (sctx->gs_shader.cso)
848 sctx->current_rast_prim = sctx->gs_shader.cso->gs_output_prim;
849 else if (sctx->tes_shader.cso)
850 sctx->current_rast_prim =
851 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
852 else
853 sctx->current_rast_prim = info->mode;
854
855 if (!si_update_shaders(sctx) ||
856 !si_upload_graphics_shader_descriptors(sctx))
857 return;
858
859 if (info->indexed) {
860 /* Initialize the index buffer struct. */
861 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
862 ib.user_buffer = sctx->index_buffer.user_buffer;
863 ib.index_size = sctx->index_buffer.index_size;
864 ib.offset = sctx->index_buffer.offset;
865
866 /* Translate or upload, if needed. */
867 /* 8-bit indices are supported on VI. */
868 if (sctx->b.chip_class <= CIK && ib.index_size == 1) {
869 struct pipe_resource *out_buffer = NULL;
870 unsigned out_offset, start, count, start_offset;
871 void *ptr;
872
873 si_get_draw_start_count(sctx, info, &start, &count);
874 start_offset = start * ib.index_size;
875
876 u_upload_alloc(sctx->b.uploader, start_offset, count * 2, 256,
877 &out_offset, &out_buffer, &ptr);
878 if (!out_buffer) {
879 pipe_resource_reference(&ib.buffer, NULL);
880 return;
881 }
882
883 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
884 ib.offset + start_offset,
885 count, ptr);
886
887 pipe_resource_reference(&ib.buffer, NULL);
888 ib.user_buffer = NULL;
889 ib.buffer = out_buffer;
890 /* info->start will be added by the drawing code */
891 ib.offset = out_offset - start_offset;
892 ib.index_size = 2;
893 } else if (ib.user_buffer && !ib.buffer) {
894 unsigned start, count, start_offset;
895
896 si_get_draw_start_count(sctx, info, &start, &count);
897 start_offset = start * ib.index_size;
898
899 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
900 256, (char*)ib.user_buffer + start_offset,
901 &ib.offset, &ib.buffer);
902 if (!ib.buffer)
903 return;
904 /* info->start will be added by the drawing code */
905 ib.offset -= start_offset;
906 }
907 }
908
909 /* VI reads index buffers through TC L2. */
910 if (info->indexed && sctx->b.chip_class <= CIK &&
911 r600_resource(ib.buffer)->TC_L2_dirty) {
912 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
913 r600_resource(ib.buffer)->TC_L2_dirty = false;
914 }
915
916 /* Check flush flags. */
917 if (sctx->b.flags)
918 si_mark_atom_dirty(sctx, sctx->atoms.s.cache_flush);
919
920 si_need_cs_space(sctx);
921
922 /* Emit states. */
923 mask = sctx->dirty_atoms;
924 while (mask) {
925 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
926
927 atom->emit(&sctx->b, atom);
928 }
929 sctx->dirty_atoms = 0;
930
931 si_pm4_emit_dirty(sctx);
932 si_emit_scratch_reloc(sctx);
933 si_emit_rasterizer_prim_state(sctx);
934 si_emit_draw_registers(sctx, info);
935
936 si_ce_pre_draw_synchronization(sctx);
937
938 si_emit_draw_packets(sctx, info, &ib);
939
940 si_ce_post_draw_synchronization(sctx);
941
942 if (sctx->trace_buf)
943 si_trace_emit(sctx);
944
945 /* Workaround for a VGT hang when streamout is enabled.
946 * It must be done after drawing. */
947 if ((sctx->b.family == CHIP_HAWAII ||
948 sctx->b.family == CHIP_TONGA ||
949 sctx->b.family == CHIP_FIJI) &&
950 r600_get_strmout_en(&sctx->b)) {
951 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
952 }
953
954 /* Set the depth buffer as dirty. */
955 if (sctx->framebuffer.state.zsbuf) {
956 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
957 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
958
959 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
960
961 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
962 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
963 }
964 if (sctx->framebuffer.compressed_cb_mask) {
965 struct pipe_surface *surf;
966 struct r600_texture *rtex;
967 unsigned mask = sctx->framebuffer.compressed_cb_mask;
968
969 do {
970 unsigned i = u_bit_scan(&mask);
971 surf = sctx->framebuffer.state.cbufs[i];
972 rtex = (struct r600_texture*)surf->texture;
973
974 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
975 } while (mask);
976 }
977
978 pipe_resource_reference(&ib.buffer, NULL);
979 sctx->b.num_draw_calls++;
980 }
981
982 void si_trace_emit(struct si_context *sctx)
983 {
984 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
985
986 sctx->trace_id++;
987 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
988 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
989 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
990 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
991 S_370_WR_CONFIRM(1) |
992 S_370_ENGINE_SEL(V_370_ME));
993 radeon_emit(cs, sctx->trace_buf->gpu_address);
994 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
995 radeon_emit(cs, sctx->trace_id);
996 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
997 radeon_emit(cs, SI_ENCODE_TRACE_POINT(sctx->trace_id));
998 }