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radeonsi: fix a GPU hang with tessellation on 2-CU configs
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "radeon/r600_cs.h"
29 #include "sid.h"
30 #include "gfx9d.h"
31
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
35
36 #include "ac_debug.h"
37
38 static unsigned si_conv_pipe_prim(unsigned mode)
39 {
40 static const unsigned prim_conv[] = {
41 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
42 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
43 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
44 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
45 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
46 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
47 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
48 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
49 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
50 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
51 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
55 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
56 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
57 };
58 assert(mode < ARRAY_SIZE(prim_conv));
59 return prim_conv[mode];
60 }
61
62 static unsigned si_conv_prim_to_gs_out(unsigned mode)
63 {
64 static const int prim_conv[] = {
65 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
66 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
67 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
68 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
69 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
73 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
74 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
75 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
76 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
77 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
78 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
79 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
80 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
81 };
82 assert(mode < ARRAY_SIZE(prim_conv));
83
84 return prim_conv[mode];
85 }
86
87 /**
88 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
89 * LS.LDS_SIZE is shared by all 3 shader stages.
90 *
91 * The information about LDS and other non-compile-time parameters is then
92 * written to userdata SGPRs.
93 */
94 static void si_emit_derived_tess_state(struct si_context *sctx,
95 const struct pipe_draw_info *info,
96 unsigned *num_patches)
97 {
98 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
99 struct si_shader *ls_current;
100 struct si_shader_selector *ls;
101 /* The TES pointer will only be used for sctx->last_tcs.
102 * It would be wrong to think that TCS = TES. */
103 struct si_shader_selector *tcs =
104 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
105 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
106 unsigned num_tcs_input_cp = info->vertices_per_patch;
107 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
108 unsigned num_tcs_patch_outputs;
109 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
110 unsigned input_patch_size, output_patch_size, output_patch0_offset;
111 unsigned perpatch_output_offset, lds_size;
112 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
113 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
114
115 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
116 if (sctx->b.chip_class >= GFX9) {
117 if (sctx->tcs_shader.cso)
118 ls_current = sctx->tcs_shader.current;
119 else
120 ls_current = sctx->fixed_func_tcs_shader.current;
121
122 ls = ls_current->key.part.tcs.ls;
123 } else {
124 ls_current = sctx->vs_shader.current;
125 ls = sctx->vs_shader.cso;
126 }
127
128 if (sctx->last_ls == ls_current &&
129 sctx->last_tcs == tcs &&
130 sctx->last_tes_sh_base == tes_sh_base &&
131 sctx->last_num_tcs_input_cp == num_tcs_input_cp) {
132 *num_patches = sctx->last_num_patches;
133 return;
134 }
135
136 sctx->last_ls = ls_current;
137 sctx->last_tcs = tcs;
138 sctx->last_tes_sh_base = tes_sh_base;
139 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
140
141 /* This calculates how shader inputs and outputs among VS, TCS, and TES
142 * are laid out in LDS. */
143 num_tcs_inputs = util_last_bit64(ls->outputs_written);
144
145 if (sctx->tcs_shader.cso) {
146 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
147 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
148 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
149 } else {
150 /* No TCS. Route varyings from LS to TES. */
151 num_tcs_outputs = num_tcs_inputs;
152 num_tcs_output_cp = num_tcs_input_cp;
153 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
154 }
155
156 input_vertex_size = num_tcs_inputs * 16;
157 output_vertex_size = num_tcs_outputs * 16;
158
159 input_patch_size = num_tcs_input_cp * input_vertex_size;
160
161 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
162 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
163
164 /* Ensure that we only need one wave per SIMD so we don't need to check
165 * resource usage. Also ensures that the number of tcs in and out
166 * vertices per threadgroup are at most 256.
167 */
168 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
169
170 /* Make sure that the data fits in LDS. This assumes the shaders only
171 * use LDS for the inputs and outputs.
172 *
173 * While CIK can use 64K per threadgroup, there is a hang on Stoney
174 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
175 * uses 32K at most on all GCN chips.
176 */
177 hardware_lds_size = 32768;
178 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
179 output_patch_size));
180
181 /* Make sure the output data fits in the offchip buffer */
182 *num_patches = MIN2(*num_patches,
183 (sctx->screen->tess_offchip_block_dw_size * 4) /
184 output_patch_size);
185
186 /* Not necessary for correctness, but improves performance. The
187 * specific value is taken from the proprietary driver.
188 */
189 *num_patches = MIN2(*num_patches, 40);
190
191 if (sctx->b.chip_class == SI) {
192 /* SI bug workaround, related to power management. Limit LS-HS
193 * threadgroups to only one wave.
194 */
195 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
196 *num_patches = MIN2(*num_patches, one_wave);
197
198 if (sctx->screen->b.info.max_se == 1) {
199 /* The VGT HS block increments the patch ID unconditionally
200 * within a single threadgroup. This results in incorrect
201 * patch IDs when instanced draws are used.
202 *
203 * The intended solution is to restrict threadgroups to
204 * a single instance by setting SWITCH_ON_EOI, which
205 * should cause IA to split instances up. However, this
206 * doesn't work correctly on SI when there is no other
207 * SE to switch to.
208 */
209 *num_patches = 1;
210 }
211 }
212
213 sctx->last_num_patches = *num_patches;
214
215 output_patch0_offset = input_patch_size * *num_patches;
216 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
217
218 /* Compute userdata SGPRs. */
219 assert(((input_vertex_size / 4) & ~0xff) == 0);
220 assert(((output_vertex_size / 4) & ~0xff) == 0);
221 assert(((input_patch_size / 4) & ~0x1fff) == 0);
222 assert(((output_patch_size / 4) & ~0x1fff) == 0);
223 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
224 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
225 assert(num_tcs_input_cp <= 32);
226 assert(num_tcs_output_cp <= 32);
227
228 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
229 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
230 tcs_out_layout = (output_patch_size / 4) |
231 ((output_vertex_size / 4) << 13);
232 tcs_out_offsets = (output_patch0_offset / 16) |
233 ((perpatch_output_offset / 16) << 16);
234 offchip_layout = *num_patches |
235 (num_tcs_output_cp << 6) |
236 (pervertex_output_patch_size * *num_patches << 12);
237
238 /* Compute the LDS size. */
239 lds_size = output_patch0_offset + output_patch_size * *num_patches;
240
241 if (sctx->b.chip_class >= CIK) {
242 assert(lds_size <= 65536);
243 lds_size = align(lds_size, 512) / 512;
244 } else {
245 assert(lds_size <= 32768);
246 lds_size = align(lds_size, 256) / 256;
247 }
248
249 /* Set SI_SGPR_VS_STATE_BITS. */
250 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
251 C_VS_STATE_LS_OUT_VERTEX_SIZE;
252 sctx->current_vs_state |= tcs_in_layout;
253
254 if (sctx->b.chip_class >= GFX9) {
255 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
256 S_00B42C_LDS_SIZE(lds_size);
257
258 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
259
260 /* Set userdata SGPRs for merged LS-HS. */
261 radeon_set_sh_reg_seq(cs,
262 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
263 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
264 radeon_emit(cs, offchip_layout);
265 radeon_emit(cs, tcs_out_offsets);
266 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
267 } else {
268 unsigned ls_rsrc2 = ls_current->config.rsrc2;
269
270 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
271 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
272
273 /* Due to a hw bug, RSRC2_LS must be written twice with another
274 * LS register written in between. */
275 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
276 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
277 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
278 radeon_emit(cs, ls_current->config.rsrc1);
279 radeon_emit(cs, ls_rsrc2);
280
281 /* Set userdata SGPRs for TCS. */
282 radeon_set_sh_reg_seq(cs,
283 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
284 radeon_emit(cs, offchip_layout);
285 radeon_emit(cs, tcs_out_offsets);
286 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
287 radeon_emit(cs, tcs_in_layout);
288 }
289
290 /* Set userdata SGPRs for TES. */
291 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
292 radeon_emit(cs, offchip_layout);
293 radeon_emit(cs, r600_resource(sctx->tess_offchip_ring)->gpu_address >> 16);
294
295 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
296 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
297 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
298
299 if (sctx->b.chip_class >= CIK)
300 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
301 ls_hs_config);
302 else
303 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
304 ls_hs_config);
305 }
306
307 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
308 {
309 switch (info->mode) {
310 case PIPE_PRIM_PATCHES:
311 return info->count / info->vertices_per_patch;
312 case R600_PRIM_RECTANGLE_LIST:
313 return info->count / 3;
314 default:
315 return u_prims_for_vertices(info->mode, info->count);
316 }
317 }
318
319 static unsigned
320 si_get_init_multi_vgt_param(struct si_screen *sscreen,
321 union si_vgt_param_key *key)
322 {
323 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
324 unsigned max_primgroup_in_wave = 2;
325
326 /* SWITCH_ON_EOP(0) is always preferable. */
327 bool wd_switch_on_eop = false;
328 bool ia_switch_on_eop = false;
329 bool ia_switch_on_eoi = false;
330 bool partial_vs_wave = false;
331 bool partial_es_wave = false;
332
333 if (key->u.uses_tess) {
334 /* SWITCH_ON_EOI must be set if PrimID is used. */
335 if (key->u.tess_uses_prim_id)
336 ia_switch_on_eoi = true;
337
338 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
339 if ((sscreen->b.family == CHIP_TAHITI ||
340 sscreen->b.family == CHIP_PITCAIRN ||
341 sscreen->b.family == CHIP_BONAIRE) &&
342 key->u.uses_gs)
343 partial_vs_wave = true;
344
345 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
346 if (sscreen->has_distributed_tess) {
347 if (key->u.uses_gs) {
348 if (sscreen->b.chip_class <= VI)
349 partial_es_wave = true;
350
351 /* GPU hang workaround. */
352 if (sscreen->b.family == CHIP_TONGA ||
353 sscreen->b.family == CHIP_FIJI ||
354 sscreen->b.family == CHIP_POLARIS10 ||
355 sscreen->b.family == CHIP_POLARIS11 ||
356 sscreen->b.family == CHIP_POLARIS12)
357 partial_vs_wave = true;
358 } else {
359 partial_vs_wave = true;
360 }
361 }
362 }
363
364 /* This is a hardware requirement. */
365 if (key->u.line_stipple_enabled ||
366 (sscreen->b.debug_flags & DBG_SWITCH_ON_EOP)) {
367 ia_switch_on_eop = true;
368 wd_switch_on_eop = true;
369 }
370
371 if (sscreen->b.chip_class >= CIK) {
372 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
373 * 4 shader engines. Set 1 to pass the assertion below.
374 * The other cases are hardware requirements.
375 *
376 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
377 * for points, line strips, and tri strips.
378 */
379 if (sscreen->b.info.max_se < 4 ||
380 key->u.prim == PIPE_PRIM_POLYGON ||
381 key->u.prim == PIPE_PRIM_LINE_LOOP ||
382 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
383 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
384 (key->u.primitive_restart &&
385 (sscreen->b.family < CHIP_POLARIS10 ||
386 (key->u.prim != PIPE_PRIM_POINTS &&
387 key->u.prim != PIPE_PRIM_LINE_STRIP &&
388 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
389 key->u.count_from_stream_output)
390 wd_switch_on_eop = true;
391
392 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
393 * We don't know that for indirect drawing, so treat it as
394 * always problematic. */
395 if (sscreen->b.family == CHIP_HAWAII &&
396 key->u.uses_instancing)
397 wd_switch_on_eop = true;
398
399 /* Performance recommendation for 4 SE Gfx7-8 parts if
400 * instances are smaller than a primgroup.
401 * Assume indirect draws always use small instances.
402 * This is needed for good VS wave utilization.
403 */
404 if (sscreen->b.chip_class <= VI &&
405 sscreen->b.info.max_se == 4 &&
406 key->u.multi_instances_smaller_than_primgroup)
407 wd_switch_on_eop = true;
408
409 /* Required on CIK and later. */
410 if (sscreen->b.info.max_se > 2 && !wd_switch_on_eop)
411 ia_switch_on_eoi = true;
412
413 /* Required by Hawaii and, for some special cases, by VI. */
414 if (ia_switch_on_eoi &&
415 (sscreen->b.family == CHIP_HAWAII ||
416 (sscreen->b.chip_class == VI &&
417 (key->u.uses_gs || max_primgroup_in_wave != 2))))
418 partial_vs_wave = true;
419
420 /* Instancing bug on Bonaire. */
421 if (sscreen->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
422 key->u.uses_instancing)
423 partial_vs_wave = true;
424
425 /* If the WD switch is false, the IA switch must be false too. */
426 assert(wd_switch_on_eop || !ia_switch_on_eop);
427 }
428
429 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
430 if (sscreen->b.chip_class <= VI && ia_switch_on_eoi)
431 partial_es_wave = true;
432
433 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
434 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
435 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
436 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
437 S_028AA8_WD_SWITCH_ON_EOP(sscreen->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
438 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
439 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->b.chip_class == VI ?
440 max_primgroup_in_wave : 0) |
441 S_030960_EN_INST_OPT_BASIC(sscreen->b.chip_class >= GFX9) |
442 S_030960_EN_INST_OPT_ADV(sscreen->b.chip_class >= GFX9);
443 }
444
445 void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
446 {
447 for (int prim = 0; prim <= R600_PRIM_RECTANGLE_LIST; prim++)
448 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
449 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
450 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
451 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
452 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
453 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
454 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
455 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
456 union si_vgt_param_key key;
457
458 key.index = 0;
459 key.u.prim = prim;
460 key.u.uses_instancing = uses_instancing;
461 key.u.multi_instances_smaller_than_primgroup = multi_instances;
462 key.u.primitive_restart = primitive_restart;
463 key.u.count_from_stream_output = count_from_so;
464 key.u.line_stipple_enabled = line_stipple;
465 key.u.uses_tess = uses_tess;
466 key.u.tess_uses_prim_id = tess_uses_primid;
467 key.u.uses_gs = uses_gs;
468
469 sctx->ia_multi_vgt_param[key.index] =
470 si_get_init_multi_vgt_param(sctx->screen, &key);
471 }
472 }
473
474 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
475 const struct pipe_draw_info *info,
476 unsigned num_patches)
477 {
478 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
479 unsigned primgroup_size;
480 unsigned ia_multi_vgt_param;
481
482 if (sctx->tes_shader.cso) {
483 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
484 } else if (sctx->gs_shader.cso) {
485 primgroup_size = 64; /* recommended with a GS */
486 } else {
487 primgroup_size = 128; /* recommended without a GS and tess */
488 }
489
490 key.u.prim = info->mode;
491 key.u.uses_instancing = info->indirect || info->instance_count > 1;
492 key.u.multi_instances_smaller_than_primgroup =
493 info->indirect ||
494 (info->instance_count > 1 &&
495 (info->count_from_stream_output ||
496 si_num_prims_for_vertices(info) < primgroup_size));
497 key.u.primitive_restart = info->primitive_restart;
498 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
499
500 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
501 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
502
503 if (sctx->gs_shader.cso) {
504 /* GS requirement. */
505 if (sctx->b.chip_class <= VI &&
506 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
507 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
508
509 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
510 * The hw doc says all multi-SE chips are affected, but Vulkan
511 * only applies it to Hawaii. Do what Vulkan does.
512 */
513 if (sctx->b.family == CHIP_HAWAII &&
514 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
515 (info->indirect ||
516 (info->instance_count > 1 &&
517 (info->count_from_stream_output ||
518 si_num_prims_for_vertices(info) <= 1))))
519 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
520 }
521
522 return ia_multi_vgt_param;
523 }
524
525 /* rast_prim is the primitive type after GS. */
526 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
527 {
528 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
529 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
530 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
531
532 /* Skip this if not rendering lines. */
533 if (rast_prim != PIPE_PRIM_LINES &&
534 rast_prim != PIPE_PRIM_LINE_LOOP &&
535 rast_prim != PIPE_PRIM_LINE_STRIP &&
536 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
537 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
538 return;
539
540 if (rast_prim == sctx->last_rast_prim &&
541 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
542 return;
543
544 /* For lines, reset the stipple pattern at each primitive. Otherwise,
545 * reset the stipple pattern at each packet (line strips, line loops).
546 */
547 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
548 rs->pa_sc_line_stipple |
549 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
550
551 sctx->last_rast_prim = rast_prim;
552 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
553 }
554
555 static void si_emit_vs_state(struct si_context *sctx,
556 const struct pipe_draw_info *info)
557 {
558 sctx->current_vs_state &= C_VS_STATE_INDEXED;
559 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
560
561 if (sctx->current_vs_state != sctx->last_vs_state) {
562 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
563
564 radeon_set_sh_reg(cs,
565 sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX] +
566 SI_SGPR_VS_STATE_BITS * 4,
567 sctx->current_vs_state);
568
569 sctx->last_vs_state = sctx->current_vs_state;
570 }
571 }
572
573 static void si_emit_draw_registers(struct si_context *sctx,
574 const struct pipe_draw_info *info,
575 unsigned num_patches)
576 {
577 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
578 unsigned prim = si_conv_pipe_prim(info->mode);
579 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
580 unsigned ia_multi_vgt_param;
581
582 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
583
584 /* Draw state. */
585 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
586 if (sctx->b.chip_class >= GFX9)
587 radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
588 else if (sctx->b.chip_class >= CIK)
589 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
590 else
591 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
592
593 sctx->last_multi_vgt_param = ia_multi_vgt_param;
594 }
595 if (prim != sctx->last_prim) {
596 if (sctx->b.chip_class >= CIK)
597 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
598 else
599 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
600
601 sctx->last_prim = prim;
602 }
603
604 if (gs_out_prim != sctx->last_gs_out_prim) {
605 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
606 sctx->last_gs_out_prim = gs_out_prim;
607 }
608
609 /* Primitive restart. */
610 if (info->primitive_restart != sctx->last_primitive_restart_en) {
611 if (sctx->b.chip_class >= GFX9)
612 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
613 info->primitive_restart);
614 else
615 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
616 info->primitive_restart);
617
618 sctx->last_primitive_restart_en = info->primitive_restart;
619
620 }
621 if (info->primitive_restart &&
622 (info->restart_index != sctx->last_restart_index ||
623 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
624 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
625 info->restart_index);
626 sctx->last_restart_index = info->restart_index;
627 }
628 }
629
630 static void si_emit_draw_packets(struct si_context *sctx,
631 const struct pipe_draw_info *info,
632 struct pipe_resource *indexbuf,
633 unsigned index_size,
634 unsigned index_offset)
635 {
636 struct pipe_draw_indirect_info *indirect = info->indirect;
637 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
638 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
639 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
640 uint32_t index_max_size = 0;
641 uint64_t index_va = 0;
642
643 if (info->count_from_stream_output) {
644 struct r600_so_target *t =
645 (struct r600_so_target*)info->count_from_stream_output;
646 uint64_t va = t->buf_filled_size->gpu_address +
647 t->buf_filled_size_offset;
648
649 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
650 t->stride_in_dw);
651
652 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
653 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
654 COPY_DATA_DST_SEL(COPY_DATA_REG) |
655 COPY_DATA_WR_CONFIRM);
656 radeon_emit(cs, va); /* src address lo */
657 radeon_emit(cs, va >> 32); /* src address hi */
658 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
659 radeon_emit(cs, 0); /* unused */
660
661 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
662 t->buf_filled_size, RADEON_USAGE_READ,
663 RADEON_PRIO_SO_FILLED_SIZE);
664 }
665
666 /* draw packet */
667 if (index_size) {
668 if (index_size != sctx->last_index_size) {
669 unsigned index_type;
670
671 /* index type */
672 switch (index_size) {
673 case 1:
674 index_type = V_028A7C_VGT_INDEX_8;
675 break;
676 case 2:
677 index_type = V_028A7C_VGT_INDEX_16 |
678 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
679 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
680 break;
681 case 4:
682 index_type = V_028A7C_VGT_INDEX_32 |
683 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
684 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
685 break;
686 default:
687 assert(!"unreachable");
688 return;
689 }
690
691 if (sctx->b.chip_class >= GFX9) {
692 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
693 2, index_type);
694 } else {
695 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
696 radeon_emit(cs, index_type);
697 }
698
699 sctx->last_index_size = index_size;
700 }
701
702 index_max_size = (indexbuf->width0 - index_offset) /
703 index_size;
704 index_va = r600_resource(indexbuf)->gpu_address + index_offset;
705
706 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
707 (struct r600_resource *)indexbuf,
708 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
709 } else {
710 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
711 * so the state must be re-emitted before the next indexed draw.
712 */
713 if (sctx->b.chip_class >= CIK)
714 sctx->last_index_size = -1;
715 }
716
717 if (indirect) {
718 uint64_t indirect_va = r600_resource(indirect->buffer)->gpu_address;
719
720 assert(indirect_va % 8 == 0);
721
722 si_invalidate_draw_sh_constants(sctx);
723
724 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
725 radeon_emit(cs, 1);
726 radeon_emit(cs, indirect_va);
727 radeon_emit(cs, indirect_va >> 32);
728
729 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
730 (struct r600_resource *)indirect->buffer,
731 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
732
733 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
734 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
735
736 assert(indirect->offset % 4 == 0);
737
738 if (index_size) {
739 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
740 radeon_emit(cs, index_va);
741 radeon_emit(cs, index_va >> 32);
742
743 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
744 radeon_emit(cs, index_max_size);
745 }
746
747 if (!sctx->screen->has_draw_indirect_multi) {
748 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
749 : PKT3_DRAW_INDIRECT,
750 3, render_cond_bit));
751 radeon_emit(cs, indirect->offset);
752 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
753 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
754 radeon_emit(cs, di_src_sel);
755 } else {
756 uint64_t count_va = 0;
757
758 if (indirect->indirect_draw_count) {
759 struct r600_resource *params_buf =
760 (struct r600_resource *)indirect->indirect_draw_count;
761
762 radeon_add_to_buffer_list(
763 &sctx->b, &sctx->b.gfx, params_buf,
764 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
765
766 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
767 }
768
769 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
770 PKT3_DRAW_INDIRECT_MULTI,
771 8, render_cond_bit));
772 radeon_emit(cs, indirect->offset);
773 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
774 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
775 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
776 S_2C3_DRAW_INDEX_ENABLE(1) |
777 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
778 radeon_emit(cs, indirect->draw_count);
779 radeon_emit(cs, count_va);
780 radeon_emit(cs, count_va >> 32);
781 radeon_emit(cs, indirect->stride);
782 radeon_emit(cs, di_src_sel);
783 }
784 } else {
785 int base_vertex;
786
787 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
788 radeon_emit(cs, info->instance_count);
789
790 /* Base vertex and start instance. */
791 base_vertex = index_size ? info->index_bias : info->start;
792
793 if (base_vertex != sctx->last_base_vertex ||
794 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
795 info->start_instance != sctx->last_start_instance ||
796 info->drawid != sctx->last_drawid ||
797 sh_base_reg != sctx->last_sh_base_reg) {
798 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
799 radeon_emit(cs, base_vertex);
800 radeon_emit(cs, info->start_instance);
801 radeon_emit(cs, info->drawid);
802
803 sctx->last_base_vertex = base_vertex;
804 sctx->last_start_instance = info->start_instance;
805 sctx->last_drawid = info->drawid;
806 sctx->last_sh_base_reg = sh_base_reg;
807 }
808
809 if (index_size) {
810 index_va += info->start * index_size;
811
812 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
813 radeon_emit(cs, index_max_size);
814 radeon_emit(cs, index_va);
815 radeon_emit(cs, index_va >> 32);
816 radeon_emit(cs, info->count);
817 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
818 } else {
819 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
820 radeon_emit(cs, info->count);
821 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
822 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
823 }
824 }
825 }
826
827 static void si_emit_surface_sync(struct r600_common_context *rctx,
828 unsigned cp_coher_cntl)
829 {
830 struct radeon_winsys_cs *cs = rctx->gfx.cs;
831
832 if (rctx->chip_class >= GFX9) {
833 /* Flush caches and wait for the caches to assert idle. */
834 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
835 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
836 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
837 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
838 radeon_emit(cs, 0); /* CP_COHER_BASE */
839 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
840 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
841 } else {
842 /* ACQUIRE_MEM is only required on a compute ring. */
843 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
844 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
845 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
846 radeon_emit(cs, 0); /* CP_COHER_BASE */
847 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
848 }
849 }
850
851 void si_emit_cache_flush(struct si_context *sctx)
852 {
853 struct r600_common_context *rctx = &sctx->b;
854 struct radeon_winsys_cs *cs = rctx->gfx.cs;
855 uint32_t cp_coher_cntl = 0;
856 uint32_t flush_cb_db = rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
857 SI_CONTEXT_FLUSH_AND_INV_DB);
858
859 if (rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
860 SI_CONTEXT_FLUSH_AND_INV_DB))
861 sctx->b.num_fb_cache_flushes++;
862
863 /* SI has a bug that it always flushes ICACHE and KCACHE if either
864 * bit is set. An alternative way is to write SQC_CACHES, but that
865 * doesn't seem to work reliably. Since the bug doesn't affect
866 * correctness (it only does more work than necessary) and
867 * the performance impact is likely negligible, there is no plan
868 * to add a workaround for it.
869 */
870
871 if (rctx->flags & SI_CONTEXT_INV_ICACHE)
872 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
873 if (rctx->flags & SI_CONTEXT_INV_SMEM_L1)
874 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
875
876 if (rctx->chip_class <= VI) {
877 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
878 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
879 S_0085F0_CB0_DEST_BASE_ENA(1) |
880 S_0085F0_CB1_DEST_BASE_ENA(1) |
881 S_0085F0_CB2_DEST_BASE_ENA(1) |
882 S_0085F0_CB3_DEST_BASE_ENA(1) |
883 S_0085F0_CB4_DEST_BASE_ENA(1) |
884 S_0085F0_CB5_DEST_BASE_ENA(1) |
885 S_0085F0_CB6_DEST_BASE_ENA(1) |
886 S_0085F0_CB7_DEST_BASE_ENA(1);
887
888 /* Necessary for DCC */
889 if (rctx->chip_class == VI)
890 r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
891 0, 0, NULL, 0, 0, 0);
892 }
893 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB)
894 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
895 S_0085F0_DB_DEST_BASE_ENA(1);
896 }
897
898 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
899 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
900 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
901 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
902 }
903 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
904 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
905 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
906 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
907 }
908
909 /* Wait for shader engines to go idle.
910 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
911 * for everything including CB/DB cache flushes.
912 */
913 if (!flush_cb_db) {
914 if (rctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
915 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
916 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
917 /* Only count explicit shader flushes, not implicit ones
918 * done by SURFACE_SYNC.
919 */
920 rctx->num_vs_flushes++;
921 rctx->num_ps_flushes++;
922 } else if (rctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
923 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
924 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
925 rctx->num_vs_flushes++;
926 }
927 }
928
929 if (rctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
930 sctx->compute_is_busy) {
931 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
932 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
933 rctx->num_cs_flushes++;
934 sctx->compute_is_busy = false;
935 }
936
937 /* VGT state synchronization. */
938 if (rctx->flags & SI_CONTEXT_VGT_FLUSH) {
939 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
940 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
941 }
942 if (rctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
943 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
944 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
945 }
946
947 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
948 * wait for idle on GFX9. We have to use a TS event.
949 */
950 if (sctx->b.chip_class >= GFX9 && flush_cb_db) {
951 struct r600_resource *rbuf = NULL;
952 uint64_t va;
953 unsigned offset = 0, tc_flags, cb_db_event;
954
955 /* Set the CB/DB flush event. */
956 switch (flush_cb_db) {
957 case SI_CONTEXT_FLUSH_AND_INV_CB:
958 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
959 break;
960 case SI_CONTEXT_FLUSH_AND_INV_DB:
961 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
962 break;
963 default:
964 /* both CB & DB */
965 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
966 }
967
968 /* TC | TC_WB = invalidate L2 data
969 * TC_MD | TC_WB = invalidate L2 metadata
970 * TC | TC_WB | TC_MD = invalidate L2 data & metadata
971 *
972 * The metadata cache must always be invalidated for coherency
973 * between CB/DB and shaders. (metadata = HTILE, CMASK, DCC)
974 *
975 * TC must be invalidated on GFX9 only if the CB/DB surface is
976 * not pipe-aligned. If the surface is RB-aligned, it might not
977 * strictly be pipe-aligned since RB alignment takes precendence.
978 */
979 tc_flags = EVENT_TC_WB_ACTION_ENA |
980 EVENT_TC_MD_ACTION_ENA;
981
982 /* Ideally flush TC together with CB/DB. */
983 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
984 tc_flags |= EVENT_TC_ACTION_ENA |
985 EVENT_TCL1_ACTION_ENA;
986
987 /* Clear the flags. */
988 rctx->flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
989 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
990 SI_CONTEXT_INV_VMEM_L1);
991 }
992
993 /* Allocate memory for the fence. */
994 u_suballocator_alloc(rctx->allocator_zeroed_memory, 4, 4,
995 &offset, (struct pipe_resource**)&rbuf);
996 va = rbuf->gpu_address + offset;
997
998 r600_gfx_write_event_eop(rctx, cb_db_event, tc_flags, 1,
999 rbuf, va, 0, 1);
1000 r600_gfx_wait_fence(rctx, va, 1, 0xffffffff);
1001 }
1002
1003 /* Make sure ME is idle (it executes most packets) before continuing.
1004 * This prevents read-after-write hazards between PFP and ME.
1005 */
1006 if (cp_coher_cntl ||
1007 (rctx->flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1008 SI_CONTEXT_INV_VMEM_L1 |
1009 SI_CONTEXT_INV_GLOBAL_L2 |
1010 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1011 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1012 radeon_emit(cs, 0);
1013 }
1014
1015 /* SI-CI-VI only:
1016 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1017 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1018 *
1019 * cp_coher_cntl should contain all necessary flags except TC flags
1020 * at this point.
1021 *
1022 * SI-CIK don't support L2 write-back.
1023 */
1024 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2 ||
1025 (rctx->chip_class <= CIK &&
1026 (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1027 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
1028 * WB must be set on VI+ when TC_ACTION is set.
1029 */
1030 si_emit_surface_sync(rctx, cp_coher_cntl |
1031 S_0085F0_TC_ACTION_ENA(1) |
1032 S_0085F0_TCL1_ACTION_ENA(1) |
1033 S_0301F0_TC_WB_ACTION_ENA(rctx->chip_class >= VI));
1034 cp_coher_cntl = 0;
1035 sctx->b.num_L2_invalidates++;
1036 } else {
1037 /* L1 invalidation and L2 writeback must be done separately,
1038 * because both operations can't be done together.
1039 */
1040 if (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
1041 /* WB = write-back
1042 * NC = apply to non-coherent MTYPEs
1043 * (i.e. MTYPE <= 1, which is what we use everywhere)
1044 *
1045 * WB doesn't work without NC.
1046 */
1047 si_emit_surface_sync(rctx, cp_coher_cntl |
1048 S_0301F0_TC_WB_ACTION_ENA(1) |
1049 S_0301F0_TC_NC_ACTION_ENA(1));
1050 cp_coher_cntl = 0;
1051 sctx->b.num_L2_writebacks++;
1052 }
1053 if (rctx->flags & SI_CONTEXT_INV_VMEM_L1) {
1054 /* Invalidate per-CU VMEM L1. */
1055 si_emit_surface_sync(rctx, cp_coher_cntl |
1056 S_0085F0_TCL1_ACTION_ENA(1));
1057 cp_coher_cntl = 0;
1058 }
1059 }
1060
1061 /* If TC flushes haven't cleared this... */
1062 if (cp_coher_cntl)
1063 si_emit_surface_sync(rctx, cp_coher_cntl);
1064
1065 if (rctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
1066 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1067 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1068 EVENT_INDEX(0));
1069 } else if (rctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
1070 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1071 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1072 EVENT_INDEX(0));
1073 }
1074
1075 rctx->flags = 0;
1076 }
1077
1078 static void si_get_draw_start_count(struct si_context *sctx,
1079 const struct pipe_draw_info *info,
1080 unsigned *start, unsigned *count)
1081 {
1082 struct pipe_draw_indirect_info *indirect = info->indirect;
1083
1084 if (indirect) {
1085 unsigned indirect_count;
1086 struct pipe_transfer *transfer;
1087 unsigned begin, end;
1088 unsigned map_size;
1089 unsigned *data;
1090
1091 if (indirect->indirect_draw_count) {
1092 data = pipe_buffer_map_range(&sctx->b.b,
1093 indirect->indirect_draw_count,
1094 indirect->indirect_draw_count_offset,
1095 sizeof(unsigned),
1096 PIPE_TRANSFER_READ, &transfer);
1097
1098 indirect_count = *data;
1099
1100 pipe_buffer_unmap(&sctx->b.b, transfer);
1101 } else {
1102 indirect_count = indirect->draw_count;
1103 }
1104
1105 if (!indirect_count) {
1106 *start = *count = 0;
1107 return;
1108 }
1109
1110 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1111 data = pipe_buffer_map_range(&sctx->b.b, indirect->buffer,
1112 indirect->offset, map_size,
1113 PIPE_TRANSFER_READ, &transfer);
1114
1115 begin = UINT_MAX;
1116 end = 0;
1117
1118 for (unsigned i = 0; i < indirect_count; ++i) {
1119 unsigned count = data[0];
1120 unsigned start = data[2];
1121
1122 if (count > 0) {
1123 begin = MIN2(begin, start);
1124 end = MAX2(end, start + count);
1125 }
1126
1127 data += indirect->stride / sizeof(unsigned);
1128 }
1129
1130 pipe_buffer_unmap(&sctx->b.b, transfer);
1131
1132 if (begin < end) {
1133 *start = begin;
1134 *count = end - begin;
1135 } else {
1136 *start = *count = 0;
1137 }
1138 } else {
1139 *start = info->start;
1140 *count = info->count;
1141 }
1142 }
1143
1144 void si_ce_pre_draw_synchronization(struct si_context *sctx)
1145 {
1146 if (sctx->ce_need_synchronization) {
1147 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
1148 radeon_emit(sctx->ce_ib, 1);
1149
1150 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
1151 radeon_emit(sctx->b.gfx.cs, 1);
1152 }
1153 }
1154
1155 void si_ce_post_draw_synchronization(struct si_context *sctx)
1156 {
1157 if (sctx->ce_need_synchronization) {
1158 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
1159 radeon_emit(sctx->b.gfx.cs, 0);
1160
1161 sctx->ce_need_synchronization = false;
1162 }
1163 }
1164
1165 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1166 {
1167 struct si_context *sctx = (struct si_context *)ctx;
1168 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1169 struct pipe_resource *indexbuf = info->index.resource;
1170 unsigned mask, dirty_tex_counter;
1171 enum pipe_prim_type rast_prim;
1172 unsigned num_patches = 0;
1173 unsigned index_size = info->index_size;
1174 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1175
1176 if (likely(!info->indirect)) {
1177 /* SI-CI treat instance_count==0 as instance_count==1. There is
1178 * no workaround for indirect draws, but we can at least skip
1179 * direct draws.
1180 */
1181 if (unlikely(!info->instance_count))
1182 return;
1183
1184 /* Handle count == 0. */
1185 if (unlikely(!info->count &&
1186 (index_size || !info->count_from_stream_output)))
1187 return;
1188 }
1189
1190 if (unlikely(!sctx->vs_shader.cso)) {
1191 assert(0);
1192 return;
1193 }
1194 if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
1195 assert(0);
1196 return;
1197 }
1198 if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
1199 assert(0);
1200 return;
1201 }
1202
1203 /* Recompute and re-emit the texture resource states if needed. */
1204 dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_counter);
1205 if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_counter)) {
1206 sctx->b.last_dirty_tex_counter = dirty_tex_counter;
1207 sctx->framebuffer.dirty_cbufs |=
1208 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1209 sctx->framebuffer.dirty_zsbuf = true;
1210 sctx->framebuffer.do_update_surf_dirtiness = true;
1211 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
1212 si_update_all_texture_descriptors(sctx);
1213 }
1214
1215 si_decompress_graphics_textures(sctx);
1216
1217 /* Set the rasterization primitive type.
1218 *
1219 * This must be done after si_decompress_textures, which can call
1220 * draw_vbo recursively, and before si_update_shaders, which uses
1221 * current_rast_prim for this draw_vbo call. */
1222 if (sctx->gs_shader.cso)
1223 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1224 else if (sctx->tes_shader.cso)
1225 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1226 else
1227 rast_prim = info->mode;
1228
1229 if (rast_prim != sctx->current_rast_prim) {
1230 sctx->current_rast_prim = rast_prim;
1231 sctx->do_update_shaders = true;
1232 }
1233
1234 if (sctx->gs_shader.cso) {
1235 /* Determine whether the GS triangle strip adjacency fix should
1236 * be applied. Rotate every other triangle if
1237 * - triangle strips with adjacency are fed to the GS and
1238 * - primitive restart is disabled (the rotation doesn't help
1239 * when the restart occurs after an odd number of triangles).
1240 */
1241 bool gs_tri_strip_adj_fix =
1242 !sctx->tes_shader.cso &&
1243 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1244 !info->primitive_restart;
1245
1246 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1247 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1248 sctx->do_update_shaders = true;
1249 }
1250 }
1251
1252 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1253 return;
1254
1255 if (!si_upload_graphics_shader_descriptors(sctx))
1256 return;
1257
1258 if (index_size) {
1259 /* Translate or upload, if needed. */
1260 /* 8-bit indices are supported on VI. */
1261 if (sctx->b.chip_class <= CIK && index_size == 1) {
1262 unsigned start, count, start_offset, size, offset;
1263 void *ptr;
1264
1265 si_get_draw_start_count(sctx, info, &start, &count);
1266 start_offset = start * 2;
1267 size = count * 2;
1268
1269 indexbuf = NULL;
1270 u_upload_alloc(ctx->stream_uploader, start_offset,
1271 size,
1272 si_optimal_tcc_alignment(sctx, size),
1273 &offset, &indexbuf, &ptr);
1274 if (!indexbuf)
1275 return;
1276
1277 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, info, 0, 0,
1278 index_offset + start,
1279 count, ptr);
1280
1281 /* info->start will be added by the drawing code */
1282 index_offset = offset - start_offset;
1283 index_size = 2;
1284 } else if (info->has_user_indices) {
1285 unsigned start_offset;
1286
1287 assert(!info->indirect);
1288 start_offset = info->start * index_size;
1289
1290 indexbuf = NULL;
1291 u_upload_data(ctx->stream_uploader, start_offset,
1292 info->count * index_size,
1293 sctx->screen->b.info.tcc_cache_line_size,
1294 (char*)info->index.user + start_offset,
1295 &index_offset, &indexbuf);
1296 if (!indexbuf)
1297 return;
1298
1299 /* info->start will be added by the drawing code */
1300 index_offset -= start_offset;
1301 } else if (sctx->b.chip_class <= CIK &&
1302 r600_resource(indexbuf)->TC_L2_dirty) {
1303 /* VI reads index buffers through TC L2, so it doesn't
1304 * need this. */
1305 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1306 r600_resource(indexbuf)->TC_L2_dirty = false;
1307 }
1308 }
1309
1310 if (info->indirect) {
1311 struct pipe_draw_indirect_info *indirect = info->indirect;
1312
1313 /* Add the buffer size for memory checking in need_cs_space. */
1314 r600_context_add_resource_size(ctx, indirect->buffer);
1315
1316 if (r600_resource(indirect->buffer)->TC_L2_dirty) {
1317 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1318 r600_resource(indirect->buffer)->TC_L2_dirty = false;
1319 }
1320
1321 if (indirect->indirect_draw_count &&
1322 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1323 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1324 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1325 }
1326 }
1327
1328 si_need_cs_space(sctx);
1329
1330 /* Since we've called r600_context_add_resource_size for vertex buffers,
1331 * this must be called after si_need_cs_space, because we must let
1332 * need_cs_space flush before we add buffers to the buffer list.
1333 */
1334 if (!si_upload_vertex_buffer_descriptors(sctx))
1335 return;
1336
1337 /* GFX9 scissor bug workaround. There is also a more efficient but
1338 * more involved alternative workaround. */
1339 if (sctx->b.chip_class == GFX9 &&
1340 si_is_atom_dirty(sctx, &sctx->b.scissors.atom))
1341 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
1342
1343 /* Flush caches before the first state atom, which does L2 prefetches. */
1344 if (sctx->b.flags)
1345 si_emit_cache_flush(sctx);
1346
1347 /* Emit state atoms. */
1348 mask = sctx->dirty_atoms;
1349 while (mask) {
1350 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
1351
1352 atom->emit(&sctx->b, atom);
1353 }
1354 sctx->dirty_atoms = 0;
1355
1356 /* Emit states. */
1357 mask = sctx->dirty_states;
1358 while (mask) {
1359 unsigned i = u_bit_scan(&mask);
1360 struct si_pm4_state *state = sctx->queued.array[i];
1361
1362 if (!state || sctx->emitted.array[i] == state)
1363 continue;
1364
1365 si_pm4_emit(sctx, state);
1366 sctx->emitted.array[i] = state;
1367 }
1368 sctx->dirty_states = 0;
1369
1370 si_emit_rasterizer_prim_state(sctx);
1371 if (sctx->tes_shader.cso)
1372 si_emit_derived_tess_state(sctx, info, &num_patches);
1373 si_emit_vs_state(sctx, info);
1374 si_emit_draw_registers(sctx, info, num_patches);
1375
1376 si_ce_pre_draw_synchronization(sctx);
1377 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1378 si_ce_post_draw_synchronization(sctx);
1379
1380 if (sctx->trace_buf)
1381 si_trace_emit(sctx);
1382
1383 /* Workaround for a VGT hang when streamout is enabled.
1384 * It must be done after drawing. */
1385 if ((sctx->b.family == CHIP_HAWAII ||
1386 sctx->b.family == CHIP_TONGA ||
1387 sctx->b.family == CHIP_FIJI) &&
1388 r600_get_strmout_en(&sctx->b)) {
1389 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1390 }
1391
1392 if (sctx->framebuffer.do_update_surf_dirtiness) {
1393 /* Set the depth buffer as dirty. */
1394 if (sctx->framebuffer.state.zsbuf) {
1395 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1396 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1397
1398 if (!rtex->tc_compatible_htile)
1399 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1400
1401 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1402 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
1403 }
1404 if (sctx->framebuffer.compressed_cb_mask) {
1405 struct pipe_surface *surf;
1406 struct r600_texture *rtex;
1407 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1408
1409 do {
1410 unsigned i = u_bit_scan(&mask);
1411 surf = sctx->framebuffer.state.cbufs[i];
1412 rtex = (struct r600_texture*)surf->texture;
1413
1414 if (rtex->fmask.size)
1415 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1416 if (rtex->dcc_gather_statistics)
1417 rtex->separate_dcc_dirty = true;
1418 } while (mask);
1419 }
1420 sctx->framebuffer.do_update_surf_dirtiness = false;
1421 }
1422
1423 sctx->b.num_draw_calls++;
1424 if (info->primitive_restart)
1425 sctx->b.num_prim_restart_calls++;
1426 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1427 sctx->b.num_spill_draw_calls++;
1428 if (index_size && indexbuf != info->index.resource)
1429 pipe_resource_reference(&indexbuf, NULL);
1430 }
1431
1432 void si_trace_emit(struct si_context *sctx)
1433 {
1434 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1435
1436 sctx->trace_id++;
1437 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
1438 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
1439 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1440 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1441 S_370_WR_CONFIRM(1) |
1442 S_370_ENGINE_SEL(V_370_ME));
1443 radeon_emit(cs, sctx->trace_buf->gpu_address);
1444 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
1445 radeon_emit(cs, sctx->trace_id);
1446 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1447 radeon_emit(cs, AC_ENCODE_TRACE_POINT(sctx->trace_id));
1448 }