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radeonsi: simplify dereferences in si_update_spi_map
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "radeon/r600_cs.h"
30 #include "sid.h"
31
32 #include "util/u_format.h"
33 #include "util/u_index_modify.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36 #include "util/u_upload_mgr.h"
37
38 /*
39 * Shaders
40 */
41
42 static void si_shader_es(struct pipe_context *ctx, struct si_shader *shader)
43 {
44 struct si_context *sctx = (struct si_context *)ctx;
45 struct si_pm4_state *pm4;
46 unsigned num_sgprs, num_user_sgprs;
47 unsigned vgpr_comp_cnt;
48 uint64_t va;
49
50 si_pm4_delete_state(sctx, es, shader->pm4);
51 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
52
53 if (pm4 == NULL)
54 return;
55
56 va = shader->bo->gpu_address;
57 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
58
59 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
60
61 num_user_sgprs = SI_VS_NUM_USER_SGPR;
62 num_sgprs = shader->num_sgprs;
63 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
64 if ((num_user_sgprs + 1) > num_sgprs) {
65 /* Last 2 reserved SGPRs are used for VCC */
66 num_sgprs = num_user_sgprs + 1 + 2;
67 }
68 assert(num_sgprs <= 104);
69
70 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
71 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
72 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
73 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
74 S_00B328_SGPRS((num_sgprs - 1) / 8) |
75 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt));
76 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
77 S_00B32C_USER_SGPR(num_user_sgprs));
78 }
79
80 static void si_shader_gs(struct pipe_context *ctx, struct si_shader *shader)
81 {
82 struct si_context *sctx = (struct si_context *)ctx;
83 unsigned gs_vert_itemsize = shader->noutput * (16 >> 2);
84 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
85 unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
86 unsigned cut_mode;
87 struct si_pm4_state *pm4;
88 unsigned num_sgprs, num_user_sgprs;
89 uint64_t va;
90
91 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
92 assert(gsvs_itemsize < (1 << 15));
93
94 si_pm4_delete_state(sctx, gs, shader->pm4);
95 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
96
97 if (pm4 == NULL)
98 return;
99
100 if (gs_max_vert_out <= 128) {
101 cut_mode = V_028A40_GS_CUT_128;
102 } else if (gs_max_vert_out <= 256) {
103 cut_mode = V_028A40_GS_CUT_256;
104 } else if (gs_max_vert_out <= 512) {
105 cut_mode = V_028A40_GS_CUT_512;
106 } else {
107 assert(gs_max_vert_out <= 1024);
108 cut_mode = V_028A40_GS_CUT_1024;
109 }
110
111 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
112 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
113 S_028A40_CUT_MODE(cut_mode)|
114 S_028A40_ES_WRITE_OPTIMIZE(1) |
115 S_028A40_GS_WRITE_OPTIMIZE(1));
116
117 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
118 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize);
119 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize);
120
121 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
122 util_bitcount64(shader->selector->gs_used_inputs) * (16 >> 2));
123 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
124
125 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
126
127 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
128
129 va = shader->bo->gpu_address;
130 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
131 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
132 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
133
134 num_user_sgprs = SI_GS_NUM_USER_SGPR;
135 num_sgprs = shader->num_sgprs;
136 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
137 if ((num_user_sgprs + 2) > num_sgprs) {
138 /* Last 2 reserved SGPRs are used for VCC */
139 num_sgprs = num_user_sgprs + 2 + 2;
140 }
141 assert(num_sgprs <= 104);
142
143 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
144 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
145 S_00B228_SGPRS((num_sgprs - 1) / 8));
146 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
147 S_00B22C_USER_SGPR(num_user_sgprs));
148 }
149
150 static void si_shader_vs(struct pipe_context *ctx, struct si_shader *shader)
151 {
152 struct si_context *sctx = (struct si_context *)ctx;
153 struct tgsi_shader_info *info = &shader->selector->info;
154 struct si_pm4_state *pm4;
155 unsigned num_sgprs, num_user_sgprs;
156 unsigned nparams, i, vgpr_comp_cnt;
157 uint64_t va;
158
159 si_pm4_delete_state(sctx, vs, shader->pm4);
160 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
161
162 if (pm4 == NULL)
163 return;
164
165 va = shader->bo->gpu_address;
166 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
167
168 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
169
170 if (shader->is_gs_copy_shader)
171 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
172 else
173 num_user_sgprs = SI_VS_NUM_USER_SGPR;
174
175 num_sgprs = shader->num_sgprs;
176 if (num_user_sgprs > num_sgprs) {
177 /* Last 2 reserved SGPRs are used for VCC */
178 num_sgprs = num_user_sgprs + 2;
179 }
180 assert(num_sgprs <= 104);
181
182 /* Certain attributes (position, psize, etc.) don't count as params.
183 * VS is required to export at least one param and r600_shader_from_tgsi()
184 * takes care of adding a dummy export.
185 */
186 for (nparams = 0, i = 0 ; i < info->num_outputs; i++) {
187 switch (info->output_semantic_name[i]) {
188 case TGSI_SEMANTIC_CLIPVERTEX:
189 case TGSI_SEMANTIC_POSITION:
190 case TGSI_SEMANTIC_PSIZE:
191 break;
192 default:
193 nparams++;
194 }
195 }
196 if (nparams < 1)
197 nparams = 1;
198
199 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
200 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
201
202 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
203 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
204 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
205 V_02870C_SPI_SHADER_4COMP :
206 V_02870C_SPI_SHADER_NONE) |
207 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
208 V_02870C_SPI_SHADER_4COMP :
209 V_02870C_SPI_SHADER_NONE) |
210 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
211 V_02870C_SPI_SHADER_4COMP :
212 V_02870C_SPI_SHADER_NONE));
213
214 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
215 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
216 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
217 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
218 S_00B128_SGPRS((num_sgprs - 1) / 8) |
219 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
220 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
221 S_00B12C_USER_SGPR(num_user_sgprs) |
222 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
223 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
224 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
225 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
226 S_00B12C_SO_EN(!!shader->selector->so.num_outputs));
227 }
228
229 static void si_shader_ps(struct pipe_context *ctx, struct si_shader *shader)
230 {
231 struct si_context *sctx = (struct si_context *)ctx;
232 struct tgsi_shader_info *info = &shader->selector->info;
233 struct si_pm4_state *pm4;
234 unsigned i, spi_ps_in_control;
235 unsigned num_sgprs, num_user_sgprs;
236 unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
237 uint64_t va;
238
239 si_pm4_delete_state(sctx, ps, shader->pm4);
240 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
241
242 if (pm4 == NULL)
243 return;
244
245 for (i = 0; i < info->num_inputs; i++) {
246 switch (info->input_semantic_name[i]) {
247 case TGSI_SEMANTIC_POSITION:
248 if (info->input_interpolate_loc[i] ==
249 TGSI_INTERPOLATE_LOC_CENTROID) {
250 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
251 * Possible vaules:
252 * 0 -> Position = pixel center (default)
253 * 1 -> Position = pixel centroid
254 * 2 -> Position = iterated sample number XXX:
255 * What does this mean?
256 */
257 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
258 }
259 /* Fall through */
260 case TGSI_SEMANTIC_FACE:
261 continue;
262 }
263 }
264
265 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
266 S_0286D8_BC_OPTIMIZE_DISABLE(1);
267
268 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
269 spi_ps_input_ena = shader->spi_ps_input_ena;
270 /* we need to enable at least one of them, otherwise we hang the GPU */
271 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
272 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
273 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
274 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
275 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
276 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
277 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
278 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
279
280 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
281 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
282 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
283
284 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
285 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
286 shader->spi_shader_col_format);
287 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
288
289 va = shader->bo->gpu_address;
290 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
291 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
292 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
293
294 num_user_sgprs = SI_PS_NUM_USER_SGPR;
295 num_sgprs = shader->num_sgprs;
296 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
297 if ((num_user_sgprs + 1) > num_sgprs) {
298 /* Last 2 reserved SGPRs are used for VCC */
299 num_sgprs = num_user_sgprs + 1 + 2;
300 }
301 assert(num_sgprs <= 104);
302
303 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
304 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
305 S_00B028_SGPRS((num_sgprs - 1) / 8));
306 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
307 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
308 S_00B02C_USER_SGPR(num_user_sgprs));
309 }
310
311 /*
312 * Drawing
313 */
314
315 static unsigned si_conv_pipe_prim(unsigned pprim)
316 {
317 static const unsigned prim_conv[] = {
318 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
319 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
320 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
321 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
322 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
323 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
324 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
325 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
326 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
327 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
328 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
329 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
330 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
331 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
332 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
333 };
334 unsigned result = prim_conv[pprim];
335 if (result == ~0) {
336 R600_ERR("unsupported primitive type %d\n", pprim);
337 }
338 return result;
339 }
340
341 static unsigned si_conv_prim_to_gs_out(unsigned mode)
342 {
343 static const int prim_conv[] = {
344 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
345 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
346 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
347 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
348 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
349 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
350 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
351 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
352 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
353 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
354 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
355 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
356 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
357 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
358 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
359 };
360 assert(mode < Elements(prim_conv));
361
362 return prim_conv[mode];
363 }
364
365 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
366 const struct pipe_draw_info *info)
367 {
368 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
369 unsigned prim = info->mode;
370 unsigned primgroup_size = 128; /* recommended without a GS */
371
372 /* SWITCH_ON_EOP(0) is always preferable. */
373 bool wd_switch_on_eop = false;
374 bool ia_switch_on_eop = false;
375 bool partial_vs_wave = false;
376
377 if (sctx->gs_shader)
378 primgroup_size = 64; /* recommended with a GS */
379
380 /* This is a hardware requirement. */
381 if ((rs && rs->line_stipple_enable) ||
382 (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
383 ia_switch_on_eop = true;
384 wd_switch_on_eop = true;
385 }
386
387 if (sctx->b.streamout.streamout_enabled ||
388 sctx->b.streamout.prims_gen_query_enabled)
389 partial_vs_wave = true;
390
391 if (sctx->b.chip_class >= CIK) {
392 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
393 * 4 shader engines. Set 1 to pass the assertion below.
394 * The other cases are hardware requirements. */
395 if (sctx->b.screen->info.max_se < 4 ||
396 prim == PIPE_PRIM_POLYGON ||
397 prim == PIPE_PRIM_LINE_LOOP ||
398 prim == PIPE_PRIM_TRIANGLE_FAN ||
399 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
400 info->primitive_restart)
401 wd_switch_on_eop = true;
402
403 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
404 * We don't know that for indirect drawing, so treat it as
405 * always problematic. */
406 if (sctx->b.family == CHIP_HAWAII &&
407 (info->indirect || info->instance_count > 1))
408 wd_switch_on_eop = true;
409
410 /* If the WD switch is false, the IA switch must be false too. */
411 assert(wd_switch_on_eop || !ia_switch_on_eop);
412 }
413
414 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
415 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
416 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
417 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0);
418 }
419
420 static bool si_update_draw_info_state(struct si_context *sctx,
421 const struct pipe_draw_info *info,
422 const struct pipe_index_buffer *ib)
423 {
424 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
425 struct si_shader *vs = si_get_vs_state(sctx);
426 unsigned prim = si_conv_pipe_prim(info->mode);
427 unsigned gs_out_prim =
428 si_conv_prim_to_gs_out(sctx->gs_shader ?
429 sctx->gs_shader->gs_output_prim :
430 info->mode);
431 unsigned ls_mask = 0;
432 unsigned ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info);
433
434 if (pm4 == NULL)
435 return false;
436
437 if (prim == ~0) {
438 FREE(pm4);
439 return false;
440 }
441
442 if (sctx->b.chip_class >= CIK) {
443 si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
444 ib->index_size == 4 ? 0xFC000000 : 0xFC00);
445
446 si_pm4_cmd_begin(pm4, PKT3_DRAW_PREAMBLE);
447 si_pm4_cmd_add(pm4, prim); /* VGT_PRIMITIVE_TYPE */
448 si_pm4_cmd_add(pm4, ia_multi_vgt_param); /* IA_MULTI_VGT_PARAM */
449 si_pm4_cmd_add(pm4, 0); /* VGT_LS_HS_CONFIG */
450 si_pm4_cmd_end(pm4, false);
451 } else {
452 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
453 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
454 }
455
456 si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
457 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
458 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
459
460 if (prim == V_008958_DI_PT_LINELIST)
461 ls_mask = 1;
462 else if (prim == V_008958_DI_PT_LINESTRIP)
463 ls_mask = 2;
464 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
465 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
466 sctx->pa_sc_line_stipple);
467
468 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
469 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
470 S_028814_PROVOKING_VTX_LAST(1) | sctx->pa_su_sc_mode_cntl);
471 } else {
472 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, sctx->pa_su_sc_mode_cntl);
473 }
474 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
475 S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
476 S_02881C_USE_VTX_EDGE_FLAG(vs->vs_out_edgeflag) |
477 S_02881C_USE_VTX_RENDER_TARGET_INDX(vs->vs_out_layer) |
478 S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs->clip_dist_write & 0x0F) != 0) |
479 S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs->clip_dist_write & 0xF0) != 0) |
480 S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write) |
481 (sctx->queued.named.rasterizer->clip_plane_enable &
482 vs->clip_dist_write));
483 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL,
484 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
485 (vs->clip_dist_write ? 0 :
486 sctx->queued.named.rasterizer->clip_plane_enable & 0x3F));
487
488 si_pm4_set_state(sctx, draw_info, pm4);
489 return true;
490 }
491
492 static void si_update_spi_map(struct si_context *sctx)
493 {
494 struct si_shader *ps = sctx->ps_shader->current;
495 struct si_shader *vs = si_get_vs_state(sctx);
496 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
497 unsigned i, j, tmp;
498
499 for (i = 0; i < ps->ninput; i++) {
500 unsigned name = ps->input[i].name;
501 unsigned param_offset = ps->input[i].param_offset;
502
503 if (name == TGSI_SEMANTIC_POSITION)
504 /* Read from preloaded VGPRs, not parameters */
505 continue;
506
507 bcolor:
508 tmp = 0;
509
510 if (ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
511 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
512 ps->key.ps.flatshade)) {
513 tmp |= S_028644_FLAT_SHADE(1);
514 }
515
516 if (name == TGSI_SEMANTIC_GENERIC &&
517 sctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
518 tmp |= S_028644_PT_SPRITE_TEX(1);
519 }
520
521 for (j = 0; j < vs->noutput; j++) {
522 if (name == vs->output[j].name &&
523 ps->input[i].sid == vs->output[j].sid) {
524 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
525 break;
526 }
527 }
528
529 if (j == vs->noutput) {
530 /* No corresponding output found, load defaults into input */
531 tmp |= S_028644_OFFSET(0x20);
532 }
533
534 si_pm4_set_reg(pm4,
535 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
536 tmp);
537
538 if (name == TGSI_SEMANTIC_COLOR &&
539 ps->key.ps.color_two_side) {
540 name = TGSI_SEMANTIC_BCOLOR;
541 param_offset++;
542 goto bcolor;
543 }
544 }
545
546 si_pm4_set_state(sctx, spi, pm4);
547 }
548
549 /* Initialize state related to ESGS / GSVS ring buffers */
550 static void si_init_gs_rings(struct si_context *sctx)
551 {
552 unsigned esgs_ring_size = 128 * 1024;
553 unsigned gsvs_ring_size = 64 * 1024 * 1024;
554
555 assert(!sctx->gs_rings);
556 sctx->gs_rings = si_pm4_alloc_state(sctx);
557
558 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
559 PIPE_USAGE_DEFAULT, esgs_ring_size);
560
561 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
562 PIPE_USAGE_DEFAULT, gsvs_ring_size);
563
564 if (sctx->b.chip_class >= CIK) {
565 si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
566 esgs_ring_size / 256);
567 si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
568 gsvs_ring_size / 256);
569 } else {
570 si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
571 esgs_ring_size / 256);
572 si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
573 gsvs_ring_size / 256);
574 }
575
576 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
577 sctx->esgs_ring, 0, esgs_ring_size,
578 true, true, 4, 64);
579 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
580 sctx->esgs_ring, 0, esgs_ring_size,
581 false, false, 0, 0);
582 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
583 sctx->gsvs_ring, 0, gsvs_ring_size,
584 false, false, 0, 0);
585 }
586
587 static void si_update_derived_state(struct si_context *sctx)
588 {
589 struct pipe_context * ctx = (struct pipe_context*)sctx;
590
591 if (!sctx->blitter->running) {
592 /* Flush depth textures which need to be flushed. */
593 for (int i = 0; i < SI_NUM_SHADERS; i++) {
594 if (sctx->samplers[i].depth_texture_mask) {
595 si_flush_depth_textures(sctx, &sctx->samplers[i]);
596 }
597 if (sctx->samplers[i].compressed_colortex_mask) {
598 si_decompress_color_textures(sctx, &sctx->samplers[i]);
599 }
600 }
601 }
602
603 if (sctx->gs_shader) {
604 si_shader_select(ctx, sctx->gs_shader);
605
606 if (!sctx->gs_shader->current->pm4) {
607 si_shader_gs(ctx, sctx->gs_shader->current);
608 si_shader_vs(ctx, sctx->gs_shader->current->gs_copy_shader);
609 }
610
611 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
612 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
613
614 sctx->b.streamout.stride_in_dw = sctx->gs_shader->so.stride;
615
616 si_shader_select(ctx, sctx->vs_shader);
617
618 if (!sctx->vs_shader->current->pm4)
619 si_shader_es(ctx, sctx->vs_shader->current);
620
621 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
622
623 if (!sctx->gs_rings)
624 si_init_gs_rings(sctx);
625 if (sctx->emitted.named.gs_rings != sctx->gs_rings)
626 sctx->b.flags |= R600_CONTEXT_VGT_FLUSH;
627 si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
628
629 si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
630 sctx->gsvs_ring,
631 sctx->gs_shader->gs_max_out_vertices *
632 sctx->gs_shader->current->noutput * 16,
633 64, true, true, 4, 16);
634
635 if (!sctx->gs_on) {
636 sctx->gs_on = si_pm4_alloc_state(sctx);
637
638 si_pm4_set_reg(sctx->gs_on, R_028B54_VGT_SHADER_STAGES_EN,
639 S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
640 S_028B54_GS_EN(1) |
641 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER));
642 }
643 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_on);
644 } else {
645 si_shader_select(ctx, sctx->vs_shader);
646
647 if (!sctx->vs_shader->current->pm4)
648 si_shader_vs(ctx, sctx->vs_shader->current);
649
650 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
651
652 sctx->b.streamout.stride_in_dw = sctx->vs_shader->so.stride;
653
654 if (!sctx->gs_off) {
655 sctx->gs_off = si_pm4_alloc_state(sctx);
656
657 si_pm4_set_reg(sctx->gs_off, R_028A40_VGT_GS_MODE, 0);
658 si_pm4_set_reg(sctx->gs_off, R_028B54_VGT_SHADER_STAGES_EN, 0);
659 }
660 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_off);
661 si_pm4_bind_state(sctx, gs_rings, NULL);
662 si_pm4_bind_state(sctx, gs, NULL);
663 si_pm4_bind_state(sctx, es, NULL);
664 }
665
666 si_shader_select(ctx, sctx->ps_shader);
667
668 if (!sctx->ps_shader->current) {
669 struct si_shader_selector *sel;
670
671 /* use a dummy shader if compiling the shader (variant) failed */
672 si_make_dummy_ps(sctx);
673 sel = sctx->dummy_pixel_shader;
674 si_shader_select(ctx, sel);
675 sctx->ps_shader->current = sel->current;
676 }
677
678 if (!sctx->ps_shader->current->pm4)
679 si_shader_ps(ctx, sctx->ps_shader->current);
680
681 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
682
683 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs)) {
684 /* XXX: Emitting the PS state even when only the VS changed
685 * fixes random failures with piglit glsl-max-varyings.
686 * Not sure why...
687 */
688 sctx->emitted.named.ps = NULL;
689 si_update_spi_map(sctx);
690 }
691
692 if (sctx->ps_db_shader_control != sctx->ps_shader->current->db_shader_control) {
693 sctx->ps_db_shader_control = sctx->ps_shader->current->db_shader_control;
694 sctx->db_render_state.dirty = true;
695 }
696 }
697
698 static void si_state_draw(struct si_context *sctx,
699 const struct pipe_draw_info *info,
700 const struct pipe_index_buffer *ib)
701 {
702 unsigned sh_base_reg = (sctx->gs_shader ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
703 R_00B130_SPI_SHADER_USER_DATA_VS_0);
704 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
705
706 if (pm4 == NULL)
707 return;
708
709 if (info->count_from_stream_output) {
710 struct r600_so_target *t =
711 (struct r600_so_target*)info->count_from_stream_output;
712 uint64_t va = t->buf_filled_size->gpu_address +
713 t->buf_filled_size_offset;
714
715 si_pm4_set_reg(pm4, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
716 t->stride_in_dw);
717
718 si_pm4_cmd_begin(pm4, PKT3_COPY_DATA);
719 si_pm4_cmd_add(pm4,
720 COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
721 COPY_DATA_DST_SEL(COPY_DATA_REG) |
722 COPY_DATA_WR_CONFIRM);
723 si_pm4_cmd_add(pm4, va); /* src address lo */
724 si_pm4_cmd_add(pm4, va >> 32UL); /* src address hi */
725 si_pm4_cmd_add(pm4, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
726 si_pm4_cmd_add(pm4, 0); /* unused */
727 si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ,
728 RADEON_PRIO_MIN);
729 si_pm4_cmd_end(pm4, true);
730 }
731
732 /* draw packet */
733 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
734 if (ib->index_size == 4) {
735 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (SI_BIG_ENDIAN ?
736 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
737 } else {
738 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (SI_BIG_ENDIAN ?
739 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
740 }
741 si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
742
743 if (!info->indirect) {
744 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
745 si_pm4_cmd_add(pm4, info->instance_count);
746 si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
747
748 si_pm4_set_reg(pm4, sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
749 info->indexed ? info->index_bias : info->start);
750 si_pm4_set_reg(pm4, sh_base_reg + SI_SGPR_START_INSTANCE * 4,
751 info->start_instance);
752 } else {
753 si_pm4_add_bo(pm4, (struct r600_resource *)info->indirect,
754 RADEON_USAGE_READ, RADEON_PRIO_MIN);
755 }
756
757 if (info->indexed) {
758 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
759 sctx->index_buffer.index_size;
760 uint64_t va = r600_resource(ib->buffer)->gpu_address + ib->offset;
761
762 si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ,
763 RADEON_PRIO_MIN);
764
765 if (info->indirect) {
766 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
767 si_cmd_draw_index_indirect(pm4, indirect_va, va, max_size,
768 info->indirect_offset,
769 sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
770 sh_base_reg + SI_SGPR_START_INSTANCE * 4,
771 sctx->b.predicate_drawing);
772 } else {
773 va += info->start * ib->index_size;
774 si_cmd_draw_index_2(pm4, max_size, va, info->count,
775 V_0287F0_DI_SRC_SEL_DMA,
776 sctx->b.predicate_drawing);
777 }
778 } else {
779 if (info->indirect) {
780 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
781 si_cmd_draw_indirect(pm4, indirect_va, info->indirect_offset,
782 sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
783 sh_base_reg + SI_SGPR_START_INSTANCE * 4,
784 sctx->b.predicate_drawing);
785 } else {
786 si_cmd_draw_index_auto(pm4, info->count,
787 V_0287F0_DI_SRC_SEL_AUTO_INDEX |
788 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output),
789 sctx->b.predicate_drawing);
790 }
791 }
792
793 si_pm4_set_state(sctx, draw, pm4);
794 }
795
796 void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom)
797 {
798 struct radeon_winsys_cs *cs = sctx->rings.gfx.cs;
799 uint32_t cp_coher_cntl = 0;
800 uint32_t compute =
801 PKT3_SHADER_TYPE_S(!!(sctx->flags & R600_CONTEXT_FLAG_COMPUTE));
802
803 /* XXX SI flushes both ICACHE and KCACHE if either flag is set.
804 * XXX CIK shouldn't have this issue. Test CIK before separating the flags
805 * XXX to ensure there is no regression. Also find out if there is another
806 * XXX way to flush either ICACHE or KCACHE but not both for SI. */
807 if (sctx->flags & (R600_CONTEXT_INV_SHADER_CACHE |
808 R600_CONTEXT_INV_CONST_CACHE)) {
809 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1) |
810 S_0085F0_SH_KCACHE_ACTION_ENA(1);
811 }
812 if (sctx->flags & (R600_CONTEXT_INV_TEX_CACHE |
813 R600_CONTEXT_STREAMOUT_FLUSH)) {
814 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1) |
815 S_0085F0_TCL1_ACTION_ENA(1);
816 }
817 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB) {
818 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
819 S_0085F0_CB0_DEST_BASE_ENA(1) |
820 S_0085F0_CB1_DEST_BASE_ENA(1) |
821 S_0085F0_CB2_DEST_BASE_ENA(1) |
822 S_0085F0_CB3_DEST_BASE_ENA(1) |
823 S_0085F0_CB4_DEST_BASE_ENA(1) |
824 S_0085F0_CB5_DEST_BASE_ENA(1) |
825 S_0085F0_CB6_DEST_BASE_ENA(1) |
826 S_0085F0_CB7_DEST_BASE_ENA(1);
827 }
828 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB) {
829 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
830 S_0085F0_DB_DEST_BASE_ENA(1);
831 }
832
833 if (cp_coher_cntl) {
834 if (sctx->chip_class >= CIK) {
835 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) | compute);
836 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
837 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
838 radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */
839 radeon_emit(cs, 0); /* CP_COHER_BASE */
840 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
841 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
842 } else {
843 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0) | compute);
844 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
845 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
846 radeon_emit(cs, 0); /* CP_COHER_BASE */
847 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
848 }
849 }
850
851 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META) {
852 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
853 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
854 }
855 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB_META) {
856 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
857 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
858 }
859 if (sctx->flags & R600_CONTEXT_FLUSH_WITH_INV_L2) {
860 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
861 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH) | EVENT_INDEX(7) |
862 EVENT_WRITE_INV_L2);
863 }
864
865 if (sctx->flags & (R600_CONTEXT_WAIT_3D_IDLE |
866 R600_CONTEXT_PS_PARTIAL_FLUSH)) {
867 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
868 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
869 } else if (sctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
870 /* Needed if streamout buffers are going to be used as a source. */
871 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
872 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
873 }
874
875 if (sctx->flags & R600_CONTEXT_CS_PARTIAL_FLUSH) {
876 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
877 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
878 }
879
880 if (sctx->flags & R600_CONTEXT_VGT_FLUSH) {
881 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
882 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
883 }
884 if (sctx->flags & R600_CONTEXT_VGT_STREAMOUT_SYNC) {
885 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
886 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
887 }
888
889 sctx->flags = 0;
890 }
891
892 const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 21 }; /* number of CS dwords */
893
894 static void si_get_draw_start_count(struct si_context *sctx,
895 const struct pipe_draw_info *info,
896 unsigned *start, unsigned *count)
897 {
898 if (info->indirect) {
899 struct r600_resource *indirect =
900 (struct r600_resource*)info->indirect;
901 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
902 indirect, PIPE_TRANSFER_READ);
903 data += info->indirect_offset/sizeof(int);
904 *start = data[2];
905 *count = data[0];
906 } else {
907 *start = info->start;
908 *count = info->count;
909 }
910 }
911
912 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
913 {
914 struct si_context *sctx = (struct si_context *)ctx;
915 struct pipe_index_buffer ib = {};
916 uint32_t i;
917
918 if (!info->count && !info->indirect &&
919 (info->indexed || !info->count_from_stream_output))
920 return;
921
922 if (!sctx->ps_shader || !sctx->vs_shader)
923 return;
924
925 si_update_derived_state(sctx);
926
927 if (sctx->vertex_buffers_dirty) {
928 si_update_vertex_buffers(sctx);
929 sctx->vertex_buffers_dirty = false;
930 }
931
932 if (info->indexed) {
933 /* Initialize the index buffer struct. */
934 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
935 ib.user_buffer = sctx->index_buffer.user_buffer;
936 ib.index_size = sctx->index_buffer.index_size;
937 ib.offset = sctx->index_buffer.offset;
938
939 /* Translate or upload, if needed. */
940 if (ib.index_size == 1) {
941 struct pipe_resource *out_buffer = NULL;
942 unsigned out_offset, start, count, start_offset;
943 void *ptr;
944
945 si_get_draw_start_count(sctx, info, &start, &count);
946 start_offset = start * ib.index_size;
947
948 u_upload_alloc(sctx->b.uploader, start_offset, count * 2,
949 &out_offset, &out_buffer, &ptr);
950
951 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
952 ib.offset + start_offset,
953 count, ptr);
954
955 pipe_resource_reference(&ib.buffer, NULL);
956 ib.user_buffer = NULL;
957 ib.buffer = out_buffer;
958 /* info->start will be added by the drawing code */
959 ib.offset = out_offset - start_offset;
960 ib.index_size = 2;
961 } else if (ib.user_buffer && !ib.buffer) {
962 unsigned start, count, start_offset;
963
964 si_get_draw_start_count(sctx, info, &start, &count);
965 start_offset = start * ib.index_size;
966
967 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
968 (char*)ib.user_buffer + start_offset,
969 &ib.offset, &ib.buffer);
970 /* info->start will be added by the drawing code */
971 ib.offset -= start_offset;
972 }
973 }
974
975 if (!si_update_draw_info_state(sctx, info, &ib))
976 return;
977
978 si_state_draw(sctx, info, &ib);
979
980 sctx->pm4_dirty_cdwords += si_pm4_dirty_dw(sctx);
981
982 /* Check flush flags. */
983 if (sctx->b.flags)
984 sctx->atoms.s.cache_flush->dirty = true;
985
986 si_need_cs_space(sctx, 0, TRUE);
987
988 /* Emit states. */
989 for (i = 0; i < SI_NUM_ATOMS(sctx); i++) {
990 if (sctx->atoms.array[i]->dirty) {
991 sctx->atoms.array[i]->emit(&sctx->b, sctx->atoms.array[i]);
992 sctx->atoms.array[i]->dirty = false;
993 }
994 }
995
996 si_pm4_emit_dirty(sctx);
997 sctx->pm4_dirty_cdwords = 0;
998
999 #if SI_TRACE_CS
1000 if (sctx->screen->b.trace_bo) {
1001 si_trace_emit(sctx);
1002 }
1003 #endif
1004
1005 /* Workaround for a VGT hang when streamout is enabled.
1006 * It must be done after drawing. */
1007 if (sctx->b.family == CHIP_HAWAII &&
1008 (sctx->b.streamout.streamout_enabled ||
1009 sctx->b.streamout.prims_gen_query_enabled)) {
1010 sctx->b.flags |= R600_CONTEXT_VGT_STREAMOUT_SYNC;
1011 }
1012
1013 /* Set the depth buffer as dirty. */
1014 if (sctx->framebuffer.state.zsbuf) {
1015 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1016 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1017
1018 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1019 }
1020 if (sctx->framebuffer.compressed_cb_mask) {
1021 struct pipe_surface *surf;
1022 struct r600_texture *rtex;
1023 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1024
1025 do {
1026 unsigned i = u_bit_scan(&mask);
1027 surf = sctx->framebuffer.state.cbufs[i];
1028 rtex = (struct r600_texture*)surf->texture;
1029
1030 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1031 } while (mask);
1032 }
1033
1034 pipe_resource_reference(&ib.buffer, NULL);
1035 sctx->b.num_draw_calls++;
1036 }
1037
1038 #if SI_TRACE_CS
1039 void si_trace_emit(struct si_context *sctx)
1040 {
1041 struct si_screen *sscreen = sctx->screen;
1042 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
1043 uint64_t va;
1044
1045 va = sscreen->b.trace_bo->gpu_address;
1046 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, sscreen->b.trace_bo,
1047 RADEON_USAGE_READWRITE, RADEON_PRIO_MIN);
1048 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1049 radeon_emit(cs, PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_MEM_SYNC) |
1050 PKT3_WRITE_DATA_WR_CONFIRM |
1051 PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME));
1052 radeon_emit(cs, va & 0xFFFFFFFFUL);
1053 radeon_emit(cs, (va >> 32UL) & 0xFFFFFFFFUL);
1054 radeon_emit(cs, cs->cdw);
1055 radeon_emit(cs, sscreen->b.cs_count);
1056 }
1057 #endif