2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "radeonsi_pipe.h"
32 #include "radeonsi_shader.h"
40 static void si_pipe_shader_vs(struct pipe_context
*ctx
, struct si_pipe_shader
*shader
)
42 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
43 struct si_pm4_state
*pm4
;
44 unsigned num_sgprs
, num_user_sgprs
;
48 si_pm4_delete_state(rctx
, vs
, shader
->pm4
);
49 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
51 si_pm4_inval_shader_cache(pm4
);
53 /* Certain attributes (position, psize, etc.) don't count as params.
54 * VS is required to export at least one param and r600_shader_from_tgsi()
55 * takes care of adding a dummy export.
57 for (nparams
= 0, i
= 0 ; i
< shader
->shader
.noutput
; i
++) {
58 if (shader
->shader
.output
[i
].name
!= TGSI_SEMANTIC_POSITION
)
64 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
65 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
67 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
68 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
69 S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE
) |
70 S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE
) |
71 S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE
));
73 va
= r600_resource_va(ctx
->screen
, (void *)shader
->bo
);
74 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
);
75 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
76 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, va
>> 40);
78 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
79 num_sgprs
= shader
->num_sgprs
;
80 if (num_user_sgprs
> num_sgprs
)
81 num_sgprs
= num_user_sgprs
;
82 /* Last 2 reserved SGPRs are used for VCC */
84 assert(num_sgprs
<= 104);
86 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
87 S_00B128_VGPRS((shader
->num_vgprs
- 1) / 4) |
88 S_00B128_SGPRS((num_sgprs
- 1) / 8));
89 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
90 S_00B12C_USER_SGPR(num_user_sgprs
));
92 si_pm4_bind_state(rctx
, vs
, shader
->pm4
);
95 static void si_pipe_shader_ps(struct pipe_context
*ctx
, struct si_pipe_shader
*shader
)
97 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
98 struct si_pm4_state
*pm4
;
99 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control
, db_shader_control
;
100 unsigned num_sgprs
, num_user_sgprs
;
101 boolean have_linear
= FALSE
, have_centroid
= FALSE
, have_perspective
= FALSE
;
102 unsigned fragcoord_interp_mode
= 0;
103 unsigned spi_baryc_cntl
, spi_ps_input_ena
, spi_shader_z_format
;
106 si_pm4_delete_state(rctx
, ps
, shader
->pm4
);
107 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
109 si_pm4_inval_shader_cache(pm4
);
111 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
112 for (i
= 0; i
< shader
->shader
.ninput
; i
++) {
113 switch (shader
->shader
.input
[i
].name
) {
114 case TGSI_SEMANTIC_POSITION
:
115 if (shader
->shader
.input
[i
].centroid
) {
116 /* fragcoord_interp_mode will be written to
117 * SPI_BARYC_CNTL.POS_FLOAT_LOCATION
119 * 0 -> Position = pixel center (default)
120 * 1 -> Position = pixel centroid
121 * 2 -> Position = iterated sample number XXX:
122 * What does this mean?
124 fragcoord_interp_mode
= 1;
127 case TGSI_SEMANTIC_FACE
:
131 /* XXX: Flat shading hangs the GPU */
132 if (shader
->shader
.input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
133 (shader
->shader
.input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
134 rctx
->queued
.named
.rasterizer
->flatshade
))
136 if (shader
->shader
.input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
)
138 if (shader
->shader
.input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
139 have_perspective
= TRUE
;
140 if (shader
->shader
.input
[i
].centroid
)
141 have_centroid
= TRUE
;
144 for (i
= 0; i
< shader
->shader
.noutput
; i
++) {
145 if (shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_POSITION
)
146 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(1);
147 if (shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
148 db_shader_control
|= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
150 if (shader
->shader
.uses_kill
|| shader
->key
.alpha_func
!= PIPE_FUNC_ALWAYS
)
151 db_shader_control
|= S_02880C_KILL_ENABLE(1);
155 for (i
= 0; i
< shader
->shader
.noutput
; i
++) {
156 if (shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_POSITION
||
157 shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
159 else if (shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
160 if (shader
->shader
.fs_write_all
)
161 num_cout
= shader
->shader
.nr_cbufs
;
167 /* always at least export 1 component per pixel */
171 spi_ps_in_control
= S_0286D8_NUM_INTERP(shader
->shader
.ninterp
);
174 if (have_perspective
)
175 spi_baryc_cntl
|= have_centroid
?
176 S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1);
178 spi_baryc_cntl
|= have_centroid
?
179 S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1);
180 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(fragcoord_interp_mode
);
182 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
183 spi_ps_input_ena
= shader
->spi_ps_input_ena
;
184 /* we need to enable at least one of them, otherwise we hang the GPU */
185 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena
) ||
186 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) ||
187 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) ||
188 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena
) ||
189 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena
) ||
190 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
) ||
191 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
) ||
192 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena
));
194 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, spi_ps_input_ena
);
195 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
, spi_ps_input_ena
);
196 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
198 if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control
))
199 spi_shader_z_format
= V_028710_SPI_SHADER_32_GR
;
200 else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control
))
201 spi_shader_z_format
= V_028710_SPI_SHADER_32_R
;
203 spi_shader_z_format
= 0;
204 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
, spi_shader_z_format
);
205 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
,
206 shader
->spi_shader_col_format
);
208 va
= r600_resource_va(ctx
->screen
, (void *)shader
->bo
);
209 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
);
210 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
211 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, va
>> 40);
213 num_user_sgprs
= SI_PS_NUM_USER_SGPR
;
214 num_sgprs
= shader
->num_sgprs
;
215 if (num_user_sgprs
> num_sgprs
)
216 num_sgprs
= num_user_sgprs
;
217 /* Last 2 reserved SGPRs are used for VCC */
219 assert(num_sgprs
<= 104);
221 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
222 S_00B028_VGPRS((shader
->num_vgprs
- 1) / 4) |
223 S_00B028_SGPRS((num_sgprs
- 1) / 8));
224 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
225 S_00B02C_USER_SGPR(num_user_sgprs
));
227 si_pm4_set_reg(pm4
, R_02880C_DB_SHADER_CONTROL
, db_shader_control
);
229 shader
->sprite_coord_enable
= rctx
->sprite_coord_enable
;
230 si_pm4_bind_state(rctx
, ps
, shader
->pm4
);
237 static unsigned si_conv_pipe_prim(unsigned pprim
)
239 static const unsigned prim_conv
[] = {
240 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
241 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
242 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
243 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
244 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
245 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
246 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
247 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
248 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
249 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
250 [PIPE_PRIM_LINES_ADJACENCY
] = ~0,
251 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = ~0,
252 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = ~0,
253 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = ~0
255 unsigned result
= prim_conv
[pprim
];
257 R600_ERR("unsupported primitive type %d\n", pprim
);
262 static bool si_update_draw_info_state(struct r600_context
*rctx
,
263 const struct pipe_draw_info
*info
)
265 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
266 unsigned prim
= si_conv_pipe_prim(info
->mode
);
267 unsigned ls_mask
= 0;
277 si_pm4_set_reg(pm4
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
278 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
279 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
280 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
,
281 info
->indexed
? info
->index_bias
: info
->start
);
282 si_pm4_set_reg(pm4
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, info
->restart_index
);
283 si_pm4_set_reg(pm4
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, info
->primitive_restart
);
285 si_pm4_set_reg(pm4
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
286 si_pm4_set_reg(pm4
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
->start_instance
);
289 if (prim
== V_008958_DI_PT_LINELIST
)
291 else if (prim
== V_008958_DI_PT_LINESTRIP
)
293 si_pm4_set_reg(pm4
, R_028A0C_PA_SC_LINE_STIPPLE
,
294 S_028A0C_AUTO_RESET_CNTL(ls_mask
) |
295 rctx
->pa_sc_line_stipple
);
297 if (info
->mode
== PIPE_PRIM_QUADS
|| info
->mode
== PIPE_PRIM_QUAD_STRIP
|| info
->mode
== PIPE_PRIM_POLYGON
) {
298 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
299 S_028814_PROVOKING_VTX_LAST(1) | rctx
->pa_su_sc_mode_cntl
);
301 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
, rctx
->pa_su_sc_mode_cntl
);
303 si_pm4_set_reg(pm4
, R_02881C_PA_CL_VS_OUT_CNTL
,
304 prim
== PIPE_PRIM_POINTS
? rctx
->pa_cl_vs_out_cntl
: 0
305 /*| (rctx->rasterizer->clip_plane_enable &
306 rctx->vs_shader->shader.clip_dist_write)*/);
307 si_pm4_set_reg(pm4
, R_028810_PA_CL_CLIP_CNTL
, rctx
->pa_cl_clip_cntl
308 /*| (rctx->vs_shader->shader.clip_dist_write ||
309 rctx->vs_shader->shader.vs_prohibit_ucps ?
310 0 : rctx->rasterizer->clip_plane_enable & 0x3F)*/);
312 si_pm4_set_state(rctx
, draw_info
, pm4
);
316 static void si_update_spi_map(struct r600_context
*rctx
)
318 struct si_shader
*ps
= &rctx
->ps_shader
->current
->shader
;
319 struct si_shader
*vs
= &rctx
->vs_shader
->current
->shader
;
320 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
323 for (i
= 0; i
< ps
->ninput
; i
++) {
324 unsigned name
= ps
->input
[i
].name
;
325 unsigned param_offset
= ps
->input
[i
].param_offset
;
331 /* XXX: Flat shading hangs the GPU */
332 if (name
== TGSI_SEMANTIC_POSITION
||
333 ps
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
334 (ps
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
335 rctx
->rasterizer
&& rctx
->rasterizer
->flatshade
)) {
336 tmp
|= S_028644_FLAT_SHADE(1);
340 if (name
== TGSI_SEMANTIC_GENERIC
&&
341 rctx
->sprite_coord_enable
& (1 << ps
->input
[i
].sid
)) {
342 tmp
|= S_028644_PT_SPRITE_TEX(1);
345 for (j
= 0; j
< vs
->noutput
; j
++) {
346 if (name
== vs
->output
[j
].name
&&
347 ps
->input
[i
].sid
== vs
->output
[j
].sid
) {
348 tmp
|= S_028644_OFFSET(vs
->output
[j
].param_offset
);
353 if (j
== vs
->noutput
) {
354 /* No corresponding output found, load defaults into input */
355 tmp
|= S_028644_OFFSET(0x20);
359 R_028644_SPI_PS_INPUT_CNTL_0
+ param_offset
* 4,
362 if (name
== TGSI_SEMANTIC_COLOR
&&
363 rctx
->ps_shader
->current
->key
.color_two_side
) {
364 name
= TGSI_SEMANTIC_BCOLOR
;
370 si_pm4_set_state(rctx
, spi
, pm4
);
373 static void si_update_derived_state(struct r600_context
*rctx
)
375 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
376 unsigned ps_dirty
= 0;
378 if (!rctx
->blitter
->running
) {
379 /* Flush depth textures which need to be flushed. */
380 if (rctx
->vs_samplers
.depth_texture_mask
) {
381 si_flush_depth_textures(rctx
, &rctx
->vs_samplers
);
383 if (rctx
->ps_samplers
.depth_texture_mask
) {
384 si_flush_depth_textures(rctx
, &rctx
->ps_samplers
);
388 si_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
390 if (!rctx
->vs_shader
->current
->pm4
) {
391 si_pipe_shader_vs(ctx
, rctx
->vs_shader
->current
);
394 if (!rctx
->ps_shader
->current
->pm4
) {
395 si_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
398 if (!rctx
->ps_shader
->current
->bo
) {
399 if (!rctx
->dummy_pixel_shader
->pm4
)
400 si_pipe_shader_ps(ctx
, rctx
->dummy_pixel_shader
);
402 si_pm4_bind_state(rctx
, vs
, rctx
->dummy_pixel_shader
->pm4
);
408 si_pm4_bind_state(rctx
, ps
, rctx
->ps_shader
->current
->pm4
);
411 if (si_pm4_state_changed(rctx
, ps
) || si_pm4_state_changed(rctx
, vs
)) {
412 si_update_spi_map(rctx
);
416 static void si_vertex_buffer_update(struct r600_context
*rctx
)
418 struct pipe_context
*ctx
= &rctx
->context
;
419 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
420 bool bound
[PIPE_MAX_ATTRIBS
] = {};
424 si_pm4_inval_vertex_cache(pm4
);
426 /* bind vertex buffer once */
427 count
= rctx
->vertex_elements
->count
;
428 assert(count
<= 256 / 4);
430 si_pm4_sh_data_begin(pm4
);
431 for (i
= 0 ; i
< count
; i
++) {
432 struct pipe_vertex_element
*ve
= &rctx
->vertex_elements
->elements
[i
];
433 struct pipe_vertex_buffer
*vb
;
434 struct si_resource
*rbuffer
;
437 if (ve
->vertex_buffer_index
>= rctx
->nr_vertex_buffers
)
440 vb
= &rctx
->vertex_buffer
[ve
->vertex_buffer_index
];
441 rbuffer
= (struct si_resource
*)vb
->buffer
;
446 offset
+= vb
->buffer_offset
;
447 offset
+= ve
->src_offset
;
449 va
= r600_resource_va(ctx
->screen
, (void*)rbuffer
);
452 /* Fill in T# buffer resource description */
453 si_pm4_sh_data_add(pm4
, va
& 0xFFFFFFFF);
454 si_pm4_sh_data_add(pm4
, (S_008F04_BASE_ADDRESS_HI(va
>> 32) |
455 S_008F04_STRIDE(vb
->stride
)));
456 si_pm4_sh_data_add(pm4
, (vb
->buffer
->width0
- vb
->buffer_offset
) /
457 MAX2(vb
->stride
, 1));
458 si_pm4_sh_data_add(pm4
, rctx
->vertex_elements
->rsrc_word3
[i
]);
460 if (!bound
[ve
->vertex_buffer_index
]) {
461 si_pm4_add_bo(pm4
, rbuffer
, RADEON_USAGE_READ
);
462 bound
[ve
->vertex_buffer_index
] = true;
465 si_pm4_sh_data_end(pm4
, R_00B130_SPI_SHADER_USER_DATA_VS_0
, SI_SGPR_VERTEX_BUFFER
);
466 si_pm4_set_state(rctx
, vertex_buffers
, pm4
);
469 static void si_state_draw(struct r600_context
*rctx
,
470 const struct pipe_draw_info
*info
,
471 const struct pipe_index_buffer
*ib
)
473 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
475 /* queries need some special values
476 * (this is non-zero if any query is active) */
477 if (rctx
->num_cs_dw_queries_suspend
) {
478 struct si_state_dsa
*dsa
= rctx
->queued
.named
.dsa
;
480 si_pm4_set_reg(pm4
, R_028004_DB_COUNT_CONTROL
,
481 S_028004_PERFECT_ZPASS_COUNTS(1));
482 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
,
483 dsa
->db_render_override
|
484 S_02800C_NOOP_CULL_DISABLE(1));
488 si_pm4_cmd_begin(pm4
, PKT3_INDEX_TYPE
);
489 if (ib
->index_size
== 4) {
490 si_pm4_cmd_add(pm4
, V_028A7C_VGT_INDEX_32
| (R600_BIG_ENDIAN
?
491 V_028A7C_VGT_DMA_SWAP_32_BIT
: 0));
493 si_pm4_cmd_add(pm4
, V_028A7C_VGT_INDEX_16
| (R600_BIG_ENDIAN
?
494 V_028A7C_VGT_DMA_SWAP_16_BIT
: 0));
496 si_pm4_cmd_end(pm4
, rctx
->predicate_drawing
);
498 si_pm4_cmd_begin(pm4
, PKT3_NUM_INSTANCES
);
499 si_pm4_cmd_add(pm4
, info
->instance_count
);
500 si_pm4_cmd_end(pm4
, rctx
->predicate_drawing
);
503 uint32_t max_size
= (ib
->buffer
->width0
- ib
->offset
) /
504 rctx
->index_buffer
.index_size
;
506 va
= r600_resource_va(&rctx
->screen
->screen
, ib
->buffer
);
509 si_pm4_add_bo(pm4
, (struct si_resource
*)ib
->buffer
, RADEON_USAGE_READ
);
510 si_cmd_draw_index_2(pm4
, max_size
, va
, info
->count
,
511 V_0287F0_DI_SRC_SEL_DMA
,
512 rctx
->predicate_drawing
);
514 uint32_t initiator
= V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
515 initiator
|= S_0287F0_USE_OPAQUE(!!info
->count_from_stream_output
);
516 si_cmd_draw_index_auto(pm4
, info
->count
, initiator
, rctx
->predicate_drawing
);
518 si_pm4_set_state(rctx
, draw
, pm4
);
521 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
523 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
524 struct pipe_index_buffer ib
= {};
525 uint32_t cp_coher_cntl
;
527 if ((!info
->count
&& (info
->indexed
|| !info
->count_from_stream_output
)) ||
528 (info
->indexed
&& !rctx
->index_buffer
.buffer
)) {
532 if (!rctx
->ps_shader
|| !rctx
->vs_shader
)
535 si_update_derived_state(rctx
);
536 si_vertex_buffer_update(rctx
);
539 /* Initialize the index buffer struct. */
540 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
541 ib
.index_size
= rctx
->index_buffer
.index_size
;
542 ib
.offset
= rctx
->index_buffer
.offset
+ info
->start
* ib
.index_size
;
544 /* Translate or upload, if needed. */
545 r600_translate_index_buffer(rctx
, &ib
, info
->count
);
547 if (ib
.user_buffer
) {
548 r600_upload_index_buffer(rctx
, &ib
, info
->count
);
551 } else if (info
->count_from_stream_output
) {
552 r600_context_draw_opaque_count(rctx
, (struct r600_so_target
*)info
->count_from_stream_output
);
555 rctx
->vs_shader_so_strides
= rctx
->vs_shader
->current
->so_strides
;
557 if (!si_update_draw_info_state(rctx
, info
))
560 si_state_draw(rctx
, info
, &ib
);
562 cp_coher_cntl
= si_pm4_sync_flags(rctx
);
564 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
565 si_cmd_surface_sync(pm4
, cp_coher_cntl
);
566 si_pm4_set_state(rctx
, sync
, pm4
);
570 rctx
->pm4_dirty_cdwords
+= si_pm4_dirty_dw(rctx
);
572 si_need_cs_space(rctx
, 0, TRUE
);
574 si_pm4_emit_dirty(rctx
);
575 rctx
->pm4_dirty_cdwords
= 0;
578 /* Enable stream out if needed. */
579 if (rctx
->streamout_start
) {
580 r600_context_streamout_begin(rctx
);
581 rctx
->streamout_start
= FALSE
;
586 rctx
->flags
|= R600_CONTEXT_DST_CACHES_DIRTY
;
588 /* Set the depth buffer as dirty. */
589 if (rctx
->framebuffer
.zsbuf
) {
590 struct pipe_surface
*surf
= rctx
->framebuffer
.zsbuf
;
591 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)surf
->texture
;
593 rtex
->dirty_db_mask
|= 1 << surf
->u
.tex
.level
;
596 pipe_resource_reference(&ib
.buffer
, NULL
);