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radeonsi: apply a tessellation bug workaround for SI
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "radeon/r600_cs.h"
29 #include "sid.h"
30
31 #include "util/u_index_modify.h"
32 #include "util/u_upload_mgr.h"
33 #include "util/u_prim.h"
34
35 static unsigned si_conv_pipe_prim(unsigned mode)
36 {
37 static const unsigned prim_conv[] = {
38 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
39 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
40 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
41 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
42 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
43 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
44 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
45 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
46 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
47 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
48 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
49 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
50 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
51 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
52 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
53 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
54 };
55 assert(mode < ARRAY_SIZE(prim_conv));
56 return prim_conv[mode];
57 }
58
59 static unsigned si_conv_prim_to_gs_out(unsigned mode)
60 {
61 static const int prim_conv[] = {
62 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
63 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
64 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
65 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
66 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
67 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
68 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
69 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
73 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
74 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
75 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
76 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
77 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
78 };
79 assert(mode < ARRAY_SIZE(prim_conv));
80
81 return prim_conv[mode];
82 }
83
84 /**
85 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
86 * LS.LDS_SIZE is shared by all 3 shader stages.
87 *
88 * The information about LDS and other non-compile-time parameters is then
89 * written to userdata SGPRs.
90 */
91 static void si_emit_derived_tess_state(struct si_context *sctx,
92 const struct pipe_draw_info *info,
93 unsigned *num_patches)
94 {
95 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
96 struct si_shader_ctx_state *ls = &sctx->vs_shader;
97 /* The TES pointer will only be used for sctx->last_tcs.
98 * It would be wrong to think that TCS = TES. */
99 struct si_shader_selector *tcs =
100 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
101 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
102 unsigned num_tcs_input_cp = info->vertices_per_patch;
103 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
104 unsigned num_tcs_patch_outputs;
105 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
106 unsigned input_patch_size, output_patch_size, output_patch0_offset;
107 unsigned perpatch_output_offset, lds_size, ls_rsrc2;
108 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
109 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
110
111 if (sctx->last_ls == ls->current &&
112 sctx->last_tcs == tcs &&
113 sctx->last_tes_sh_base == tes_sh_base &&
114 sctx->last_num_tcs_input_cp == num_tcs_input_cp) {
115 *num_patches = sctx->last_num_patches;
116 return;
117 }
118
119 sctx->last_ls = ls->current;
120 sctx->last_tcs = tcs;
121 sctx->last_tes_sh_base = tes_sh_base;
122 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
123
124 /* This calculates how shader inputs and outputs among VS, TCS, and TES
125 * are laid out in LDS. */
126 num_tcs_inputs = util_last_bit64(ls->cso->outputs_written);
127
128 if (sctx->tcs_shader.cso) {
129 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
130 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
131 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
132 } else {
133 /* No TCS. Route varyings from LS to TES. */
134 num_tcs_outputs = num_tcs_inputs;
135 num_tcs_output_cp = num_tcs_input_cp;
136 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
137 }
138
139 input_vertex_size = num_tcs_inputs * 16;
140 output_vertex_size = num_tcs_outputs * 16;
141
142 input_patch_size = num_tcs_input_cp * input_vertex_size;
143
144 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
145 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
146
147 /* Ensure that we only need one wave per SIMD so we don't need to check
148 * resource usage. Also ensures that the number of tcs in and out
149 * vertices per threadgroup are at most 256.
150 */
151 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
152
153 /* Make sure that the data fits in LDS. This assumes the shaders only
154 * use LDS for the inputs and outputs.
155 */
156 hardware_lds_size = sctx->b.chip_class >= CIK ? 65536 : 32768;
157 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
158 output_patch_size));
159
160 /* Make sure the output data fits in the offchip buffer */
161 *num_patches = MIN2(*num_patches,
162 (sctx->screen->tess_offchip_block_dw_size * 4) /
163 output_patch_size);
164
165 /* Not necessary for correctness, but improves performance. The
166 * specific value is taken from the proprietary driver.
167 */
168 *num_patches = MIN2(*num_patches, 40);
169
170 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
171 if (sctx->b.chip_class == SI) {
172 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
173 *num_patches = MIN2(*num_patches, one_wave);
174 }
175
176 sctx->last_num_patches = *num_patches;
177
178 output_patch0_offset = input_patch_size * *num_patches;
179 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
180
181 lds_size = output_patch0_offset + output_patch_size * *num_patches;
182 ls_rsrc2 = ls->current->config.rsrc2;
183
184 if (sctx->b.chip_class >= CIK) {
185 assert(lds_size <= 65536);
186 lds_size = align(lds_size, 512) / 512;
187 } else {
188 assert(lds_size <= 32768);
189 lds_size = align(lds_size, 256) / 256;
190 }
191 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
192 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
193
194 /* Due to a hw bug, RSRC2_LS must be written twice with another
195 * LS register written in between. */
196 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
197 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
198 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
199 radeon_emit(cs, ls->current->config.rsrc1);
200 radeon_emit(cs, ls_rsrc2);
201
202 /* Compute userdata SGPRs. */
203 assert(((input_vertex_size / 4) & ~0xff) == 0);
204 assert(((output_vertex_size / 4) & ~0xff) == 0);
205 assert(((input_patch_size / 4) & ~0x1fff) == 0);
206 assert(((output_patch_size / 4) & ~0x1fff) == 0);
207 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
208 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
209 assert(num_tcs_input_cp <= 32);
210 assert(num_tcs_output_cp <= 32);
211
212 tcs_in_layout = (input_patch_size / 4) |
213 ((input_vertex_size / 4) << 13);
214 tcs_out_layout = (output_patch_size / 4) |
215 ((output_vertex_size / 4) << 13);
216 tcs_out_offsets = (output_patch0_offset / 16) |
217 ((perpatch_output_offset / 16) << 16);
218 offchip_layout = (pervertex_output_patch_size * *num_patches << 16) |
219 (num_tcs_output_cp << 9) | *num_patches;
220
221 /* Set them for LS. */
222 radeon_set_sh_reg(cs,
223 R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4,
224 tcs_in_layout);
225
226 /* Set them for TCS. */
227 radeon_set_sh_reg_seq(cs,
228 R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
229 radeon_emit(cs, offchip_layout);
230 radeon_emit(cs, tcs_out_offsets);
231 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
232 radeon_emit(cs, tcs_in_layout);
233
234 /* Set them for TES. */
235 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 1);
236 radeon_emit(cs, offchip_layout);
237
238 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
239 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
240 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
241
242 if (sctx->b.chip_class >= CIK)
243 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
244 ls_hs_config);
245 else
246 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
247 ls_hs_config);
248 }
249
250 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
251 {
252 switch (info->mode) {
253 case PIPE_PRIM_PATCHES:
254 return info->count / info->vertices_per_patch;
255 case R600_PRIM_RECTANGLE_LIST:
256 return info->count / 3;
257 default:
258 return u_prims_for_vertices(info->mode, info->count);
259 }
260 }
261
262 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
263 const struct pipe_draw_info *info,
264 unsigned num_patches)
265 {
266 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
267 unsigned prim = info->mode;
268 unsigned primgroup_size = 128; /* recommended without a GS */
269 unsigned max_primgroup_in_wave = 2;
270
271 /* SWITCH_ON_EOP(0) is always preferable. */
272 bool wd_switch_on_eop = false;
273 bool ia_switch_on_eop = false;
274 bool ia_switch_on_eoi = false;
275 bool partial_vs_wave = false;
276 bool partial_es_wave = false;
277
278 if (sctx->gs_shader.cso)
279 primgroup_size = 64; /* recommended with a GS */
280
281 if (sctx->tes_shader.cso) {
282 /* primgroup_size must be set to a multiple of NUM_PATCHES */
283 primgroup_size = num_patches;
284
285 /* SWITCH_ON_EOI must be set if PrimID is used. */
286 if ((sctx->tcs_shader.cso && sctx->tcs_shader.cso->info.uses_primid) ||
287 sctx->tes_shader.cso->info.uses_primid)
288 ia_switch_on_eoi = true;
289
290 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
291 if ((sctx->b.family == CHIP_TAHITI ||
292 sctx->b.family == CHIP_PITCAIRN ||
293 sctx->b.family == CHIP_BONAIRE) &&
294 sctx->gs_shader.cso)
295 partial_vs_wave = true;
296
297 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
298 if (sctx->screen->has_distributed_tess) {
299 if (sctx->gs_shader.cso)
300 partial_es_wave = true;
301 else
302 partial_vs_wave = true;
303 }
304 }
305
306 /* This is a hardware requirement. */
307 if ((rs && rs->line_stipple_enable) ||
308 (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
309 ia_switch_on_eop = true;
310 wd_switch_on_eop = true;
311 }
312
313 if (sctx->b.chip_class >= CIK) {
314 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
315 * 4 shader engines. Set 1 to pass the assertion below.
316 * The other cases are hardware requirements.
317 *
318 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
319 * for points, line strips, and tri strips.
320 */
321 if (sctx->b.screen->info.max_se < 4 ||
322 prim == PIPE_PRIM_POLYGON ||
323 prim == PIPE_PRIM_LINE_LOOP ||
324 prim == PIPE_PRIM_TRIANGLE_FAN ||
325 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
326 (info->primitive_restart &&
327 (sctx->b.family < CHIP_POLARIS10 ||
328 (prim != PIPE_PRIM_POINTS &&
329 prim != PIPE_PRIM_LINE_STRIP &&
330 prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
331 info->count_from_stream_output)
332 wd_switch_on_eop = true;
333
334 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
335 * We don't know that for indirect drawing, so treat it as
336 * always problematic. */
337 if (sctx->b.family == CHIP_HAWAII &&
338 (info->indirect || info->instance_count > 1))
339 wd_switch_on_eop = true;
340
341 /* Performance recommendation for 4 SE Gfx7-8 parts if
342 * instances are smaller than a primgroup.
343 * Assume indirect draws always use small instances.
344 * This is needed for good VS wave utilization.
345 */
346 if (sctx->b.chip_class <= VI &&
347 sctx->b.screen->info.max_se >= 4 &&
348 (info->indirect ||
349 (info->instance_count > 1 &&
350 si_num_prims_for_vertices(info) < primgroup_size)))
351 wd_switch_on_eop = true;
352
353 /* Required on CIK and later. */
354 if (sctx->b.screen->info.max_se > 2 && !wd_switch_on_eop)
355 ia_switch_on_eoi = true;
356
357 /* Required by Hawaii and, for some special cases, by VI. */
358 if (ia_switch_on_eoi &&
359 (sctx->b.family == CHIP_HAWAII ||
360 (sctx->b.chip_class == VI &&
361 (sctx->gs_shader.cso || max_primgroup_in_wave != 2))))
362 partial_vs_wave = true;
363
364 /* Instancing bug on Bonaire. */
365 if (sctx->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
366 (info->indirect || info->instance_count > 1))
367 partial_vs_wave = true;
368
369 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
370 * The hw doc says all multi-SE chips are affected, but Vulkan
371 * only applies it to Hawaii. Do what Vulkan does.
372 */
373 if (sctx->b.family == CHIP_HAWAII &&
374 sctx->gs_shader.cso &&
375 ia_switch_on_eoi &&
376 (info->indirect ||
377 (info->instance_count > 1 &&
378 si_num_prims_for_vertices(info) <= 1)))
379 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
380
381
382 /* If the WD switch is false, the IA switch must be false too. */
383 assert(wd_switch_on_eop || !ia_switch_on_eop);
384 }
385
386 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
387 if (ia_switch_on_eoi)
388 partial_es_wave = true;
389
390 /* GS requirement. */
391 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
392 partial_es_wave = true;
393
394 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
395 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
396 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
397 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
398 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
399 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
400 S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx->b.chip_class >= VI ?
401 max_primgroup_in_wave : 0);
402 }
403
404 static void si_emit_scratch_reloc(struct si_context *sctx)
405 {
406 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
407
408 if (!sctx->emit_scratch_reloc)
409 return;
410
411 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
412 sctx->spi_tmpring_size);
413
414 if (sctx->scratch_buffer) {
415 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
416 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
417 RADEON_PRIO_SCRATCH_BUFFER);
418
419 }
420 sctx->emit_scratch_reloc = false;
421 }
422
423 /* rast_prim is the primitive type after GS. */
424 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
425 {
426 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
427 unsigned rast_prim = sctx->current_rast_prim;
428 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
429
430 /* Skip this if not rendering lines. */
431 if (rast_prim != PIPE_PRIM_LINES &&
432 rast_prim != PIPE_PRIM_LINE_LOOP &&
433 rast_prim != PIPE_PRIM_LINE_STRIP &&
434 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
435 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
436 return;
437
438 if (rast_prim == sctx->last_rast_prim &&
439 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
440 return;
441
442 /* For lines, reset the stipple pattern at each primitive. Otherwise,
443 * reset the stipple pattern at each packet (line strips, line loops).
444 */
445 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
446 rs->pa_sc_line_stipple |
447 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
448
449 sctx->last_rast_prim = rast_prim;
450 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
451 }
452
453 static void si_emit_draw_registers(struct si_context *sctx,
454 const struct pipe_draw_info *info)
455 {
456 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
457 unsigned prim = si_conv_pipe_prim(info->mode);
458 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
459 unsigned ia_multi_vgt_param, num_patches = 0;
460
461 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
462 * whether the "fractional odd" tessellation spacing is used.
463 */
464 if (sctx->b.family >= CHIP_POLARIS10) {
465 struct si_shader_selector *tes = sctx->tes_shader.cso;
466 unsigned vtx_reuse_depth = 30;
467
468 if (tes &&
469 tes->info.properties[TGSI_PROPERTY_TES_SPACING] ==
470 PIPE_TESS_SPACING_FRACTIONAL_ODD)
471 vtx_reuse_depth = 14;
472
473 if (vtx_reuse_depth != sctx->last_vtx_reuse_depth) {
474 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
475 vtx_reuse_depth);
476 sctx->last_vtx_reuse_depth = vtx_reuse_depth;
477 }
478 }
479
480 if (sctx->tes_shader.cso)
481 si_emit_derived_tess_state(sctx, info, &num_patches);
482
483 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
484
485 /* Draw state. */
486 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
487 if (sctx->b.chip_class >= CIK)
488 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
489 else
490 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
491
492 sctx->last_multi_vgt_param = ia_multi_vgt_param;
493 }
494 if (prim != sctx->last_prim) {
495 if (sctx->b.chip_class >= CIK)
496 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
497 else
498 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
499
500 sctx->last_prim = prim;
501 }
502
503 if (gs_out_prim != sctx->last_gs_out_prim) {
504 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
505 sctx->last_gs_out_prim = gs_out_prim;
506 }
507
508 /* Primitive restart. */
509 if (info->primitive_restart != sctx->last_primitive_restart_en) {
510 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
511 sctx->last_primitive_restart_en = info->primitive_restart;
512
513 }
514 if (info->primitive_restart &&
515 (info->restart_index != sctx->last_restart_index ||
516 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
517 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
518 info->restart_index);
519 sctx->last_restart_index = info->restart_index;
520 }
521 }
522
523 static void si_emit_draw_packets(struct si_context *sctx,
524 const struct pipe_draw_info *info,
525 const struct pipe_index_buffer *ib)
526 {
527 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
528 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
529 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
530 uint32_t index_max_size = 0;
531 uint64_t index_va = 0;
532
533 if (info->count_from_stream_output) {
534 struct r600_so_target *t =
535 (struct r600_so_target*)info->count_from_stream_output;
536 uint64_t va = t->buf_filled_size->gpu_address +
537 t->buf_filled_size_offset;
538
539 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
540 t->stride_in_dw);
541
542 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
543 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
544 COPY_DATA_DST_SEL(COPY_DATA_REG) |
545 COPY_DATA_WR_CONFIRM);
546 radeon_emit(cs, va); /* src address lo */
547 radeon_emit(cs, va >> 32); /* src address hi */
548 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
549 radeon_emit(cs, 0); /* unused */
550
551 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
552 t->buf_filled_size, RADEON_USAGE_READ,
553 RADEON_PRIO_SO_FILLED_SIZE);
554 }
555
556 /* draw packet */
557 if (info->indexed) {
558 if (ib->index_size != sctx->last_index_size) {
559 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
560
561 /* index type */
562 switch (ib->index_size) {
563 case 1:
564 radeon_emit(cs, V_028A7C_VGT_INDEX_8);
565 break;
566 case 2:
567 radeon_emit(cs, V_028A7C_VGT_INDEX_16 |
568 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
569 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
570 break;
571 case 4:
572 radeon_emit(cs, V_028A7C_VGT_INDEX_32 |
573 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
574 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
575 break;
576 default:
577 assert(!"unreachable");
578 return;
579 }
580
581 sctx->last_index_size = ib->index_size;
582 }
583
584 index_max_size = (ib->buffer->width0 - ib->offset) /
585 ib->index_size;
586 index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
587
588 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
589 (struct r600_resource *)ib->buffer,
590 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
591 } else {
592 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
593 * so the state must be re-emitted before the next indexed draw.
594 */
595 if (sctx->b.chip_class >= CIK)
596 sctx->last_index_size = -1;
597 }
598
599 if (!info->indirect) {
600 int base_vertex;
601
602 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
603 radeon_emit(cs, info->instance_count);
604
605 /* Base vertex and start instance. */
606 base_vertex = info->indexed ? info->index_bias : info->start;
607
608 if (base_vertex != sctx->last_base_vertex ||
609 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
610 info->start_instance != sctx->last_start_instance ||
611 info->drawid != sctx->last_drawid ||
612 sh_base_reg != sctx->last_sh_base_reg) {
613 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
614 radeon_emit(cs, base_vertex);
615 radeon_emit(cs, info->start_instance);
616 radeon_emit(cs, info->drawid);
617
618 sctx->last_base_vertex = base_vertex;
619 sctx->last_start_instance = info->start_instance;
620 sctx->last_drawid = info->drawid;
621 sctx->last_sh_base_reg = sh_base_reg;
622 }
623 } else {
624 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
625
626 assert(indirect_va % 8 == 0);
627
628 si_invalidate_draw_sh_constants(sctx);
629
630 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
631 radeon_emit(cs, 1);
632 radeon_emit(cs, indirect_va);
633 radeon_emit(cs, indirect_va >> 32);
634
635 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
636 (struct r600_resource *)info->indirect,
637 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
638 }
639
640 if (info->indirect) {
641 unsigned di_src_sel = info->indexed ? V_0287F0_DI_SRC_SEL_DMA
642 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
643
644 assert(info->indirect_offset % 4 == 0);
645
646 if (info->indexed) {
647 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
648 radeon_emit(cs, index_va);
649 radeon_emit(cs, index_va >> 32);
650
651 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
652 radeon_emit(cs, index_max_size);
653 }
654
655 if (!sctx->screen->has_draw_indirect_multi) {
656 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT
657 : PKT3_DRAW_INDIRECT,
658 3, render_cond_bit));
659 radeon_emit(cs, info->indirect_offset);
660 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
661 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
662 radeon_emit(cs, di_src_sel);
663 } else {
664 uint64_t count_va = 0;
665
666 if (info->indirect_params) {
667 struct r600_resource *params_buf =
668 (struct r600_resource *)info->indirect_params;
669
670 radeon_add_to_buffer_list(
671 &sctx->b, &sctx->b.gfx, params_buf,
672 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
673
674 count_va = params_buf->gpu_address + info->indirect_params_offset;
675 }
676
677 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
678 PKT3_DRAW_INDIRECT_MULTI,
679 8, render_cond_bit));
680 radeon_emit(cs, info->indirect_offset);
681 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
682 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
683 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
684 S_2C3_DRAW_INDEX_ENABLE(1) |
685 S_2C3_COUNT_INDIRECT_ENABLE(!!info->indirect_params));
686 radeon_emit(cs, info->indirect_count);
687 radeon_emit(cs, count_va);
688 radeon_emit(cs, count_va >> 32);
689 radeon_emit(cs, info->indirect_stride);
690 radeon_emit(cs, di_src_sel);
691 }
692 } else {
693 if (info->indexed) {
694 index_va += info->start * ib->index_size;
695
696 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
697 radeon_emit(cs, index_max_size);
698 radeon_emit(cs, index_va);
699 radeon_emit(cs, (index_va >> 32UL) & 0xFF);
700 radeon_emit(cs, info->count);
701 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
702 } else {
703 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
704 radeon_emit(cs, info->count);
705 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
706 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
707 }
708 }
709 }
710
711 static void si_emit_surface_sync(struct r600_common_context *rctx,
712 unsigned cp_coher_cntl)
713 {
714 struct radeon_winsys_cs *cs = rctx->gfx.cs;
715
716 /* ACQUIRE_MEM is only required on a compute ring. */
717 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
718 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
719 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
720 radeon_emit(cs, 0); /* CP_COHER_BASE */
721 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
722 }
723
724 void si_emit_cache_flush(struct si_context *sctx)
725 {
726 struct r600_common_context *rctx = &sctx->b;
727 struct radeon_winsys_cs *cs = rctx->gfx.cs;
728 uint32_t cp_coher_cntl = 0;
729
730 /* SI has a bug that it always flushes ICACHE and KCACHE if either
731 * bit is set. An alternative way is to write SQC_CACHES, but that
732 * doesn't seem to work reliably. Since the bug doesn't affect
733 * correctness (it only does more work than necessary) and
734 * the performance impact is likely negligible, there is no plan
735 * to add a workaround for it.
736 */
737
738 if (rctx->flags & SI_CONTEXT_INV_ICACHE)
739 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
740 if (rctx->flags & SI_CONTEXT_INV_SMEM_L1)
741 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
742
743 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
744 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
745 S_0085F0_CB0_DEST_BASE_ENA(1) |
746 S_0085F0_CB1_DEST_BASE_ENA(1) |
747 S_0085F0_CB2_DEST_BASE_ENA(1) |
748 S_0085F0_CB3_DEST_BASE_ENA(1) |
749 S_0085F0_CB4_DEST_BASE_ENA(1) |
750 S_0085F0_CB5_DEST_BASE_ENA(1) |
751 S_0085F0_CB6_DEST_BASE_ENA(1) |
752 S_0085F0_CB7_DEST_BASE_ENA(1);
753
754 /* Necessary for DCC */
755 if (rctx->chip_class == VI)
756 r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
757 0, 0, NULL, 0, 0, 0);
758 }
759 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
760 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
761 S_0085F0_DB_DEST_BASE_ENA(1);
762 }
763
764 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) {
765 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
766 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
767 /* needed for wait for idle in SURFACE_SYNC */
768 assert(rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB);
769 }
770 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) {
771 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
772 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
773 /* needed for wait for idle in SURFACE_SYNC */
774 assert(rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB);
775 }
776
777 /* Wait for shader engines to go idle.
778 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
779 * for everything including CB/DB cache flushes.
780 */
781 if (!(rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
782 SI_CONTEXT_FLUSH_AND_INV_DB))) {
783 if (rctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
784 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
785 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
786 /* Only count explicit shader flushes, not implicit ones
787 * done by SURFACE_SYNC.
788 */
789 rctx->num_vs_flushes++;
790 rctx->num_ps_flushes++;
791 } else if (rctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
792 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
793 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
794 rctx->num_vs_flushes++;
795 }
796 }
797
798 if (rctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
799 sctx->compute_is_busy) {
800 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
801 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
802 rctx->num_cs_flushes++;
803 sctx->compute_is_busy = false;
804 }
805
806 /* VGT state synchronization. */
807 if (rctx->flags & SI_CONTEXT_VGT_FLUSH) {
808 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
809 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
810 }
811 if (rctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
812 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
813 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
814 }
815
816 /* Make sure ME is idle (it executes most packets) before continuing.
817 * This prevents read-after-write hazards between PFP and ME.
818 */
819 if (cp_coher_cntl ||
820 (rctx->flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
821 SI_CONTEXT_INV_VMEM_L1 |
822 SI_CONTEXT_INV_GLOBAL_L2 |
823 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
824 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
825 radeon_emit(cs, 0);
826 }
827
828 /* When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
829 * waits for idle. Therefore, it should be last. SURFACE_SYNC is done
830 * in PFP.
831 *
832 * cp_coher_cntl should contain all necessary flags except TC flags
833 * at this point.
834 *
835 * SI-CIK don't support L2 write-back.
836 */
837 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2 ||
838 (rctx->chip_class <= CIK &&
839 (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
840 /* Invalidate L1 & L2. (L1 is always invalidated)
841 * WB must be set on VI+ when TC_ACTION is set.
842 */
843 si_emit_surface_sync(rctx, cp_coher_cntl |
844 S_0085F0_TC_ACTION_ENA(1) |
845 S_0301F0_TC_WB_ACTION_ENA(rctx->chip_class >= VI));
846 cp_coher_cntl = 0;
847 } else {
848 /* L1 invalidation and L2 writeback must be done separately,
849 * because both operations can't be done together.
850 */
851 if (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
852 /* WB = write-back
853 * NC = apply to non-coherent MTYPEs
854 * (i.e. MTYPE <= 1, which is what we use everywhere)
855 *
856 * WB doesn't work without NC.
857 */
858 si_emit_surface_sync(rctx, cp_coher_cntl |
859 S_0301F0_TC_WB_ACTION_ENA(1) |
860 S_0301F0_TC_NC_ACTION_ENA(1));
861 cp_coher_cntl = 0;
862 }
863 if (rctx->flags & SI_CONTEXT_INV_VMEM_L1) {
864 /* Invalidate per-CU VMEM L1. */
865 si_emit_surface_sync(rctx, cp_coher_cntl |
866 S_0085F0_TCL1_ACTION_ENA(1));
867 cp_coher_cntl = 0;
868 }
869 }
870
871 /* If TC flushes haven't cleared this... */
872 if (cp_coher_cntl)
873 si_emit_surface_sync(rctx, cp_coher_cntl);
874
875 if (rctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
876 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
877 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
878 EVENT_INDEX(0));
879 } else if (rctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
880 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
881 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
882 EVENT_INDEX(0));
883 }
884
885 rctx->flags = 0;
886 }
887
888 static void si_get_draw_start_count(struct si_context *sctx,
889 const struct pipe_draw_info *info,
890 unsigned *start, unsigned *count)
891 {
892 if (info->indirect) {
893 struct r600_resource *indirect =
894 (struct r600_resource*)info->indirect;
895 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
896 indirect, PIPE_TRANSFER_READ);
897 data += info->indirect_offset/sizeof(int);
898 *start = data[2];
899 *count = data[0];
900 } else {
901 *start = info->start;
902 *count = info->count;
903 }
904 }
905
906 void si_ce_pre_draw_synchronization(struct si_context *sctx)
907 {
908 if (sctx->ce_need_synchronization) {
909 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
910 radeon_emit(sctx->ce_ib, 1);
911
912 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
913 radeon_emit(sctx->b.gfx.cs, 1);
914 }
915 }
916
917 void si_ce_post_draw_synchronization(struct si_context *sctx)
918 {
919 if (sctx->ce_need_synchronization) {
920 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
921 radeon_emit(sctx->b.gfx.cs, 0);
922
923 sctx->ce_need_synchronization = false;
924 }
925 }
926
927 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
928 {
929 struct si_context *sctx = (struct si_context *)ctx;
930 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
931 struct pipe_index_buffer ib = {};
932 unsigned mask, dirty_fb_counter, dirty_tex_counter, rast_prim;
933
934 if (likely(!info->indirect)) {
935 /* SI-CI treat instance_count==0 as instance_count==1. There is
936 * no workaround for indirect draws, but we can at least skip
937 * direct draws.
938 */
939 if (unlikely(!info->instance_count))
940 return;
941
942 /* Handle count == 0. */
943 if (unlikely(!info->count &&
944 (info->indexed || !info->count_from_stream_output)))
945 return;
946 }
947
948 if (unlikely(!sctx->vs_shader.cso)) {
949 assert(0);
950 return;
951 }
952 if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
953 assert(0);
954 return;
955 }
956 if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
957 assert(0);
958 return;
959 }
960
961 /* Re-emit the framebuffer state if needed. */
962 dirty_fb_counter = p_atomic_read(&sctx->b.screen->dirty_fb_counter);
963 if (unlikely(dirty_fb_counter != sctx->b.last_dirty_fb_counter)) {
964 sctx->b.last_dirty_fb_counter = dirty_fb_counter;
965 sctx->framebuffer.dirty_cbufs |=
966 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
967 sctx->framebuffer.dirty_zsbuf = true;
968 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
969 }
970
971 /* Invalidate & recompute texture descriptors if needed. */
972 dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_descriptor_counter);
973 if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_descriptor_counter)) {
974 sctx->b.last_dirty_tex_descriptor_counter = dirty_tex_counter;
975 si_update_all_texture_descriptors(sctx);
976 }
977
978 si_decompress_graphics_textures(sctx);
979
980 /* Set the rasterization primitive type.
981 *
982 * This must be done after si_decompress_textures, which can call
983 * draw_vbo recursively, and before si_update_shaders, which uses
984 * current_rast_prim for this draw_vbo call. */
985 if (sctx->gs_shader.cso)
986 rast_prim = sctx->gs_shader.cso->gs_output_prim;
987 else if (sctx->tes_shader.cso)
988 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
989 else
990 rast_prim = info->mode;
991
992 if (rast_prim != sctx->current_rast_prim) {
993 sctx->current_rast_prim = rast_prim;
994 sctx->do_update_shaders = true;
995 }
996
997 if (sctx->gs_shader.cso) {
998 /* Determine whether the GS triangle strip adjacency fix should
999 * be applied. Rotate every other triangle if
1000 * - triangle strips with adjacency are fed to the GS and
1001 * - primitive restart is disabled (the rotation doesn't help
1002 * when the restart occurs after an odd number of triangles).
1003 */
1004 bool gs_tri_strip_adj_fix =
1005 !sctx->tes_shader.cso &&
1006 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1007 !info->primitive_restart;
1008
1009 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1010 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1011 sctx->do_update_shaders = true;
1012 }
1013 }
1014
1015 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1016 return;
1017
1018 if (!si_upload_graphics_shader_descriptors(sctx))
1019 return;
1020
1021 if (info->indexed) {
1022 /* Initialize the index buffer struct. */
1023 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
1024 ib.user_buffer = sctx->index_buffer.user_buffer;
1025 ib.index_size = sctx->index_buffer.index_size;
1026 ib.offset = sctx->index_buffer.offset;
1027
1028 /* Translate or upload, if needed. */
1029 /* 8-bit indices are supported on VI. */
1030 if (sctx->b.chip_class <= CIK && ib.index_size == 1) {
1031 struct pipe_resource *out_buffer = NULL;
1032 unsigned out_offset, start, count, start_offset;
1033 void *ptr;
1034
1035 si_get_draw_start_count(sctx, info, &start, &count);
1036 start_offset = start * ib.index_size;
1037
1038 u_upload_alloc(sctx->b.uploader, start_offset, count * 2, 256,
1039 &out_offset, &out_buffer, &ptr);
1040 if (!out_buffer) {
1041 pipe_resource_reference(&ib.buffer, NULL);
1042 return;
1043 }
1044
1045 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
1046 ib.offset + start_offset,
1047 count, ptr);
1048
1049 pipe_resource_reference(&ib.buffer, NULL);
1050 ib.user_buffer = NULL;
1051 ib.buffer = out_buffer;
1052 /* info->start will be added by the drawing code */
1053 ib.offset = out_offset - start_offset;
1054 ib.index_size = 2;
1055 } else if (ib.user_buffer && !ib.buffer) {
1056 unsigned start, count, start_offset;
1057
1058 si_get_draw_start_count(sctx, info, &start, &count);
1059 start_offset = start * ib.index_size;
1060
1061 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
1062 256, (char*)ib.user_buffer + start_offset,
1063 &ib.offset, &ib.buffer);
1064 if (!ib.buffer)
1065 return;
1066 /* info->start will be added by the drawing code */
1067 ib.offset -= start_offset;
1068 }
1069 }
1070
1071 /* VI reads index buffers through TC L2. */
1072 if (info->indexed && sctx->b.chip_class <= CIK &&
1073 r600_resource(ib.buffer)->TC_L2_dirty) {
1074 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1075 r600_resource(ib.buffer)->TC_L2_dirty = false;
1076 }
1077
1078 if (info->indirect && r600_resource(info->indirect)->TC_L2_dirty) {
1079 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1080 r600_resource(info->indirect)->TC_L2_dirty = false;
1081 }
1082
1083 if (info->indirect_params &&
1084 r600_resource(info->indirect_params)->TC_L2_dirty) {
1085 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1086 r600_resource(info->indirect_params)->TC_L2_dirty = false;
1087 }
1088
1089 /* Add buffer sizes for memory checking in need_cs_space. */
1090 if (sctx->emit_scratch_reloc && sctx->scratch_buffer)
1091 r600_context_add_resource_size(ctx, &sctx->scratch_buffer->b.b);
1092 if (info->indirect)
1093 r600_context_add_resource_size(ctx, info->indirect);
1094
1095 si_need_cs_space(sctx);
1096
1097 /* Since we've called r600_context_add_resource_size for vertex buffers,
1098 * this must be called after si_need_cs_space, because we must let
1099 * need_cs_space flush before we add buffers to the buffer list.
1100 */
1101 if (!si_upload_vertex_buffer_descriptors(sctx))
1102 return;
1103
1104 /* Flushed caches prior to emitting states. */
1105 if (sctx->b.flags)
1106 si_emit_cache_flush(sctx);
1107
1108 /* Emit states. */
1109 mask = sctx->dirty_atoms;
1110 while (mask) {
1111 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
1112
1113 atom->emit(&sctx->b, atom);
1114 }
1115 sctx->dirty_atoms = 0;
1116
1117 si_pm4_emit_dirty(sctx);
1118 si_emit_scratch_reloc(sctx);
1119 si_emit_rasterizer_prim_state(sctx);
1120 si_emit_draw_registers(sctx, info);
1121
1122 si_ce_pre_draw_synchronization(sctx);
1123
1124 si_emit_draw_packets(sctx, info, &ib);
1125
1126 si_ce_post_draw_synchronization(sctx);
1127
1128 if (sctx->trace_buf)
1129 si_trace_emit(sctx);
1130
1131 /* Workaround for a VGT hang when streamout is enabled.
1132 * It must be done after drawing. */
1133 if ((sctx->b.family == CHIP_HAWAII ||
1134 sctx->b.family == CHIP_TONGA ||
1135 sctx->b.family == CHIP_FIJI) &&
1136 r600_get_strmout_en(&sctx->b)) {
1137 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1138 }
1139
1140 /* Set the depth buffer as dirty. */
1141 if (sctx->framebuffer.state.zsbuf) {
1142 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1143 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1144
1145 if (!rtex->tc_compatible_htile)
1146 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1147
1148 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1149 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
1150 }
1151 if (sctx->framebuffer.compressed_cb_mask) {
1152 struct pipe_surface *surf;
1153 struct r600_texture *rtex;
1154 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1155
1156 do {
1157 unsigned i = u_bit_scan(&mask);
1158 surf = sctx->framebuffer.state.cbufs[i];
1159 rtex = (struct r600_texture*)surf->texture;
1160
1161 if (rtex->fmask.size)
1162 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1163 if (rtex->dcc_gather_statistics)
1164 rtex->separate_dcc_dirty = true;
1165 } while (mask);
1166 }
1167
1168 pipe_resource_reference(&ib.buffer, NULL);
1169 sctx->b.num_draw_calls++;
1170 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1171 sctx->b.num_spill_draw_calls++;
1172 }
1173
1174 void si_trace_emit(struct si_context *sctx)
1175 {
1176 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1177
1178 sctx->trace_id++;
1179 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
1180 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
1181 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1182 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1183 S_370_WR_CONFIRM(1) |
1184 S_370_ENGINE_SEL(V_370_ME));
1185 radeon_emit(cs, sctx->trace_buf->gpu_address);
1186 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
1187 radeon_emit(cs, sctx->trace_id);
1188 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1189 radeon_emit(cs, SI_ENCODE_TRACE_POINT(sctx->trace_id));
1190 }