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radeonsi: use a clever alignment for index buffer uploads
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "radeon/r600_cs.h"
29 #include "sid.h"
30
31 #include "util/u_index_modify.h"
32 #include "util/u_upload_mgr.h"
33 #include "util/u_prim.h"
34
35 #include "ac_debug.h"
36
37 static unsigned si_conv_pipe_prim(unsigned mode)
38 {
39 static const unsigned prim_conv[] = {
40 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
41 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
42 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
43 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
44 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
45 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
46 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
47 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
48 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
49 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
50 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
51 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
52 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
53 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
54 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
55 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
56 };
57 assert(mode < ARRAY_SIZE(prim_conv));
58 return prim_conv[mode];
59 }
60
61 static unsigned si_conv_prim_to_gs_out(unsigned mode)
62 {
63 static const int prim_conv[] = {
64 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
65 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
66 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
67 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
68 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
69 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
73 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
74 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
75 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
76 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
77 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
78 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
79 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
80 };
81 assert(mode < ARRAY_SIZE(prim_conv));
82
83 return prim_conv[mode];
84 }
85
86 /**
87 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
88 * LS.LDS_SIZE is shared by all 3 shader stages.
89 *
90 * The information about LDS and other non-compile-time parameters is then
91 * written to userdata SGPRs.
92 */
93 static void si_emit_derived_tess_state(struct si_context *sctx,
94 const struct pipe_draw_info *info,
95 unsigned *num_patches)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_shader_ctx_state *ls = &sctx->vs_shader;
99 /* The TES pointer will only be used for sctx->last_tcs.
100 * It would be wrong to think that TCS = TES. */
101 struct si_shader_selector *tcs =
102 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
103 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
104 unsigned num_tcs_input_cp = info->vertices_per_patch;
105 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
106 unsigned num_tcs_patch_outputs;
107 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
108 unsigned input_patch_size, output_patch_size, output_patch0_offset;
109 unsigned perpatch_output_offset, lds_size, ls_rsrc2;
110 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
111 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
112
113 if (sctx->last_ls == ls->current &&
114 sctx->last_tcs == tcs &&
115 sctx->last_tes_sh_base == tes_sh_base &&
116 sctx->last_num_tcs_input_cp == num_tcs_input_cp) {
117 *num_patches = sctx->last_num_patches;
118 return;
119 }
120
121 sctx->last_ls = ls->current;
122 sctx->last_tcs = tcs;
123 sctx->last_tes_sh_base = tes_sh_base;
124 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
125
126 /* This calculates how shader inputs and outputs among VS, TCS, and TES
127 * are laid out in LDS. */
128 num_tcs_inputs = util_last_bit64(ls->cso->outputs_written);
129
130 if (sctx->tcs_shader.cso) {
131 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
132 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
133 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
134 } else {
135 /* No TCS. Route varyings from LS to TES. */
136 num_tcs_outputs = num_tcs_inputs;
137 num_tcs_output_cp = num_tcs_input_cp;
138 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
139 }
140
141 input_vertex_size = num_tcs_inputs * 16;
142 output_vertex_size = num_tcs_outputs * 16;
143
144 input_patch_size = num_tcs_input_cp * input_vertex_size;
145
146 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
147 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
148
149 /* Ensure that we only need one wave per SIMD so we don't need to check
150 * resource usage. Also ensures that the number of tcs in and out
151 * vertices per threadgroup are at most 256.
152 */
153 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
154
155 /* Make sure that the data fits in LDS. This assumes the shaders only
156 * use LDS for the inputs and outputs.
157 */
158 hardware_lds_size = sctx->b.chip_class >= CIK ? 65536 : 32768;
159 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
160 output_patch_size));
161
162 /* Make sure the output data fits in the offchip buffer */
163 *num_patches = MIN2(*num_patches,
164 (sctx->screen->tess_offchip_block_dw_size * 4) /
165 output_patch_size);
166
167 /* Not necessary for correctness, but improves performance. The
168 * specific value is taken from the proprietary driver.
169 */
170 *num_patches = MIN2(*num_patches, 40);
171
172 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
173 if (sctx->b.chip_class == SI) {
174 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
175 *num_patches = MIN2(*num_patches, one_wave);
176 }
177
178 sctx->last_num_patches = *num_patches;
179
180 output_patch0_offset = input_patch_size * *num_patches;
181 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
182
183 lds_size = output_patch0_offset + output_patch_size * *num_patches;
184 ls_rsrc2 = ls->current->config.rsrc2;
185
186 if (sctx->b.chip_class >= CIK) {
187 assert(lds_size <= 65536);
188 lds_size = align(lds_size, 512) / 512;
189 } else {
190 assert(lds_size <= 32768);
191 lds_size = align(lds_size, 256) / 256;
192 }
193 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
194 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
195
196 /* Due to a hw bug, RSRC2_LS must be written twice with another
197 * LS register written in between. */
198 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
199 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
200 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
201 radeon_emit(cs, ls->current->config.rsrc1);
202 radeon_emit(cs, ls_rsrc2);
203
204 /* Compute userdata SGPRs. */
205 assert(((input_vertex_size / 4) & ~0xff) == 0);
206 assert(((output_vertex_size / 4) & ~0xff) == 0);
207 assert(((input_patch_size / 4) & ~0x1fff) == 0);
208 assert(((output_patch_size / 4) & ~0x1fff) == 0);
209 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
210 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
211 assert(num_tcs_input_cp <= 32);
212 assert(num_tcs_output_cp <= 32);
213
214 tcs_in_layout = (input_patch_size / 4) |
215 ((input_vertex_size / 4) << 13);
216 tcs_out_layout = (output_patch_size / 4) |
217 ((output_vertex_size / 4) << 13);
218 tcs_out_offsets = (output_patch0_offset / 16) |
219 ((perpatch_output_offset / 16) << 16);
220 offchip_layout = (pervertex_output_patch_size * *num_patches << 16) |
221 (num_tcs_output_cp << 9) | *num_patches;
222
223 /* Set them for LS. */
224 radeon_set_sh_reg(cs,
225 R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4,
226 tcs_in_layout);
227
228 /* Set them for TCS. */
229 radeon_set_sh_reg_seq(cs,
230 R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
231 radeon_emit(cs, offchip_layout);
232 radeon_emit(cs, tcs_out_offsets);
233 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
234 radeon_emit(cs, tcs_in_layout);
235
236 /* Set them for TES. */
237 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 1);
238 radeon_emit(cs, offchip_layout);
239
240 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
241 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
242 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
243
244 if (sctx->b.chip_class >= CIK)
245 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
246 ls_hs_config);
247 else
248 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
249 ls_hs_config);
250 }
251
252 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
253 {
254 switch (info->mode) {
255 case PIPE_PRIM_PATCHES:
256 return info->count / info->vertices_per_patch;
257 case R600_PRIM_RECTANGLE_LIST:
258 return info->count / 3;
259 default:
260 return u_prims_for_vertices(info->mode, info->count);
261 }
262 }
263
264 static unsigned
265 si_get_init_multi_vgt_param(struct si_screen *sscreen,
266 union si_vgt_param_key *key)
267 {
268 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
269 unsigned max_primgroup_in_wave = 2;
270
271 /* SWITCH_ON_EOP(0) is always preferable. */
272 bool wd_switch_on_eop = false;
273 bool ia_switch_on_eop = false;
274 bool ia_switch_on_eoi = false;
275 bool partial_vs_wave = false;
276 bool partial_es_wave = false;
277
278 if (key->u.uses_tess) {
279 /* SWITCH_ON_EOI must be set if PrimID is used. */
280 if (key->u.tcs_tes_uses_prim_id)
281 ia_switch_on_eoi = true;
282
283 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
284 if ((sscreen->b.family == CHIP_TAHITI ||
285 sscreen->b.family == CHIP_PITCAIRN ||
286 sscreen->b.family == CHIP_BONAIRE) &&
287 key->u.uses_gs)
288 partial_vs_wave = true;
289
290 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
291 if (sscreen->has_distributed_tess) {
292 if (key->u.uses_gs) {
293 partial_es_wave = true;
294
295 /* GPU hang workaround. */
296 if (sscreen->b.family == CHIP_TONGA ||
297 sscreen->b.family == CHIP_FIJI ||
298 sscreen->b.family == CHIP_POLARIS10 ||
299 sscreen->b.family == CHIP_POLARIS11)
300 partial_vs_wave = true;
301 } else {
302 partial_vs_wave = true;
303 }
304 }
305 }
306
307 /* This is a hardware requirement. */
308 if (key->u.line_stipple_enabled ||
309 (sscreen->b.debug_flags & DBG_SWITCH_ON_EOP)) {
310 ia_switch_on_eop = true;
311 wd_switch_on_eop = true;
312 }
313
314 if (sscreen->b.chip_class >= CIK) {
315 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
316 * 4 shader engines. Set 1 to pass the assertion below.
317 * The other cases are hardware requirements.
318 *
319 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
320 * for points, line strips, and tri strips.
321 */
322 if (sscreen->b.info.max_se < 4 ||
323 key->u.prim == PIPE_PRIM_POLYGON ||
324 key->u.prim == PIPE_PRIM_LINE_LOOP ||
325 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
326 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
327 (key->u.primitive_restart &&
328 (sscreen->b.family < CHIP_POLARIS10 ||
329 (key->u.prim != PIPE_PRIM_POINTS &&
330 key->u.prim != PIPE_PRIM_LINE_STRIP &&
331 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
332 key->u.count_from_stream_output)
333 wd_switch_on_eop = true;
334
335 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
336 * We don't know that for indirect drawing, so treat it as
337 * always problematic. */
338 if (sscreen->b.family == CHIP_HAWAII &&
339 key->u.uses_instancing)
340 wd_switch_on_eop = true;
341
342 /* Performance recommendation for 4 SE Gfx7-8 parts if
343 * instances are smaller than a primgroup.
344 * Assume indirect draws always use small instances.
345 * This is needed for good VS wave utilization.
346 */
347 if (sscreen->b.chip_class <= VI &&
348 sscreen->b.info.max_se == 4 &&
349 key->u.multi_instances_smaller_than_primgroup)
350 wd_switch_on_eop = true;
351
352 /* Required on CIK and later. */
353 if (sscreen->b.info.max_se > 2 && !wd_switch_on_eop)
354 ia_switch_on_eoi = true;
355
356 /* Required by Hawaii and, for some special cases, by VI. */
357 if (ia_switch_on_eoi &&
358 (sscreen->b.family == CHIP_HAWAII ||
359 (sscreen->b.chip_class == VI &&
360 (key->u.uses_gs || max_primgroup_in_wave != 2))))
361 partial_vs_wave = true;
362
363 /* Instancing bug on Bonaire. */
364 if (sscreen->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
365 key->u.uses_instancing)
366 partial_vs_wave = true;
367
368 /* If the WD switch is false, the IA switch must be false too. */
369 assert(wd_switch_on_eop || !ia_switch_on_eop);
370 }
371
372 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
373 if (ia_switch_on_eoi)
374 partial_es_wave = true;
375
376 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
377 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
378 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
379 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
380 S_028AA8_WD_SWITCH_ON_EOP(sscreen->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
381 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->b.chip_class >= VI ?
382 max_primgroup_in_wave : 0);
383 }
384
385 void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
386 {
387 for (int prim = 0; prim <= R600_PRIM_RECTANGLE_LIST; prim++)
388 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
389 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
390 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
391 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
392 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
393 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
394 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
395 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
396 union si_vgt_param_key key;
397
398 key.index = 0;
399 key.u.prim = prim;
400 key.u.uses_instancing = uses_instancing;
401 key.u.multi_instances_smaller_than_primgroup = multi_instances;
402 key.u.primitive_restart = primitive_restart;
403 key.u.count_from_stream_output = count_from_so;
404 key.u.line_stipple_enabled = line_stipple;
405 key.u.uses_tess = uses_tess;
406 key.u.tcs_tes_uses_prim_id = tess_uses_primid;
407 key.u.uses_gs = uses_gs;
408
409 sctx->ia_multi_vgt_param[key.index] =
410 si_get_init_multi_vgt_param(sctx->screen, &key);
411 }
412 }
413
414 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
415 const struct pipe_draw_info *info,
416 unsigned num_patches)
417 {
418 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
419 unsigned primgroup_size;
420 unsigned ia_multi_vgt_param;
421
422 if (sctx->tes_shader.cso) {
423 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
424 } else if (sctx->gs_shader.cso) {
425 primgroup_size = 64; /* recommended with a GS */
426 } else {
427 primgroup_size = 128; /* recommended without a GS and tess */
428 }
429
430 key.u.prim = info->mode;
431 key.u.uses_instancing = info->indirect || info->instance_count > 1;
432 key.u.multi_instances_smaller_than_primgroup =
433 info->indirect ||
434 (info->instance_count > 1 &&
435 (info->count_from_stream_output ||
436 si_num_prims_for_vertices(info) < primgroup_size));
437 key.u.primitive_restart = info->primitive_restart;
438 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
439
440 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
441 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
442
443 if (sctx->gs_shader.cso) {
444 /* GS requirement. */
445 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
446 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
447
448 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
449 * The hw doc says all multi-SE chips are affected, but Vulkan
450 * only applies it to Hawaii. Do what Vulkan does.
451 */
452 if (sctx->b.family == CHIP_HAWAII &&
453 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
454 (info->indirect ||
455 (info->instance_count > 1 &&
456 (info->count_from_stream_output ||
457 si_num_prims_for_vertices(info) <= 1))))
458 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
459 }
460
461 return ia_multi_vgt_param;
462 }
463
464 /* rast_prim is the primitive type after GS. */
465 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
466 {
467 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
468 unsigned rast_prim = sctx->current_rast_prim;
469 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
470
471 /* Skip this if not rendering lines. */
472 if (rast_prim != PIPE_PRIM_LINES &&
473 rast_prim != PIPE_PRIM_LINE_LOOP &&
474 rast_prim != PIPE_PRIM_LINE_STRIP &&
475 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
476 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
477 return;
478
479 if (rast_prim == sctx->last_rast_prim &&
480 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
481 return;
482
483 /* For lines, reset the stipple pattern at each primitive. Otherwise,
484 * reset the stipple pattern at each packet (line strips, line loops).
485 */
486 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
487 rs->pa_sc_line_stipple |
488 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
489
490 sctx->last_rast_prim = rast_prim;
491 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
492 }
493
494 static void si_emit_draw_registers(struct si_context *sctx,
495 const struct pipe_draw_info *info)
496 {
497 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
498 unsigned prim = si_conv_pipe_prim(info->mode);
499 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
500 unsigned ia_multi_vgt_param, num_patches = 0;
501
502 if (sctx->tes_shader.cso)
503 si_emit_derived_tess_state(sctx, info, &num_patches);
504
505 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
506
507 /* Draw state. */
508 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
509 if (sctx->b.chip_class >= CIK)
510 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
511 else
512 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
513
514 sctx->last_multi_vgt_param = ia_multi_vgt_param;
515 }
516 if (prim != sctx->last_prim) {
517 if (sctx->b.chip_class >= CIK)
518 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
519 else
520 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
521
522 sctx->last_prim = prim;
523 }
524
525 if (gs_out_prim != sctx->last_gs_out_prim) {
526 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
527 sctx->last_gs_out_prim = gs_out_prim;
528 }
529
530 /* Primitive restart. */
531 if (info->primitive_restart != sctx->last_primitive_restart_en) {
532 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
533 sctx->last_primitive_restart_en = info->primitive_restart;
534
535 }
536 if (info->primitive_restart &&
537 (info->restart_index != sctx->last_restart_index ||
538 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
539 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
540 info->restart_index);
541 sctx->last_restart_index = info->restart_index;
542 }
543 }
544
545 static void si_emit_draw_packets(struct si_context *sctx,
546 const struct pipe_draw_info *info,
547 const struct pipe_index_buffer *ib)
548 {
549 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
550 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
551 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
552 uint32_t index_max_size = 0;
553 uint64_t index_va = 0;
554
555 if (info->count_from_stream_output) {
556 struct r600_so_target *t =
557 (struct r600_so_target*)info->count_from_stream_output;
558 uint64_t va = t->buf_filled_size->gpu_address +
559 t->buf_filled_size_offset;
560
561 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
562 t->stride_in_dw);
563
564 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
565 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
566 COPY_DATA_DST_SEL(COPY_DATA_REG) |
567 COPY_DATA_WR_CONFIRM);
568 radeon_emit(cs, va); /* src address lo */
569 radeon_emit(cs, va >> 32); /* src address hi */
570 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
571 radeon_emit(cs, 0); /* unused */
572
573 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
574 t->buf_filled_size, RADEON_USAGE_READ,
575 RADEON_PRIO_SO_FILLED_SIZE);
576 }
577
578 /* draw packet */
579 if (info->indexed) {
580 if (ib->index_size != sctx->last_index_size) {
581 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
582
583 /* index type */
584 switch (ib->index_size) {
585 case 1:
586 radeon_emit(cs, V_028A7C_VGT_INDEX_8);
587 break;
588 case 2:
589 radeon_emit(cs, V_028A7C_VGT_INDEX_16 |
590 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
591 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
592 break;
593 case 4:
594 radeon_emit(cs, V_028A7C_VGT_INDEX_32 |
595 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
596 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
597 break;
598 default:
599 assert(!"unreachable");
600 return;
601 }
602
603 sctx->last_index_size = ib->index_size;
604 }
605
606 index_max_size = (ib->buffer->width0 - ib->offset) /
607 ib->index_size;
608 index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
609
610 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
611 (struct r600_resource *)ib->buffer,
612 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
613 } else {
614 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
615 * so the state must be re-emitted before the next indexed draw.
616 */
617 if (sctx->b.chip_class >= CIK)
618 sctx->last_index_size = -1;
619 }
620
621 if (!info->indirect) {
622 int base_vertex;
623
624 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
625 radeon_emit(cs, info->instance_count);
626
627 /* Base vertex and start instance. */
628 base_vertex = info->indexed ? info->index_bias : info->start;
629
630 if (base_vertex != sctx->last_base_vertex ||
631 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
632 info->start_instance != sctx->last_start_instance ||
633 info->drawid != sctx->last_drawid ||
634 sh_base_reg != sctx->last_sh_base_reg) {
635 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
636 radeon_emit(cs, base_vertex);
637 radeon_emit(cs, info->start_instance);
638 radeon_emit(cs, info->drawid);
639
640 sctx->last_base_vertex = base_vertex;
641 sctx->last_start_instance = info->start_instance;
642 sctx->last_drawid = info->drawid;
643 sctx->last_sh_base_reg = sh_base_reg;
644 }
645 } else {
646 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
647
648 assert(indirect_va % 8 == 0);
649
650 si_invalidate_draw_sh_constants(sctx);
651
652 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
653 radeon_emit(cs, 1);
654 radeon_emit(cs, indirect_va);
655 radeon_emit(cs, indirect_va >> 32);
656
657 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
658 (struct r600_resource *)info->indirect,
659 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
660 }
661
662 if (info->indirect) {
663 unsigned di_src_sel = info->indexed ? V_0287F0_DI_SRC_SEL_DMA
664 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
665
666 assert(info->indirect_offset % 4 == 0);
667
668 if (info->indexed) {
669 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
670 radeon_emit(cs, index_va);
671 radeon_emit(cs, index_va >> 32);
672
673 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
674 radeon_emit(cs, index_max_size);
675 }
676
677 if (!sctx->screen->has_draw_indirect_multi) {
678 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT
679 : PKT3_DRAW_INDIRECT,
680 3, render_cond_bit));
681 radeon_emit(cs, info->indirect_offset);
682 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
683 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
684 radeon_emit(cs, di_src_sel);
685 } else {
686 uint64_t count_va = 0;
687
688 if (info->indirect_params) {
689 struct r600_resource *params_buf =
690 (struct r600_resource *)info->indirect_params;
691
692 radeon_add_to_buffer_list(
693 &sctx->b, &sctx->b.gfx, params_buf,
694 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
695
696 count_va = params_buf->gpu_address + info->indirect_params_offset;
697 }
698
699 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
700 PKT3_DRAW_INDIRECT_MULTI,
701 8, render_cond_bit));
702 radeon_emit(cs, info->indirect_offset);
703 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
704 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
705 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
706 S_2C3_DRAW_INDEX_ENABLE(1) |
707 S_2C3_COUNT_INDIRECT_ENABLE(!!info->indirect_params));
708 radeon_emit(cs, info->indirect_count);
709 radeon_emit(cs, count_va);
710 radeon_emit(cs, count_va >> 32);
711 radeon_emit(cs, info->indirect_stride);
712 radeon_emit(cs, di_src_sel);
713 }
714 } else {
715 if (info->indexed) {
716 index_va += info->start * ib->index_size;
717
718 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
719 radeon_emit(cs, index_max_size);
720 radeon_emit(cs, index_va);
721 radeon_emit(cs, (index_va >> 32UL) & 0xFF);
722 radeon_emit(cs, info->count);
723 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
724 } else {
725 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
726 radeon_emit(cs, info->count);
727 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
728 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
729 }
730 }
731 }
732
733 static void si_emit_surface_sync(struct r600_common_context *rctx,
734 unsigned cp_coher_cntl)
735 {
736 struct radeon_winsys_cs *cs = rctx->gfx.cs;
737
738 /* ACQUIRE_MEM is only required on a compute ring. */
739 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
740 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
741 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
742 radeon_emit(cs, 0); /* CP_COHER_BASE */
743 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
744 }
745
746 void si_emit_cache_flush(struct si_context *sctx)
747 {
748 struct r600_common_context *rctx = &sctx->b;
749 struct radeon_winsys_cs *cs = rctx->gfx.cs;
750 uint32_t cp_coher_cntl = 0;
751
752 if (rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
753 SI_CONTEXT_FLUSH_AND_INV_DB))
754 sctx->b.num_fb_cache_flushes++;
755
756 /* SI has a bug that it always flushes ICACHE and KCACHE if either
757 * bit is set. An alternative way is to write SQC_CACHES, but that
758 * doesn't seem to work reliably. Since the bug doesn't affect
759 * correctness (it only does more work than necessary) and
760 * the performance impact is likely negligible, there is no plan
761 * to add a workaround for it.
762 */
763
764 if (rctx->flags & SI_CONTEXT_INV_ICACHE)
765 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
766 if (rctx->flags & SI_CONTEXT_INV_SMEM_L1)
767 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
768
769 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
770 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
771 S_0085F0_CB0_DEST_BASE_ENA(1) |
772 S_0085F0_CB1_DEST_BASE_ENA(1) |
773 S_0085F0_CB2_DEST_BASE_ENA(1) |
774 S_0085F0_CB3_DEST_BASE_ENA(1) |
775 S_0085F0_CB4_DEST_BASE_ENA(1) |
776 S_0085F0_CB5_DEST_BASE_ENA(1) |
777 S_0085F0_CB6_DEST_BASE_ENA(1) |
778 S_0085F0_CB7_DEST_BASE_ENA(1);
779
780 /* Necessary for DCC */
781 if (rctx->chip_class == VI)
782 r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
783 0, 0, NULL, 0, 0, 0);
784
785 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
786 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
787 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
788 }
789 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
790 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
791 S_0085F0_DB_DEST_BASE_ENA(1);
792
793 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
794 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
795 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
796 }
797
798 /* Wait for shader engines to go idle.
799 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
800 * for everything including CB/DB cache flushes.
801 */
802 if (!(rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
803 SI_CONTEXT_FLUSH_AND_INV_DB))) {
804 if (rctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
805 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
806 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
807 /* Only count explicit shader flushes, not implicit ones
808 * done by SURFACE_SYNC.
809 */
810 rctx->num_vs_flushes++;
811 rctx->num_ps_flushes++;
812 } else if (rctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
813 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
814 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
815 rctx->num_vs_flushes++;
816 }
817 }
818
819 if (rctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
820 sctx->compute_is_busy) {
821 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
822 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
823 rctx->num_cs_flushes++;
824 sctx->compute_is_busy = false;
825 }
826
827 /* VGT state synchronization. */
828 if (rctx->flags & SI_CONTEXT_VGT_FLUSH) {
829 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
830 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
831 }
832 if (rctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
833 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
834 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
835 }
836
837 /* Make sure ME is idle (it executes most packets) before continuing.
838 * This prevents read-after-write hazards between PFP and ME.
839 */
840 if (cp_coher_cntl ||
841 (rctx->flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
842 SI_CONTEXT_INV_VMEM_L1 |
843 SI_CONTEXT_INV_GLOBAL_L2 |
844 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
845 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
846 radeon_emit(cs, 0);
847 }
848
849 /* When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
850 * waits for idle. Therefore, it should be last. SURFACE_SYNC is done
851 * in PFP.
852 *
853 * cp_coher_cntl should contain all necessary flags except TC flags
854 * at this point.
855 *
856 * SI-CIK don't support L2 write-back.
857 */
858 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2 ||
859 (rctx->chip_class <= CIK &&
860 (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
861 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
862 * WB must be set on VI+ when TC_ACTION is set.
863 */
864 si_emit_surface_sync(rctx, cp_coher_cntl |
865 S_0085F0_TC_ACTION_ENA(1) |
866 S_0085F0_TCL1_ACTION_ENA(1) |
867 S_0301F0_TC_WB_ACTION_ENA(rctx->chip_class >= VI));
868 cp_coher_cntl = 0;
869 sctx->b.num_L2_invalidates++;
870 } else {
871 /* L1 invalidation and L2 writeback must be done separately,
872 * because both operations can't be done together.
873 */
874 if (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
875 /* WB = write-back
876 * NC = apply to non-coherent MTYPEs
877 * (i.e. MTYPE <= 1, which is what we use everywhere)
878 *
879 * WB doesn't work without NC.
880 */
881 si_emit_surface_sync(rctx, cp_coher_cntl |
882 S_0301F0_TC_WB_ACTION_ENA(1) |
883 S_0301F0_TC_NC_ACTION_ENA(1));
884 cp_coher_cntl = 0;
885 sctx->b.num_L2_writebacks++;
886 }
887 if (rctx->flags & SI_CONTEXT_INV_VMEM_L1) {
888 /* Invalidate per-CU VMEM L1. */
889 si_emit_surface_sync(rctx, cp_coher_cntl |
890 S_0085F0_TCL1_ACTION_ENA(1));
891 cp_coher_cntl = 0;
892 }
893 }
894
895 /* If TC flushes haven't cleared this... */
896 if (cp_coher_cntl)
897 si_emit_surface_sync(rctx, cp_coher_cntl);
898
899 if (rctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
900 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
901 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
902 EVENT_INDEX(0));
903 } else if (rctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
904 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
905 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
906 EVENT_INDEX(0));
907 }
908
909 rctx->flags = 0;
910 }
911
912 static void si_get_draw_start_count(struct si_context *sctx,
913 const struct pipe_draw_info *info,
914 unsigned *start, unsigned *count)
915 {
916 if (info->indirect) {
917 struct r600_resource *indirect =
918 (struct r600_resource*)info->indirect;
919 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
920 indirect, PIPE_TRANSFER_READ);
921 data += info->indirect_offset/sizeof(int);
922 *start = data[2];
923 *count = data[0];
924 } else {
925 *start = info->start;
926 *count = info->count;
927 }
928 }
929
930 void si_ce_pre_draw_synchronization(struct si_context *sctx)
931 {
932 if (sctx->ce_need_synchronization) {
933 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
934 radeon_emit(sctx->ce_ib, 1);
935
936 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
937 radeon_emit(sctx->b.gfx.cs, 1);
938 }
939 }
940
941 void si_ce_post_draw_synchronization(struct si_context *sctx)
942 {
943 if (sctx->ce_need_synchronization) {
944 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
945 radeon_emit(sctx->b.gfx.cs, 0);
946
947 sctx->ce_need_synchronization = false;
948 }
949 }
950
951 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
952 {
953 struct si_context *sctx = (struct si_context *)ctx;
954 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
955 struct pipe_index_buffer ib = {};
956 unsigned mask, dirty_tex_counter, rast_prim;
957
958 if (likely(!info->indirect)) {
959 /* SI-CI treat instance_count==0 as instance_count==1. There is
960 * no workaround for indirect draws, but we can at least skip
961 * direct draws.
962 */
963 if (unlikely(!info->instance_count))
964 return;
965
966 /* Handle count == 0. */
967 if (unlikely(!info->count &&
968 (info->indexed || !info->count_from_stream_output)))
969 return;
970 }
971
972 if (unlikely(!sctx->vs_shader.cso)) {
973 assert(0);
974 return;
975 }
976 if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
977 assert(0);
978 return;
979 }
980 if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
981 assert(0);
982 return;
983 }
984
985 /* Recompute and re-emit the texture resource states if needed. */
986 dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_counter);
987 if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_counter)) {
988 sctx->b.last_dirty_tex_counter = dirty_tex_counter;
989 sctx->framebuffer.dirty_cbufs |=
990 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
991 sctx->framebuffer.dirty_zsbuf = true;
992 sctx->framebuffer.do_update_surf_dirtiness = true;
993 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
994 si_update_all_texture_descriptors(sctx);
995 }
996
997 si_decompress_graphics_textures(sctx);
998
999 /* Set the rasterization primitive type.
1000 *
1001 * This must be done after si_decompress_textures, which can call
1002 * draw_vbo recursively, and before si_update_shaders, which uses
1003 * current_rast_prim for this draw_vbo call. */
1004 if (sctx->gs_shader.cso)
1005 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1006 else if (sctx->tes_shader.cso)
1007 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1008 else
1009 rast_prim = info->mode;
1010
1011 if (rast_prim != sctx->current_rast_prim) {
1012 sctx->current_rast_prim = rast_prim;
1013 sctx->do_update_shaders = true;
1014 }
1015
1016 if (sctx->gs_shader.cso) {
1017 /* Determine whether the GS triangle strip adjacency fix should
1018 * be applied. Rotate every other triangle if
1019 * - triangle strips with adjacency are fed to the GS and
1020 * - primitive restart is disabled (the rotation doesn't help
1021 * when the restart occurs after an odd number of triangles).
1022 */
1023 bool gs_tri_strip_adj_fix =
1024 !sctx->tes_shader.cso &&
1025 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1026 !info->primitive_restart;
1027
1028 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1029 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1030 sctx->do_update_shaders = true;
1031 }
1032 }
1033
1034 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1035 return;
1036
1037 if (!si_upload_graphics_shader_descriptors(sctx))
1038 return;
1039
1040 if (info->indexed) {
1041 /* Initialize the index buffer struct. */
1042 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
1043 ib.user_buffer = sctx->index_buffer.user_buffer;
1044 ib.index_size = sctx->index_buffer.index_size;
1045 ib.offset = sctx->index_buffer.offset;
1046
1047 /* Translate or upload, if needed. */
1048 /* 8-bit indices are supported on VI. */
1049 if (sctx->b.chip_class <= CIK && ib.index_size == 1) {
1050 struct pipe_resource *out_buffer = NULL;
1051 unsigned out_offset, start, count, start_offset, size;
1052 void *ptr;
1053
1054 si_get_draw_start_count(sctx, info, &start, &count);
1055 start_offset = start * ib.index_size;
1056 size = count * 2;
1057
1058 u_upload_alloc(ctx->stream_uploader, start_offset,
1059 size,
1060 si_optimal_tcc_alignment(sctx, size),
1061 &out_offset, &out_buffer, &ptr);
1062 if (!out_buffer) {
1063 pipe_resource_reference(&ib.buffer, NULL);
1064 return;
1065 }
1066
1067 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
1068 ib.offset + start_offset,
1069 count, ptr);
1070
1071 pipe_resource_reference(&ib.buffer, NULL);
1072 ib.user_buffer = NULL;
1073 ib.buffer = out_buffer;
1074 /* info->start will be added by the drawing code */
1075 ib.offset = out_offset - start_offset;
1076 ib.index_size = 2;
1077 } else if (ib.user_buffer && !ib.buffer) {
1078 unsigned start, count, start_offset;
1079
1080 si_get_draw_start_count(sctx, info, &start, &count);
1081 start_offset = start * ib.index_size;
1082
1083 u_upload_data(ctx->stream_uploader, start_offset,
1084 count * ib.index_size,
1085 sctx->screen->b.info.tcc_cache_line_size,
1086 (char*)ib.user_buffer + start_offset,
1087 &ib.offset, &ib.buffer);
1088 if (!ib.buffer)
1089 return;
1090 /* info->start will be added by the drawing code */
1091 ib.offset -= start_offset;
1092 } else if (sctx->b.chip_class <= CIK &&
1093 r600_resource(ib.buffer)->TC_L2_dirty) {
1094 /* VI reads index buffers through TC L2, so it doesn't
1095 * need this. */
1096 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1097 r600_resource(ib.buffer)->TC_L2_dirty = false;
1098 }
1099 }
1100
1101 if (info->indirect) {
1102 /* Add the buffer size for memory checking in need_cs_space. */
1103 r600_context_add_resource_size(ctx, info->indirect);
1104
1105 if (r600_resource(info->indirect)->TC_L2_dirty) {
1106 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1107 r600_resource(info->indirect)->TC_L2_dirty = false;
1108 }
1109
1110 if (info->indirect_params &&
1111 r600_resource(info->indirect_params)->TC_L2_dirty) {
1112 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1113 r600_resource(info->indirect_params)->TC_L2_dirty = false;
1114 }
1115 }
1116
1117 si_need_cs_space(sctx);
1118
1119 /* Since we've called r600_context_add_resource_size for vertex buffers,
1120 * this must be called after si_need_cs_space, because we must let
1121 * need_cs_space flush before we add buffers to the buffer list.
1122 */
1123 if (!si_upload_vertex_buffer_descriptors(sctx))
1124 return;
1125
1126 /* Flush caches before the first state atom, which does L2 prefetches. */
1127 if (sctx->b.flags)
1128 si_emit_cache_flush(sctx);
1129
1130 /* Emit state atoms. */
1131 mask = sctx->dirty_atoms;
1132 while (mask) {
1133 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
1134
1135 atom->emit(&sctx->b, atom);
1136 }
1137 sctx->dirty_atoms = 0;
1138
1139 /* Emit states. */
1140 mask = sctx->dirty_states;
1141 while (mask) {
1142 unsigned i = u_bit_scan(&mask);
1143 struct si_pm4_state *state = sctx->queued.array[i];
1144
1145 if (!state || sctx->emitted.array[i] == state)
1146 continue;
1147
1148 si_pm4_emit(sctx, state);
1149 sctx->emitted.array[i] = state;
1150 }
1151 sctx->dirty_states = 0;
1152
1153 si_emit_rasterizer_prim_state(sctx);
1154 si_emit_draw_registers(sctx, info);
1155
1156 si_ce_pre_draw_synchronization(sctx);
1157 si_emit_draw_packets(sctx, info, &ib);
1158 si_ce_post_draw_synchronization(sctx);
1159
1160 if (sctx->trace_buf)
1161 si_trace_emit(sctx);
1162
1163 /* Workaround for a VGT hang when streamout is enabled.
1164 * It must be done after drawing. */
1165 if ((sctx->b.family == CHIP_HAWAII ||
1166 sctx->b.family == CHIP_TONGA ||
1167 sctx->b.family == CHIP_FIJI) &&
1168 r600_get_strmout_en(&sctx->b)) {
1169 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1170 }
1171
1172 if (sctx->framebuffer.do_update_surf_dirtiness) {
1173 /* Set the depth buffer as dirty. */
1174 if (sctx->framebuffer.state.zsbuf) {
1175 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1176 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1177
1178 if (!rtex->tc_compatible_htile)
1179 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1180
1181 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1182 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
1183 }
1184 if (sctx->framebuffer.compressed_cb_mask) {
1185 struct pipe_surface *surf;
1186 struct r600_texture *rtex;
1187 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1188
1189 do {
1190 unsigned i = u_bit_scan(&mask);
1191 surf = sctx->framebuffer.state.cbufs[i];
1192 rtex = (struct r600_texture*)surf->texture;
1193
1194 if (rtex->fmask.size)
1195 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1196 if (rtex->dcc_gather_statistics)
1197 rtex->separate_dcc_dirty = true;
1198 } while (mask);
1199 }
1200 sctx->framebuffer.do_update_surf_dirtiness = false;
1201 }
1202
1203 pipe_resource_reference(&ib.buffer, NULL);
1204 sctx->b.num_draw_calls++;
1205 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1206 sctx->b.num_spill_draw_calls++;
1207 }
1208
1209 void si_trace_emit(struct si_context *sctx)
1210 {
1211 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1212
1213 sctx->trace_id++;
1214 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
1215 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
1216 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1217 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1218 S_370_WR_CONFIRM(1) |
1219 S_370_ENGINE_SEL(V_370_ME));
1220 radeon_emit(cs, sctx->trace_buf->gpu_address);
1221 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
1222 radeon_emit(cs, sctx->trace_id);
1223 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1224 radeon_emit(cs, AC_ENCODE_TRACE_POINT(sctx->trace_id));
1225 }