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radeonsi/gfx10: implement gfx10_emit_cache_flush
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32 #include "util/u_suballoc.h"
33
34 #include "ac_debug.h"
35
36 /* special primitive types */
37 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
38
39 static unsigned si_conv_pipe_prim(unsigned mode)
40 {
41 static const unsigned prim_conv[] = {
42 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
43 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
44 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
45 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
46 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
47 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
48 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
49 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
50 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
51 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
52 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
53 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
54 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
55 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
56 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
57 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
58 };
59 assert(mode < ARRAY_SIZE(prim_conv));
60 return prim_conv[mode];
61 }
62
63 /**
64 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
65 * LS.LDS_SIZE is shared by all 3 shader stages.
66 *
67 * The information about LDS and other non-compile-time parameters is then
68 * written to userdata SGPRs.
69 */
70 static void si_emit_derived_tess_state(struct si_context *sctx,
71 const struct pipe_draw_info *info,
72 unsigned *num_patches)
73 {
74 struct radeon_cmdbuf *cs = sctx->gfx_cs;
75 struct si_shader *ls_current;
76 struct si_shader_selector *ls;
77 /* The TES pointer will only be used for sctx->last_tcs.
78 * It would be wrong to think that TCS = TES. */
79 struct si_shader_selector *tcs =
80 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
81 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
82 bool has_primid_instancing_bug = sctx->chip_class == GFX6 &&
83 sctx->screen->info.max_se == 1;
84 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
85 unsigned num_tcs_input_cp = info->vertices_per_patch;
86 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
87 unsigned num_tcs_patch_outputs;
88 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
89 unsigned input_patch_size, output_patch_size, output_patch0_offset;
90 unsigned perpatch_output_offset, lds_size;
91 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
92 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
93
94 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
95 if (sctx->chip_class >= GFX9) {
96 if (sctx->tcs_shader.cso)
97 ls_current = sctx->tcs_shader.current;
98 else
99 ls_current = sctx->fixed_func_tcs_shader.current;
100
101 ls = ls_current->key.part.tcs.ls;
102 } else {
103 ls_current = sctx->vs_shader.current;
104 ls = sctx->vs_shader.cso;
105 }
106
107 if (sctx->last_ls == ls_current &&
108 sctx->last_tcs == tcs &&
109 sctx->last_tes_sh_base == tes_sh_base &&
110 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
111 (!has_primid_instancing_bug ||
112 (sctx->last_tess_uses_primid == tess_uses_primid))) {
113 *num_patches = sctx->last_num_patches;
114 return;
115 }
116
117 sctx->last_ls = ls_current;
118 sctx->last_tcs = tcs;
119 sctx->last_tes_sh_base = tes_sh_base;
120 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
121 sctx->last_tess_uses_primid = tess_uses_primid;
122
123 /* This calculates how shader inputs and outputs among VS, TCS, and TES
124 * are laid out in LDS. */
125 num_tcs_inputs = util_last_bit64(ls->outputs_written);
126
127 if (sctx->tcs_shader.cso) {
128 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
129 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
130 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
131 } else {
132 /* No TCS. Route varyings from LS to TES. */
133 num_tcs_outputs = num_tcs_inputs;
134 num_tcs_output_cp = num_tcs_input_cp;
135 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
136 }
137
138 input_vertex_size = ls->lshs_vertex_stride;
139 output_vertex_size = num_tcs_outputs * 16;
140
141 input_patch_size = num_tcs_input_cp * input_vertex_size;
142
143 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
144 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
145
146 /* Ensure that we only need one wave per SIMD so we don't need to check
147 * resource usage. Also ensures that the number of tcs in and out
148 * vertices per threadgroup are at most 256.
149 */
150 unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
151 *num_patches = 256 / max_verts_per_patch;
152
153 /* Make sure that the data fits in LDS. This assumes the shaders only
154 * use LDS for the inputs and outputs.
155 *
156 * While GFX7 can use 64K per threadgroup, there is a hang on Stoney
157 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
158 * uses 32K at most on all GCN chips.
159 */
160 hardware_lds_size = 32768;
161 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
162 output_patch_size));
163
164 /* Make sure the output data fits in the offchip buffer */
165 *num_patches = MIN2(*num_patches,
166 (sctx->screen->tess_offchip_block_dw_size * 4) /
167 output_patch_size);
168
169 /* Not necessary for correctness, but improves performance.
170 * The hardware can do more, but the radeonsi shader constant is
171 * limited to 6 bits.
172 */
173 *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */
174
175 /* When distributed tessellation is unsupported, switch between SEs
176 * at a higher frequency to compensate for it.
177 */
178 if (!sctx->screen->has_distributed_tess && sctx->screen->info.max_se > 1)
179 *num_patches = MIN2(*num_patches, 16); /* recommended */
180
181 /* Make sure that vector lanes are reasonably occupied. It probably
182 * doesn't matter much because this is LS-HS, and TES is likely to
183 * occupy significantly more CUs.
184 */
185 unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
186 if (temp_verts_per_tg > 64 && temp_verts_per_tg % 64 < 48)
187 *num_patches = (temp_verts_per_tg & ~63) / max_verts_per_patch;
188
189 if (sctx->chip_class == GFX6) {
190 /* GFX6 bug workaround, related to power management. Limit LS-HS
191 * threadgroups to only one wave.
192 */
193 unsigned one_wave = 64 / max_verts_per_patch;
194 *num_patches = MIN2(*num_patches, one_wave);
195 }
196
197 /* The VGT HS block increments the patch ID unconditionally
198 * within a single threadgroup. This results in incorrect
199 * patch IDs when instanced draws are used.
200 *
201 * The intended solution is to restrict threadgroups to
202 * a single instance by setting SWITCH_ON_EOI, which
203 * should cause IA to split instances up. However, this
204 * doesn't work correctly on GFX6 when there is no other
205 * SE to switch to.
206 */
207 if (has_primid_instancing_bug && tess_uses_primid)
208 *num_patches = 1;
209
210 sctx->last_num_patches = *num_patches;
211
212 output_patch0_offset = input_patch_size * *num_patches;
213 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
214
215 /* Compute userdata SGPRs. */
216 assert(((input_vertex_size / 4) & ~0xff) == 0);
217 assert(((output_vertex_size / 4) & ~0xff) == 0);
218 assert(((input_patch_size / 4) & ~0x1fff) == 0);
219 assert(((output_patch_size / 4) & ~0x1fff) == 0);
220 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
221 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
222 assert(num_tcs_input_cp <= 32);
223 assert(num_tcs_output_cp <= 32);
224
225 uint64_t ring_va = si_resource(sctx->tess_rings)->gpu_address;
226 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
227
228 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
229 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
230 tcs_out_layout = (output_patch_size / 4) |
231 (num_tcs_input_cp << 13) |
232 ring_va;
233 tcs_out_offsets = (output_patch0_offset / 16) |
234 ((perpatch_output_offset / 16) << 16);
235 offchip_layout = *num_patches |
236 (num_tcs_output_cp << 6) |
237 (pervertex_output_patch_size * *num_patches << 12);
238
239 /* Compute the LDS size. */
240 lds_size = output_patch0_offset + output_patch_size * *num_patches;
241
242 if (sctx->chip_class >= GFX7) {
243 assert(lds_size <= 65536);
244 lds_size = align(lds_size, 512) / 512;
245 } else {
246 assert(lds_size <= 32768);
247 lds_size = align(lds_size, 256) / 256;
248 }
249
250 /* Set SI_SGPR_VS_STATE_BITS. */
251 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
252 C_VS_STATE_LS_OUT_VERTEX_SIZE;
253 sctx->current_vs_state |= tcs_in_layout;
254
255 /* We should be able to support in-shader LDS use with LLVM >= 9
256 * by just adding the lds_sizes together, but it has never
257 * been tested. */
258 assert(ls_current->config.lds_size == 0);
259
260 if (sctx->chip_class >= GFX9) {
261 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
262 S_00B42C_LDS_SIZE_GFX9(lds_size);
263
264 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
265
266 /* Set userdata SGPRs for merged LS-HS. */
267 radeon_set_sh_reg_seq(cs,
268 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
269 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
270 radeon_emit(cs, offchip_layout);
271 radeon_emit(cs, tcs_out_offsets);
272 radeon_emit(cs, tcs_out_layout);
273 } else {
274 unsigned ls_rsrc2 = ls_current->config.rsrc2;
275
276 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
277 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
278
279 /* Due to a hw bug, RSRC2_LS must be written twice with another
280 * LS register written in between. */
281 if (sctx->chip_class == GFX7 && sctx->family != CHIP_HAWAII)
282 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
283 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
284 radeon_emit(cs, ls_current->config.rsrc1);
285 radeon_emit(cs, ls_rsrc2);
286
287 /* Set userdata SGPRs for TCS. */
288 radeon_set_sh_reg_seq(cs,
289 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
290 radeon_emit(cs, offchip_layout);
291 radeon_emit(cs, tcs_out_offsets);
292 radeon_emit(cs, tcs_out_layout);
293 radeon_emit(cs, tcs_in_layout);
294 }
295
296 /* Set userdata SGPRs for TES. */
297 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
298 radeon_emit(cs, offchip_layout);
299 radeon_emit(cs, ring_va);
300
301 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
302 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
303 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
304
305 if (sctx->last_ls_hs_config != ls_hs_config) {
306 if (sctx->chip_class >= GFX7) {
307 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
308 ls_hs_config);
309 } else {
310 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
311 ls_hs_config);
312 }
313 sctx->last_ls_hs_config = ls_hs_config;
314 sctx->context_roll = true;
315 }
316 }
317
318 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info,
319 enum pipe_prim_type prim)
320 {
321 switch (prim) {
322 case PIPE_PRIM_PATCHES:
323 return info->count / info->vertices_per_patch;
324 case PIPE_PRIM_POLYGON:
325 return info->count >= 3;
326 case SI_PRIM_RECTANGLE_LIST:
327 return info->count / 3;
328 default:
329 return u_decomposed_prims_for_vertices(prim, info->count);
330 }
331 }
332
333 static unsigned
334 si_get_init_multi_vgt_param(struct si_screen *sscreen,
335 union si_vgt_param_key *key)
336 {
337 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
338 unsigned max_primgroup_in_wave = 2;
339
340 /* SWITCH_ON_EOP(0) is always preferable. */
341 bool wd_switch_on_eop = false;
342 bool ia_switch_on_eop = false;
343 bool ia_switch_on_eoi = false;
344 bool partial_vs_wave = false;
345 bool partial_es_wave = false;
346
347 if (key->u.uses_tess) {
348 /* SWITCH_ON_EOI must be set if PrimID is used. */
349 if (key->u.tess_uses_prim_id)
350 ia_switch_on_eoi = true;
351
352 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
353 if ((sscreen->info.family == CHIP_TAHITI ||
354 sscreen->info.family == CHIP_PITCAIRN ||
355 sscreen->info.family == CHIP_BONAIRE) &&
356 key->u.uses_gs)
357 partial_vs_wave = true;
358
359 /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
360 if (sscreen->has_distributed_tess) {
361 if (key->u.uses_gs) {
362 if (sscreen->info.chip_class == GFX8)
363 partial_es_wave = true;
364 } else {
365 partial_vs_wave = true;
366 }
367 }
368 }
369
370 /* This is a hardware requirement. */
371 if (key->u.line_stipple_enabled ||
372 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
373 ia_switch_on_eop = true;
374 wd_switch_on_eop = true;
375 }
376
377 if (sscreen->info.chip_class >= GFX7) {
378 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
379 * 4 shader engines. Set 1 to pass the assertion below.
380 * The other cases are hardware requirements.
381 *
382 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
383 * for points, line strips, and tri strips.
384 */
385 if (sscreen->info.max_se <= 2 ||
386 key->u.prim == PIPE_PRIM_POLYGON ||
387 key->u.prim == PIPE_PRIM_LINE_LOOP ||
388 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
389 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
390 (key->u.primitive_restart &&
391 (sscreen->info.family < CHIP_POLARIS10 ||
392 (key->u.prim != PIPE_PRIM_POINTS &&
393 key->u.prim != PIPE_PRIM_LINE_STRIP &&
394 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
395 key->u.count_from_stream_output)
396 wd_switch_on_eop = true;
397
398 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
399 * We don't know that for indirect drawing, so treat it as
400 * always problematic. */
401 if (sscreen->info.family == CHIP_HAWAII &&
402 key->u.uses_instancing)
403 wd_switch_on_eop = true;
404
405 /* Performance recommendation for 4 SE Gfx7-8 parts if
406 * instances are smaller than a primgroup.
407 * Assume indirect draws always use small instances.
408 * This is needed for good VS wave utilization.
409 */
410 if (sscreen->info.chip_class <= GFX8 &&
411 sscreen->info.max_se == 4 &&
412 key->u.multi_instances_smaller_than_primgroup)
413 wd_switch_on_eop = true;
414
415 /* Required on GFX7 and later. */
416 if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
417 ia_switch_on_eoi = true;
418
419 /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
420 * to work around a GS hang.
421 */
422 if (key->u.uses_gs &&
423 (sscreen->info.family == CHIP_TONGA ||
424 sscreen->info.family == CHIP_FIJI ||
425 sscreen->info.family == CHIP_POLARIS10 ||
426 sscreen->info.family == CHIP_POLARIS11 ||
427 sscreen->info.family == CHIP_POLARIS12 ||
428 sscreen->info.family == CHIP_VEGAM))
429 partial_vs_wave = true;
430
431 /* Required by Hawaii and, for some special cases, by GFX8. */
432 if (ia_switch_on_eoi &&
433 (sscreen->info.family == CHIP_HAWAII ||
434 (sscreen->info.chip_class == GFX8 &&
435 (key->u.uses_gs || max_primgroup_in_wave != 2))))
436 partial_vs_wave = true;
437
438 /* Instancing bug on Bonaire. */
439 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
440 key->u.uses_instancing)
441 partial_vs_wave = true;
442
443 /* This only applies to Polaris10 and later 4 SE chips.
444 * wd_switch_on_eop is already true on all other chips.
445 */
446 if (!wd_switch_on_eop && key->u.primitive_restart)
447 partial_vs_wave = true;
448
449 /* If the WD switch is false, the IA switch must be false too. */
450 assert(wd_switch_on_eop || !ia_switch_on_eop);
451 }
452
453 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
454 if (sscreen->info.chip_class <= GFX8 && ia_switch_on_eoi)
455 partial_es_wave = true;
456
457 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
458 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
459 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
460 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
461 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= GFX7 ? wd_switch_on_eop : 0) |
462 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
463 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == GFX8 ?
464 max_primgroup_in_wave : 0) |
465 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
466 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
467 }
468
469 static void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
470 {
471 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
472 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
473 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
474 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
475 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
476 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
477 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
478 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
479 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
480 union si_vgt_param_key key;
481
482 key.index = 0;
483 key.u.prim = prim;
484 key.u.uses_instancing = uses_instancing;
485 key.u.multi_instances_smaller_than_primgroup = multi_instances;
486 key.u.primitive_restart = primitive_restart;
487 key.u.count_from_stream_output = count_from_so;
488 key.u.line_stipple_enabled = line_stipple;
489 key.u.uses_tess = uses_tess;
490 key.u.tess_uses_prim_id = tess_uses_primid;
491 key.u.uses_gs = uses_gs;
492
493 sctx->ia_multi_vgt_param[key.index] =
494 si_get_init_multi_vgt_param(sctx->screen, &key);
495 }
496 }
497
498 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
499 const struct pipe_draw_info *info,
500 enum pipe_prim_type prim,
501 unsigned num_patches,
502 unsigned instance_count,
503 bool primitive_restart)
504 {
505 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
506 unsigned primgroup_size;
507 unsigned ia_multi_vgt_param;
508
509 if (sctx->tes_shader.cso) {
510 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
511 } else if (sctx->gs_shader.cso) {
512 primgroup_size = 64; /* recommended with a GS */
513 } else {
514 primgroup_size = 128; /* recommended without a GS and tess */
515 }
516
517 key.u.prim = prim;
518 key.u.uses_instancing = info->indirect || instance_count > 1;
519 key.u.multi_instances_smaller_than_primgroup =
520 info->indirect ||
521 (instance_count > 1 &&
522 (info->count_from_stream_output ||
523 si_num_prims_for_vertices(info, prim) < primgroup_size));
524 key.u.primitive_restart = primitive_restart;
525 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
526
527 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
528 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
529
530 if (sctx->gs_shader.cso) {
531 /* GS requirement. */
532 if (sctx->chip_class <= GFX8 &&
533 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
534 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
535
536 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
537 * The hw doc says all multi-SE chips are affected, but Vulkan
538 * only applies it to Hawaii. Do what Vulkan does.
539 */
540 if (sctx->family == CHIP_HAWAII &&
541 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
542 (info->indirect ||
543 (instance_count > 1 &&
544 (info->count_from_stream_output ||
545 si_num_prims_for_vertices(info, prim) <= 1))))
546 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
547 }
548
549 return ia_multi_vgt_param;
550 }
551
552 /* rast_prim is the primitive type after GS. */
553 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
554 {
555 struct radeon_cmdbuf *cs = sctx->gfx_cs;
556 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
557 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
558
559 /* Skip this if not rendering lines. */
560 if (!util_prim_is_lines(rast_prim))
561 return;
562
563 if (rast_prim == sctx->last_rast_prim &&
564 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
565 return;
566
567 /* For lines, reset the stipple pattern at each primitive. Otherwise,
568 * reset the stipple pattern at each packet (line strips, line loops).
569 */
570 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
571 rs->pa_sc_line_stipple |
572 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
573
574 sctx->last_rast_prim = rast_prim;
575 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
576 sctx->context_roll = true;
577 }
578
579 static void si_emit_vs_state(struct si_context *sctx,
580 const struct pipe_draw_info *info)
581 {
582 sctx->current_vs_state &= C_VS_STATE_INDEXED;
583 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
584
585 if (sctx->num_vs_blit_sgprs) {
586 /* Re-emit the state after we leave u_blitter. */
587 sctx->last_vs_state = ~0;
588 return;
589 }
590
591 if (sctx->current_vs_state != sctx->last_vs_state) {
592 struct radeon_cmdbuf *cs = sctx->gfx_cs;
593
594 /* For the API vertex shader (VS_STATE_INDEXED). */
595 radeon_set_sh_reg(cs,
596 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
597 SI_SGPR_VS_STATE_BITS * 4,
598 sctx->current_vs_state);
599
600 /* For vertex color clamping, which is done in the last stage
601 * before the rasterizer. */
602 if (sctx->gs_shader.cso || sctx->tes_shader.cso) {
603 /* GS copy shader or TES if GS is missing. */
604 radeon_set_sh_reg(cs,
605 R_00B130_SPI_SHADER_USER_DATA_VS_0 +
606 SI_SGPR_VS_STATE_BITS * 4,
607 sctx->current_vs_state);
608 }
609
610 sctx->last_vs_state = sctx->current_vs_state;
611 }
612 }
613
614 static inline bool si_prim_restart_index_changed(struct si_context *sctx,
615 bool primitive_restart,
616 unsigned restart_index)
617 {
618 return primitive_restart &&
619 (restart_index != sctx->last_restart_index ||
620 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
621 }
622
623 static void si_emit_draw_registers(struct si_context *sctx,
624 const struct pipe_draw_info *info,
625 enum pipe_prim_type prim,
626 unsigned num_patches,
627 unsigned instance_count,
628 bool primitive_restart)
629 {
630 struct radeon_cmdbuf *cs = sctx->gfx_cs;
631 unsigned vgt_prim = si_conv_pipe_prim(prim);
632 unsigned ia_multi_vgt_param;
633
634 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, prim, num_patches,
635 instance_count, primitive_restart);
636
637 /* Draw state. */
638 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
639 if (sctx->chip_class >= GFX9)
640 radeon_set_uconfig_reg_idx(cs, sctx->screen,
641 R_030960_IA_MULTI_VGT_PARAM, 4,
642 ia_multi_vgt_param);
643 else if (sctx->chip_class >= GFX7)
644 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
645 else
646 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
647
648 sctx->last_multi_vgt_param = ia_multi_vgt_param;
649 }
650 if (vgt_prim != sctx->last_prim) {
651 if (sctx->chip_class >= GFX7)
652 radeon_set_uconfig_reg_idx(cs, sctx->screen,
653 R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
654 else
655 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);
656
657 sctx->last_prim = vgt_prim;
658 }
659
660 /* Primitive restart. */
661 if (primitive_restart != sctx->last_primitive_restart_en) {
662 if (sctx->chip_class >= GFX9)
663 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
664 primitive_restart);
665 else
666 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
667 primitive_restart);
668
669 sctx->last_primitive_restart_en = primitive_restart;
670
671 }
672 if (si_prim_restart_index_changed(sctx, primitive_restart, info->restart_index)) {
673 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
674 info->restart_index);
675 sctx->last_restart_index = info->restart_index;
676 sctx->context_roll = true;
677 }
678 }
679
680 static void si_emit_draw_packets(struct si_context *sctx,
681 const struct pipe_draw_info *info,
682 struct pipe_resource *indexbuf,
683 unsigned index_size,
684 unsigned index_offset,
685 unsigned instance_count,
686 bool dispatch_prim_discard_cs,
687 unsigned original_index_size)
688 {
689 struct pipe_draw_indirect_info *indirect = info->indirect;
690 struct radeon_cmdbuf *cs = sctx->gfx_cs;
691 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
692 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
693 uint32_t index_max_size = 0;
694 uint64_t index_va = 0;
695
696 if (info->count_from_stream_output) {
697 struct si_streamout_target *t =
698 (struct si_streamout_target*)info->count_from_stream_output;
699
700 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
701 t->stride_in_dw);
702 si_cp_copy_data(sctx, sctx->gfx_cs,
703 COPY_DATA_REG, NULL,
704 R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2,
705 COPY_DATA_SRC_MEM, t->buf_filled_size,
706 t->buf_filled_size_offset);
707 }
708
709 /* draw packet */
710 if (index_size) {
711 if (index_size != sctx->last_index_size) {
712 unsigned index_type;
713
714 /* index type */
715 switch (index_size) {
716 case 1:
717 index_type = V_028A7C_VGT_INDEX_8;
718 break;
719 case 2:
720 index_type = V_028A7C_VGT_INDEX_16 |
721 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
722 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
723 break;
724 case 4:
725 index_type = V_028A7C_VGT_INDEX_32 |
726 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
727 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
728 break;
729 default:
730 assert(!"unreachable");
731 return;
732 }
733
734 if (sctx->chip_class >= GFX9) {
735 radeon_set_uconfig_reg_idx(cs, sctx->screen,
736 R_03090C_VGT_INDEX_TYPE, 2,
737 index_type);
738 } else {
739 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
740 radeon_emit(cs, index_type);
741 }
742
743 sctx->last_index_size = index_size;
744 }
745
746 if (original_index_size) {
747 index_max_size = (indexbuf->width0 - index_offset) /
748 original_index_size;
749 index_va = si_resource(indexbuf)->gpu_address + index_offset;
750
751 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
752 si_resource(indexbuf),
753 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
754 }
755 } else {
756 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
757 * so the state must be re-emitted before the next indexed draw.
758 */
759 if (sctx->chip_class >= GFX7)
760 sctx->last_index_size = -1;
761 }
762
763 if (indirect) {
764 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address;
765
766 assert(indirect_va % 8 == 0);
767
768 si_invalidate_draw_sh_constants(sctx);
769
770 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
771 radeon_emit(cs, 1);
772 radeon_emit(cs, indirect_va);
773 radeon_emit(cs, indirect_va >> 32);
774
775 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
776 si_resource(indirect->buffer),
777 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
778
779 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
780 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
781
782 assert(indirect->offset % 4 == 0);
783
784 if (index_size) {
785 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
786 radeon_emit(cs, index_va);
787 radeon_emit(cs, index_va >> 32);
788
789 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
790 radeon_emit(cs, index_max_size);
791 }
792
793 if (!sctx->screen->has_draw_indirect_multi) {
794 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
795 : PKT3_DRAW_INDIRECT,
796 3, render_cond_bit));
797 radeon_emit(cs, indirect->offset);
798 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
799 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
800 radeon_emit(cs, di_src_sel);
801 } else {
802 uint64_t count_va = 0;
803
804 if (indirect->indirect_draw_count) {
805 struct si_resource *params_buf =
806 si_resource(indirect->indirect_draw_count);
807
808 radeon_add_to_buffer_list(
809 sctx, sctx->gfx_cs, params_buf,
810 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
811
812 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
813 }
814
815 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
816 PKT3_DRAW_INDIRECT_MULTI,
817 8, render_cond_bit));
818 radeon_emit(cs, indirect->offset);
819 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
820 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
821 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
822 S_2C3_DRAW_INDEX_ENABLE(1) |
823 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
824 radeon_emit(cs, indirect->draw_count);
825 radeon_emit(cs, count_va);
826 radeon_emit(cs, count_va >> 32);
827 radeon_emit(cs, indirect->stride);
828 radeon_emit(cs, di_src_sel);
829 }
830 } else {
831 int base_vertex;
832
833 if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
834 sctx->last_instance_count != instance_count) {
835 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
836 radeon_emit(cs, instance_count);
837 sctx->last_instance_count = instance_count;
838 }
839
840 /* Base vertex and start instance. */
841 base_vertex = original_index_size ? info->index_bias : info->start;
842
843 if (sctx->num_vs_blit_sgprs) {
844 /* Re-emit draw constants after we leave u_blitter. */
845 si_invalidate_draw_sh_constants(sctx);
846
847 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
848 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
849 sctx->num_vs_blit_sgprs);
850 radeon_emit_array(cs, sctx->vs_blit_sh_data,
851 sctx->num_vs_blit_sgprs);
852 } else if (base_vertex != sctx->last_base_vertex ||
853 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
854 info->start_instance != sctx->last_start_instance ||
855 info->drawid != sctx->last_drawid ||
856 sh_base_reg != sctx->last_sh_base_reg) {
857 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
858 radeon_emit(cs, base_vertex);
859 radeon_emit(cs, info->start_instance);
860 radeon_emit(cs, info->drawid);
861
862 sctx->last_base_vertex = base_vertex;
863 sctx->last_start_instance = info->start_instance;
864 sctx->last_drawid = info->drawid;
865 sctx->last_sh_base_reg = sh_base_reg;
866 }
867
868 if (index_size) {
869 if (dispatch_prim_discard_cs) {
870 index_va += info->start * original_index_size;
871 index_max_size = MIN2(index_max_size, info->count);
872
873 si_dispatch_prim_discard_cs_and_draw(sctx, info,
874 original_index_size,
875 base_vertex,
876 index_va, index_max_size);
877 return;
878 }
879
880 index_va += info->start * index_size;
881
882 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
883 radeon_emit(cs, index_max_size);
884 radeon_emit(cs, index_va);
885 radeon_emit(cs, index_va >> 32);
886 radeon_emit(cs, info->count);
887 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
888 } else {
889 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
890 radeon_emit(cs, info->count);
891 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
892 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
893 }
894 }
895 }
896
897 void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs,
898 unsigned cp_coher_cntl)
899 {
900 bool compute_ib = !sctx->has_graphics ||
901 cs == sctx->prim_discard_compute_cs;
902
903 if (sctx->chip_class >= GFX9 || compute_ib) {
904 /* Flush caches and wait for the caches to assert idle. */
905 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
906 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
907 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
908 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
909 radeon_emit(cs, 0); /* CP_COHER_BASE */
910 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
911 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
912 } else {
913 /* ACQUIRE_MEM is only required on a compute ring. */
914 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
915 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
916 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
917 radeon_emit(cs, 0); /* CP_COHER_BASE */
918 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
919 }
920
921 /* ACQUIRE_MEM has an implicit context roll if the current context
922 * is busy. */
923 if (!compute_ib)
924 sctx->context_roll = true;
925 }
926
927 void si_prim_discard_signal_next_compute_ib_start(struct si_context *sctx)
928 {
929 if (!si_compute_prim_discard_enabled(sctx))
930 return;
931
932 if (!sctx->barrier_buf) {
933 u_suballocator_alloc(sctx->allocator_zeroed_memory, 4, 4,
934 &sctx->barrier_buf_offset,
935 (struct pipe_resource**)&sctx->barrier_buf);
936 }
937
938 /* Emit a placeholder to signal the next compute IB to start.
939 * See si_compute_prim_discard.c for explanation.
940 */
941 uint32_t signal = 1;
942 si_cp_write_data(sctx, sctx->barrier_buf, sctx->barrier_buf_offset,
943 4, V_370_MEM, V_370_ME, &signal);
944
945 sctx->last_pkt3_write_data =
946 &sctx->gfx_cs->current.buf[sctx->gfx_cs->current.cdw - 5];
947
948 /* Only the last occurence of WRITE_DATA will be executed.
949 * The packet will be enabled in si_flush_gfx_cs.
950 */
951 *sctx->last_pkt3_write_data = PKT3(PKT3_NOP, 3, 0);
952 }
953
954 void gfx10_emit_cache_flush(struct si_context *ctx)
955 {
956 struct radeon_cmdbuf *cs = ctx->gfx_cs;
957 uint32_t gcr_cntl = 0;
958 unsigned cb_db_event = 0;
959 unsigned flags = ctx->flags;
960
961 if (!ctx->has_graphics) {
962 /* Only process compute flags. */
963 flags &= SI_CONTEXT_INV_ICACHE |
964 SI_CONTEXT_INV_SCACHE |
965 SI_CONTEXT_INV_VCACHE |
966 SI_CONTEXT_INV_L2 |
967 SI_CONTEXT_WB_L2 |
968 SI_CONTEXT_INV_L2_METADATA |
969 SI_CONTEXT_CS_PARTIAL_FLUSH;
970 }
971
972 /* We don't need these. */
973 assert(!(flags & (SI_CONTEXT_VGT_FLUSH |
974 SI_CONTEXT_VGT_STREAMOUT_SYNC |
975 SI_CONTEXT_FLUSH_AND_INV_DB_META)));
976
977 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
978 ctx->num_cb_cache_flushes++;
979 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
980 ctx->num_db_cache_flushes++;
981
982 if (flags & SI_CONTEXT_INV_ICACHE)
983 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
984 if (flags & SI_CONTEXT_INV_SCACHE) {
985 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
986 * to FORWARD when both L1 and L2 are written out (WB or INV).
987 */
988 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
989 }
990 if (flags & SI_CONTEXT_INV_VCACHE)
991 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
992 if (flags & SI_CONTEXT_INV_L2) {
993 /* Writeback and invalidate everything in L2. */
994 gcr_cntl |= S_586_GL2_INV(1) | S_586_GLM_INV(1);
995 ctx->num_L2_invalidates++;
996 } else if (flags & SI_CONTEXT_WB_L2) {
997 /* Writeback but do not invalidate. */
998 gcr_cntl |= S_586_GL2_WB(1);
999 }
1000 if (flags & SI_CONTEXT_INV_L2_METADATA)
1001 gcr_cntl |= S_586_GLM_INV(1);
1002
1003 if (flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1004 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1005 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1006 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1007 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
1008 EVENT_INDEX(0));
1009 }
1010 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1011 /* Flush HTILE. Will wait for idle later. */
1012 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1013 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
1014 EVENT_INDEX(0));
1015 }
1016
1017 /* First flush CB/DB, then L1/L2. */
1018 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
1019
1020 if ((flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) ==
1021 (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1022 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1023 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1024 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1025 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1026 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1027 } else {
1028 assert(0);
1029 }
1030 } else {
1031 /* Wait for graphics shaders to go idle if requested. */
1032 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1033 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1034 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1035 /* Only count explicit shader flushes, not implicit ones. */
1036 ctx->num_vs_flushes++;
1037 ctx->num_ps_flushes++;
1038 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1039 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1040 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1041 ctx->num_vs_flushes++;
1042 }
1043 }
1044
1045 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH && ctx->compute_is_busy) {
1046 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1047 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
1048 ctx->num_cs_flushes++;
1049 ctx->compute_is_busy = false;
1050 }
1051
1052 if (cb_db_event) {
1053 /* CB/DB flush and invalidate (or possibly just a wait for a
1054 * meta flush) via RELEASE_MEM.
1055 *
1056 * Combine this with other cache flushes when possible; this
1057 * requires affected shaders to be idle, so do it after the
1058 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1059 * implied).
1060 */
1061 uint64_t va;
1062
1063 /* Do the flush (enqueue the event and wait for it). */
1064 va = ctx->wait_mem_scratch->gpu_address;
1065 ctx->wait_mem_number++;
1066
1067 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1068 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
1069 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
1070 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
1071 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
1072 assert(G_586_GL2_US(gcr_cntl) == 0);
1073 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
1074 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
1075 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
1076 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
1077 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
1078
1079 gcr_cntl &= C_586_GLM_WB &
1080 C_586_GLM_INV &
1081 C_586_GLV_INV &
1082 C_586_GL1_INV &
1083 C_586_GL2_INV &
1084 C_586_GL2_WB; /* keep SEQ */
1085
1086 si_cp_release_mem(ctx, cs, cb_db_event,
1087 S_490_GLM_WB(glm_wb) |
1088 S_490_GLM_INV(glm_inv) |
1089 S_490_GLV_INV(glv_inv) |
1090 S_490_GL1_INV(gl1_inv) |
1091 S_490_GL2_INV(gl2_inv) |
1092 S_490_GL2_WB(gl2_wb) |
1093 S_490_SEQ(gcr_seq),
1094 EOP_DST_SEL_MEM,
1095 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1096 EOP_DATA_SEL_VALUE_32BIT,
1097 ctx->wait_mem_scratch, va,
1098 ctx->wait_mem_number, SI_NOT_QUERY);
1099 si_cp_wait_mem(ctx, ctx->gfx_cs, va, ctx->wait_mem_number, 0xffffffff,
1100 WAIT_REG_MEM_EQUAL);
1101 }
1102
1103 /* Ignore fields that only modify the behavior of other fields. */
1104 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1105 /* Flush caches and wait for the caches to assert idle.
1106 * The cache flush is executed in the ME, but the PFP waits
1107 * for completion.
1108 */
1109 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1110 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1111 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1112 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1113 radeon_emit(cs, 0); /* CP_COHER_BASE */
1114 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1115 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1116 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1117 } else if (cb_db_event ||
1118 (flags & (SI_CONTEXT_VS_PARTIAL_FLUSH |
1119 SI_CONTEXT_PS_PARTIAL_FLUSH |
1120 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1121 /* We need to ensure that PFP waits as well. */
1122 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1123 radeon_emit(cs, 0);
1124 }
1125
1126 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1127 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1128 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1129 EVENT_INDEX(0));
1130 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1131 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1132 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1133 EVENT_INDEX(0));
1134 }
1135
1136 ctx->flags = 0;
1137 }
1138
1139 void si_emit_cache_flush(struct si_context *sctx)
1140 {
1141 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1142 uint32_t flags = sctx->flags;
1143
1144 if (!sctx->has_graphics) {
1145 /* Only process compute flags. */
1146 flags &= SI_CONTEXT_INV_ICACHE |
1147 SI_CONTEXT_INV_SCACHE |
1148 SI_CONTEXT_INV_VCACHE |
1149 SI_CONTEXT_INV_L2 |
1150 SI_CONTEXT_WB_L2 |
1151 SI_CONTEXT_INV_L2_METADATA |
1152 SI_CONTEXT_CS_PARTIAL_FLUSH;
1153 }
1154
1155 uint32_t cp_coher_cntl = 0;
1156 const uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1157 SI_CONTEXT_FLUSH_AND_INV_DB);
1158 const bool is_barrier = flush_cb_db ||
1159 /* INV_ICACHE == beginning of gfx IB. Checking
1160 * INV_ICACHE fixes corruption for DeusExMD with
1161 * compute-based culling, but I don't know why.
1162 */
1163 flags & (SI_CONTEXT_INV_ICACHE |
1164 SI_CONTEXT_PS_PARTIAL_FLUSH |
1165 SI_CONTEXT_VS_PARTIAL_FLUSH) ||
1166 (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1167 sctx->compute_is_busy);
1168
1169 assert(sctx->chip_class <= GFX9);
1170
1171 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1172 sctx->num_cb_cache_flushes++;
1173 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1174 sctx->num_db_cache_flushes++;
1175
1176 /* GFX6 has a bug that it always flushes ICACHE and KCACHE if either
1177 * bit is set. An alternative way is to write SQC_CACHES, but that
1178 * doesn't seem to work reliably. Since the bug doesn't affect
1179 * correctness (it only does more work than necessary) and
1180 * the performance impact is likely negligible, there is no plan
1181 * to add a workaround for it.
1182 */
1183
1184 if (flags & SI_CONTEXT_INV_ICACHE)
1185 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1186 if (flags & SI_CONTEXT_INV_SCACHE)
1187 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1188
1189 if (sctx->chip_class <= GFX8) {
1190 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1191 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1192 S_0085F0_CB0_DEST_BASE_ENA(1) |
1193 S_0085F0_CB1_DEST_BASE_ENA(1) |
1194 S_0085F0_CB2_DEST_BASE_ENA(1) |
1195 S_0085F0_CB3_DEST_BASE_ENA(1) |
1196 S_0085F0_CB4_DEST_BASE_ENA(1) |
1197 S_0085F0_CB5_DEST_BASE_ENA(1) |
1198 S_0085F0_CB6_DEST_BASE_ENA(1) |
1199 S_0085F0_CB7_DEST_BASE_ENA(1);
1200
1201 /* Necessary for DCC */
1202 if (sctx->chip_class == GFX8)
1203 si_cp_release_mem(sctx, cs,
1204 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1205 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
1206 EOP_DATA_SEL_DISCARD, NULL,
1207 0, 0, SI_NOT_QUERY);
1208 }
1209 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1210 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1211 S_0085F0_DB_DEST_BASE_ENA(1);
1212 }
1213
1214 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1215 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
1216 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1217 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1218 }
1219 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
1220 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
1221 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
1222 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1223 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1224 }
1225
1226 /* Wait for shader engines to go idle.
1227 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
1228 * for everything including CB/DB cache flushes.
1229 */
1230 if (!flush_cb_db) {
1231 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1232 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1233 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1234 /* Only count explicit shader flushes, not implicit ones
1235 * done by SURFACE_SYNC.
1236 */
1237 sctx->num_vs_flushes++;
1238 sctx->num_ps_flushes++;
1239 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1240 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1241 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1242 sctx->num_vs_flushes++;
1243 }
1244 }
1245
1246 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1247 sctx->compute_is_busy) {
1248 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1249 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1250 sctx->num_cs_flushes++;
1251 sctx->compute_is_busy = false;
1252 }
1253
1254 /* VGT state synchronization. */
1255 if (flags & SI_CONTEXT_VGT_FLUSH) {
1256 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1257 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1258 }
1259 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
1260 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1261 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1262 }
1263
1264 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
1265 * wait for idle on GFX9. We have to use a TS event.
1266 */
1267 if (sctx->chip_class >= GFX9 && flush_cb_db) {
1268 uint64_t va;
1269 unsigned tc_flags, cb_db_event;
1270
1271 /* Set the CB/DB flush event. */
1272 switch (flush_cb_db) {
1273 case SI_CONTEXT_FLUSH_AND_INV_CB:
1274 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1275 break;
1276 case SI_CONTEXT_FLUSH_AND_INV_DB:
1277 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1278 break;
1279 default:
1280 /* both CB & DB */
1281 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1282 }
1283
1284 /* These are the only allowed combinations. If you need to
1285 * do multiple operations at once, do them separately.
1286 * All operations that invalidate L2 also seem to invalidate
1287 * metadata. Volatile (VOL) and WC flushes are not listed here.
1288 *
1289 * TC | TC_WB = writeback & invalidate L2 & L1
1290 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1291 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1292 * TC | TC_NC = invalidate L2 for MTYPE == NC
1293 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1294 * TCL1 = invalidate L1
1295 */
1296 tc_flags = 0;
1297
1298 if (flags & SI_CONTEXT_INV_L2_METADATA) {
1299 tc_flags = EVENT_TC_ACTION_ENA |
1300 EVENT_TC_MD_ACTION_ENA;
1301 }
1302
1303 /* Ideally flush TC together with CB/DB. */
1304 if (flags & SI_CONTEXT_INV_L2) {
1305 /* Writeback and invalidate everything in L2 & L1. */
1306 tc_flags = EVENT_TC_ACTION_ENA |
1307 EVENT_TC_WB_ACTION_ENA;
1308
1309 /* Clear the flags. */
1310 flags &= ~(SI_CONTEXT_INV_L2 |
1311 SI_CONTEXT_WB_L2 |
1312 SI_CONTEXT_INV_VCACHE);
1313 sctx->num_L2_invalidates++;
1314 }
1315
1316 /* Do the flush (enqueue the event and wait for it). */
1317 va = sctx->wait_mem_scratch->gpu_address;
1318 sctx->wait_mem_number++;
1319
1320 si_cp_release_mem(sctx, cs, cb_db_event, tc_flags,
1321 EOP_DST_SEL_MEM,
1322 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1323 EOP_DATA_SEL_VALUE_32BIT,
1324 sctx->wait_mem_scratch, va,
1325 sctx->wait_mem_number, SI_NOT_QUERY);
1326 si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff,
1327 WAIT_REG_MEM_EQUAL);
1328 }
1329
1330 /* Make sure ME is idle (it executes most packets) before continuing.
1331 * This prevents read-after-write hazards between PFP and ME.
1332 */
1333 if (sctx->has_graphics &&
1334 (cp_coher_cntl ||
1335 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1336 SI_CONTEXT_INV_VCACHE |
1337 SI_CONTEXT_INV_L2 |
1338 SI_CONTEXT_WB_L2)))) {
1339 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1340 radeon_emit(cs, 0);
1341 }
1342
1343 /* GFX6-GFX8 only:
1344 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1345 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1346 *
1347 * cp_coher_cntl should contain all necessary flags except TC flags
1348 * at this point.
1349 *
1350 * GFX6-GFX7 don't support L2 write-back.
1351 */
1352 if (flags & SI_CONTEXT_INV_L2 ||
1353 (sctx->chip_class <= GFX7 &&
1354 (flags & SI_CONTEXT_WB_L2))) {
1355 /* Invalidate L1 & L2. (L1 is always invalidated on GFX6)
1356 * WB must be set on GFX8+ when TC_ACTION is set.
1357 */
1358 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1359 S_0085F0_TC_ACTION_ENA(1) |
1360 S_0085F0_TCL1_ACTION_ENA(1) |
1361 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= GFX8));
1362 cp_coher_cntl = 0;
1363 sctx->num_L2_invalidates++;
1364 } else {
1365 /* L1 invalidation and L2 writeback must be done separately,
1366 * because both operations can't be done together.
1367 */
1368 if (flags & SI_CONTEXT_WB_L2) {
1369 /* WB = write-back
1370 * NC = apply to non-coherent MTYPEs
1371 * (i.e. MTYPE <= 1, which is what we use everywhere)
1372 *
1373 * WB doesn't work without NC.
1374 */
1375 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1376 S_0301F0_TC_WB_ACTION_ENA(1) |
1377 S_0301F0_TC_NC_ACTION_ENA(1));
1378 cp_coher_cntl = 0;
1379 sctx->num_L2_writebacks++;
1380 }
1381 if (flags & SI_CONTEXT_INV_VCACHE) {
1382 /* Invalidate per-CU VMEM L1. */
1383 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1384 S_0085F0_TCL1_ACTION_ENA(1));
1385 cp_coher_cntl = 0;
1386 }
1387 }
1388
1389 /* If TC flushes haven't cleared this... */
1390 if (cp_coher_cntl)
1391 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl);
1392
1393 if (is_barrier)
1394 si_prim_discard_signal_next_compute_ib_start(sctx);
1395
1396 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1397 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1398 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1399 EVENT_INDEX(0));
1400 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1401 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1402 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1403 EVENT_INDEX(0));
1404 }
1405
1406 sctx->flags = 0;
1407 }
1408
1409 static void si_get_draw_start_count(struct si_context *sctx,
1410 const struct pipe_draw_info *info,
1411 unsigned *start, unsigned *count)
1412 {
1413 struct pipe_draw_indirect_info *indirect = info->indirect;
1414
1415 if (indirect) {
1416 unsigned indirect_count;
1417 struct pipe_transfer *transfer;
1418 unsigned begin, end;
1419 unsigned map_size;
1420 unsigned *data;
1421
1422 if (indirect->indirect_draw_count) {
1423 data = pipe_buffer_map_range(&sctx->b,
1424 indirect->indirect_draw_count,
1425 indirect->indirect_draw_count_offset,
1426 sizeof(unsigned),
1427 PIPE_TRANSFER_READ, &transfer);
1428
1429 indirect_count = *data;
1430
1431 pipe_buffer_unmap(&sctx->b, transfer);
1432 } else {
1433 indirect_count = indirect->draw_count;
1434 }
1435
1436 if (!indirect_count) {
1437 *start = *count = 0;
1438 return;
1439 }
1440
1441 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1442 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1443 indirect->offset, map_size,
1444 PIPE_TRANSFER_READ, &transfer);
1445
1446 begin = UINT_MAX;
1447 end = 0;
1448
1449 for (unsigned i = 0; i < indirect_count; ++i) {
1450 unsigned count = data[0];
1451 unsigned start = data[2];
1452
1453 if (count > 0) {
1454 begin = MIN2(begin, start);
1455 end = MAX2(end, start + count);
1456 }
1457
1458 data += indirect->stride / sizeof(unsigned);
1459 }
1460
1461 pipe_buffer_unmap(&sctx->b, transfer);
1462
1463 if (begin < end) {
1464 *start = begin;
1465 *count = end - begin;
1466 } else {
1467 *start = *count = 0;
1468 }
1469 } else {
1470 *start = info->start;
1471 *count = info->count;
1472 }
1473 }
1474
1475 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1476 enum pipe_prim_type prim, unsigned instance_count,
1477 bool primitive_restart, unsigned skip_atom_mask)
1478 {
1479 unsigned num_patches = 0;
1480
1481 si_emit_rasterizer_prim_state(sctx);
1482 if (sctx->tes_shader.cso)
1483 si_emit_derived_tess_state(sctx, info, &num_patches);
1484
1485 /* Emit state atoms. */
1486 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1487 while (mask)
1488 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1489
1490 sctx->dirty_atoms &= skip_atom_mask;
1491
1492 /* Emit states. */
1493 mask = sctx->dirty_states;
1494 while (mask) {
1495 unsigned i = u_bit_scan(&mask);
1496 struct si_pm4_state *state = sctx->queued.array[i];
1497
1498 if (!state || sctx->emitted.array[i] == state)
1499 continue;
1500
1501 si_pm4_emit(sctx, state);
1502 sctx->emitted.array[i] = state;
1503 }
1504 sctx->dirty_states = 0;
1505
1506 /* Emit draw states. */
1507 si_emit_vs_state(sctx, info);
1508 si_emit_draw_registers(sctx, info, prim, num_patches, instance_count,
1509 primitive_restart);
1510 }
1511
1512 static bool
1513 si_all_vs_resources_read_only(struct si_context *sctx,
1514 struct pipe_resource *indexbuf)
1515 {
1516 struct radeon_winsys *ws = sctx->ws;
1517 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1518
1519 /* Index buffer. */
1520 if (indexbuf &&
1521 ws->cs_is_buffer_referenced(cs, si_resource(indexbuf)->buf,
1522 RADEON_USAGE_WRITE))
1523 goto has_write_reference;
1524
1525 /* Vertex buffers. */
1526 struct si_vertex_elements *velems = sctx->vertex_elements;
1527 unsigned num_velems = velems->count;
1528
1529 for (unsigned i = 0; i < num_velems; i++) {
1530 if (!((1 << i) & velems->first_vb_use_mask))
1531 continue;
1532
1533 unsigned vb_index = velems->vertex_buffer_index[i];
1534 struct pipe_resource *res = sctx->vertex_buffer[vb_index].buffer.resource;
1535 if (!res)
1536 continue;
1537
1538 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1539 RADEON_USAGE_WRITE))
1540 goto has_write_reference;
1541 }
1542
1543 /* Constant and shader buffers. */
1544 struct si_descriptors *buffers =
1545 &sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_VERTEX)];
1546 for (unsigned i = 0; i < buffers->num_active_slots; i++) {
1547 unsigned index = buffers->first_active_slot + i;
1548 struct pipe_resource *res =
1549 sctx->const_and_shader_buffers[PIPE_SHADER_VERTEX].buffers[index];
1550 if (!res)
1551 continue;
1552
1553 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1554 RADEON_USAGE_WRITE))
1555 goto has_write_reference;
1556 }
1557
1558 /* Samplers. */
1559 struct si_shader_selector *vs = sctx->vs_shader.cso;
1560 if (vs->info.samplers_declared) {
1561 unsigned num_samplers = util_last_bit(vs->info.samplers_declared);
1562
1563 for (unsigned i = 0; i < num_samplers; i++) {
1564 struct pipe_sampler_view *view = sctx->samplers[PIPE_SHADER_VERTEX].views[i];
1565 if (!view)
1566 continue;
1567
1568 if (ws->cs_is_buffer_referenced(cs,
1569 si_resource(view->texture)->buf,
1570 RADEON_USAGE_WRITE))
1571 goto has_write_reference;
1572 }
1573 }
1574
1575 /* Images. */
1576 if (vs->info.images_declared) {
1577 unsigned num_images = util_last_bit(vs->info.images_declared);
1578
1579 for (unsigned i = 0; i < num_images; i++) {
1580 struct pipe_resource *res = sctx->images[PIPE_SHADER_VERTEX].views[i].resource;
1581 if (!res)
1582 continue;
1583
1584 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1585 RADEON_USAGE_WRITE))
1586 goto has_write_reference;
1587 }
1588 }
1589
1590 return true;
1591
1592 has_write_reference:
1593 /* If the current gfx IB has enough packets, flush it to remove write
1594 * references to buffers.
1595 */
1596 if (cs->prev_dw + cs->current.cdw > 2048) {
1597 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1598 assert(si_all_vs_resources_read_only(sctx, indexbuf));
1599 return true;
1600 }
1601 return false;
1602 }
1603
1604 static ALWAYS_INLINE bool pd_msg(const char *s)
1605 {
1606 if (SI_PRIM_DISCARD_DEBUG)
1607 printf("PD failed: %s\n", s);
1608 return false;
1609 }
1610
1611 static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1612 {
1613 struct si_context *sctx = (struct si_context *)ctx;
1614 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1615 struct pipe_resource *indexbuf = info->index.resource;
1616 unsigned dirty_tex_counter, dirty_buf_counter;
1617 enum pipe_prim_type rast_prim, prim = info->mode;
1618 unsigned index_size = info->index_size;
1619 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1620 unsigned instance_count = info->instance_count;
1621 bool primitive_restart = info->primitive_restart &&
1622 (!sctx->screen->options.prim_restart_tri_strips_only ||
1623 (prim != PIPE_PRIM_TRIANGLE_STRIP &&
1624 prim != PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY));
1625
1626 if (likely(!info->indirect)) {
1627 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
1628 * no workaround for indirect draws, but we can at least skip
1629 * direct draws.
1630 */
1631 if (unlikely(!instance_count))
1632 return;
1633
1634 /* Handle count == 0. */
1635 if (unlikely(!info->count &&
1636 (index_size || !info->count_from_stream_output)))
1637 return;
1638 }
1639
1640 if (unlikely(!sctx->vs_shader.cso ||
1641 !rs ||
1642 (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
1643 (!!sctx->tes_shader.cso != (prim == PIPE_PRIM_PATCHES)))) {
1644 assert(0);
1645 return;
1646 }
1647
1648 /* Recompute and re-emit the texture resource states if needed. */
1649 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1650 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1651 sctx->last_dirty_tex_counter = dirty_tex_counter;
1652 sctx->framebuffer.dirty_cbufs |=
1653 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1654 sctx->framebuffer.dirty_zsbuf = true;
1655 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1656 si_update_all_texture_descriptors(sctx);
1657 }
1658
1659 dirty_buf_counter = p_atomic_read(&sctx->screen->dirty_buf_counter);
1660 if (unlikely(dirty_buf_counter != sctx->last_dirty_buf_counter)) {
1661 sctx->last_dirty_buf_counter = dirty_buf_counter;
1662 /* Rebind all buffers unconditionally. */
1663 si_rebind_buffer(sctx, NULL);
1664 }
1665
1666 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1667
1668 /* Set the rasterization primitive type.
1669 *
1670 * This must be done after si_decompress_textures, which can call
1671 * draw_vbo recursively, and before si_update_shaders, which uses
1672 * current_rast_prim for this draw_vbo call. */
1673 if (sctx->gs_shader.cso)
1674 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1675 else if (sctx->tes_shader.cso) {
1676 if (sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1677 rast_prim = PIPE_PRIM_POINTS;
1678 else
1679 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1680 } else
1681 rast_prim = prim;
1682
1683 if (rast_prim != sctx->current_rast_prim) {
1684 if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
1685 util_prim_is_points_or_lines(rast_prim))
1686 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1687
1688 sctx->current_rast_prim = rast_prim;
1689 sctx->do_update_shaders = true;
1690 }
1691
1692 if (sctx->tes_shader.cso &&
1693 sctx->screen->has_ls_vgpr_init_bug) {
1694 /* Determine whether the LS VGPR fix should be applied.
1695 *
1696 * It is only required when num input CPs > num output CPs,
1697 * which cannot happen with the fixed function TCS. We should
1698 * also update this bit when switching from TCS to fixed
1699 * function TCS.
1700 */
1701 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1702 bool ls_vgpr_fix =
1703 tcs &&
1704 info->vertices_per_patch >
1705 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1706
1707 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1708 sctx->ls_vgpr_fix = ls_vgpr_fix;
1709 sctx->do_update_shaders = true;
1710 }
1711 }
1712
1713 if (sctx->gs_shader.cso) {
1714 /* Determine whether the GS triangle strip adjacency fix should
1715 * be applied. Rotate every other triangle if
1716 * - triangle strips with adjacency are fed to the GS and
1717 * - primitive restart is disabled (the rotation doesn't help
1718 * when the restart occurs after an odd number of triangles).
1719 */
1720 bool gs_tri_strip_adj_fix =
1721 !sctx->tes_shader.cso &&
1722 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1723 !primitive_restart;
1724
1725 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1726 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1727 sctx->do_update_shaders = true;
1728 }
1729 }
1730
1731 if (index_size) {
1732 /* Translate or upload, if needed. */
1733 /* 8-bit indices are supported on GFX8. */
1734 if (sctx->chip_class <= GFX7 && index_size == 1) {
1735 unsigned start, count, start_offset, size, offset;
1736 void *ptr;
1737
1738 si_get_draw_start_count(sctx, info, &start, &count);
1739 start_offset = start * 2;
1740 size = count * 2;
1741
1742 indexbuf = NULL;
1743 u_upload_alloc(ctx->stream_uploader, start_offset,
1744 size,
1745 si_optimal_tcc_alignment(sctx, size),
1746 &offset, &indexbuf, &ptr);
1747 if (!indexbuf)
1748 return;
1749
1750 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1751 index_offset + start,
1752 count, ptr);
1753
1754 /* info->start will be added by the drawing code */
1755 index_offset = offset - start_offset;
1756 index_size = 2;
1757 } else if (info->has_user_indices) {
1758 unsigned start_offset;
1759
1760 assert(!info->indirect);
1761 start_offset = info->start * index_size;
1762
1763 indexbuf = NULL;
1764 u_upload_data(ctx->stream_uploader, start_offset,
1765 info->count * index_size,
1766 sctx->screen->info.tcc_cache_line_size,
1767 (char*)info->index.user + start_offset,
1768 &index_offset, &indexbuf);
1769 if (!indexbuf)
1770 return;
1771
1772 /* info->start will be added by the drawing code */
1773 index_offset -= start_offset;
1774 } else if (sctx->chip_class <= GFX7 &&
1775 si_resource(indexbuf)->TC_L2_dirty) {
1776 /* GFX8 reads index buffers through TC L2, so it doesn't
1777 * need this. */
1778 sctx->flags |= SI_CONTEXT_WB_L2;
1779 si_resource(indexbuf)->TC_L2_dirty = false;
1780 }
1781 }
1782
1783 bool dispatch_prim_discard_cs = false;
1784 bool prim_discard_cs_instancing = false;
1785 unsigned original_index_size = index_size;
1786 unsigned direct_count = 0;
1787
1788 if (info->indirect) {
1789 struct pipe_draw_indirect_info *indirect = info->indirect;
1790
1791 /* Add the buffer size for memory checking in need_cs_space. */
1792 si_context_add_resource_size(sctx, indirect->buffer);
1793
1794 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1795 if (sctx->chip_class <= GFX8) {
1796 if (si_resource(indirect->buffer)->TC_L2_dirty) {
1797 sctx->flags |= SI_CONTEXT_WB_L2;
1798 si_resource(indirect->buffer)->TC_L2_dirty = false;
1799 }
1800
1801 if (indirect->indirect_draw_count &&
1802 si_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1803 sctx->flags |= SI_CONTEXT_WB_L2;
1804 si_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1805 }
1806 }
1807 } else {
1808 /* Multiply by 3 for strips and fans to get an approximate vertex
1809 * count as triangles. */
1810 direct_count = info->count * instance_count *
1811 (prim == PIPE_PRIM_TRIANGLES ? 1 : 3);
1812 }
1813
1814 /* Determine if we can use the primitive discard compute shader. */
1815 if (si_compute_prim_discard_enabled(sctx) &&
1816 (direct_count > sctx->prim_discard_vertex_count_threshold ?
1817 (sctx->compute_num_verts_rejected += direct_count, true) : /* Add, then return true. */
1818 (sctx->compute_num_verts_ineligible += direct_count, false)) && /* Add, then return false. */
1819 (!info->count_from_stream_output || pd_msg("draw_opaque")) &&
1820 (primitive_restart ?
1821 /* Supported prim types with primitive restart: */
1822 (prim == PIPE_PRIM_TRIANGLE_STRIP || pd_msg("bad prim type with primitive restart")) &&
1823 /* Disallow instancing with primitive restart: */
1824 (instance_count == 1 || pd_msg("instance_count > 1 with primitive restart")) :
1825 /* Supported prim types without primitive restart + allow instancing: */
1826 (1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1827 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1828 (1 << PIPE_PRIM_TRIANGLE_FAN)) &&
1829 /* Instancing is limited to 16-bit indices, because InstanceID is packed into VertexID. */
1830 /* TODO: DrawArraysInstanced doesn't sometimes work, so it's disabled. */
1831 (instance_count == 1 ||
1832 (instance_count <= USHRT_MAX && index_size && index_size <= 2) ||
1833 pd_msg("instance_count too large or index_size == 4 or DrawArraysInstanced"))) &&
1834 (info->drawid == 0 || !sctx->vs_shader.cso->info.uses_drawid || pd_msg("draw_id > 0")) &&
1835 (!sctx->render_cond || pd_msg("render condition")) &&
1836 /* Forced enablement ignores pipeline statistics queries. */
1837 (sctx->screen->debug_flags & (DBG(PD) | DBG(ALWAYS_PD)) ||
1838 (!sctx->num_pipeline_stat_queries && !sctx->streamout.prims_gen_query_enabled) ||
1839 pd_msg("pipestat or primgen query")) &&
1840 (!sctx->vertex_elements->instance_divisor_is_fetched || pd_msg("loads instance divisors")) &&
1841 (!sctx->tes_shader.cso || pd_msg("uses tess")) &&
1842 (!sctx->gs_shader.cso || pd_msg("uses GS")) &&
1843 (!sctx->ps_shader.cso->info.uses_primid || pd_msg("PS uses PrimID")) &&
1844 #if SI_PRIM_DISCARD_DEBUG /* same as cso->prim_discard_cs_allowed */
1845 (!sctx->vs_shader.cso->info.uses_bindless_images || pd_msg("uses bindless images")) &&
1846 (!sctx->vs_shader.cso->info.uses_bindless_samplers || pd_msg("uses bindless samplers")) &&
1847 (!sctx->vs_shader.cso->info.writes_memory || pd_msg("writes memory")) &&
1848 (!sctx->vs_shader.cso->info.writes_viewport_index || pd_msg("writes viewport index")) &&
1849 !sctx->vs_shader.cso->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
1850 !sctx->vs_shader.cso->so.num_outputs &&
1851 #else
1852 (sctx->vs_shader.cso->prim_discard_cs_allowed || pd_msg("VS shader uses unsupported features")) &&
1853 #endif
1854 /* Check that all buffers are used for read only, because compute
1855 * dispatches can run ahead. */
1856 (si_all_vs_resources_read_only(sctx, index_size ? indexbuf : NULL) || pd_msg("write reference"))) {
1857 switch (si_prepare_prim_discard_or_split_draw(sctx, info, primitive_restart)) {
1858 case SI_PRIM_DISCARD_ENABLED:
1859 original_index_size = index_size;
1860 prim_discard_cs_instancing = instance_count > 1;
1861 dispatch_prim_discard_cs = true;
1862
1863 /* The compute shader changes/lowers the following: */
1864 prim = PIPE_PRIM_TRIANGLES;
1865 index_size = 4;
1866 instance_count = 1;
1867 primitive_restart = false;
1868 sctx->compute_num_verts_rejected -= direct_count;
1869 sctx->compute_num_verts_accepted += direct_count;
1870 break;
1871 case SI_PRIM_DISCARD_DISABLED:
1872 break;
1873 case SI_PRIM_DISCARD_DRAW_SPLIT:
1874 sctx->compute_num_verts_rejected -= direct_count;
1875 goto return_cleanup;
1876 }
1877 }
1878
1879 if (prim_discard_cs_instancing != sctx->prim_discard_cs_instancing) {
1880 sctx->prim_discard_cs_instancing = prim_discard_cs_instancing;
1881 sctx->do_update_shaders = true;
1882 }
1883
1884 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1885 goto return_cleanup;
1886
1887 si_need_gfx_cs_space(sctx);
1888
1889 if (sctx->bo_list_add_all_gfx_resources)
1890 si_gfx_resources_add_all_to_bo_list(sctx);
1891
1892 /* Since we've called si_context_add_resource_size for vertex buffers,
1893 * this must be called after si_need_cs_space, because we must let
1894 * need_cs_space flush before we add buffers to the buffer list.
1895 */
1896 if (!si_upload_vertex_buffer_descriptors(sctx))
1897 goto return_cleanup;
1898
1899 /* Vega10/Raven scissor bug workaround. When any context register is
1900 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
1901 * registers must be written too.
1902 */
1903 bool has_gfx9_scissor_bug = sctx->screen->has_gfx9_scissor_bug;
1904 unsigned masked_atoms = 0;
1905
1906 if (has_gfx9_scissor_bug) {
1907 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
1908
1909 if (info->count_from_stream_output ||
1910 sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
1911 sctx->dirty_states & si_states_that_always_roll_context())
1912 sctx->context_roll = true;
1913 }
1914
1915 /* Use optimal packet order based on whether we need to sync the pipeline. */
1916 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1917 SI_CONTEXT_FLUSH_AND_INV_DB |
1918 SI_CONTEXT_PS_PARTIAL_FLUSH |
1919 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1920 /* If we have to wait for idle, set all states first, so that all
1921 * SET packets are processed in parallel with previous draw calls.
1922 * Then draw and prefetch at the end. This ensures that the time
1923 * the CUs are idle is very short.
1924 */
1925 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
1926 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
1927
1928 if (!si_upload_graphics_shader_descriptors(sctx))
1929 goto return_cleanup;
1930
1931 /* Emit all states except possibly render condition. */
1932 si_emit_all_states(sctx, info, prim, instance_count,
1933 primitive_restart, masked_atoms);
1934 sctx->emit_cache_flush(sctx);
1935 /* <-- CUs are idle here. */
1936
1937 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
1938 sctx->atoms.s.render_cond.emit(sctx);
1939
1940 if (has_gfx9_scissor_bug &&
1941 (sctx->context_roll ||
1942 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
1943 sctx->atoms.s.scissors.emit(sctx);
1944
1945 sctx->dirty_atoms = 0;
1946
1947 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
1948 instance_count, dispatch_prim_discard_cs,
1949 original_index_size);
1950 /* <-- CUs are busy here. */
1951
1952 /* Start prefetches after the draw has been started. Both will run
1953 * in parallel, but starting the draw first is more important.
1954 */
1955 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
1956 cik_emit_prefetch_L2(sctx, false);
1957 } else {
1958 /* If we don't wait for idle, start prefetches first, then set
1959 * states, and draw at the end.
1960 */
1961 if (sctx->flags)
1962 sctx->emit_cache_flush(sctx);
1963
1964 /* Only prefetch the API VS and VBO descriptors. */
1965 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
1966 cik_emit_prefetch_L2(sctx, true);
1967
1968 if (!si_upload_graphics_shader_descriptors(sctx))
1969 goto return_cleanup;
1970
1971 si_emit_all_states(sctx, info, prim, instance_count,
1972 primitive_restart, masked_atoms);
1973
1974 if (has_gfx9_scissor_bug &&
1975 (sctx->context_roll ||
1976 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
1977 sctx->atoms.s.scissors.emit(sctx);
1978
1979 sctx->dirty_atoms = 0;
1980
1981 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
1982 instance_count, dispatch_prim_discard_cs,
1983 original_index_size);
1984
1985 /* Prefetch the remaining shaders after the draw has been
1986 * started. */
1987 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
1988 cik_emit_prefetch_L2(sctx, false);
1989 }
1990
1991 /* Clear the context roll flag after the draw call. */
1992 sctx->context_roll = false;
1993
1994 if (unlikely(sctx->current_saved_cs)) {
1995 si_trace_emit(sctx);
1996 si_log_draw_state(sctx, sctx->log);
1997 }
1998
1999 /* Workaround for a VGT hang when streamout is enabled.
2000 * It must be done after drawing. */
2001 if ((sctx->family == CHIP_HAWAII ||
2002 sctx->family == CHIP_TONGA ||
2003 sctx->family == CHIP_FIJI) &&
2004 si_get_strmout_en(sctx)) {
2005 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
2006 }
2007
2008 if (unlikely(sctx->decompression_enabled)) {
2009 sctx->num_decompress_calls++;
2010 } else {
2011 sctx->num_draw_calls++;
2012 if (sctx->framebuffer.state.nr_cbufs > 1)
2013 sctx->num_mrt_draw_calls++;
2014 if (primitive_restart)
2015 sctx->num_prim_restart_calls++;
2016 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
2017 sctx->num_spill_draw_calls++;
2018 }
2019
2020 return_cleanup:
2021 if (index_size && indexbuf != info->index.resource)
2022 pipe_resource_reference(&indexbuf, NULL);
2023 }
2024
2025 static void
2026 si_draw_rectangle(struct blitter_context *blitter,
2027 void *vertex_elements_cso,
2028 blitter_get_vs_func get_vs,
2029 int x1, int y1, int x2, int y2,
2030 float depth, unsigned num_instances,
2031 enum blitter_attrib_type type,
2032 const union blitter_attrib *attrib)
2033 {
2034 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
2035 struct si_context *sctx = (struct si_context*)pipe;
2036
2037 /* Pack position coordinates as signed int16. */
2038 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
2039 ((uint32_t)(y1 & 0xffff) << 16);
2040 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
2041 ((uint32_t)(y2 & 0xffff) << 16);
2042 sctx->vs_blit_sh_data[2] = fui(depth);
2043
2044 switch (type) {
2045 case UTIL_BLITTER_ATTRIB_COLOR:
2046 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
2047 sizeof(float)*4);
2048 break;
2049 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
2050 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
2051 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
2052 sizeof(attrib->texcoord));
2053 break;
2054 case UTIL_BLITTER_ATTRIB_NONE:;
2055 }
2056
2057 pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
2058
2059 struct pipe_draw_info info = {};
2060 info.mode = SI_PRIM_RECTANGLE_LIST;
2061 info.count = 3;
2062 info.instance_count = num_instances;
2063
2064 /* Don't set per-stage shader pointers for VS. */
2065 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
2066 sctx->vertex_buffer_pointer_dirty = false;
2067
2068 si_draw_vbo(pipe, &info);
2069 }
2070
2071 void si_trace_emit(struct si_context *sctx)
2072 {
2073 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2074 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
2075
2076 si_cp_write_data(sctx, sctx->current_saved_cs->trace_buf,
2077 0, 4, V_370_MEM, V_370_ME, &trace_id);
2078
2079 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2080 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
2081
2082 if (sctx->log)
2083 u_log_flush(sctx->log);
2084 }
2085
2086 void si_init_draw_functions(struct si_context *sctx)
2087 {
2088 sctx->b.draw_vbo = si_draw_vbo;
2089
2090 sctx->blitter->draw_rectangle = si_draw_rectangle;
2091
2092 si_init_ia_multi_vgt_param_table(sctx);
2093 }