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radeonsi: Add FLUSH_AND_INV_CB_DATA_TS for DCC.
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "radeon/r600_cs.h"
30 #include "sid.h"
31
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
35
36 static void si_decompress_textures(struct si_context *sctx)
37 {
38 if (!sctx->blitter->running) {
39 /* Flush depth textures which need to be flushed. */
40 for (int i = 0; i < SI_NUM_SHADERS; i++) {
41 if (sctx->samplers[i].depth_texture_mask) {
42 si_flush_depth_textures(sctx, &sctx->samplers[i]);
43 }
44 if (sctx->samplers[i].compressed_colortex_mask) {
45 si_decompress_color_textures(sctx, &sctx->samplers[i]);
46 }
47 }
48 }
49 }
50
51 static unsigned si_conv_pipe_prim(unsigned mode)
52 {
53 static const unsigned prim_conv[] = {
54 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
55 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
56 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
57 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
58 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
59 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
60 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
61 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
62 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
63 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
64 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
65 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
66 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
67 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
68 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
69 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
70 };
71 assert(mode < Elements(prim_conv));
72 return prim_conv[mode];
73 }
74
75 static unsigned si_conv_prim_to_gs_out(unsigned mode)
76 {
77 static const int prim_conv[] = {
78 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
79 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
80 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
81 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
82 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
83 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
84 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
85 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
86 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
87 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
88 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
89 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
90 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
91 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
92 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
93 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
94 };
95 assert(mode < Elements(prim_conv));
96
97 return prim_conv[mode];
98 }
99
100 /**
101 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
102 * LS.LDS_SIZE is shared by all 3 shader stages.
103 *
104 * The information about LDS and other non-compile-time parameters is then
105 * written to userdata SGPRs.
106 */
107 static void si_emit_derived_tess_state(struct si_context *sctx,
108 const struct pipe_draw_info *info,
109 unsigned *num_patches)
110 {
111 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
112 struct si_shader_ctx_state *ls = &sctx->vs_shader;
113 /* The TES pointer will only be used for sctx->last_tcs.
114 * It would be wrong to think that TCS = TES. */
115 struct si_shader_selector *tcs =
116 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
117 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
118 unsigned num_tcs_input_cp = info->vertices_per_patch;
119 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
120 unsigned num_tcs_patch_outputs;
121 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
122 unsigned input_patch_size, output_patch_size, output_patch0_offset;
123 unsigned perpatch_output_offset, lds_size, ls_rsrc2;
124 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
125
126 *num_patches = 1; /* TODO: calculate this */
127
128 if (sctx->last_ls == ls->current &&
129 sctx->last_tcs == tcs &&
130 sctx->last_tes_sh_base == tes_sh_base &&
131 sctx->last_num_tcs_input_cp == num_tcs_input_cp)
132 return;
133
134 sctx->last_ls = ls->current;
135 sctx->last_tcs = tcs;
136 sctx->last_tes_sh_base = tes_sh_base;
137 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
138
139 /* This calculates how shader inputs and outputs among VS, TCS, and TES
140 * are laid out in LDS. */
141 num_tcs_inputs = util_last_bit64(ls->cso->outputs_written);
142
143 if (sctx->tcs_shader.cso) {
144 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
145 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
146 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
147 } else {
148 /* No TCS. Route varyings from LS to TES. */
149 num_tcs_outputs = num_tcs_inputs;
150 num_tcs_output_cp = num_tcs_input_cp;
151 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
152 }
153
154 input_vertex_size = num_tcs_inputs * 16;
155 output_vertex_size = num_tcs_outputs * 16;
156
157 input_patch_size = num_tcs_input_cp * input_vertex_size;
158
159 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
160 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
161
162 output_patch0_offset = sctx->tcs_shader.cso ? input_patch_size * *num_patches : 0;
163 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
164
165 lds_size = output_patch0_offset + output_patch_size * *num_patches;
166 ls_rsrc2 = ls->current->ls_rsrc2;
167
168 if (sctx->b.chip_class >= CIK) {
169 assert(lds_size <= 65536);
170 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 512) / 512);
171 } else {
172 assert(lds_size <= 32768);
173 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 256) / 256);
174 }
175
176 /* Due to a hw bug, RSRC2_LS must be written twice with another
177 * LS register written in between. */
178 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
179 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
180 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
181 radeon_emit(cs, ls->current->ls_rsrc1);
182 radeon_emit(cs, ls_rsrc2);
183
184 /* Compute userdata SGPRs. */
185 assert(((input_vertex_size / 4) & ~0xff) == 0);
186 assert(((output_vertex_size / 4) & ~0xff) == 0);
187 assert(((input_patch_size / 4) & ~0x1fff) == 0);
188 assert(((output_patch_size / 4) & ~0x1fff) == 0);
189 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
190 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
191 assert(num_tcs_input_cp <= 32);
192 assert(num_tcs_output_cp <= 32);
193
194 tcs_in_layout = (input_patch_size / 4) |
195 ((input_vertex_size / 4) << 13);
196 tcs_out_layout = (output_patch_size / 4) |
197 ((output_vertex_size / 4) << 13);
198 tcs_out_offsets = (output_patch0_offset / 16) |
199 ((perpatch_output_offset / 16) << 16);
200
201 /* Set them for LS. */
202 radeon_set_sh_reg(cs,
203 R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4,
204 tcs_in_layout);
205
206 /* Set them for TCS. */
207 radeon_set_sh_reg_seq(cs,
208 R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OUT_OFFSETS * 4, 3);
209 radeon_emit(cs, tcs_out_offsets);
210 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
211 radeon_emit(cs, tcs_in_layout);
212
213 /* Set them for TES. */
214 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OUT_OFFSETS * 4, 2);
215 radeon_emit(cs, tcs_out_offsets);
216 radeon_emit(cs, tcs_out_layout | (num_tcs_output_cp << 26));
217 }
218
219 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
220 const struct pipe_draw_info *info,
221 unsigned num_patches)
222 {
223 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
224 unsigned prim = info->mode;
225 unsigned primgroup_size = 128; /* recommended without a GS */
226 unsigned max_primgroup_in_wave = 2;
227
228 /* SWITCH_ON_EOP(0) is always preferable. */
229 bool wd_switch_on_eop = false;
230 bool ia_switch_on_eop = false;
231 bool ia_switch_on_eoi = false;
232 bool partial_vs_wave = false;
233 bool partial_es_wave = false;
234
235 if (sctx->gs_shader.cso)
236 primgroup_size = 64; /* recommended with a GS */
237
238 if (sctx->tes_shader.cso) {
239 unsigned num_cp_out =
240 sctx->tcs_shader.cso ?
241 sctx->tcs_shader.cso->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
242 info->vertices_per_patch;
243 unsigned max_size = 256 / MAX2(info->vertices_per_patch, num_cp_out);
244
245 primgroup_size = MIN2(primgroup_size, max_size);
246
247 /* primgroup_size must be set to a multiple of NUM_PATCHES */
248 primgroup_size = (primgroup_size / num_patches) * num_patches;
249
250 /* SWITCH_ON_EOI must be set if PrimID is used. */
251 if ((sctx->tcs_shader.cso && sctx->tcs_shader.cso->info.uses_primid) ||
252 sctx->tes_shader.cso->info.uses_primid)
253 ia_switch_on_eoi = true;
254
255 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
256 if ((sctx->b.family == CHIP_TAHITI ||
257 sctx->b.family == CHIP_PITCAIRN ||
258 sctx->b.family == CHIP_BONAIRE) &&
259 sctx->gs_shader.cso)
260 partial_vs_wave = true;
261 }
262
263 /* This is a hardware requirement. */
264 if ((rs && rs->line_stipple_enable) ||
265 (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
266 ia_switch_on_eop = true;
267 wd_switch_on_eop = true;
268 }
269
270 if (sctx->b.chip_class >= CIK) {
271 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
272 * 4 shader engines. Set 1 to pass the assertion below.
273 * The other cases are hardware requirements. */
274 if (sctx->b.screen->info.max_se < 4 ||
275 prim == PIPE_PRIM_POLYGON ||
276 prim == PIPE_PRIM_LINE_LOOP ||
277 prim == PIPE_PRIM_TRIANGLE_FAN ||
278 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
279 info->primitive_restart ||
280 info->count_from_stream_output)
281 wd_switch_on_eop = true;
282
283 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
284 * We don't know that for indirect drawing, so treat it as
285 * always problematic. */
286 if (sctx->b.family == CHIP_HAWAII &&
287 (info->indirect || info->instance_count > 1))
288 wd_switch_on_eop = true;
289
290 /* Required on CIK and later. */
291 if (sctx->b.screen->info.max_se > 2 && !wd_switch_on_eop)
292 ia_switch_on_eoi = true;
293
294 /* Required by Hawaii and, for some special cases, by VI. */
295 if (ia_switch_on_eoi &&
296 (sctx->b.family == CHIP_HAWAII ||
297 (sctx->b.chip_class == VI &&
298 (sctx->gs_shader.cso || max_primgroup_in_wave != 2))))
299 partial_vs_wave = true;
300
301 /* Instancing bug on Bonaire. */
302 if (sctx->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
303 (info->indirect || info->instance_count > 1))
304 partial_vs_wave = true;
305
306 /* If the WD switch is false, the IA switch must be false too. */
307 assert(wd_switch_on_eop || !ia_switch_on_eop);
308 }
309
310 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
311 if (ia_switch_on_eoi)
312 partial_es_wave = true;
313
314 /* GS requirement. */
315 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
316 partial_es_wave = true;
317
318 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
319 * on multi-SE chips. */
320 if (sctx->b.screen->info.max_se >= 2 && ia_switch_on_eoi &&
321 (info->indirect ||
322 (info->instance_count > 1 &&
323 u_prims_for_vertices(info->mode, info->count) <= 1)))
324 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
325
326 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
327 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
328 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
329 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
330 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
331 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
332 S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx->b.chip_class >= VI ?
333 max_primgroup_in_wave : 0);
334 }
335
336 static unsigned si_get_ls_hs_config(struct si_context *sctx,
337 const struct pipe_draw_info *info,
338 unsigned num_patches)
339 {
340 unsigned num_output_cp;
341
342 if (!sctx->tes_shader.cso)
343 return 0;
344
345 num_output_cp = sctx->tcs_shader.cso ?
346 sctx->tcs_shader.cso->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
347 info->vertices_per_patch;
348
349 return S_028B58_NUM_PATCHES(num_patches) |
350 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
351 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
352 }
353
354 static void si_emit_scratch_reloc(struct si_context *sctx)
355 {
356 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
357
358 if (!sctx->emit_scratch_reloc)
359 return;
360
361 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
362 sctx->spi_tmpring_size);
363
364 if (sctx->scratch_buffer) {
365 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
366 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
367 RADEON_PRIO_SCRATCH_BUFFER);
368
369 }
370 sctx->emit_scratch_reloc = false;
371 }
372
373 /* rast_prim is the primitive type after GS. */
374 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
375 {
376 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
377 unsigned rast_prim = sctx->current_rast_prim;
378 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
379
380 /* Skip this if not rendering lines. */
381 if (rast_prim != PIPE_PRIM_LINES &&
382 rast_prim != PIPE_PRIM_LINE_LOOP &&
383 rast_prim != PIPE_PRIM_LINE_STRIP &&
384 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
385 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
386 return;
387
388 if (rast_prim == sctx->last_rast_prim &&
389 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
390 return;
391
392 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
393 rs->pa_sc_line_stipple |
394 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 :
395 rast_prim == PIPE_PRIM_LINE_STRIP ? 2 : 0));
396
397 sctx->last_rast_prim = rast_prim;
398 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
399 }
400
401 static void si_emit_draw_registers(struct si_context *sctx,
402 const struct pipe_draw_info *info)
403 {
404 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
405 unsigned prim = si_conv_pipe_prim(info->mode);
406 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
407 unsigned ia_multi_vgt_param, ls_hs_config, num_patches = 0;
408
409 if (sctx->tes_shader.cso)
410 si_emit_derived_tess_state(sctx, info, &num_patches);
411
412 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
413 ls_hs_config = si_get_ls_hs_config(sctx, info, num_patches);
414
415 /* Draw state. */
416 if (prim != sctx->last_prim ||
417 ia_multi_vgt_param != sctx->last_multi_vgt_param ||
418 ls_hs_config != sctx->last_ls_hs_config) {
419 if (sctx->b.chip_class >= CIK) {
420 radeon_emit(cs, PKT3(PKT3_DRAW_PREAMBLE, 2, 0));
421 radeon_emit(cs, prim); /* VGT_PRIMITIVE_TYPE */
422 radeon_emit(cs, ia_multi_vgt_param); /* IA_MULTI_VGT_PARAM */
423 radeon_emit(cs, ls_hs_config); /* VGT_LS_HS_CONFIG */
424 } else {
425 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
426 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
427 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
428 }
429 sctx->last_prim = prim;
430 sctx->last_multi_vgt_param = ia_multi_vgt_param;
431 sctx->last_ls_hs_config = ls_hs_config;
432 }
433
434 if (gs_out_prim != sctx->last_gs_out_prim) {
435 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
436 sctx->last_gs_out_prim = gs_out_prim;
437 }
438
439 /* Primitive restart. */
440 if (info->primitive_restart != sctx->last_primitive_restart_en) {
441 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
442 sctx->last_primitive_restart_en = info->primitive_restart;
443
444 if (info->primitive_restart &&
445 (info->restart_index != sctx->last_restart_index ||
446 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
447 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
448 info->restart_index);
449 sctx->last_restart_index = info->restart_index;
450 }
451 }
452 }
453
454 static void si_emit_draw_packets(struct si_context *sctx,
455 const struct pipe_draw_info *info,
456 const struct pipe_index_buffer *ib)
457 {
458 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
459 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
460
461 if (info->count_from_stream_output) {
462 struct r600_so_target *t =
463 (struct r600_so_target*)info->count_from_stream_output;
464 uint64_t va = t->buf_filled_size->gpu_address +
465 t->buf_filled_size_offset;
466
467 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
468 t->stride_in_dw);
469
470 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
471 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
472 COPY_DATA_DST_SEL(COPY_DATA_REG) |
473 COPY_DATA_WR_CONFIRM);
474 radeon_emit(cs, va); /* src address lo */
475 radeon_emit(cs, va >> 32); /* src address hi */
476 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
477 radeon_emit(cs, 0); /* unused */
478
479 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
480 t->buf_filled_size, RADEON_USAGE_READ,
481 RADEON_PRIO_SO_FILLED_SIZE);
482 }
483
484 /* draw packet */
485 if (info->indexed) {
486 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
487
488 /* index type */
489 switch (ib->index_size) {
490 case 1:
491 radeon_emit(cs, V_028A7C_VGT_INDEX_8);
492 break;
493 case 2:
494 radeon_emit(cs, V_028A7C_VGT_INDEX_16 |
495 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
496 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
497 break;
498 case 4:
499 radeon_emit(cs, V_028A7C_VGT_INDEX_32 |
500 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
501 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
502 break;
503 default:
504 assert(!"unreachable");
505 return;
506 }
507 }
508
509 if (!info->indirect) {
510 int base_vertex;
511
512 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
513 radeon_emit(cs, info->instance_count);
514
515 /* Base vertex and start instance. */
516 base_vertex = info->indexed ? info->index_bias : info->start;
517
518 if (base_vertex != sctx->last_base_vertex ||
519 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
520 info->start_instance != sctx->last_start_instance ||
521 sh_base_reg != sctx->last_sh_base_reg) {
522 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
523 radeon_emit(cs, base_vertex);
524 radeon_emit(cs, info->start_instance);
525
526 sctx->last_base_vertex = base_vertex;
527 sctx->last_start_instance = info->start_instance;
528 sctx->last_sh_base_reg = sh_base_reg;
529 }
530 } else {
531 si_invalidate_draw_sh_constants(sctx);
532
533 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
534 (struct r600_resource *)info->indirect,
535 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
536 }
537
538 if (info->indexed) {
539 uint32_t index_max_size = (ib->buffer->width0 - ib->offset) /
540 ib->index_size;
541 uint64_t index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
542
543 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
544 (struct r600_resource *)ib->buffer,
545 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
546
547 if (info->indirect) {
548 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
549
550 assert(indirect_va % 8 == 0);
551 assert(index_va % 2 == 0);
552 assert(info->indirect_offset % 4 == 0);
553
554 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
555 radeon_emit(cs, 1);
556 radeon_emit(cs, indirect_va);
557 radeon_emit(cs, indirect_va >> 32);
558
559 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
560 radeon_emit(cs, index_va);
561 radeon_emit(cs, index_va >> 32);
562
563 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
564 radeon_emit(cs, index_max_size);
565
566 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT, 3, sctx->b.predicate_drawing));
567 radeon_emit(cs, info->indirect_offset);
568 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
569 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
570 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
571 } else {
572 index_va += info->start * ib->index_size;
573
574 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, sctx->b.predicate_drawing));
575 radeon_emit(cs, index_max_size);
576 radeon_emit(cs, index_va);
577 radeon_emit(cs, (index_va >> 32UL) & 0xFF);
578 radeon_emit(cs, info->count);
579 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
580 }
581 } else {
582 if (info->indirect) {
583 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
584
585 assert(indirect_va % 8 == 0);
586 assert(info->indirect_offset % 4 == 0);
587
588 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
589 radeon_emit(cs, 1);
590 radeon_emit(cs, indirect_va);
591 radeon_emit(cs, indirect_va >> 32);
592
593 radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, sctx->b.predicate_drawing));
594 radeon_emit(cs, info->indirect_offset);
595 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
596 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
597 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
598 } else {
599 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, sctx->b.predicate_drawing));
600 radeon_emit(cs, info->count);
601 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
602 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
603 }
604 }
605 }
606
607 #define BOTH_ICACHE_KCACHE (SI_CONTEXT_INV_ICACHE | SI_CONTEXT_INV_KCACHE)
608
609 void si_emit_cache_flush(struct si_context *si_ctx, struct r600_atom *atom)
610 {
611 struct r600_common_context *sctx = &si_ctx->b;
612 struct radeon_winsys_cs *cs = sctx->rings.gfx.cs;
613 uint32_t cp_coher_cntl = 0;
614 uint32_t compute =
615 PKT3_SHADER_TYPE_S(!!(sctx->flags & SI_CONTEXT_FLAG_COMPUTE));
616
617 /* SI has a bug that it always flushes ICACHE and KCACHE if either
618 * bit is set. An alternative way is to write SQC_CACHES, but that
619 * doesn't seem to work reliably. Since the bug doesn't affect
620 * correctness (it only does more work than necessary) and
621 * the performance impact is likely negligible, there is no plan
622 * to fix it.
623 */
624
625 if (sctx->flags & SI_CONTEXT_INV_ICACHE)
626 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
627 if (sctx->flags & SI_CONTEXT_INV_KCACHE)
628 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
629
630 if (sctx->flags & SI_CONTEXT_INV_TC_L1)
631 cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
632 if (sctx->flags & SI_CONTEXT_INV_TC_L2) {
633 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
634
635 /* TODO: this might not be needed. */
636 if (sctx->chip_class >= VI)
637 cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1);
638 }
639
640 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
641 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
642 S_0085F0_CB0_DEST_BASE_ENA(1) |
643 S_0085F0_CB1_DEST_BASE_ENA(1) |
644 S_0085F0_CB2_DEST_BASE_ENA(1) |
645 S_0085F0_CB3_DEST_BASE_ENA(1) |
646 S_0085F0_CB4_DEST_BASE_ENA(1) |
647 S_0085F0_CB5_DEST_BASE_ENA(1) |
648 S_0085F0_CB6_DEST_BASE_ENA(1) |
649 S_0085F0_CB7_DEST_BASE_ENA(1);
650
651 /* Necessary for DCC */
652 if (sctx->chip_class >= VI) {
653 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0) | compute);
654 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) |
655 EVENT_INDEX(5));
656 radeon_emit(cs, 0);
657 radeon_emit(cs, 0);
658 radeon_emit(cs, 0);
659 radeon_emit(cs, 0);
660 }
661 }
662 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
663 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
664 S_0085F0_DB_DEST_BASE_ENA(1);
665 }
666
667 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) {
668 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
669 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
670 }
671 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) {
672 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
673 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
674 }
675 if (sctx->flags & SI_CONTEXT_FLUSH_WITH_INV_L2) {
676 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
677 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH) | EVENT_INDEX(7) |
678 EVENT_WRITE_INV_L2);
679 }
680
681 /* FLUSH_AND_INV events must be emitted before PS_PARTIAL_FLUSH.
682 * Otherwise, clearing CMASK (CB meta) with CP DMA isn't reliable.
683 *
684 * I think the reason is that FLUSH_AND_INV is only added to a queue
685 * and it is PS_PARTIAL_FLUSH that waits for it to complete.
686 */
687 if (sctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
688 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
689 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
690 } else if (sctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
691 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
692 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
693 }
694 if (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH) {
695 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
696 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
697 }
698 if (sctx->flags & SI_CONTEXT_VGT_FLUSH) {
699 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
700 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
701 }
702 if (sctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
703 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
704 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
705 }
706
707 /* SURFACE_SYNC must be emitted after partial flushes.
708 * It looks like SURFACE_SYNC flushes caches immediately and doesn't
709 * wait for any engines. This should be last.
710 */
711 if (cp_coher_cntl) {
712 if (sctx->chip_class >= CIK) {
713 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) | compute);
714 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
715 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
716 radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */
717 radeon_emit(cs, 0); /* CP_COHER_BASE */
718 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
719 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
720 } else {
721 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0) | compute);
722 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
723 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
724 radeon_emit(cs, 0); /* CP_COHER_BASE */
725 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
726 }
727 }
728
729 sctx->flags = 0;
730 }
731
732 static void si_get_draw_start_count(struct si_context *sctx,
733 const struct pipe_draw_info *info,
734 unsigned *start, unsigned *count)
735 {
736 if (info->indirect) {
737 struct r600_resource *indirect =
738 (struct r600_resource*)info->indirect;
739 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
740 indirect, PIPE_TRANSFER_READ);
741 data += info->indirect_offset/sizeof(int);
742 *start = data[2];
743 *count = data[0];
744 } else {
745 *start = info->start;
746 *count = info->count;
747 }
748 }
749
750 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
751 {
752 struct si_context *sctx = (struct si_context *)ctx;
753 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
754 struct pipe_index_buffer ib = {};
755 unsigned mask;
756
757 if (!info->count && !info->indirect &&
758 (info->indexed || !info->count_from_stream_output))
759 return;
760
761 if (!sctx->vs_shader.cso) {
762 assert(0);
763 return;
764 }
765 if (!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard)) {
766 assert(0);
767 return;
768 }
769 if (!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES)) {
770 assert(0);
771 return;
772 }
773
774 si_decompress_textures(sctx);
775
776 /* Set the rasterization primitive type.
777 *
778 * This must be done after si_decompress_textures, which can call
779 * draw_vbo recursively, and before si_update_shaders, which uses
780 * current_rast_prim for this draw_vbo call. */
781 if (sctx->gs_shader.cso)
782 sctx->current_rast_prim = sctx->gs_shader.cso->gs_output_prim;
783 else if (sctx->tes_shader.cso)
784 sctx->current_rast_prim =
785 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
786 else
787 sctx->current_rast_prim = info->mode;
788
789 if (!si_update_shaders(sctx) ||
790 !si_upload_shader_descriptors(sctx))
791 return;
792
793 if (info->indexed) {
794 /* Initialize the index buffer struct. */
795 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
796 ib.user_buffer = sctx->index_buffer.user_buffer;
797 ib.index_size = sctx->index_buffer.index_size;
798 ib.offset = sctx->index_buffer.offset;
799
800 /* Translate or upload, if needed. */
801 /* 8-bit indices are supported on VI. */
802 if (sctx->b.chip_class <= CIK && ib.index_size == 1) {
803 struct pipe_resource *out_buffer = NULL;
804 unsigned out_offset, start, count, start_offset;
805 void *ptr;
806
807 si_get_draw_start_count(sctx, info, &start, &count);
808 start_offset = start * ib.index_size;
809
810 u_upload_alloc(sctx->b.uploader, start_offset, count * 2,
811 &out_offset, &out_buffer, &ptr);
812 if (!out_buffer) {
813 pipe_resource_reference(&ib.buffer, NULL);
814 return;
815 }
816
817 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
818 ib.offset + start_offset,
819 count, ptr);
820
821 pipe_resource_reference(&ib.buffer, NULL);
822 ib.user_buffer = NULL;
823 ib.buffer = out_buffer;
824 /* info->start will be added by the drawing code */
825 ib.offset = out_offset - start_offset;
826 ib.index_size = 2;
827 } else if (ib.user_buffer && !ib.buffer) {
828 unsigned start, count, start_offset;
829
830 si_get_draw_start_count(sctx, info, &start, &count);
831 start_offset = start * ib.index_size;
832
833 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
834 (char*)ib.user_buffer + start_offset,
835 &ib.offset, &ib.buffer);
836 if (!ib.buffer)
837 return;
838 /* info->start will be added by the drawing code */
839 ib.offset -= start_offset;
840 }
841 }
842
843 /* VI reads index buffers through TC L2. */
844 if (info->indexed && sctx->b.chip_class <= CIK &&
845 r600_resource(ib.buffer)->TC_L2_dirty) {
846 sctx->b.flags |= SI_CONTEXT_INV_TC_L2;
847 r600_resource(ib.buffer)->TC_L2_dirty = false;
848 }
849
850 /* Check flush flags. */
851 if (sctx->b.flags)
852 si_mark_atom_dirty(sctx, sctx->atoms.s.cache_flush);
853
854 si_need_cs_space(sctx);
855
856 /* Emit states. */
857 mask = sctx->dirty_atoms;
858 while (mask) {
859 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
860
861 atom->emit(&sctx->b, atom);
862 }
863 sctx->dirty_atoms = 0;
864
865 si_pm4_emit_dirty(sctx);
866 si_emit_scratch_reloc(sctx);
867 si_emit_rasterizer_prim_state(sctx);
868 si_emit_draw_registers(sctx, info);
869 si_emit_draw_packets(sctx, info, &ib);
870
871 if (sctx->trace_buf)
872 si_trace_emit(sctx);
873
874 /* Workaround for a VGT hang when streamout is enabled.
875 * It must be done after drawing. */
876 if ((sctx->b.family == CHIP_HAWAII || sctx->b.family == CHIP_TONGA) &&
877 (sctx->b.streamout.streamout_enabled ||
878 sctx->b.streamout.prims_gen_query_enabled)) {
879 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
880 }
881
882 /* Set the depth buffer as dirty. */
883 if (sctx->framebuffer.state.zsbuf) {
884 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
885 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
886
887 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
888
889 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
890 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
891 }
892 if (sctx->framebuffer.compressed_cb_mask) {
893 struct pipe_surface *surf;
894 struct r600_texture *rtex;
895 unsigned mask = sctx->framebuffer.compressed_cb_mask;
896
897 do {
898 unsigned i = u_bit_scan(&mask);
899 surf = sctx->framebuffer.state.cbufs[i];
900 rtex = (struct r600_texture*)surf->texture;
901
902 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
903 } while (mask);
904 }
905
906 pipe_resource_reference(&ib.buffer, NULL);
907 sctx->b.num_draw_calls++;
908 }
909
910 void si_trace_emit(struct si_context *sctx)
911 {
912 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
913
914 sctx->trace_id++;
915 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx, sctx->trace_buf,
916 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
917 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
918 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
919 S_370_WR_CONFIRM(1) |
920 S_370_ENGINE_SEL(V_370_ME));
921 radeon_emit(cs, sctx->trace_buf->gpu_address);
922 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
923 radeon_emit(cs, sctx->trace_id);
924 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
925 radeon_emit(cs, SI_ENCODE_TRACE_POINT(sctx->trace_id));
926 }