radeonsi: extract derived tess state emit to higher level
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "radeon/r600_cs.h"
29 #include "sid.h"
30 #include "gfx9d.h"
31
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
35
36 #include "ac_debug.h"
37
38 static unsigned si_conv_pipe_prim(unsigned mode)
39 {
40 static const unsigned prim_conv[] = {
41 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
42 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
43 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
44 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
45 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
46 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
47 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
48 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
49 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
50 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
51 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
55 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
56 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
57 };
58 assert(mode < ARRAY_SIZE(prim_conv));
59 return prim_conv[mode];
60 }
61
62 static unsigned si_conv_prim_to_gs_out(unsigned mode)
63 {
64 static const int prim_conv[] = {
65 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
66 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
67 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
68 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
69 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
73 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
74 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
75 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
76 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
77 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
78 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
79 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
80 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
81 };
82 assert(mode < ARRAY_SIZE(prim_conv));
83
84 return prim_conv[mode];
85 }
86
87 /**
88 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
89 * LS.LDS_SIZE is shared by all 3 shader stages.
90 *
91 * The information about LDS and other non-compile-time parameters is then
92 * written to userdata SGPRs.
93 */
94 static void si_emit_derived_tess_state(struct si_context *sctx,
95 const struct pipe_draw_info *info,
96 unsigned *num_patches)
97 {
98 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
99 struct si_shader_ctx_state *ls = &sctx->vs_shader;
100 /* The TES pointer will only be used for sctx->last_tcs.
101 * It would be wrong to think that TCS = TES. */
102 struct si_shader_selector *tcs =
103 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
104 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
105 unsigned num_tcs_input_cp = info->vertices_per_patch;
106 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
107 unsigned num_tcs_patch_outputs;
108 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
109 unsigned input_patch_size, output_patch_size, output_patch0_offset;
110 unsigned perpatch_output_offset, lds_size, ls_rsrc2;
111 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
112 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
113
114 if (sctx->last_ls == ls->current &&
115 sctx->last_tcs == tcs &&
116 sctx->last_tes_sh_base == tes_sh_base &&
117 sctx->last_num_tcs_input_cp == num_tcs_input_cp) {
118 *num_patches = sctx->last_num_patches;
119 return;
120 }
121
122 sctx->last_ls = ls->current;
123 sctx->last_tcs = tcs;
124 sctx->last_tes_sh_base = tes_sh_base;
125 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
126
127 /* This calculates how shader inputs and outputs among VS, TCS, and TES
128 * are laid out in LDS. */
129 num_tcs_inputs = util_last_bit64(ls->cso->outputs_written);
130
131 if (sctx->tcs_shader.cso) {
132 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
133 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
134 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
135 } else {
136 /* No TCS. Route varyings from LS to TES. */
137 num_tcs_outputs = num_tcs_inputs;
138 num_tcs_output_cp = num_tcs_input_cp;
139 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
140 }
141
142 input_vertex_size = num_tcs_inputs * 16;
143 output_vertex_size = num_tcs_outputs * 16;
144
145 input_patch_size = num_tcs_input_cp * input_vertex_size;
146
147 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
148 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
149
150 /* Ensure that we only need one wave per SIMD so we don't need to check
151 * resource usage. Also ensures that the number of tcs in and out
152 * vertices per threadgroup are at most 256.
153 */
154 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
155
156 /* Make sure that the data fits in LDS. This assumes the shaders only
157 * use LDS for the inputs and outputs.
158 */
159 hardware_lds_size = sctx->b.chip_class >= CIK ? 65536 : 32768;
160 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
161 output_patch_size));
162
163 /* Make sure the output data fits in the offchip buffer */
164 *num_patches = MIN2(*num_patches,
165 (sctx->screen->tess_offchip_block_dw_size * 4) /
166 output_patch_size);
167
168 /* Not necessary for correctness, but improves performance. The
169 * specific value is taken from the proprietary driver.
170 */
171 *num_patches = MIN2(*num_patches, 40);
172
173 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
174 if (sctx->b.chip_class == SI) {
175 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
176 *num_patches = MIN2(*num_patches, one_wave);
177 }
178
179 sctx->last_num_patches = *num_patches;
180
181 output_patch0_offset = input_patch_size * *num_patches;
182 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
183
184 lds_size = output_patch0_offset + output_patch_size * *num_patches;
185 ls_rsrc2 = ls->current->config.rsrc2;
186
187 if (sctx->b.chip_class >= CIK) {
188 assert(lds_size <= 65536);
189 lds_size = align(lds_size, 512) / 512;
190 } else {
191 assert(lds_size <= 32768);
192 lds_size = align(lds_size, 256) / 256;
193 }
194 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
195 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
196
197 /* Due to a hw bug, RSRC2_LS must be written twice with another
198 * LS register written in between. */
199 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
200 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
201 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
202 radeon_emit(cs, ls->current->config.rsrc1);
203 radeon_emit(cs, ls_rsrc2);
204
205 /* Compute userdata SGPRs. */
206 assert(((input_vertex_size / 4) & ~0xff) == 0);
207 assert(((output_vertex_size / 4) & ~0xff) == 0);
208 assert(((input_patch_size / 4) & ~0x1fff) == 0);
209 assert(((output_patch_size / 4) & ~0x1fff) == 0);
210 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
211 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
212 assert(num_tcs_input_cp <= 32);
213 assert(num_tcs_output_cp <= 32);
214
215 tcs_in_layout = (input_patch_size / 4) |
216 ((input_vertex_size / 4) << 13);
217 tcs_out_layout = (output_patch_size / 4) |
218 ((output_vertex_size / 4) << 13);
219 tcs_out_offsets = (output_patch0_offset / 16) |
220 ((perpatch_output_offset / 16) << 16);
221 offchip_layout = (pervertex_output_patch_size * *num_patches << 16) |
222 (num_tcs_output_cp << 9) | *num_patches;
223
224 /* Set them for LS. */
225 radeon_set_sh_reg(cs,
226 R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4,
227 tcs_in_layout);
228
229 /* Set them for TCS. */
230 radeon_set_sh_reg_seq(cs,
231 R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
232 radeon_emit(cs, offchip_layout);
233 radeon_emit(cs, tcs_out_offsets);
234 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
235 radeon_emit(cs, tcs_in_layout);
236
237 /* Set them for TES. */
238 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 1);
239 radeon_emit(cs, offchip_layout);
240
241 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
242 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
243 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
244
245 if (sctx->b.chip_class >= CIK)
246 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
247 ls_hs_config);
248 else
249 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
250 ls_hs_config);
251 }
252
253 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
254 {
255 switch (info->mode) {
256 case PIPE_PRIM_PATCHES:
257 return info->count / info->vertices_per_patch;
258 case R600_PRIM_RECTANGLE_LIST:
259 return info->count / 3;
260 default:
261 return u_prims_for_vertices(info->mode, info->count);
262 }
263 }
264
265 static unsigned
266 si_get_init_multi_vgt_param(struct si_screen *sscreen,
267 union si_vgt_param_key *key)
268 {
269 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
270 unsigned max_primgroup_in_wave = 2;
271
272 /* SWITCH_ON_EOP(0) is always preferable. */
273 bool wd_switch_on_eop = false;
274 bool ia_switch_on_eop = false;
275 bool ia_switch_on_eoi = false;
276 bool partial_vs_wave = false;
277 bool partial_es_wave = false;
278
279 if (key->u.uses_tess) {
280 /* SWITCH_ON_EOI must be set if PrimID is used. */
281 if (key->u.tcs_tes_uses_prim_id)
282 ia_switch_on_eoi = true;
283
284 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
285 if ((sscreen->b.family == CHIP_TAHITI ||
286 sscreen->b.family == CHIP_PITCAIRN ||
287 sscreen->b.family == CHIP_BONAIRE) &&
288 key->u.uses_gs)
289 partial_vs_wave = true;
290
291 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
292 if (sscreen->has_distributed_tess) {
293 if (key->u.uses_gs) {
294 partial_es_wave = true;
295
296 /* GPU hang workaround. */
297 if (sscreen->b.family == CHIP_TONGA ||
298 sscreen->b.family == CHIP_FIJI ||
299 sscreen->b.family == CHIP_POLARIS10 ||
300 sscreen->b.family == CHIP_POLARIS11)
301 partial_vs_wave = true;
302 } else {
303 partial_vs_wave = true;
304 }
305 }
306 }
307
308 /* This is a hardware requirement. */
309 if (key->u.line_stipple_enabled ||
310 (sscreen->b.debug_flags & DBG_SWITCH_ON_EOP)) {
311 ia_switch_on_eop = true;
312 wd_switch_on_eop = true;
313 }
314
315 if (sscreen->b.chip_class >= CIK) {
316 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
317 * 4 shader engines. Set 1 to pass the assertion below.
318 * The other cases are hardware requirements.
319 *
320 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
321 * for points, line strips, and tri strips.
322 */
323 if (sscreen->b.info.max_se < 4 ||
324 key->u.prim == PIPE_PRIM_POLYGON ||
325 key->u.prim == PIPE_PRIM_LINE_LOOP ||
326 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
327 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
328 (key->u.primitive_restart &&
329 (sscreen->b.family < CHIP_POLARIS10 ||
330 (key->u.prim != PIPE_PRIM_POINTS &&
331 key->u.prim != PIPE_PRIM_LINE_STRIP &&
332 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
333 key->u.count_from_stream_output)
334 wd_switch_on_eop = true;
335
336 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
337 * We don't know that for indirect drawing, so treat it as
338 * always problematic. */
339 if (sscreen->b.family == CHIP_HAWAII &&
340 key->u.uses_instancing)
341 wd_switch_on_eop = true;
342
343 /* Performance recommendation for 4 SE Gfx7-8 parts if
344 * instances are smaller than a primgroup.
345 * Assume indirect draws always use small instances.
346 * This is needed for good VS wave utilization.
347 */
348 if (sscreen->b.chip_class <= VI &&
349 sscreen->b.info.max_se == 4 &&
350 key->u.multi_instances_smaller_than_primgroup)
351 wd_switch_on_eop = true;
352
353 /* Required on CIK and later. */
354 if (sscreen->b.info.max_se > 2 && !wd_switch_on_eop)
355 ia_switch_on_eoi = true;
356
357 /* Required by Hawaii and, for some special cases, by VI. */
358 if (ia_switch_on_eoi &&
359 (sscreen->b.family == CHIP_HAWAII ||
360 (sscreen->b.chip_class == VI &&
361 (key->u.uses_gs || max_primgroup_in_wave != 2))))
362 partial_vs_wave = true;
363
364 /* Instancing bug on Bonaire. */
365 if (sscreen->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
366 key->u.uses_instancing)
367 partial_vs_wave = true;
368
369 /* If the WD switch is false, the IA switch must be false too. */
370 assert(wd_switch_on_eop || !ia_switch_on_eop);
371 }
372
373 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
374 if (ia_switch_on_eoi)
375 partial_es_wave = true;
376
377 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
378 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
379 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
380 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
381 S_028AA8_WD_SWITCH_ON_EOP(sscreen->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
382 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->b.chip_class >= VI ?
383 max_primgroup_in_wave : 0) |
384 S_030960_EN_INST_OPT_BASIC(sscreen->b.chip_class >= GFX9) |
385 S_030960_EN_INST_OPT_ADV(sscreen->b.chip_class >= GFX9);
386 }
387
388 void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
389 {
390 for (int prim = 0; prim <= R600_PRIM_RECTANGLE_LIST; prim++)
391 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
392 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
393 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
394 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
395 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
396 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
397 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
398 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
399 union si_vgt_param_key key;
400
401 key.index = 0;
402 key.u.prim = prim;
403 key.u.uses_instancing = uses_instancing;
404 key.u.multi_instances_smaller_than_primgroup = multi_instances;
405 key.u.primitive_restart = primitive_restart;
406 key.u.count_from_stream_output = count_from_so;
407 key.u.line_stipple_enabled = line_stipple;
408 key.u.uses_tess = uses_tess;
409 key.u.tcs_tes_uses_prim_id = tess_uses_primid;
410 key.u.uses_gs = uses_gs;
411
412 sctx->ia_multi_vgt_param[key.index] =
413 si_get_init_multi_vgt_param(sctx->screen, &key);
414 }
415 }
416
417 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
418 const struct pipe_draw_info *info,
419 unsigned num_patches)
420 {
421 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
422 unsigned primgroup_size;
423 unsigned ia_multi_vgt_param;
424
425 if (sctx->tes_shader.cso) {
426 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
427 } else if (sctx->gs_shader.cso) {
428 primgroup_size = 64; /* recommended with a GS */
429 } else {
430 primgroup_size = 128; /* recommended without a GS and tess */
431 }
432
433 key.u.prim = info->mode;
434 key.u.uses_instancing = info->indirect || info->instance_count > 1;
435 key.u.multi_instances_smaller_than_primgroup =
436 info->indirect ||
437 (info->instance_count > 1 &&
438 (info->count_from_stream_output ||
439 si_num_prims_for_vertices(info) < primgroup_size));
440 key.u.primitive_restart = info->primitive_restart;
441 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
442
443 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
444 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
445
446 if (sctx->gs_shader.cso) {
447 /* GS requirement. */
448 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
449 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
450
451 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
452 * The hw doc says all multi-SE chips are affected, but Vulkan
453 * only applies it to Hawaii. Do what Vulkan does.
454 */
455 if (sctx->b.family == CHIP_HAWAII &&
456 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
457 (info->indirect ||
458 (info->instance_count > 1 &&
459 (info->count_from_stream_output ||
460 si_num_prims_for_vertices(info) <= 1))))
461 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
462 }
463
464 return ia_multi_vgt_param;
465 }
466
467 /* rast_prim is the primitive type after GS. */
468 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
469 {
470 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
471 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
472 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
473
474 /* Skip this if not rendering lines. */
475 if (rast_prim != PIPE_PRIM_LINES &&
476 rast_prim != PIPE_PRIM_LINE_LOOP &&
477 rast_prim != PIPE_PRIM_LINE_STRIP &&
478 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
479 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
480 return;
481
482 if (rast_prim == sctx->last_rast_prim &&
483 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
484 return;
485
486 /* For lines, reset the stipple pattern at each primitive. Otherwise,
487 * reset the stipple pattern at each packet (line strips, line loops).
488 */
489 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
490 rs->pa_sc_line_stipple |
491 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
492
493 sctx->last_rast_prim = rast_prim;
494 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
495 }
496
497 static void si_emit_draw_registers(struct si_context *sctx,
498 const struct pipe_draw_info *info,
499 unsigned num_patches)
500 {
501 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
502 unsigned prim = si_conv_pipe_prim(info->mode);
503 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
504 unsigned ia_multi_vgt_param;
505
506 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
507
508 /* Draw state. */
509 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
510 if (sctx->b.chip_class >= GFX9)
511 radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
512 else if (sctx->b.chip_class >= CIK)
513 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
514 else
515 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
516
517 sctx->last_multi_vgt_param = ia_multi_vgt_param;
518 }
519 if (prim != sctx->last_prim) {
520 if (sctx->b.chip_class >= CIK)
521 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
522 else
523 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
524
525 sctx->last_prim = prim;
526 }
527
528 if (gs_out_prim != sctx->last_gs_out_prim) {
529 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
530 sctx->last_gs_out_prim = gs_out_prim;
531 }
532
533 /* Primitive restart. */
534 if (info->primitive_restart != sctx->last_primitive_restart_en) {
535 if (sctx->b.chip_class >= GFX9)
536 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
537 info->primitive_restart);
538 else
539 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
540 info->primitive_restart);
541
542 sctx->last_primitive_restart_en = info->primitive_restart;
543
544 }
545 if (info->primitive_restart &&
546 (info->restart_index != sctx->last_restart_index ||
547 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
548 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
549 info->restart_index);
550 sctx->last_restart_index = info->restart_index;
551 }
552 }
553
554 static void si_emit_draw_packets(struct si_context *sctx,
555 const struct pipe_draw_info *info,
556 const struct pipe_index_buffer *ib)
557 {
558 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
559 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
560 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
561 uint32_t index_max_size = 0;
562 uint64_t index_va = 0;
563
564 if (info->count_from_stream_output) {
565 struct r600_so_target *t =
566 (struct r600_so_target*)info->count_from_stream_output;
567 uint64_t va = t->buf_filled_size->gpu_address +
568 t->buf_filled_size_offset;
569
570 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
571 t->stride_in_dw);
572
573 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
574 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
575 COPY_DATA_DST_SEL(COPY_DATA_REG) |
576 COPY_DATA_WR_CONFIRM);
577 radeon_emit(cs, va); /* src address lo */
578 radeon_emit(cs, va >> 32); /* src address hi */
579 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
580 radeon_emit(cs, 0); /* unused */
581
582 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
583 t->buf_filled_size, RADEON_USAGE_READ,
584 RADEON_PRIO_SO_FILLED_SIZE);
585 }
586
587 /* draw packet */
588 if (info->indexed) {
589 if (ib->index_size != sctx->last_index_size) {
590 unsigned index_type;
591
592 /* index type */
593 switch (ib->index_size) {
594 case 1:
595 index_type = V_028A7C_VGT_INDEX_8;
596 break;
597 case 2:
598 index_type = V_028A7C_VGT_INDEX_16 |
599 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
600 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
601 break;
602 case 4:
603 index_type = V_028A7C_VGT_INDEX_32 |
604 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
605 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
606 break;
607 default:
608 assert(!"unreachable");
609 return;
610 }
611
612 if (sctx->b.chip_class >= GFX9) {
613 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
614 2, index_type);
615 } else {
616 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
617 radeon_emit(cs, index_type);
618 }
619
620 sctx->last_index_size = ib->index_size;
621 }
622
623 index_max_size = (ib->buffer->width0 - ib->offset) /
624 ib->index_size;
625 index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
626
627 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
628 (struct r600_resource *)ib->buffer,
629 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
630 } else {
631 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
632 * so the state must be re-emitted before the next indexed draw.
633 */
634 if (sctx->b.chip_class >= CIK)
635 sctx->last_index_size = -1;
636 }
637
638 if (!info->indirect) {
639 int base_vertex;
640
641 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
642 radeon_emit(cs, info->instance_count);
643
644 /* Base vertex and start instance. */
645 base_vertex = info->indexed ? info->index_bias : info->start;
646
647 if (base_vertex != sctx->last_base_vertex ||
648 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
649 info->start_instance != sctx->last_start_instance ||
650 info->drawid != sctx->last_drawid ||
651 sh_base_reg != sctx->last_sh_base_reg) {
652 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
653 radeon_emit(cs, base_vertex);
654 radeon_emit(cs, info->start_instance);
655 radeon_emit(cs, info->drawid);
656
657 sctx->last_base_vertex = base_vertex;
658 sctx->last_start_instance = info->start_instance;
659 sctx->last_drawid = info->drawid;
660 sctx->last_sh_base_reg = sh_base_reg;
661 }
662 } else {
663 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
664
665 assert(indirect_va % 8 == 0);
666
667 si_invalidate_draw_sh_constants(sctx);
668
669 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
670 radeon_emit(cs, 1);
671 radeon_emit(cs, indirect_va);
672 radeon_emit(cs, indirect_va >> 32);
673
674 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
675 (struct r600_resource *)info->indirect,
676 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
677 }
678
679 if (info->indirect) {
680 unsigned di_src_sel = info->indexed ? V_0287F0_DI_SRC_SEL_DMA
681 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
682
683 assert(info->indirect_offset % 4 == 0);
684
685 if (info->indexed) {
686 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
687 radeon_emit(cs, index_va);
688 radeon_emit(cs, index_va >> 32);
689
690 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
691 radeon_emit(cs, index_max_size);
692 }
693
694 if (!sctx->screen->has_draw_indirect_multi) {
695 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT
696 : PKT3_DRAW_INDIRECT,
697 3, render_cond_bit));
698 radeon_emit(cs, info->indirect_offset);
699 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
700 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
701 radeon_emit(cs, di_src_sel);
702 } else {
703 uint64_t count_va = 0;
704
705 if (info->indirect_params) {
706 struct r600_resource *params_buf =
707 (struct r600_resource *)info->indirect_params;
708
709 radeon_add_to_buffer_list(
710 &sctx->b, &sctx->b.gfx, params_buf,
711 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
712
713 count_va = params_buf->gpu_address + info->indirect_params_offset;
714 }
715
716 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
717 PKT3_DRAW_INDIRECT_MULTI,
718 8, render_cond_bit));
719 radeon_emit(cs, info->indirect_offset);
720 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
721 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
722 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
723 S_2C3_DRAW_INDEX_ENABLE(1) |
724 S_2C3_COUNT_INDIRECT_ENABLE(!!info->indirect_params));
725 radeon_emit(cs, info->indirect_count);
726 radeon_emit(cs, count_va);
727 radeon_emit(cs, count_va >> 32);
728 radeon_emit(cs, info->indirect_stride);
729 radeon_emit(cs, di_src_sel);
730 }
731 } else {
732 if (info->indexed) {
733 index_va += info->start * ib->index_size;
734
735 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
736 radeon_emit(cs, index_max_size);
737 radeon_emit(cs, index_va);
738 radeon_emit(cs, index_va >> 32);
739 radeon_emit(cs, info->count);
740 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
741 } else {
742 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
743 radeon_emit(cs, info->count);
744 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
745 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
746 }
747 }
748 }
749
750 static void si_emit_surface_sync(struct r600_common_context *rctx,
751 unsigned cp_coher_cntl)
752 {
753 struct radeon_winsys_cs *cs = rctx->gfx.cs;
754
755 if (rctx->chip_class >= GFX9) {
756 /* Flush caches and wait for the caches to assert idle. */
757 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
758 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
759 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
760 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
761 radeon_emit(cs, 0); /* CP_COHER_BASE */
762 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
763 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
764 } else {
765 /* ACQUIRE_MEM is only required on a compute ring. */
766 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
767 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
768 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
769 radeon_emit(cs, 0); /* CP_COHER_BASE */
770 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
771 }
772 }
773
774 void si_emit_cache_flush(struct si_context *sctx)
775 {
776 struct r600_common_context *rctx = &sctx->b;
777 struct radeon_winsys_cs *cs = rctx->gfx.cs;
778 uint32_t cp_coher_cntl = 0;
779 uint32_t flush_cb_db = rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
780 SI_CONTEXT_FLUSH_AND_INV_DB);
781
782 if (rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
783 SI_CONTEXT_FLUSH_AND_INV_DB))
784 sctx->b.num_fb_cache_flushes++;
785
786 /* SI has a bug that it always flushes ICACHE and KCACHE if either
787 * bit is set. An alternative way is to write SQC_CACHES, but that
788 * doesn't seem to work reliably. Since the bug doesn't affect
789 * correctness (it only does more work than necessary) and
790 * the performance impact is likely negligible, there is no plan
791 * to add a workaround for it.
792 */
793
794 if (rctx->flags & SI_CONTEXT_INV_ICACHE)
795 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
796 if (rctx->flags & SI_CONTEXT_INV_SMEM_L1)
797 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
798
799 if (rctx->chip_class <= VI) {
800 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
801 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
802 S_0085F0_CB0_DEST_BASE_ENA(1) |
803 S_0085F0_CB1_DEST_BASE_ENA(1) |
804 S_0085F0_CB2_DEST_BASE_ENA(1) |
805 S_0085F0_CB3_DEST_BASE_ENA(1) |
806 S_0085F0_CB4_DEST_BASE_ENA(1) |
807 S_0085F0_CB5_DEST_BASE_ENA(1) |
808 S_0085F0_CB6_DEST_BASE_ENA(1) |
809 S_0085F0_CB7_DEST_BASE_ENA(1);
810
811 /* Necessary for DCC */
812 if (rctx->chip_class == VI)
813 r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
814 0, 0, NULL, 0, 0, 0);
815 }
816 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB)
817 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
818 S_0085F0_DB_DEST_BASE_ENA(1);
819 }
820
821 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
822 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
823 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
824 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
825 }
826 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
827 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
828 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
829 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
830 }
831
832 /* Wait for shader engines to go idle.
833 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
834 * for everything including CB/DB cache flushes.
835 */
836 if (!flush_cb_db) {
837 if (rctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
838 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
839 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
840 /* Only count explicit shader flushes, not implicit ones
841 * done by SURFACE_SYNC.
842 */
843 rctx->num_vs_flushes++;
844 rctx->num_ps_flushes++;
845 } else if (rctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
846 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
847 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
848 rctx->num_vs_flushes++;
849 }
850 }
851
852 if (rctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
853 sctx->compute_is_busy) {
854 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
855 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
856 rctx->num_cs_flushes++;
857 sctx->compute_is_busy = false;
858 }
859
860 /* VGT state synchronization. */
861 if (rctx->flags & SI_CONTEXT_VGT_FLUSH) {
862 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
863 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
864 }
865 if (rctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
866 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
867 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
868 }
869
870 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
871 * wait for idle on GFX9. We have to use a TS event.
872 */
873 if (sctx->b.chip_class >= GFX9 && flush_cb_db) {
874 struct r600_resource *rbuf = NULL;
875 uint64_t va;
876 unsigned offset = 0, tc_flags, cb_db_event;
877
878 /* Set the CB/DB flush event. */
879 switch (flush_cb_db) {
880 case SI_CONTEXT_FLUSH_AND_INV_CB:
881 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
882 break;
883 case SI_CONTEXT_FLUSH_AND_INV_DB:
884 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
885 break;
886 default:
887 /* both CB & DB */
888 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
889 }
890
891 /* TC | TC_WB = invalidate L2 data
892 * TC_MD | TC_WB = invalidate L2 metadata
893 * TC | TC_WB | TC_MD = invalidate L2 data & metadata
894 *
895 * The metadata cache must always be invalidated for coherency
896 * between CB/DB and shaders. (metadata = HTILE, CMASK, DCC)
897 *
898 * TC must be invalidated on GFX9 only if the CB/DB surface is
899 * not pipe-aligned. If the surface is RB-aligned, it might not
900 * strictly be pipe-aligned since RB alignment takes precendence.
901 */
902 tc_flags = EVENT_TC_WB_ACTION_ENA |
903 EVENT_TC_MD_ACTION_ENA;
904
905 /* Ideally flush TC together with CB/DB. */
906 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
907 tc_flags |= EVENT_TC_ACTION_ENA |
908 EVENT_TCL1_ACTION_ENA;
909
910 /* Clear the flags. */
911 rctx->flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
912 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
913 SI_CONTEXT_INV_VMEM_L1);
914 }
915
916 /* Allocate memory for the fence. */
917 u_suballocator_alloc(rctx->allocator_zeroed_memory, 4, 4,
918 &offset, (struct pipe_resource**)&rbuf);
919 va = rbuf->gpu_address + offset;
920
921 r600_gfx_write_event_eop(rctx, cb_db_event, tc_flags, 1,
922 rbuf, va, 0, 1);
923 r600_gfx_wait_fence(rctx, va, 1, 0xffffffff);
924 }
925
926 /* Make sure ME is idle (it executes most packets) before continuing.
927 * This prevents read-after-write hazards between PFP and ME.
928 */
929 if (cp_coher_cntl ||
930 (rctx->flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
931 SI_CONTEXT_INV_VMEM_L1 |
932 SI_CONTEXT_INV_GLOBAL_L2 |
933 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
934 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
935 radeon_emit(cs, 0);
936 }
937
938 /* SI-CI-VI only:
939 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
940 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
941 *
942 * cp_coher_cntl should contain all necessary flags except TC flags
943 * at this point.
944 *
945 * SI-CIK don't support L2 write-back.
946 */
947 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2 ||
948 (rctx->chip_class <= CIK &&
949 (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
950 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
951 * WB must be set on VI+ when TC_ACTION is set.
952 */
953 si_emit_surface_sync(rctx, cp_coher_cntl |
954 S_0085F0_TC_ACTION_ENA(1) |
955 S_0085F0_TCL1_ACTION_ENA(1) |
956 S_0301F0_TC_WB_ACTION_ENA(rctx->chip_class >= VI));
957 cp_coher_cntl = 0;
958 sctx->b.num_L2_invalidates++;
959 } else {
960 /* L1 invalidation and L2 writeback must be done separately,
961 * because both operations can't be done together.
962 */
963 if (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
964 /* WB = write-back
965 * NC = apply to non-coherent MTYPEs
966 * (i.e. MTYPE <= 1, which is what we use everywhere)
967 *
968 * WB doesn't work without NC.
969 */
970 si_emit_surface_sync(rctx, cp_coher_cntl |
971 S_0301F0_TC_WB_ACTION_ENA(1) |
972 S_0301F0_TC_NC_ACTION_ENA(1));
973 cp_coher_cntl = 0;
974 sctx->b.num_L2_writebacks++;
975 }
976 if (rctx->flags & SI_CONTEXT_INV_VMEM_L1) {
977 /* Invalidate per-CU VMEM L1. */
978 si_emit_surface_sync(rctx, cp_coher_cntl |
979 S_0085F0_TCL1_ACTION_ENA(1));
980 cp_coher_cntl = 0;
981 }
982 }
983
984 /* If TC flushes haven't cleared this... */
985 if (cp_coher_cntl)
986 si_emit_surface_sync(rctx, cp_coher_cntl);
987
988 if (rctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
989 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
990 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
991 EVENT_INDEX(0));
992 } else if (rctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
993 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
994 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
995 EVENT_INDEX(0));
996 }
997
998 rctx->flags = 0;
999 }
1000
1001 static void si_get_draw_start_count(struct si_context *sctx,
1002 const struct pipe_draw_info *info,
1003 unsigned *start, unsigned *count)
1004 {
1005 if (info->indirect) {
1006 unsigned indirect_count;
1007 struct pipe_transfer *transfer;
1008 unsigned begin, end;
1009 unsigned map_size;
1010 unsigned *data;
1011
1012 if (info->indirect_params) {
1013 data = pipe_buffer_map_range(&sctx->b.b,
1014 info->indirect_params,
1015 info->indirect_params_offset,
1016 sizeof(unsigned),
1017 PIPE_TRANSFER_READ, &transfer);
1018
1019 indirect_count = *data;
1020
1021 pipe_buffer_unmap(&sctx->b.b, transfer);
1022 } else {
1023 indirect_count = info->indirect_count;
1024 }
1025
1026 if (!indirect_count) {
1027 *start = *count = 0;
1028 return;
1029 }
1030
1031 map_size = (indirect_count - 1) * info->indirect_stride + 3 * sizeof(unsigned);
1032 data = pipe_buffer_map_range(&sctx->b.b, info->indirect,
1033 info->indirect_offset, map_size,
1034 PIPE_TRANSFER_READ, &transfer);
1035
1036 begin = UINT_MAX;
1037 end = 0;
1038
1039 for (unsigned i = 0; i < indirect_count; ++i) {
1040 unsigned count = data[0];
1041 unsigned start = data[2];
1042
1043 if (count > 0) {
1044 begin = MIN2(begin, start);
1045 end = MAX2(end, start + count);
1046 }
1047
1048 data += info->indirect_stride / sizeof(unsigned);
1049 }
1050
1051 pipe_buffer_unmap(&sctx->b.b, transfer);
1052
1053 if (begin < end) {
1054 *start = begin;
1055 *count = end - begin;
1056 } else {
1057 *start = *count = 0;
1058 }
1059 } else {
1060 *start = info->start;
1061 *count = info->count;
1062 }
1063 }
1064
1065 void si_ce_pre_draw_synchronization(struct si_context *sctx)
1066 {
1067 if (sctx->ce_need_synchronization) {
1068 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
1069 radeon_emit(sctx->ce_ib, 1);
1070
1071 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
1072 radeon_emit(sctx->b.gfx.cs, 1);
1073 }
1074 }
1075
1076 void si_ce_post_draw_synchronization(struct si_context *sctx)
1077 {
1078 if (sctx->ce_need_synchronization) {
1079 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
1080 radeon_emit(sctx->b.gfx.cs, 0);
1081
1082 sctx->ce_need_synchronization = false;
1083 }
1084 }
1085
1086 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1087 {
1088 struct si_context *sctx = (struct si_context *)ctx;
1089 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1090 const struct pipe_index_buffer *ib = &sctx->index_buffer;
1091 struct pipe_index_buffer ib_tmp; /* for index buffer uploads only */
1092 unsigned mask, dirty_tex_counter;
1093 enum pipe_prim_type rast_prim;
1094 unsigned num_patches = 0;
1095
1096 if (likely(!info->indirect)) {
1097 /* SI-CI treat instance_count==0 as instance_count==1. There is
1098 * no workaround for indirect draws, but we can at least skip
1099 * direct draws.
1100 */
1101 if (unlikely(!info->instance_count))
1102 return;
1103
1104 /* Handle count == 0. */
1105 if (unlikely(!info->count &&
1106 (info->indexed || !info->count_from_stream_output)))
1107 return;
1108 }
1109
1110 if (unlikely(!sctx->vs_shader.cso)) {
1111 assert(0);
1112 return;
1113 }
1114 if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
1115 assert(0);
1116 return;
1117 }
1118 if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
1119 assert(0);
1120 return;
1121 }
1122
1123 /* Recompute and re-emit the texture resource states if needed. */
1124 dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_counter);
1125 if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_counter)) {
1126 sctx->b.last_dirty_tex_counter = dirty_tex_counter;
1127 sctx->framebuffer.dirty_cbufs |=
1128 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1129 sctx->framebuffer.dirty_zsbuf = true;
1130 sctx->framebuffer.do_update_surf_dirtiness = true;
1131 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
1132 si_update_all_texture_descriptors(sctx);
1133 }
1134
1135 si_decompress_graphics_textures(sctx);
1136
1137 /* Set the rasterization primitive type.
1138 *
1139 * This must be done after si_decompress_textures, which can call
1140 * draw_vbo recursively, and before si_update_shaders, which uses
1141 * current_rast_prim for this draw_vbo call. */
1142 if (sctx->gs_shader.cso)
1143 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1144 else if (sctx->tes_shader.cso)
1145 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1146 else
1147 rast_prim = info->mode;
1148
1149 if (rast_prim != sctx->current_rast_prim) {
1150 sctx->current_rast_prim = rast_prim;
1151 sctx->do_update_shaders = true;
1152 }
1153
1154 if (sctx->gs_shader.cso) {
1155 /* Determine whether the GS triangle strip adjacency fix should
1156 * be applied. Rotate every other triangle if
1157 * - triangle strips with adjacency are fed to the GS and
1158 * - primitive restart is disabled (the rotation doesn't help
1159 * when the restart occurs after an odd number of triangles).
1160 */
1161 bool gs_tri_strip_adj_fix =
1162 !sctx->tes_shader.cso &&
1163 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1164 !info->primitive_restart;
1165
1166 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1167 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1168 sctx->do_update_shaders = true;
1169 }
1170 }
1171
1172 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1173 return;
1174
1175 if (!si_upload_graphics_shader_descriptors(sctx))
1176 return;
1177
1178 ib_tmp.buffer = NULL;
1179
1180 if (info->indexed) {
1181 /* Translate or upload, if needed. */
1182 /* 8-bit indices are supported on VI. */
1183 if (sctx->b.chip_class <= CIK && ib->index_size == 1) {
1184 unsigned start, count, start_offset, size;
1185 void *ptr;
1186
1187 si_get_draw_start_count(sctx, info, &start, &count);
1188 start_offset = start * 2;
1189 size = count * 2;
1190
1191 u_upload_alloc(ctx->stream_uploader, start_offset,
1192 size,
1193 si_optimal_tcc_alignment(sctx, size),
1194 &ib_tmp.offset, &ib_tmp.buffer, &ptr);
1195 if (!ib_tmp.buffer)
1196 return;
1197
1198 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, ib, 0, 0,
1199 ib->offset + start,
1200 count, ptr);
1201
1202 /* info->start will be added by the drawing code */
1203 ib_tmp.offset -= start_offset;
1204 ib_tmp.index_size = 2;
1205 ib = &ib_tmp;
1206 } else if (ib->user_buffer && !ib->buffer) {
1207 unsigned start, count, start_offset;
1208
1209 si_get_draw_start_count(sctx, info, &start, &count);
1210 start_offset = start * ib->index_size;
1211
1212 u_upload_data(ctx->stream_uploader, start_offset,
1213 count * ib->index_size,
1214 sctx->screen->b.info.tcc_cache_line_size,
1215 (char*)ib->user_buffer + start_offset,
1216 &ib_tmp.offset, &ib_tmp.buffer);
1217 if (!ib_tmp.buffer)
1218 return;
1219
1220 /* info->start will be added by the drawing code */
1221 ib_tmp.offset -= start_offset;
1222 ib_tmp.index_size = ib->index_size;
1223 ib = &ib_tmp;
1224 } else if (sctx->b.chip_class <= CIK &&
1225 r600_resource(ib->buffer)->TC_L2_dirty) {
1226 /* VI reads index buffers through TC L2, so it doesn't
1227 * need this. */
1228 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1229 r600_resource(ib->buffer)->TC_L2_dirty = false;
1230 }
1231 }
1232
1233 if (info->indirect) {
1234 /* Add the buffer size for memory checking in need_cs_space. */
1235 r600_context_add_resource_size(ctx, info->indirect);
1236
1237 if (r600_resource(info->indirect)->TC_L2_dirty) {
1238 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1239 r600_resource(info->indirect)->TC_L2_dirty = false;
1240 }
1241
1242 if (info->indirect_params &&
1243 r600_resource(info->indirect_params)->TC_L2_dirty) {
1244 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1245 r600_resource(info->indirect_params)->TC_L2_dirty = false;
1246 }
1247 }
1248
1249 si_need_cs_space(sctx);
1250
1251 /* Since we've called r600_context_add_resource_size for vertex buffers,
1252 * this must be called after si_need_cs_space, because we must let
1253 * need_cs_space flush before we add buffers to the buffer list.
1254 */
1255 if (!si_upload_vertex_buffer_descriptors(sctx))
1256 return;
1257
1258 /* GFX9 scissor bug workaround. There is also a more efficient but
1259 * more involved alternative workaround. */
1260 if (sctx->b.chip_class == GFX9 &&
1261 si_is_atom_dirty(sctx, &sctx->b.scissors.atom))
1262 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
1263
1264 /* Flush caches before the first state atom, which does L2 prefetches. */
1265 if (sctx->b.flags)
1266 si_emit_cache_flush(sctx);
1267
1268 /* Emit state atoms. */
1269 mask = sctx->dirty_atoms;
1270 while (mask) {
1271 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
1272
1273 atom->emit(&sctx->b, atom);
1274 }
1275 sctx->dirty_atoms = 0;
1276
1277 /* Emit states. */
1278 mask = sctx->dirty_states;
1279 while (mask) {
1280 unsigned i = u_bit_scan(&mask);
1281 struct si_pm4_state *state = sctx->queued.array[i];
1282
1283 if (!state || sctx->emitted.array[i] == state)
1284 continue;
1285
1286 si_pm4_emit(sctx, state);
1287 sctx->emitted.array[i] = state;
1288 }
1289 sctx->dirty_states = 0;
1290
1291 si_emit_rasterizer_prim_state(sctx);
1292 if (sctx->tes_shader.cso)
1293 si_emit_derived_tess_state(sctx, info, &num_patches);
1294 si_emit_draw_registers(sctx, info, num_patches);
1295
1296 si_ce_pre_draw_synchronization(sctx);
1297 si_emit_draw_packets(sctx, info, ib);
1298 si_ce_post_draw_synchronization(sctx);
1299
1300 if (sctx->trace_buf)
1301 si_trace_emit(sctx);
1302
1303 /* Workaround for a VGT hang when streamout is enabled.
1304 * It must be done after drawing. */
1305 if ((sctx->b.family == CHIP_HAWAII ||
1306 sctx->b.family == CHIP_TONGA ||
1307 sctx->b.family == CHIP_FIJI) &&
1308 r600_get_strmout_en(&sctx->b)) {
1309 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1310 }
1311
1312 if (sctx->framebuffer.do_update_surf_dirtiness) {
1313 /* Set the depth buffer as dirty. */
1314 if (sctx->framebuffer.state.zsbuf) {
1315 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1316 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1317
1318 if (!rtex->tc_compatible_htile)
1319 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1320
1321 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1322 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
1323 }
1324 if (sctx->framebuffer.compressed_cb_mask) {
1325 struct pipe_surface *surf;
1326 struct r600_texture *rtex;
1327 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1328
1329 do {
1330 unsigned i = u_bit_scan(&mask);
1331 surf = sctx->framebuffer.state.cbufs[i];
1332 rtex = (struct r600_texture*)surf->texture;
1333
1334 if (rtex->fmask.size)
1335 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1336 if (rtex->dcc_gather_statistics)
1337 rtex->separate_dcc_dirty = true;
1338 } while (mask);
1339 }
1340 sctx->framebuffer.do_update_surf_dirtiness = false;
1341 }
1342
1343 pipe_resource_reference(&ib_tmp.buffer, NULL);
1344 sctx->b.num_draw_calls++;
1345 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1346 sctx->b.num_spill_draw_calls++;
1347 }
1348
1349 void si_trace_emit(struct si_context *sctx)
1350 {
1351 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1352
1353 sctx->trace_id++;
1354 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
1355 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
1356 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1357 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1358 S_370_WR_CONFIRM(1) |
1359 S_370_ENGINE_SEL(V_370_ME));
1360 radeon_emit(cs, sctx->trace_buf->gpu_address);
1361 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
1362 radeon_emit(cs, sctx->trace_id);
1363 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1364 radeon_emit(cs, AC_ENCODE_TRACE_POINT(sctx->trace_id));
1365 }