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radeonsi: emit additional shader pgm rsrc registers for CIK
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "radeonsi_pipe.h"
32 #include "radeonsi_shader.h"
33 #include "si_state.h"
34 #include "sid.h"
35
36 /*
37 * Shaders
38 */
39
40 static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
41 {
42 struct r600_context *rctx = (struct r600_context *)ctx;
43 struct si_pm4_state *pm4;
44 unsigned num_sgprs, num_user_sgprs;
45 unsigned nparams, i, vgpr_comp_cnt;
46 uint64_t va;
47
48 si_pm4_delete_state(rctx, vs, shader->pm4);
49 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
50
51 si_pm4_inval_shader_cache(pm4);
52
53 /* Certain attributes (position, psize, etc.) don't count as params.
54 * VS is required to export at least one param and r600_shader_from_tgsi()
55 * takes care of adding a dummy export.
56 */
57 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
58 switch (shader->shader.output[i].name) {
59 case TGSI_SEMANTIC_POSITION:
60 case TGSI_SEMANTIC_PSIZE:
61 break;
62 default:
63 nparams++;
64 }
65 }
66 if (nparams < 1)
67 nparams = 1;
68
69 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
70 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
71
72 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
73 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
74 S_02870C_POS1_EXPORT_FORMAT(shader->shader.vs_out_misc_write ?
75 V_02870C_SPI_SHADER_4COMP :
76 V_02870C_SPI_SHADER_NONE) |
77 S_02870C_POS2_EXPORT_FORMAT((shader->shader.clip_dist_write & 0x0F) ?
78 V_02870C_SPI_SHADER_4COMP :
79 V_02870C_SPI_SHADER_NONE) |
80 S_02870C_POS3_EXPORT_FORMAT((shader->shader.clip_dist_write & 0xF0) ?
81 V_02870C_SPI_SHADER_4COMP :
82 V_02870C_SPI_SHADER_NONE));
83
84 va = r600_resource_va(ctx->screen, (void *)shader->bo);
85 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
86 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
87 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
88
89 num_user_sgprs = SI_VS_NUM_USER_SGPR;
90 num_sgprs = shader->num_sgprs;
91 if (num_user_sgprs > num_sgprs)
92 num_sgprs = num_user_sgprs;
93 /* Last 2 reserved SGPRs are used for VCC */
94 num_sgprs += 2;
95 assert(num_sgprs <= 104);
96
97 vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
98
99 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
100 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
101 S_00B128_SGPRS((num_sgprs - 1) / 8) |
102 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
103 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
104 S_00B12C_USER_SGPR(num_user_sgprs));
105
106 if (rctx->chip_class >= CIK) {
107 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
108 S_00B118_CU_EN(0xffff));
109 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
110 S_00B11C_LIMIT(0));
111 }
112
113 si_pm4_bind_state(rctx, vs, shader->pm4);
114 }
115
116 static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
117 {
118 struct r600_context *rctx = (struct r600_context *)ctx;
119 struct si_pm4_state *pm4;
120 unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
121 unsigned num_sgprs, num_user_sgprs;
122 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
123 unsigned fragcoord_interp_mode = 0;
124 unsigned spi_baryc_cntl, spi_ps_input_ena, spi_shader_z_format;
125 uint64_t va;
126
127 si_pm4_delete_state(rctx, ps, shader->pm4);
128 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
129
130 si_pm4_inval_shader_cache(pm4);
131
132 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
133 for (i = 0; i < shader->shader.ninput; i++) {
134 switch (shader->shader.input[i].name) {
135 case TGSI_SEMANTIC_POSITION:
136 if (shader->shader.input[i].centroid) {
137 /* fragcoord_interp_mode will be written to
138 * SPI_BARYC_CNTL.POS_FLOAT_LOCATION
139 * Possible vaules:
140 * 0 -> Position = pixel center (default)
141 * 1 -> Position = pixel centroid
142 * 2 -> Position = iterated sample number XXX:
143 * What does this mean?
144 */
145 fragcoord_interp_mode = 1;
146 }
147 /* Fall through */
148 case TGSI_SEMANTIC_FACE:
149 continue;
150 }
151
152 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
153 have_linear = TRUE;
154 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
155 have_perspective = TRUE;
156 if (shader->shader.input[i].centroid)
157 have_centroid = TRUE;
158 }
159
160 for (i = 0; i < shader->shader.noutput; i++) {
161 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
162 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
163 if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
164 db_shader_control |= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
165 }
166 if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
167 db_shader_control |= S_02880C_KILL_ENABLE(1);
168
169 exports_ps = 0;
170 num_cout = 0;
171 for (i = 0; i < shader->shader.noutput; i++) {
172 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
173 shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
174 exports_ps |= 1;
175 else if (shader->shader.output[i].name == TGSI_SEMANTIC_COLOR) {
176 if (shader->shader.fs_write_all)
177 num_cout = shader->shader.nr_cbufs;
178 else
179 num_cout++;
180 }
181 }
182 if (!exports_ps) {
183 /* always at least export 1 component per pixel */
184 exports_ps = 2;
185 }
186
187 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.ninterp);
188
189 spi_baryc_cntl = 0;
190 if (have_perspective)
191 spi_baryc_cntl |= have_centroid ?
192 S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1);
193 if (have_linear)
194 spi_baryc_cntl |= have_centroid ?
195 S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1);
196 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(fragcoord_interp_mode);
197
198 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
199 spi_ps_input_ena = shader->spi_ps_input_ena;
200 /* we need to enable at least one of them, otherwise we hang the GPU */
201 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
202 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
203 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
204 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
205 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
206 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
207 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
208 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
209
210 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
211 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
212 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
213
214 if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control))
215 spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
216 else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control))
217 spi_shader_z_format = V_028710_SPI_SHADER_32_R;
218 else
219 spi_shader_z_format = 0;
220 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, spi_shader_z_format);
221 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
222 shader->spi_shader_col_format);
223 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
224
225 va = r600_resource_va(ctx->screen, (void *)shader->bo);
226 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
227 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
228 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
229
230 num_user_sgprs = SI_PS_NUM_USER_SGPR;
231 num_sgprs = shader->num_sgprs;
232 if (num_user_sgprs > num_sgprs)
233 num_sgprs = num_user_sgprs;
234 /* Last 2 reserved SGPRs are used for VCC */
235 num_sgprs += 2;
236 assert(num_sgprs <= 104);
237
238 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
239 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
240 S_00B028_SGPRS((num_sgprs - 1) / 8));
241 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
242 S_00B02C_USER_SGPR(num_user_sgprs));
243 if (rctx->chip_class >= CIK) {
244 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
245 S_00B01C_CU_EN(0xffff));
246 }
247
248 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
249
250 shader->sprite_coord_enable = rctx->sprite_coord_enable;
251 si_pm4_bind_state(rctx, ps, shader->pm4);
252 }
253
254 /*
255 * Drawing
256 */
257
258 static unsigned si_conv_pipe_prim(unsigned pprim)
259 {
260 static const unsigned prim_conv[] = {
261 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
262 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
263 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
264 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
265 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
266 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
267 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
268 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
269 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
270 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
271 [PIPE_PRIM_LINES_ADJACENCY] = ~0,
272 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0,
273 [PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0,
274 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0
275 };
276 unsigned result = prim_conv[pprim];
277 if (result == ~0) {
278 R600_ERR("unsupported primitive type %d\n", pprim);
279 }
280 return result;
281 }
282
283 static bool si_update_draw_info_state(struct r600_context *rctx,
284 const struct pipe_draw_info *info)
285 {
286 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
287 struct si_shader *vs = &rctx->vs_shader->current->shader;
288 unsigned prim = si_conv_pipe_prim(info->mode);
289 unsigned ls_mask = 0;
290
291 if (pm4 == NULL)
292 return false;
293
294 if (prim == ~0) {
295 FREE(pm4);
296 return false;
297 }
298
299 if (rctx->chip_class >= CIK)
300 si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim);
301 else
302 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
303 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
304 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
305 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET,
306 info->indexed ? info->index_bias : info->start);
307 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
308 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
309 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_START_INSTANCE * 4,
310 info->start_instance);
311
312 if (prim == V_008958_DI_PT_LINELIST)
313 ls_mask = 1;
314 else if (prim == V_008958_DI_PT_LINESTRIP)
315 ls_mask = 2;
316 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
317 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
318 rctx->pa_sc_line_stipple);
319
320 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
321 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
322 S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
323 } else {
324 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
325 }
326 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
327 S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
328 S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs->clip_dist_write & 0x0F) != 0) |
329 S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs->clip_dist_write & 0xF0) != 0) |
330 S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write) |
331 (rctx->queued.named.rasterizer->clip_plane_enable &
332 vs->clip_dist_write));
333 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL,
334 rctx->queued.named.rasterizer->pa_cl_clip_cntl |
335 (vs->clip_dist_write ? 0 :
336 rctx->queued.named.rasterizer->clip_plane_enable & 0x3F));
337
338 si_pm4_set_state(rctx, draw_info, pm4);
339 return true;
340 }
341
342 static void si_update_spi_map(struct r600_context *rctx)
343 {
344 struct si_shader *ps = &rctx->ps_shader->current->shader;
345 struct si_shader *vs = &rctx->vs_shader->current->shader;
346 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
347 unsigned i, j, tmp;
348
349 for (i = 0; i < ps->ninput; i++) {
350 unsigned name = ps->input[i].name;
351 unsigned param_offset = ps->input[i].param_offset;
352
353 if (name == TGSI_SEMANTIC_POSITION)
354 /* Read from preloaded VGPRs, not parameters */
355 continue;
356
357 bcolor:
358 tmp = 0;
359
360 if (ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
361 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
362 rctx->ps_shader->current->key.ps.flatshade)) {
363 tmp |= S_028644_FLAT_SHADE(1);
364 }
365
366 if (name == TGSI_SEMANTIC_GENERIC &&
367 rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
368 tmp |= S_028644_PT_SPRITE_TEX(1);
369 }
370
371 for (j = 0; j < vs->noutput; j++) {
372 if (name == vs->output[j].name &&
373 ps->input[i].sid == vs->output[j].sid) {
374 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
375 break;
376 }
377 }
378
379 if (j == vs->noutput) {
380 /* No corresponding output found, load defaults into input */
381 tmp |= S_028644_OFFSET(0x20);
382 }
383
384 si_pm4_set_reg(pm4,
385 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
386 tmp);
387
388 if (name == TGSI_SEMANTIC_COLOR &&
389 rctx->ps_shader->current->key.ps.color_two_side) {
390 name = TGSI_SEMANTIC_BCOLOR;
391 param_offset++;
392 goto bcolor;
393 }
394 }
395
396 si_pm4_set_state(rctx, spi, pm4);
397 }
398
399 static void si_update_derived_state(struct r600_context *rctx)
400 {
401 struct pipe_context * ctx = (struct pipe_context*)rctx;
402 unsigned vs_dirty = 0, ps_dirty = 0;
403
404 if (!rctx->blitter->running) {
405 /* Flush depth textures which need to be flushed. */
406 if (rctx->vs_samplers.depth_texture_mask) {
407 si_flush_depth_textures(rctx, &rctx->vs_samplers);
408 }
409 if (rctx->ps_samplers.depth_texture_mask) {
410 si_flush_depth_textures(rctx, &rctx->ps_samplers);
411 }
412 }
413
414 si_shader_select(ctx, rctx->vs_shader, &vs_dirty);
415
416 if (!rctx->vs_shader->current->pm4) {
417 si_pipe_shader_vs(ctx, rctx->vs_shader->current);
418 vs_dirty = 0;
419 }
420
421 if (vs_dirty) {
422 si_pm4_bind_state(rctx, vs, rctx->vs_shader->current->pm4);
423 }
424
425
426 si_shader_select(ctx, rctx->ps_shader, &ps_dirty);
427
428 if (!rctx->ps_shader->current->pm4) {
429 si_pipe_shader_ps(ctx, rctx->ps_shader->current);
430 ps_dirty = 0;
431 }
432 if (!rctx->ps_shader->current->bo) {
433 if (!rctx->dummy_pixel_shader->pm4)
434 si_pipe_shader_ps(ctx, rctx->dummy_pixel_shader);
435 else
436 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
437
438 ps_dirty = 0;
439 }
440
441 if (ps_dirty) {
442 si_pm4_bind_state(rctx, ps, rctx->ps_shader->current->pm4);
443 }
444
445 if (si_pm4_state_changed(rctx, ps) || si_pm4_state_changed(rctx, vs)) {
446 /* XXX: Emitting the PS state even when only the VS changed
447 * fixes random failures with piglit glsl-max-varyings.
448 * Not sure why...
449 */
450 rctx->emitted.named.ps = NULL;
451 si_update_spi_map(rctx);
452 }
453 }
454
455 static void si_constant_buffer_update(struct r600_context *rctx)
456 {
457 struct pipe_context *ctx = &rctx->context;
458 struct si_pm4_state *pm4;
459 unsigned shader, i;
460 uint64_t va;
461
462 if (!rctx->constbuf_state[PIPE_SHADER_VERTEX].dirty_mask &&
463 !rctx->constbuf_state[PIPE_SHADER_FRAGMENT].dirty_mask)
464 return;
465
466 for (shader = PIPE_SHADER_VERTEX ; shader <= PIPE_SHADER_FRAGMENT; shader++) {
467 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
468
469 pm4 = CALLOC_STRUCT(si_pm4_state);
470 if (!pm4)
471 continue;
472
473 si_pm4_inval_shader_cache(pm4);
474 si_pm4_sh_data_begin(pm4);
475
476 for (i = 0; i < 2; i++) {
477 if (state->enabled_mask & (1 << i)) {
478 struct pipe_constant_buffer *cb = &state->cb[i];
479 struct si_resource *rbuffer = si_resource(cb->buffer);
480
481 va = r600_resource_va(ctx->screen, (void*)rbuffer);
482 va += cb->buffer_offset;
483
484 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
485
486 /* Fill in a T# buffer resource description */
487 si_pm4_sh_data_add(pm4, va);
488 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
489 S_008F04_STRIDE(0)));
490 si_pm4_sh_data_add(pm4, cb->buffer_size);
491 si_pm4_sh_data_add(pm4, S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
492 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
493 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
494 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
495 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
496 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32));
497 } else {
498 /* Fill in an empty T# buffer resource description */
499 si_pm4_sh_data_add(pm4, 0);
500 si_pm4_sh_data_add(pm4, 0);
501 si_pm4_sh_data_add(pm4, 0);
502 si_pm4_sh_data_add(pm4, 0);
503 }
504 }
505
506 switch (shader) {
507 case PIPE_SHADER_VERTEX:
508 si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_CONST);
509 si_pm4_set_state(rctx, vs_const, pm4);
510 break;
511
512 case PIPE_SHADER_FRAGMENT:
513 si_pm4_sh_data_end(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, SI_SGPR_CONST);
514 si_pm4_set_state(rctx, ps_const, pm4);
515 break;
516
517 default:
518 R600_ERR("unsupported %d\n", shader);
519 FREE(pm4);
520 return;
521 }
522
523 state->dirty_mask = 0;
524 }
525 }
526
527 static void si_vertex_buffer_update(struct r600_context *rctx)
528 {
529 struct pipe_context *ctx = &rctx->context;
530 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
531 bool bound[PIPE_MAX_ATTRIBS] = {};
532 unsigned i, count;
533 uint64_t va;
534
535 si_pm4_inval_texture_cache(pm4);
536
537 /* bind vertex buffer once */
538 count = rctx->vertex_elements->count;
539 assert(count <= 256 / 4);
540
541 si_pm4_sh_data_begin(pm4);
542 for (i = 0 ; i < count; i++) {
543 struct pipe_vertex_element *ve = &rctx->vertex_elements->elements[i];
544 struct pipe_vertex_buffer *vb;
545 struct si_resource *rbuffer;
546 unsigned offset;
547
548 if (ve->vertex_buffer_index >= rctx->nr_vertex_buffers)
549 continue;
550
551 vb = &rctx->vertex_buffer[ve->vertex_buffer_index];
552 rbuffer = (struct si_resource*)vb->buffer;
553 if (rbuffer == NULL)
554 continue;
555
556 offset = 0;
557 offset += vb->buffer_offset;
558 offset += ve->src_offset;
559
560 va = r600_resource_va(ctx->screen, (void*)rbuffer);
561 va += offset;
562
563 /* Fill in T# buffer resource description */
564 si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF);
565 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
566 S_008F04_STRIDE(vb->stride)));
567 if (vb->stride)
568 /* Round up by rounding down and adding 1 */
569 si_pm4_sh_data_add(pm4,
570 (vb->buffer->width0 - offset -
571 util_format_get_blocksize(ve->src_format)) /
572 vb->stride + 1);
573 else
574 si_pm4_sh_data_add(pm4, vb->buffer->width0 - offset);
575 si_pm4_sh_data_add(pm4, rctx->vertex_elements->rsrc_word3[i]);
576
577 if (!bound[ve->vertex_buffer_index]) {
578 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
579 bound[ve->vertex_buffer_index] = true;
580 }
581 }
582 si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_VERTEX_BUFFER);
583 si_pm4_set_state(rctx, vertex_buffers, pm4);
584 }
585
586 static void si_state_draw(struct r600_context *rctx,
587 const struct pipe_draw_info *info,
588 const struct pipe_index_buffer *ib)
589 {
590 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
591
592 /* queries need some special values
593 * (this is non-zero if any query is active) */
594 if (rctx->num_cs_dw_queries_suspend) {
595 struct si_state_dsa *dsa = rctx->queued.named.dsa;
596
597 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
598 S_028004_PERFECT_ZPASS_COUNTS(1));
599 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
600 dsa->db_render_override |
601 S_02800C_NOOP_CULL_DISABLE(1));
602 }
603
604 /* draw packet */
605 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
606 if (ib->index_size == 4) {
607 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (R600_BIG_ENDIAN ?
608 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
609 } else {
610 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (R600_BIG_ENDIAN ?
611 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
612 }
613 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
614
615 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
616 si_pm4_cmd_add(pm4, info->instance_count);
617 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
618
619 if (info->indexed) {
620 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
621 rctx->index_buffer.index_size;
622 uint64_t va;
623 va = r600_resource_va(&rctx->screen->screen, ib->buffer);
624 va += ib->offset;
625
626 si_pm4_add_bo(pm4, (struct si_resource *)ib->buffer, RADEON_USAGE_READ);
627 si_cmd_draw_index_2(pm4, max_size, va, info->count,
628 V_0287F0_DI_SRC_SEL_DMA,
629 rctx->predicate_drawing);
630 } else {
631 uint32_t initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
632 initiator |= S_0287F0_USE_OPAQUE(!!info->count_from_stream_output);
633 si_cmd_draw_index_auto(pm4, info->count, initiator, rctx->predicate_drawing);
634 }
635 si_pm4_set_state(rctx, draw, pm4);
636 }
637
638 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
639 {
640 struct r600_context *rctx = (struct r600_context *)ctx;
641 struct pipe_index_buffer ib = {};
642 uint32_t cp_coher_cntl;
643
644 if (!info->count && (info->indexed || !info->count_from_stream_output))
645 return;
646
647 if (!rctx->ps_shader || !rctx->vs_shader)
648 return;
649
650 si_update_derived_state(rctx);
651 si_constant_buffer_update(rctx);
652 si_vertex_buffer_update(rctx);
653
654 if (info->indexed) {
655 /* Initialize the index buffer struct. */
656 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
657 ib.user_buffer = rctx->index_buffer.user_buffer;
658 ib.index_size = rctx->index_buffer.index_size;
659 ib.offset = rctx->index_buffer.offset + info->start * ib.index_size;
660
661 /* Translate or upload, if needed. */
662 r600_translate_index_buffer(rctx, &ib, info->count);
663
664 if (ib.user_buffer && !ib.buffer) {
665 r600_upload_index_buffer(rctx, &ib, info->count);
666 }
667
668 } else if (info->count_from_stream_output) {
669 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info->count_from_stream_output);
670 }
671
672 rctx->vs_shader_so_strides = rctx->vs_shader->current->so_strides;
673
674 if (!si_update_draw_info_state(rctx, info))
675 return;
676
677 si_state_draw(rctx, info, &ib);
678
679 cp_coher_cntl = si_pm4_sync_flags(rctx);
680 if (cp_coher_cntl) {
681 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
682 si_cmd_surface_sync(pm4, cp_coher_cntl);
683 si_pm4_set_state(rctx, sync, pm4);
684 }
685
686 /* Emit states. */
687 rctx->pm4_dirty_cdwords += si_pm4_dirty_dw(rctx);
688
689 si_need_cs_space(rctx, 0, TRUE);
690
691 si_pm4_emit_dirty(rctx);
692 rctx->pm4_dirty_cdwords = 0;
693
694 #if R600_TRACE_CS
695 if (rctx->screen->trace_bo) {
696 r600_trace_emit(rctx);
697 }
698 #endif
699
700 #if 0
701 /* Enable stream out if needed. */
702 if (rctx->streamout_start) {
703 r600_context_streamout_begin(rctx);
704 rctx->streamout_start = FALSE;
705 }
706 #endif
707
708 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY;
709
710 /* Set the depth buffer as dirty. */
711 if (rctx->framebuffer.zsbuf) {
712 struct pipe_surface *surf = rctx->framebuffer.zsbuf;
713 struct r600_resource_texture *rtex = (struct r600_resource_texture *)surf->texture;
714
715 rtex->dirty_db_mask |= 1 << surf->u.tex.level;
716 }
717
718 pipe_resource_reference(&ib.buffer, NULL);
719 }