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radeonsi: implement glDrawTransformFeedback functionality
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "radeonsi_pipe.h"
32 #include "radeonsi_shader.h"
33 #include "si_state.h"
34 #include "../radeon/r600_cs.h"
35 #include "sid.h"
36
37 /*
38 * Shaders
39 */
40
41 static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
42 {
43 struct r600_context *rctx = (struct r600_context *)ctx;
44 struct si_pm4_state *pm4;
45 unsigned num_sgprs, num_user_sgprs;
46 unsigned nparams, i, vgpr_comp_cnt;
47 uint64_t va;
48
49 si_pm4_delete_state(rctx, vs, shader->pm4);
50 pm4 = shader->pm4 = si_pm4_alloc_state(rctx);
51
52 if (pm4 == NULL)
53 return;
54
55 /* Certain attributes (position, psize, etc.) don't count as params.
56 * VS is required to export at least one param and r600_shader_from_tgsi()
57 * takes care of adding a dummy export.
58 */
59 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
60 switch (shader->shader.output[i].name) {
61 case TGSI_SEMANTIC_CLIPVERTEX:
62 case TGSI_SEMANTIC_POSITION:
63 case TGSI_SEMANTIC_PSIZE:
64 break;
65 default:
66 nparams++;
67 }
68 }
69 if (nparams < 1)
70 nparams = 1;
71
72 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
73 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
74
75 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
76 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
77 S_02870C_POS1_EXPORT_FORMAT(shader->shader.nr_pos_exports > 1 ?
78 V_02870C_SPI_SHADER_4COMP :
79 V_02870C_SPI_SHADER_NONE) |
80 S_02870C_POS2_EXPORT_FORMAT(shader->shader.nr_pos_exports > 2 ?
81 V_02870C_SPI_SHADER_4COMP :
82 V_02870C_SPI_SHADER_NONE) |
83 S_02870C_POS3_EXPORT_FORMAT(shader->shader.nr_pos_exports > 3 ?
84 V_02870C_SPI_SHADER_4COMP :
85 V_02870C_SPI_SHADER_NONE));
86
87 va = r600_resource_va(ctx->screen, (void *)shader->bo);
88 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
89 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
90 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
91
92 num_user_sgprs = SI_VS_NUM_USER_SGPR;
93 num_sgprs = shader->num_sgprs;
94 if (num_user_sgprs > num_sgprs) {
95 /* Last 2 reserved SGPRs are used for VCC */
96 num_sgprs = num_user_sgprs + 2;
97 }
98 assert(num_sgprs <= 104);
99
100 vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
101
102 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
103 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
104 S_00B128_SGPRS((num_sgprs - 1) / 8) |
105 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
106 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
107 S_00B12C_USER_SGPR(num_user_sgprs));
108
109 if (rctx->b.chip_class >= CIK) {
110 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
111 S_00B118_CU_EN(0xffff));
112 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
113 S_00B11C_LIMIT(0));
114 }
115
116 si_pm4_bind_state(rctx, vs, shader->pm4);
117 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
118 }
119
120 static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
121 {
122 struct r600_context *rctx = (struct r600_context *)ctx;
123 struct si_pm4_state *pm4;
124 unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
125 unsigned num_sgprs, num_user_sgprs;
126 unsigned spi_baryc_cntl = 0, spi_ps_input_ena, spi_shader_z_format;
127 uint64_t va;
128
129 si_pm4_delete_state(rctx, ps, shader->pm4);
130 pm4 = shader->pm4 = si_pm4_alloc_state(rctx);
131
132 if (pm4 == NULL)
133 return;
134
135 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
136 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->fb_cb0_is_integer);
137
138 for (i = 0; i < shader->shader.ninput; i++) {
139 switch (shader->shader.input[i].name) {
140 case TGSI_SEMANTIC_POSITION:
141 if (shader->shader.input[i].centroid) {
142 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
143 * Possible vaules:
144 * 0 -> Position = pixel center (default)
145 * 1 -> Position = pixel centroid
146 * 2 -> Position = iterated sample number XXX:
147 * What does this mean?
148 */
149 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
150 }
151 /* Fall through */
152 case TGSI_SEMANTIC_FACE:
153 continue;
154 }
155 }
156
157 for (i = 0; i < shader->shader.noutput; i++) {
158 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
159 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
160 if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
161 db_shader_control |= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
162 }
163 if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
164 db_shader_control |= S_02880C_KILL_ENABLE(1);
165
166 exports_ps = 0;
167 num_cout = 0;
168 for (i = 0; i < shader->shader.noutput; i++) {
169 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
170 shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
171 exports_ps |= 1;
172 else if (shader->shader.output[i].name == TGSI_SEMANTIC_COLOR) {
173 if (shader->shader.fs_write_all)
174 num_cout = shader->shader.nr_cbufs;
175 else
176 num_cout++;
177 }
178 }
179 if (!exports_ps) {
180 /* always at least export 1 component per pixel */
181 exports_ps = 2;
182 }
183
184 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.ninterp) |
185 S_0286D8_BC_OPTIMIZE_DISABLE(1);
186
187 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
188 spi_ps_input_ena = shader->spi_ps_input_ena;
189 /* we need to enable at least one of them, otherwise we hang the GPU */
190 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
191 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
192 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
193 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
194 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
195 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
196 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
197 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
198
199 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
200 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
201 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
202
203 if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control))
204 spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
205 else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control))
206 spi_shader_z_format = V_028710_SPI_SHADER_32_R;
207 else
208 spi_shader_z_format = 0;
209 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, spi_shader_z_format);
210 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
211 shader->spi_shader_col_format);
212 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
213
214 va = r600_resource_va(ctx->screen, (void *)shader->bo);
215 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
216 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
217 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
218
219 num_user_sgprs = SI_PS_NUM_USER_SGPR;
220 num_sgprs = shader->num_sgprs;
221 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
222 if ((num_user_sgprs + 1) > num_sgprs) {
223 /* Last 2 reserved SGPRs are used for VCC */
224 num_sgprs = num_user_sgprs + 1 + 2;
225 }
226 assert(num_sgprs <= 104);
227
228 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
229 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
230 S_00B028_SGPRS((num_sgprs - 1) / 8));
231 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
232 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
233 S_00B02C_USER_SGPR(num_user_sgprs));
234 if (rctx->b.chip_class >= CIK) {
235 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
236 S_00B01C_CU_EN(0xffff));
237 }
238
239 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
240
241 shader->cb0_is_integer = rctx->fb_cb0_is_integer;
242 shader->sprite_coord_enable = rctx->sprite_coord_enable;
243 si_pm4_bind_state(rctx, ps, shader->pm4);
244 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
245 }
246
247 /*
248 * Drawing
249 */
250
251 static unsigned si_conv_pipe_prim(unsigned pprim)
252 {
253 static const unsigned prim_conv[] = {
254 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
255 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
256 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
257 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
258 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
259 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
260 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
261 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
262 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
263 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
264 [PIPE_PRIM_LINES_ADJACENCY] = ~0,
265 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0,
266 [PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0,
267 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0
268 };
269 unsigned result = prim_conv[pprim];
270 if (result == ~0) {
271 R600_ERR("unsupported primitive type %d\n", pprim);
272 }
273 return result;
274 }
275
276 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
277 {
278 static const int prim_conv[] = {
279 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
280 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
281 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
282 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
283 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
284 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
285 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
286 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
287 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
288 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
289 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
290 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
291 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
292 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
293 };
294 assert(mode < Elements(prim_conv));
295
296 return prim_conv[mode];
297 }
298
299 static bool si_update_draw_info_state(struct r600_context *rctx,
300 const struct pipe_draw_info *info)
301 {
302 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
303 struct si_shader *vs = &rctx->vs_shader->current->shader;
304 unsigned prim = si_conv_pipe_prim(info->mode);
305 unsigned gs_out_prim = r600_conv_prim_to_gs_out(info->mode);
306 unsigned ls_mask = 0;
307
308 if (pm4 == NULL)
309 return false;
310
311 if (prim == ~0) {
312 FREE(pm4);
313 return false;
314 }
315
316 if (rctx->b.chip_class >= CIK)
317 si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim);
318 else {
319 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
320 si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
321 }
322 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
323 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
324 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET,
325 info->indexed ? info->index_bias : info->start);
326 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
327 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
328 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_START_INSTANCE * 4,
329 info->start_instance);
330
331 if (prim == V_008958_DI_PT_LINELIST)
332 ls_mask = 1;
333 else if (prim == V_008958_DI_PT_LINESTRIP)
334 ls_mask = 2;
335 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
336 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
337 rctx->pa_sc_line_stipple);
338
339 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
340 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
341 S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
342 } else {
343 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
344 }
345 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
346 S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
347 S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs->clip_dist_write & 0x0F) != 0) |
348 S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs->clip_dist_write & 0xF0) != 0) |
349 S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write) |
350 (rctx->queued.named.rasterizer->clip_plane_enable &
351 vs->clip_dist_write));
352 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL,
353 rctx->queued.named.rasterizer->pa_cl_clip_cntl |
354 (vs->clip_dist_write ? 0 :
355 rctx->queued.named.rasterizer->clip_plane_enable & 0x3F));
356
357 si_pm4_set_state(rctx, draw_info, pm4);
358 return true;
359 }
360
361 static void si_update_spi_map(struct r600_context *rctx)
362 {
363 struct si_shader *ps = &rctx->ps_shader->current->shader;
364 struct si_shader *vs = &rctx->vs_shader->current->shader;
365 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
366 unsigned i, j, tmp;
367
368 for (i = 0; i < ps->ninput; i++) {
369 unsigned name = ps->input[i].name;
370 unsigned param_offset = ps->input[i].param_offset;
371
372 if (name == TGSI_SEMANTIC_POSITION)
373 /* Read from preloaded VGPRs, not parameters */
374 continue;
375
376 bcolor:
377 tmp = 0;
378
379 if (ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
380 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
381 rctx->ps_shader->current->key.ps.flatshade)) {
382 tmp |= S_028644_FLAT_SHADE(1);
383 }
384
385 if (name == TGSI_SEMANTIC_GENERIC &&
386 rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
387 tmp |= S_028644_PT_SPRITE_TEX(1);
388 }
389
390 for (j = 0; j < vs->noutput; j++) {
391 if (name == vs->output[j].name &&
392 ps->input[i].sid == vs->output[j].sid) {
393 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
394 break;
395 }
396 }
397
398 if (j == vs->noutput) {
399 /* No corresponding output found, load defaults into input */
400 tmp |= S_028644_OFFSET(0x20);
401 }
402
403 si_pm4_set_reg(pm4,
404 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
405 tmp);
406
407 if (name == TGSI_SEMANTIC_COLOR &&
408 rctx->ps_shader->current->key.ps.color_two_side) {
409 name = TGSI_SEMANTIC_BCOLOR;
410 param_offset++;
411 goto bcolor;
412 }
413 }
414
415 si_pm4_set_state(rctx, spi, pm4);
416 }
417
418 static void si_update_derived_state(struct r600_context *rctx)
419 {
420 struct pipe_context * ctx = (struct pipe_context*)rctx;
421 unsigned vs_dirty = 0, ps_dirty = 0;
422
423 if (!rctx->blitter->running) {
424 /* Flush depth textures which need to be flushed. */
425 for (int i = 0; i < SI_NUM_SHADERS; i++) {
426 if (rctx->samplers[i].depth_texture_mask) {
427 si_flush_depth_textures(rctx, &rctx->samplers[i]);
428 }
429 if (rctx->samplers[i].compressed_colortex_mask) {
430 r600_decompress_color_textures(rctx, &rctx->samplers[i]);
431 }
432 }
433 }
434
435 si_shader_select(ctx, rctx->vs_shader, &vs_dirty);
436
437 if (!rctx->vs_shader->current->pm4) {
438 si_pipe_shader_vs(ctx, rctx->vs_shader->current);
439 vs_dirty = 0;
440 }
441
442 if (vs_dirty) {
443 si_pm4_bind_state(rctx, vs, rctx->vs_shader->current->pm4);
444 }
445
446
447 si_shader_select(ctx, rctx->ps_shader, &ps_dirty);
448
449 if (!rctx->ps_shader->current->pm4) {
450 si_pipe_shader_ps(ctx, rctx->ps_shader->current);
451 ps_dirty = 0;
452 }
453 if (!rctx->ps_shader->current->bo) {
454 if (!rctx->dummy_pixel_shader->pm4)
455 si_pipe_shader_ps(ctx, rctx->dummy_pixel_shader);
456 else
457 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
458
459 ps_dirty = 0;
460 }
461 if (rctx->ps_shader->current->cb0_is_integer != rctx->fb_cb0_is_integer) {
462 si_pipe_shader_ps(ctx, rctx->ps_shader->current);
463 ps_dirty = 1;
464 }
465
466 if (ps_dirty) {
467 si_pm4_bind_state(rctx, ps, rctx->ps_shader->current->pm4);
468 }
469
470 if (si_pm4_state_changed(rctx, ps) || si_pm4_state_changed(rctx, vs)) {
471 /* XXX: Emitting the PS state even when only the VS changed
472 * fixes random failures with piglit glsl-max-varyings.
473 * Not sure why...
474 */
475 rctx->emitted.named.ps = NULL;
476 si_update_spi_map(rctx);
477 }
478 }
479
480 static void si_vertex_buffer_update(struct r600_context *rctx)
481 {
482 struct pipe_context *ctx = &rctx->b.b;
483 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
484 bool bound[PIPE_MAX_ATTRIBS] = {};
485 unsigned i, count;
486 uint64_t va;
487
488 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
489
490 count = rctx->vertex_elements->count;
491 assert(count <= 256 / 4);
492
493 si_pm4_sh_data_begin(pm4);
494 for (i = 0 ; i < count; i++) {
495 struct pipe_vertex_element *ve = &rctx->vertex_elements->elements[i];
496 struct pipe_vertex_buffer *vb;
497 struct r600_resource *rbuffer;
498 unsigned offset;
499
500 if (ve->vertex_buffer_index >= rctx->nr_vertex_buffers)
501 continue;
502
503 vb = &rctx->vertex_buffer[ve->vertex_buffer_index];
504 rbuffer = (struct r600_resource*)vb->buffer;
505 if (rbuffer == NULL)
506 continue;
507
508 offset = 0;
509 offset += vb->buffer_offset;
510 offset += ve->src_offset;
511
512 va = r600_resource_va(ctx->screen, (void*)rbuffer);
513 va += offset;
514
515 /* Fill in T# buffer resource description */
516 si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF);
517 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
518 S_008F04_STRIDE(vb->stride)));
519 if (vb->stride)
520 /* Round up by rounding down and adding 1 */
521 si_pm4_sh_data_add(pm4,
522 (vb->buffer->width0 - offset -
523 util_format_get_blocksize(ve->src_format)) /
524 vb->stride + 1);
525 else
526 si_pm4_sh_data_add(pm4, vb->buffer->width0 - offset);
527 si_pm4_sh_data_add(pm4, rctx->vertex_elements->rsrc_word3[i]);
528
529 if (!bound[ve->vertex_buffer_index]) {
530 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
531 bound[ve->vertex_buffer_index] = true;
532 }
533 }
534 si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_VERTEX_BUFFER);
535 si_pm4_set_state(rctx, vertex_buffers, pm4);
536 }
537
538 static void si_state_draw(struct r600_context *rctx,
539 const struct pipe_draw_info *info,
540 const struct pipe_index_buffer *ib)
541 {
542 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
543
544 if (pm4 == NULL)
545 return;
546
547 /* queries need some special values
548 * (this is non-zero if any query is active) */
549 if (rctx->num_cs_dw_nontimer_queries_suspend) {
550 struct si_state_dsa *dsa = rctx->queued.named.dsa;
551
552 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
553 S_028004_PERFECT_ZPASS_COUNTS(1) |
554 S_028004_SAMPLE_RATE(rctx->fb_log_samples));
555 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
556 dsa->db_render_override |
557 S_02800C_NOOP_CULL_DISABLE(1));
558 }
559
560 if (info->count_from_stream_output) {
561 struct r600_so_target *t =
562 (struct r600_so_target*)info->count_from_stream_output;
563 uint64_t va = r600_resource_va(&rctx->screen->b.b,
564 &t->buf_filled_size->b.b);
565 va += t->buf_filled_size_offset;
566
567 si_pm4_set_reg(pm4, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
568 t->stride_in_dw);
569
570 si_pm4_cmd_begin(pm4, PKT3_COPY_DATA);
571 si_pm4_cmd_add(pm4,
572 COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
573 COPY_DATA_DST_SEL(COPY_DATA_REG) |
574 COPY_DATA_WR_CONFIRM);
575 si_pm4_cmd_add(pm4, va); /* src address lo */
576 si_pm4_cmd_add(pm4, va >> 32UL); /* src address hi */
577 si_pm4_cmd_add(pm4, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
578 si_pm4_cmd_add(pm4, 0); /* unused */
579 si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ);
580 si_pm4_cmd_end(pm4, true);
581 }
582
583 /* draw packet */
584 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
585 if (ib->index_size == 4) {
586 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (R600_BIG_ENDIAN ?
587 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
588 } else {
589 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (R600_BIG_ENDIAN ?
590 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
591 }
592 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
593
594 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
595 si_pm4_cmd_add(pm4, info->instance_count);
596 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
597
598 if (info->indexed) {
599 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
600 rctx->index_buffer.index_size;
601 uint64_t va;
602 va = r600_resource_va(&rctx->screen->b.b, ib->buffer);
603 va += ib->offset;
604
605 si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ);
606 si_cmd_draw_index_2(pm4, max_size, va, info->count,
607 V_0287F0_DI_SRC_SEL_DMA,
608 rctx->predicate_drawing);
609 } else {
610 uint32_t initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
611 initiator |= S_0287F0_USE_OPAQUE(!!info->count_from_stream_output);
612 si_cmd_draw_index_auto(pm4, info->count, initiator, rctx->predicate_drawing);
613 }
614 si_pm4_set_state(rctx, draw, pm4);
615 }
616
617 void si_emit_cache_flush(struct r600_common_context *rctx, struct r600_atom *atom)
618 {
619 struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
620 uint32_t cp_coher_cntl = 0;
621
622 /* XXX SI flushes both ICACHE and KCACHE if either flag is set.
623 * XXX CIK shouldn't have this issue. Test CIK before separating the flags
624 * XXX to ensure there is no regression. Also find out if there is another
625 * XXX way to flush either ICACHE or KCACHE but not both for SI. */
626 if (rctx->flags & (R600_CONTEXT_INV_SHADER_CACHE |
627 R600_CONTEXT_INV_CONST_CACHE)) {
628 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1) |
629 S_0085F0_SH_KCACHE_ACTION_ENA(1);
630 }
631 if (rctx->flags & (R600_CONTEXT_INV_TEX_CACHE |
632 R600_CONTEXT_STREAMOUT_FLUSH)) {
633 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1) |
634 S_0085F0_TCL1_ACTION_ENA(1);
635 }
636 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB) {
637 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
638 S_0085F0_CB0_DEST_BASE_ENA(1) |
639 S_0085F0_CB1_DEST_BASE_ENA(1) |
640 S_0085F0_CB2_DEST_BASE_ENA(1) |
641 S_0085F0_CB3_DEST_BASE_ENA(1) |
642 S_0085F0_CB4_DEST_BASE_ENA(1) |
643 S_0085F0_CB5_DEST_BASE_ENA(1) |
644 S_0085F0_CB6_DEST_BASE_ENA(1) |
645 S_0085F0_CB7_DEST_BASE_ENA(1);
646 }
647 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB) {
648 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
649 S_0085F0_DB_DEST_BASE_ENA(1);
650 }
651
652 if (cp_coher_cntl) {
653 if (rctx->chip_class >= CIK) {
654 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
655 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
656 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
657 radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */
658 radeon_emit(cs, 0); /* CP_COHER_BASE */
659 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
660 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
661 } else {
662 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
663 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
664 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
665 radeon_emit(cs, 0); /* CP_COHER_BASE */
666 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
667 }
668 }
669
670 if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META) {
671 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
672 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
673 }
674
675 if (rctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
676 /* Needed if streamout buffers are going to be used as a source. */
677 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
678 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
679 }
680
681 rctx->flags = 0;
682 }
683
684 const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 11 }; /* number of CS dwords */
685
686 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
687 {
688 struct r600_context *rctx = (struct r600_context *)ctx;
689 struct pipe_index_buffer ib = {};
690 uint32_t i;
691
692 if (!info->count && (info->indexed || !info->count_from_stream_output))
693 return;
694
695 if (!rctx->ps_shader || !rctx->vs_shader)
696 return;
697
698 si_update_derived_state(rctx);
699 si_vertex_buffer_update(rctx);
700
701 if (info->indexed) {
702 /* Initialize the index buffer struct. */
703 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
704 ib.user_buffer = rctx->index_buffer.user_buffer;
705 ib.index_size = rctx->index_buffer.index_size;
706 ib.offset = rctx->index_buffer.offset + info->start * ib.index_size;
707
708 /* Translate or upload, if needed. */
709 r600_translate_index_buffer(rctx, &ib, info->count);
710
711 if (ib.user_buffer && !ib.buffer) {
712 r600_upload_index_buffer(rctx, &ib, info->count);
713 }
714 }
715
716 if (!si_update_draw_info_state(rctx, info))
717 return;
718
719 si_state_draw(rctx, info, &ib);
720
721 rctx->pm4_dirty_cdwords += si_pm4_dirty_dw(rctx);
722
723 /* Check flush flags. */
724 if (rctx->b.flags)
725 rctx->atoms.cache_flush->dirty = true;
726
727 si_need_cs_space(rctx, 0, TRUE);
728
729 /* Emit states. */
730 for (i = 0; i < SI_NUM_ATOMS(rctx); i++) {
731 if (rctx->atoms.array[i]->dirty) {
732 rctx->atoms.array[i]->emit(&rctx->b, rctx->atoms.array[i]);
733 rctx->atoms.array[i]->dirty = false;
734 }
735 }
736
737 si_pm4_emit_dirty(rctx);
738 rctx->pm4_dirty_cdwords = 0;
739
740 #if R600_TRACE_CS
741 if (rctx->screen->trace_bo) {
742 r600_trace_emit(rctx);
743 }
744 #endif
745
746 /* Set the depth buffer as dirty. */
747 if (rctx->framebuffer.zsbuf) {
748 struct pipe_surface *surf = rctx->framebuffer.zsbuf;
749 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
750
751 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
752 }
753 if (rctx->fb_compressed_cb_mask) {
754 struct pipe_surface *surf;
755 struct r600_texture *rtex;
756 unsigned mask = rctx->fb_compressed_cb_mask;
757
758 do {
759 unsigned i = u_bit_scan(&mask);
760 surf = rctx->framebuffer.cbufs[i];
761 rtex = (struct r600_texture*)surf->texture;
762
763 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
764 } while (mask);
765 }
766
767 pipe_resource_reference(&ib.buffer, NULL);
768 }