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radeonsi: remove unused variable si_pipe_shader::sprite_coord_enable
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "radeon/r600_cs.h"
30 #include "sid.h"
31
32 #include "util/u_format.h"
33 #include "util/u_index_modify.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36 #include "util/u_upload_mgr.h"
37
38 /*
39 * Shaders
40 */
41
42 static void si_pipe_shader_es(struct pipe_context *ctx, struct si_pipe_shader *shader)
43 {
44 struct si_context *sctx = (struct si_context *)ctx;
45 struct si_pm4_state *pm4;
46 unsigned num_sgprs, num_user_sgprs;
47 unsigned vgpr_comp_cnt;
48 uint64_t va;
49
50 si_pm4_delete_state(sctx, es, shader->pm4);
51 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
52
53 if (pm4 == NULL)
54 return;
55
56 va = shader->bo->gpu_address;
57 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
58
59 vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
60
61 num_user_sgprs = SI_VS_NUM_USER_SGPR;
62 num_sgprs = shader->num_sgprs;
63 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
64 if ((num_user_sgprs + 1) > num_sgprs) {
65 /* Last 2 reserved SGPRs are used for VCC */
66 num_sgprs = num_user_sgprs + 1 + 2;
67 }
68 assert(num_sgprs <= 104);
69
70 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
71 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
72 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
73 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
74 S_00B328_SGPRS((num_sgprs - 1) / 8) |
75 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt));
76 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
77 S_00B32C_USER_SGPR(num_user_sgprs));
78
79 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
80 }
81
82 static void si_pipe_shader_gs(struct pipe_context *ctx, struct si_pipe_shader *shader)
83 {
84 struct si_context *sctx = (struct si_context *)ctx;
85 unsigned gs_vert_itemsize = shader->shader.noutput * (16 >> 2);
86 unsigned gs_max_vert_out = shader->shader.gs_max_out_vertices;
87 unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
88 unsigned cut_mode;
89 struct si_pm4_state *pm4;
90 unsigned num_sgprs, num_user_sgprs;
91 uint64_t va;
92
93 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
94 assert(gsvs_itemsize < (1 << 15));
95
96 si_pm4_delete_state(sctx, gs, shader->pm4);
97 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
98
99 if (pm4 == NULL)
100 return;
101
102 if (gs_max_vert_out <= 128) {
103 cut_mode = V_028A40_GS_CUT_128;
104 } else if (gs_max_vert_out <= 256) {
105 cut_mode = V_028A40_GS_CUT_256;
106 } else if (gs_max_vert_out <= 512) {
107 cut_mode = V_028A40_GS_CUT_512;
108 } else {
109 assert(gs_max_vert_out <= 1024);
110 cut_mode = V_028A40_GS_CUT_1024;
111 }
112
113 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
114 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
115 S_028A40_CUT_MODE(cut_mode)|
116 S_028A40_ES_WRITE_OPTIMIZE(1) |
117 S_028A40_GS_WRITE_OPTIMIZE(1));
118
119 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
120 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize);
121 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize);
122
123 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
124 shader->shader.nparam * (16 >> 2));
125 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
126
127 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
128
129 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
130
131 va = shader->bo->gpu_address;
132 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
133 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
134 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
135
136 num_user_sgprs = SI_GS_NUM_USER_SGPR;
137 num_sgprs = shader->num_sgprs;
138 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
139 if ((num_user_sgprs + 2) > num_sgprs) {
140 /* Last 2 reserved SGPRs are used for VCC */
141 num_sgprs = num_user_sgprs + 2 + 2;
142 }
143 assert(num_sgprs <= 104);
144
145 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
146 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
147 S_00B228_SGPRS((num_sgprs - 1) / 8));
148 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
149 S_00B22C_USER_SGPR(num_user_sgprs));
150
151 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
152 }
153
154 static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
155 {
156 struct si_context *sctx = (struct si_context *)ctx;
157 struct si_pm4_state *pm4;
158 unsigned num_sgprs, num_user_sgprs;
159 unsigned nparams, i, vgpr_comp_cnt;
160 uint64_t va;
161
162 si_pm4_delete_state(sctx, vs, shader->pm4);
163 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
164
165 if (pm4 == NULL)
166 return;
167
168 va = shader->bo->gpu_address;
169 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
170
171 vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
172
173 num_user_sgprs = SI_VS_NUM_USER_SGPR;
174 num_sgprs = shader->num_sgprs;
175 if (num_user_sgprs > num_sgprs) {
176 /* Last 2 reserved SGPRs are used for VCC */
177 num_sgprs = num_user_sgprs + 2;
178 }
179 assert(num_sgprs <= 104);
180
181 /* Certain attributes (position, psize, etc.) don't count as params.
182 * VS is required to export at least one param and r600_shader_from_tgsi()
183 * takes care of adding a dummy export.
184 */
185 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
186 switch (shader->shader.output[i].name) {
187 case TGSI_SEMANTIC_CLIPVERTEX:
188 case TGSI_SEMANTIC_POSITION:
189 case TGSI_SEMANTIC_PSIZE:
190 break;
191 default:
192 nparams++;
193 }
194 }
195 if (nparams < 1)
196 nparams = 1;
197
198 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
199 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
200
201 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
202 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
203 S_02870C_POS1_EXPORT_FORMAT(shader->shader.nr_pos_exports > 1 ?
204 V_02870C_SPI_SHADER_4COMP :
205 V_02870C_SPI_SHADER_NONE) |
206 S_02870C_POS2_EXPORT_FORMAT(shader->shader.nr_pos_exports > 2 ?
207 V_02870C_SPI_SHADER_4COMP :
208 V_02870C_SPI_SHADER_NONE) |
209 S_02870C_POS3_EXPORT_FORMAT(shader->shader.nr_pos_exports > 3 ?
210 V_02870C_SPI_SHADER_4COMP :
211 V_02870C_SPI_SHADER_NONE));
212
213 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
214 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
215 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
216 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
217 S_00B128_SGPRS((num_sgprs - 1) / 8) |
218 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
219 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
220 S_00B12C_USER_SGPR(num_user_sgprs) |
221 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
222 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
223 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
224 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
225 S_00B12C_SO_EN(!!shader->selector->so.num_outputs));
226
227 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
228 }
229
230 static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
231 {
232 struct si_context *sctx = (struct si_context *)ctx;
233 struct si_pm4_state *pm4;
234 unsigned i, spi_ps_in_control, db_shader_control;
235 unsigned num_sgprs, num_user_sgprs;
236 unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
237 uint64_t va;
238
239 si_pm4_delete_state(sctx, ps, shader->pm4);
240 pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
241
242 if (pm4 == NULL)
243 return;
244
245 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
246 S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer);
247
248 for (i = 0; i < shader->shader.ninput; i++) {
249 switch (shader->shader.input[i].name) {
250 case TGSI_SEMANTIC_POSITION:
251 if (shader->shader.input[i].centroid) {
252 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
253 * Possible vaules:
254 * 0 -> Position = pixel center (default)
255 * 1 -> Position = pixel centroid
256 * 2 -> Position = iterated sample number XXX:
257 * What does this mean?
258 */
259 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
260 }
261 /* Fall through */
262 case TGSI_SEMANTIC_FACE:
263 continue;
264 }
265 }
266
267 db_shader_control |= shader->db_shader_control;
268
269 if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
270 db_shader_control |= S_02880C_KILL_ENABLE(1);
271
272 if (sctx->b.chip_class >= CIK)
273 db_shader_control |=
274 S_02880C_CONSERVATIVE_Z_EXPORT(shader->shader.ps_conservative_z);
275
276 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.nparam) |
277 S_0286D8_BC_OPTIMIZE_DISABLE(1);
278
279 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
280 spi_ps_input_ena = shader->spi_ps_input_ena;
281 /* we need to enable at least one of them, otherwise we hang the GPU */
282 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
283 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
284 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
285 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
286 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
287 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
288 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
289 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
290
291 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
292 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
293 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
294
295 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
296 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
297 shader->spi_shader_col_format);
298 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
299
300 va = shader->bo->gpu_address;
301 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
302 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
303 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
304
305 num_user_sgprs = SI_PS_NUM_USER_SGPR;
306 num_sgprs = shader->num_sgprs;
307 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
308 if ((num_user_sgprs + 1) > num_sgprs) {
309 /* Last 2 reserved SGPRs are used for VCC */
310 num_sgprs = num_user_sgprs + 1 + 2;
311 }
312 assert(num_sgprs <= 104);
313
314 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
315 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
316 S_00B028_SGPRS((num_sgprs - 1) / 8));
317 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
318 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
319 S_00B02C_USER_SGPR(num_user_sgprs));
320
321 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
322
323 shader->cb0_is_integer = sctx->framebuffer.cb0_is_integer;
324 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
325 }
326
327 /*
328 * Drawing
329 */
330
331 static unsigned si_conv_pipe_prim(unsigned pprim)
332 {
333 static const unsigned prim_conv[] = {
334 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
335 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
336 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
337 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
338 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
339 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
340 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
341 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
342 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
343 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
344 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
345 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
346 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
347 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
348 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
349 };
350 unsigned result = prim_conv[pprim];
351 if (result == ~0) {
352 R600_ERR("unsupported primitive type %d\n", pprim);
353 }
354 return result;
355 }
356
357 static unsigned si_conv_prim_to_gs_out(unsigned mode)
358 {
359 static const int prim_conv[] = {
360 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
361 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
362 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
363 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
364 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
365 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
366 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
367 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
368 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
369 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
370 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
371 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
372 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
373 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
374 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
375 };
376 assert(mode < Elements(prim_conv));
377
378 return prim_conv[mode];
379 }
380
381 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
382 const struct pipe_draw_info *info)
383 {
384 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
385 unsigned prim = info->mode;
386 unsigned primgroup_size = 128; /* recommended without a GS */
387
388 /* SWITCH_ON_EOP(0) is always preferable. */
389 bool wd_switch_on_eop = false;
390 bool ia_switch_on_eop = false;
391 bool partial_vs_wave = false;
392
393 if (sctx->gs_shader)
394 primgroup_size = 64; /* recommended with a GS */
395
396 /* This is a hardware requirement. */
397 if ((rs && rs->line_stipple_enable) ||
398 (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
399 ia_switch_on_eop = true;
400 wd_switch_on_eop = true;
401 }
402
403 if (sctx->b.streamout.streamout_enabled ||
404 sctx->b.streamout.prims_gen_query_enabled)
405 partial_vs_wave = true;
406
407 if (sctx->b.chip_class >= CIK) {
408 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
409 * 4 shader engines. Set 1 to pass the assertion below.
410 * The other cases are hardware requirements. */
411 if (sctx->b.screen->info.max_se < 4 ||
412 prim == PIPE_PRIM_POLYGON ||
413 prim == PIPE_PRIM_LINE_LOOP ||
414 prim == PIPE_PRIM_TRIANGLE_FAN ||
415 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
416 info->primitive_restart)
417 wd_switch_on_eop = true;
418
419 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
420 * We don't know that for indirect drawing, so treat it as
421 * always problematic. */
422 if (sctx->b.family == CHIP_HAWAII &&
423 (info->indirect || info->instance_count > 1))
424 wd_switch_on_eop = true;
425
426 /* If the WD switch is false, the IA switch must be false too. */
427 assert(wd_switch_on_eop || !ia_switch_on_eop);
428 }
429
430 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
431 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
432 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
433 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0);
434 }
435
436 static bool si_update_draw_info_state(struct si_context *sctx,
437 const struct pipe_draw_info *info,
438 const struct pipe_index_buffer *ib)
439 {
440 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
441 struct si_shader *vs = si_get_vs_state(sctx);
442 unsigned prim = si_conv_pipe_prim(info->mode);
443 unsigned gs_out_prim =
444 si_conv_prim_to_gs_out(sctx->gs_shader ?
445 sctx->gs_shader->current->shader.gs_output_prim :
446 info->mode);
447 unsigned ls_mask = 0;
448 unsigned ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info);
449
450 if (pm4 == NULL)
451 return false;
452
453 if (prim == ~0) {
454 FREE(pm4);
455 return false;
456 }
457
458 if (sctx->b.chip_class >= CIK) {
459 si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
460 ib->index_size == 4 ? 0xFC000000 : 0xFC00);
461
462 si_pm4_cmd_begin(pm4, PKT3_DRAW_PREAMBLE);
463 si_pm4_cmd_add(pm4, prim); /* VGT_PRIMITIVE_TYPE */
464 si_pm4_cmd_add(pm4, ia_multi_vgt_param); /* IA_MULTI_VGT_PARAM */
465 si_pm4_cmd_add(pm4, 0); /* VGT_LS_HS_CONFIG */
466 si_pm4_cmd_end(pm4, false);
467 } else {
468 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
469 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
470 }
471
472 si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
473 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
474 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
475
476 if (prim == V_008958_DI_PT_LINELIST)
477 ls_mask = 1;
478 else if (prim == V_008958_DI_PT_LINESTRIP)
479 ls_mask = 2;
480 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
481 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
482 sctx->pa_sc_line_stipple);
483
484 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
485 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
486 S_028814_PROVOKING_VTX_LAST(1) | sctx->pa_su_sc_mode_cntl);
487 } else {
488 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, sctx->pa_su_sc_mode_cntl);
489 }
490 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
491 S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
492 S_02881C_USE_VTX_EDGE_FLAG(vs->vs_out_edgeflag) |
493 S_02881C_USE_VTX_RENDER_TARGET_INDX(vs->vs_out_layer) |
494 S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs->clip_dist_write & 0x0F) != 0) |
495 S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs->clip_dist_write & 0xF0) != 0) |
496 S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write) |
497 (sctx->queued.named.rasterizer->clip_plane_enable &
498 vs->clip_dist_write));
499 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL,
500 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
501 (vs->clip_dist_write ? 0 :
502 sctx->queued.named.rasterizer->clip_plane_enable & 0x3F));
503
504 si_pm4_set_state(sctx, draw_info, pm4);
505 return true;
506 }
507
508 static void si_update_spi_map(struct si_context *sctx)
509 {
510 struct si_shader *ps = &sctx->ps_shader->current->shader;
511 struct si_shader *vs = si_get_vs_state(sctx);
512 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
513 unsigned i, j, tmp;
514
515 for (i = 0; i < ps->ninput; i++) {
516 unsigned name = ps->input[i].name;
517 unsigned param_offset = ps->input[i].param_offset;
518
519 if (name == TGSI_SEMANTIC_POSITION)
520 /* Read from preloaded VGPRs, not parameters */
521 continue;
522
523 bcolor:
524 tmp = 0;
525
526 if (ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
527 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
528 sctx->ps_shader->current->key.ps.flatshade)) {
529 tmp |= S_028644_FLAT_SHADE(1);
530 }
531
532 if (name == TGSI_SEMANTIC_GENERIC &&
533 sctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
534 tmp |= S_028644_PT_SPRITE_TEX(1);
535 }
536
537 for (j = 0; j < vs->noutput; j++) {
538 if (name == vs->output[j].name &&
539 ps->input[i].sid == vs->output[j].sid) {
540 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
541 break;
542 }
543 }
544
545 if (j == vs->noutput) {
546 /* No corresponding output found, load defaults into input */
547 tmp |= S_028644_OFFSET(0x20);
548 }
549
550 si_pm4_set_reg(pm4,
551 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
552 tmp);
553
554 if (name == TGSI_SEMANTIC_COLOR &&
555 sctx->ps_shader->current->key.ps.color_two_side) {
556 name = TGSI_SEMANTIC_BCOLOR;
557 param_offset++;
558 goto bcolor;
559 }
560 }
561
562 si_pm4_set_state(sctx, spi, pm4);
563 }
564
565 /* Initialize state related to ESGS / GSVS ring buffers */
566 static void si_init_gs_rings(struct si_context *sctx)
567 {
568 unsigned size = 128 * 1024;
569
570 assert(!sctx->gs_rings);
571 sctx->gs_rings = si_pm4_alloc_state(sctx);
572
573 sctx->esgs_ring.buffer =
574 pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
575 PIPE_USAGE_DEFAULT, size);
576 sctx->esgs_ring.buffer_size = size;
577
578 size = 64 * 1024 * 1024;
579 sctx->gsvs_ring.buffer =
580 pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
581 PIPE_USAGE_DEFAULT, size);
582 sctx->gsvs_ring.buffer_size = size;
583
584 if (sctx->b.chip_class >= CIK) {
585 si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
586 sctx->esgs_ring.buffer_size / 256);
587 si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
588 sctx->gsvs_ring.buffer_size / 256);
589 } else {
590 si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
591 sctx->esgs_ring.buffer_size / 256);
592 si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
593 sctx->gsvs_ring.buffer_size / 256);
594 }
595
596 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
597 &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size,
598 true, true, 4, 64);
599 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
600 &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size,
601 false, false, 0, 0);
602 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
603 &sctx->gsvs_ring, 0, sctx->gsvs_ring.buffer_size,
604 false, false, 0, 0);
605 }
606
607 static void si_update_derived_state(struct si_context *sctx)
608 {
609 struct pipe_context * ctx = (struct pipe_context*)sctx;
610
611 if (!sctx->blitter->running) {
612 /* Flush depth textures which need to be flushed. */
613 for (int i = 0; i < SI_NUM_SHADERS; i++) {
614 if (sctx->samplers[i].depth_texture_mask) {
615 si_flush_depth_textures(sctx, &sctx->samplers[i]);
616 }
617 if (sctx->samplers[i].compressed_colortex_mask) {
618 si_decompress_color_textures(sctx, &sctx->samplers[i]);
619 }
620 }
621 }
622
623 if (sctx->gs_shader) {
624 si_shader_select(ctx, sctx->gs_shader);
625
626 if (!sctx->gs_shader->current->pm4) {
627 si_pipe_shader_gs(ctx, sctx->gs_shader->current);
628 si_pipe_shader_vs(ctx,
629 sctx->gs_shader->current->gs_copy_shader);
630 }
631
632 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
633 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
634
635 sctx->b.streamout.stride_in_dw = sctx->gs_shader->so.stride;
636
637 si_shader_select(ctx, sctx->vs_shader);
638
639 if (!sctx->vs_shader->current->pm4)
640 si_pipe_shader_es(ctx, sctx->vs_shader->current);
641
642 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
643
644 if (!sctx->gs_rings)
645 si_init_gs_rings(sctx);
646 if (sctx->emitted.named.gs_rings != sctx->gs_rings)
647 sctx->b.flags |= R600_CONTEXT_VGT_FLUSH;
648 si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
649
650 si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
651 &sctx->gsvs_ring,
652 sctx->gs_shader->current->shader.gs_max_out_vertices *
653 sctx->gs_shader->current->shader.noutput * 16,
654 64, true, true, 4, 16);
655
656 if (!sctx->gs_on) {
657 sctx->gs_on = si_pm4_alloc_state(sctx);
658
659 si_pm4_set_reg(sctx->gs_on, R_028B54_VGT_SHADER_STAGES_EN,
660 S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
661 S_028B54_GS_EN(1) |
662 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER));
663 }
664 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_on);
665 } else {
666 si_shader_select(ctx, sctx->vs_shader);
667
668 if (!sctx->vs_shader->current->pm4)
669 si_pipe_shader_vs(ctx, sctx->vs_shader->current);
670
671 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
672
673 sctx->b.streamout.stride_in_dw = sctx->vs_shader->so.stride;
674
675 if (!sctx->gs_off) {
676 sctx->gs_off = si_pm4_alloc_state(sctx);
677
678 si_pm4_set_reg(sctx->gs_off, R_028A40_VGT_GS_MODE, 0);
679 si_pm4_set_reg(sctx->gs_off, R_028B54_VGT_SHADER_STAGES_EN, 0);
680 }
681 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_off);
682 si_pm4_bind_state(sctx, gs_rings, NULL);
683 si_pm4_bind_state(sctx, gs, NULL);
684 si_pm4_bind_state(sctx, es, NULL);
685 }
686
687 si_shader_select(ctx, sctx->ps_shader);
688
689 if (!sctx->ps_shader->current->pm4 ||
690 sctx->ps_shader->current->cb0_is_integer != sctx->framebuffer.cb0_is_integer)
691 si_pipe_shader_ps(ctx, sctx->ps_shader->current);
692
693 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
694
695 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs)) {
696 /* XXX: Emitting the PS state even when only the VS changed
697 * fixes random failures with piglit glsl-max-varyings.
698 * Not sure why...
699 */
700 sctx->emitted.named.ps = NULL;
701 si_update_spi_map(sctx);
702 }
703 }
704
705 static void si_state_draw(struct si_context *sctx,
706 const struct pipe_draw_info *info,
707 const struct pipe_index_buffer *ib)
708 {
709 unsigned sh_base_reg = (sctx->gs_shader ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
710 R_00B130_SPI_SHADER_USER_DATA_VS_0);
711 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
712
713 if (pm4 == NULL)
714 return;
715
716 /* queries need some special values
717 * (this is non-zero if any query is active) */
718 if (sctx->b.num_occlusion_queries > 0) {
719 if (sctx->b.chip_class >= CIK) {
720 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
721 S_028004_PERFECT_ZPASS_COUNTS(1) |
722 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
723 S_028004_ZPASS_ENABLE(1) |
724 S_028004_SLICE_EVEN_ENABLE(1) |
725 S_028004_SLICE_ODD_ENABLE(1));
726 } else {
727 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
728 S_028004_PERFECT_ZPASS_COUNTS(1) |
729 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
730 }
731 } else {
732 /* Disable occlusion queries. */
733 if (sctx->b.chip_class >= CIK) {
734 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL, 0);
735 } else {
736 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
737 S_028004_ZPASS_INCREMENT_DISABLE(1));
738 }
739 }
740
741 /* DB_RENDER_CONTROL */
742 if (sctx->dbcb_depth_copy_enabled ||
743 sctx->dbcb_stencil_copy_enabled) {
744 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL,
745 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
746 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
747 S_028000_COPY_CENTROID(1) |
748 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
749 } else if (sctx->db_inplace_flush_enabled) {
750 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL,
751 S_028000_DEPTH_COMPRESS_DISABLE(1) |
752 S_028000_STENCIL_COMPRESS_DISABLE(1));
753 } else if (sctx->db_depth_clear) {
754 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL,
755 S_028000_DEPTH_CLEAR_ENABLE(1));
756 } else {
757 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, 0);
758 }
759
760 /* DB_RENDER_OVERRIDE2 */
761 if (sctx->db_depth_disable_expclear) {
762 si_pm4_set_reg(pm4, R_028010_DB_RENDER_OVERRIDE2,
763 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
764 } else {
765 si_pm4_set_reg(pm4, R_028010_DB_RENDER_OVERRIDE2, 0);
766 }
767
768 if (info->count_from_stream_output) {
769 struct r600_so_target *t =
770 (struct r600_so_target*)info->count_from_stream_output;
771 uint64_t va = t->buf_filled_size->gpu_address +
772 t->buf_filled_size_offset;
773
774 si_pm4_set_reg(pm4, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
775 t->stride_in_dw);
776
777 si_pm4_cmd_begin(pm4, PKT3_COPY_DATA);
778 si_pm4_cmd_add(pm4,
779 COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
780 COPY_DATA_DST_SEL(COPY_DATA_REG) |
781 COPY_DATA_WR_CONFIRM);
782 si_pm4_cmd_add(pm4, va); /* src address lo */
783 si_pm4_cmd_add(pm4, va >> 32UL); /* src address hi */
784 si_pm4_cmd_add(pm4, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
785 si_pm4_cmd_add(pm4, 0); /* unused */
786 si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ,
787 RADEON_PRIO_MIN);
788 si_pm4_cmd_end(pm4, true);
789 }
790
791 /* draw packet */
792 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
793 if (ib->index_size == 4) {
794 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (SI_BIG_ENDIAN ?
795 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
796 } else {
797 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (SI_BIG_ENDIAN ?
798 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
799 }
800 si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
801
802 if (!info->indirect) {
803 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
804 si_pm4_cmd_add(pm4, info->instance_count);
805 si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
806
807 si_pm4_set_reg(pm4, sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
808 info->indexed ? info->index_bias : info->start);
809 si_pm4_set_reg(pm4, sh_base_reg + SI_SGPR_START_INSTANCE * 4,
810 info->start_instance);
811 } else {
812 si_pm4_add_bo(pm4, (struct r600_resource *)info->indirect,
813 RADEON_USAGE_READ, RADEON_PRIO_MIN);
814 }
815
816 if (info->indexed) {
817 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
818 sctx->index_buffer.index_size;
819 uint64_t va = r600_resource(ib->buffer)->gpu_address + ib->offset;
820
821 si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ,
822 RADEON_PRIO_MIN);
823
824 if (info->indirect) {
825 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
826 si_cmd_draw_index_indirect(pm4, indirect_va, va, max_size,
827 info->indirect_offset,
828 sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
829 sh_base_reg + SI_SGPR_START_INSTANCE * 4,
830 sctx->b.predicate_drawing);
831 } else {
832 va += info->start * ib->index_size;
833 si_cmd_draw_index_2(pm4, max_size, va, info->count,
834 V_0287F0_DI_SRC_SEL_DMA,
835 sctx->b.predicate_drawing);
836 }
837 } else {
838 if (info->indirect) {
839 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
840 si_cmd_draw_indirect(pm4, indirect_va, info->indirect_offset,
841 sh_base_reg + SI_SGPR_BASE_VERTEX * 4,
842 sh_base_reg + SI_SGPR_START_INSTANCE * 4,
843 sctx->b.predicate_drawing);
844 } else {
845 si_cmd_draw_index_auto(pm4, info->count,
846 V_0287F0_DI_SRC_SEL_AUTO_INDEX |
847 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output),
848 sctx->b.predicate_drawing);
849 }
850 }
851
852 si_pm4_set_state(sctx, draw, pm4);
853 }
854
855 void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom)
856 {
857 struct radeon_winsys_cs *cs = sctx->rings.gfx.cs;
858 uint32_t cp_coher_cntl = 0;
859
860 /* XXX SI flushes both ICACHE and KCACHE if either flag is set.
861 * XXX CIK shouldn't have this issue. Test CIK before separating the flags
862 * XXX to ensure there is no regression. Also find out if there is another
863 * XXX way to flush either ICACHE or KCACHE but not both for SI. */
864 if (sctx->flags & (R600_CONTEXT_INV_SHADER_CACHE |
865 R600_CONTEXT_INV_CONST_CACHE)) {
866 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1) |
867 S_0085F0_SH_KCACHE_ACTION_ENA(1);
868 }
869 if (sctx->flags & (R600_CONTEXT_INV_TEX_CACHE |
870 R600_CONTEXT_STREAMOUT_FLUSH)) {
871 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1) |
872 S_0085F0_TCL1_ACTION_ENA(1);
873 }
874 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB) {
875 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
876 S_0085F0_CB0_DEST_BASE_ENA(1) |
877 S_0085F0_CB1_DEST_BASE_ENA(1) |
878 S_0085F0_CB2_DEST_BASE_ENA(1) |
879 S_0085F0_CB3_DEST_BASE_ENA(1) |
880 S_0085F0_CB4_DEST_BASE_ENA(1) |
881 S_0085F0_CB5_DEST_BASE_ENA(1) |
882 S_0085F0_CB6_DEST_BASE_ENA(1) |
883 S_0085F0_CB7_DEST_BASE_ENA(1);
884 }
885 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB) {
886 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
887 S_0085F0_DB_DEST_BASE_ENA(1);
888 }
889
890 if (cp_coher_cntl) {
891 if (sctx->chip_class >= CIK) {
892 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
893 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
894 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
895 radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */
896 radeon_emit(cs, 0); /* CP_COHER_BASE */
897 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
898 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
899 } else {
900 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
901 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
902 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
903 radeon_emit(cs, 0); /* CP_COHER_BASE */
904 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
905 }
906 }
907
908 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META) {
909 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
910 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
911 }
912 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB_META) {
913 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
914 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
915 }
916
917 if (sctx->flags & (R600_CONTEXT_WAIT_3D_IDLE |
918 R600_CONTEXT_PS_PARTIAL_FLUSH)) {
919 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
920 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
921 } else if (sctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
922 /* Needed if streamout buffers are going to be used as a source. */
923 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
924 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
925 }
926
927 if (sctx->flags & R600_CONTEXT_VGT_FLUSH) {
928 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
929 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
930 }
931 if (sctx->flags & R600_CONTEXT_VGT_STREAMOUT_SYNC) {
932 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
933 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
934 }
935
936 sctx->flags = 0;
937 }
938
939 const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 17 }; /* number of CS dwords */
940
941 static void si_get_draw_start_count(struct si_context *sctx,
942 const struct pipe_draw_info *info,
943 unsigned *start, unsigned *count)
944 {
945 if (info->indirect) {
946 struct r600_resource *indirect =
947 (struct r600_resource*)info->indirect;
948 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
949 indirect, PIPE_TRANSFER_READ);
950 data += info->indirect_offset/sizeof(int);
951 *start = data[2];
952 *count = data[0];
953 } else {
954 *start = info->start;
955 *count = info->count;
956 }
957 }
958
959 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
960 {
961 struct si_context *sctx = (struct si_context *)ctx;
962 struct pipe_index_buffer ib = {};
963 uint32_t i;
964
965 if (!info->count && !info->indirect &&
966 (info->indexed || !info->count_from_stream_output))
967 return;
968
969 if (!sctx->ps_shader || !sctx->vs_shader)
970 return;
971
972 si_update_derived_state(sctx);
973
974 if (sctx->vertex_buffers_dirty) {
975 si_update_vertex_buffers(sctx);
976 sctx->vertex_buffers_dirty = false;
977 }
978
979 if (info->indexed) {
980 /* Initialize the index buffer struct. */
981 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
982 ib.user_buffer = sctx->index_buffer.user_buffer;
983 ib.index_size = sctx->index_buffer.index_size;
984 ib.offset = sctx->index_buffer.offset;
985
986 /* Translate or upload, if needed. */
987 if (ib.index_size == 1) {
988 struct pipe_resource *out_buffer = NULL;
989 unsigned out_offset, start, count, start_offset;
990 void *ptr;
991
992 si_get_draw_start_count(sctx, info, &start, &count);
993 start_offset = start * ib.index_size;
994
995 u_upload_alloc(sctx->b.uploader, start_offset, count * 2,
996 &out_offset, &out_buffer, &ptr);
997
998 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
999 ib.offset + start_offset,
1000 count, ptr);
1001
1002 pipe_resource_reference(&ib.buffer, NULL);
1003 ib.user_buffer = NULL;
1004 ib.buffer = out_buffer;
1005 /* info->start will be added by the drawing code */
1006 ib.offset = out_offset - start_offset;
1007 ib.index_size = 2;
1008 } else if (ib.user_buffer && !ib.buffer) {
1009 unsigned start, count, start_offset;
1010
1011 si_get_draw_start_count(sctx, info, &start, &count);
1012 start_offset = start * ib.index_size;
1013
1014 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
1015 (char*)ib.user_buffer + start_offset,
1016 &ib.offset, &ib.buffer);
1017 /* info->start will be added by the drawing code */
1018 ib.offset -= start_offset;
1019 }
1020 }
1021
1022 if (!si_update_draw_info_state(sctx, info, &ib))
1023 return;
1024
1025 si_state_draw(sctx, info, &ib);
1026
1027 sctx->pm4_dirty_cdwords += si_pm4_dirty_dw(sctx);
1028
1029 /* Check flush flags. */
1030 if (sctx->b.flags)
1031 sctx->atoms.s.cache_flush->dirty = true;
1032
1033 si_need_cs_space(sctx, 0, TRUE);
1034
1035 /* Emit states. */
1036 for (i = 0; i < SI_NUM_ATOMS(sctx); i++) {
1037 if (sctx->atoms.array[i]->dirty) {
1038 sctx->atoms.array[i]->emit(&sctx->b, sctx->atoms.array[i]);
1039 sctx->atoms.array[i]->dirty = false;
1040 }
1041 }
1042
1043 si_pm4_emit_dirty(sctx);
1044 sctx->pm4_dirty_cdwords = 0;
1045
1046 #if SI_TRACE_CS
1047 if (sctx->screen->b.trace_bo) {
1048 si_trace_emit(sctx);
1049 }
1050 #endif
1051
1052 /* Workaround for a VGT hang when streamout is enabled.
1053 * It must be done after drawing. */
1054 if (sctx->b.family == CHIP_HAWAII &&
1055 (sctx->b.streamout.streamout_enabled ||
1056 sctx->b.streamout.prims_gen_query_enabled)) {
1057 sctx->b.flags |= R600_CONTEXT_VGT_STREAMOUT_SYNC;
1058 }
1059
1060 /* Set the depth buffer as dirty. */
1061 if (sctx->framebuffer.state.zsbuf) {
1062 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1063 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1064
1065 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1066 }
1067 if (sctx->framebuffer.compressed_cb_mask) {
1068 struct pipe_surface *surf;
1069 struct r600_texture *rtex;
1070 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1071
1072 do {
1073 unsigned i = u_bit_scan(&mask);
1074 surf = sctx->framebuffer.state.cbufs[i];
1075 rtex = (struct r600_texture*)surf->texture;
1076
1077 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1078 } while (mask);
1079 }
1080
1081 pipe_resource_reference(&ib.buffer, NULL);
1082 sctx->b.num_draw_calls++;
1083 }