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radeonsi: convert constant buffers to si_descriptors
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "radeonsi_pipe.h"
32 #include "radeonsi_shader.h"
33 #include "si_state.h"
34 #include "../radeon/r600_cs.h"
35 #include "sid.h"
36
37 /*
38 * Shaders
39 */
40
41 static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
42 {
43 struct r600_context *rctx = (struct r600_context *)ctx;
44 struct si_pm4_state *pm4;
45 unsigned num_sgprs, num_user_sgprs;
46 unsigned nparams, i, vgpr_comp_cnt;
47 uint64_t va;
48
49 si_pm4_delete_state(rctx, vs, shader->pm4);
50 pm4 = shader->pm4 = si_pm4_alloc_state(rctx);
51
52 if (pm4 == NULL)
53 return;
54
55 si_pm4_inval_shader_cache(pm4);
56
57 /* Certain attributes (position, psize, etc.) don't count as params.
58 * VS is required to export at least one param and r600_shader_from_tgsi()
59 * takes care of adding a dummy export.
60 */
61 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
62 switch (shader->shader.output[i].name) {
63 case TGSI_SEMANTIC_CLIPVERTEX:
64 case TGSI_SEMANTIC_POSITION:
65 case TGSI_SEMANTIC_PSIZE:
66 break;
67 default:
68 nparams++;
69 }
70 }
71 if (nparams < 1)
72 nparams = 1;
73
74 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
75 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
76
77 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
78 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
79 S_02870C_POS1_EXPORT_FORMAT(shader->shader.nr_pos_exports > 1 ?
80 V_02870C_SPI_SHADER_4COMP :
81 V_02870C_SPI_SHADER_NONE) |
82 S_02870C_POS2_EXPORT_FORMAT(shader->shader.nr_pos_exports > 2 ?
83 V_02870C_SPI_SHADER_4COMP :
84 V_02870C_SPI_SHADER_NONE) |
85 S_02870C_POS3_EXPORT_FORMAT(shader->shader.nr_pos_exports > 3 ?
86 V_02870C_SPI_SHADER_4COMP :
87 V_02870C_SPI_SHADER_NONE));
88
89 va = r600_resource_va(ctx->screen, (void *)shader->bo);
90 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
91 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
92 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
93
94 num_user_sgprs = SI_VS_NUM_USER_SGPR;
95 num_sgprs = shader->num_sgprs;
96 if (num_user_sgprs > num_sgprs) {
97 /* Last 2 reserved SGPRs are used for VCC */
98 num_sgprs = num_user_sgprs + 2;
99 }
100 assert(num_sgprs <= 104);
101
102 vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
103
104 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
105 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
106 S_00B128_SGPRS((num_sgprs - 1) / 8) |
107 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
108 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
109 S_00B12C_USER_SGPR(num_user_sgprs));
110
111 if (rctx->b.chip_class >= CIK) {
112 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
113 S_00B118_CU_EN(0xffff));
114 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
115 S_00B11C_LIMIT(0));
116 }
117
118 si_pm4_bind_state(rctx, vs, shader->pm4);
119 }
120
121 static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
122 {
123 struct r600_context *rctx = (struct r600_context *)ctx;
124 struct si_pm4_state *pm4;
125 unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
126 unsigned num_sgprs, num_user_sgprs;
127 unsigned spi_baryc_cntl = 0, spi_ps_input_ena, spi_shader_z_format;
128 uint64_t va;
129
130 si_pm4_delete_state(rctx, ps, shader->pm4);
131 pm4 = shader->pm4 = si_pm4_alloc_state(rctx);
132
133 if (pm4 == NULL)
134 return;
135
136 si_pm4_inval_shader_cache(pm4);
137
138 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
139 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->fb_cb0_is_integer);
140
141 for (i = 0; i < shader->shader.ninput; i++) {
142 switch (shader->shader.input[i].name) {
143 case TGSI_SEMANTIC_POSITION:
144 if (shader->shader.input[i].centroid) {
145 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
146 * Possible vaules:
147 * 0 -> Position = pixel center (default)
148 * 1 -> Position = pixel centroid
149 * 2 -> Position = iterated sample number XXX:
150 * What does this mean?
151 */
152 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
153 }
154 /* Fall through */
155 case TGSI_SEMANTIC_FACE:
156 continue;
157 }
158 }
159
160 for (i = 0; i < shader->shader.noutput; i++) {
161 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
162 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
163 if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
164 db_shader_control |= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
165 }
166 if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
167 db_shader_control |= S_02880C_KILL_ENABLE(1);
168
169 exports_ps = 0;
170 num_cout = 0;
171 for (i = 0; i < shader->shader.noutput; i++) {
172 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
173 shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
174 exports_ps |= 1;
175 else if (shader->shader.output[i].name == TGSI_SEMANTIC_COLOR) {
176 if (shader->shader.fs_write_all)
177 num_cout = shader->shader.nr_cbufs;
178 else
179 num_cout++;
180 }
181 }
182 if (!exports_ps) {
183 /* always at least export 1 component per pixel */
184 exports_ps = 2;
185 }
186
187 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.ninterp) |
188 S_0286D8_BC_OPTIMIZE_DISABLE(1);
189
190 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
191 spi_ps_input_ena = shader->spi_ps_input_ena;
192 /* we need to enable at least one of them, otherwise we hang the GPU */
193 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
194 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
195 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
196 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
197 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
198 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
199 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
200 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
201
202 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
203 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
204 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
205
206 if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control))
207 spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
208 else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control))
209 spi_shader_z_format = V_028710_SPI_SHADER_32_R;
210 else
211 spi_shader_z_format = 0;
212 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, spi_shader_z_format);
213 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
214 shader->spi_shader_col_format);
215 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
216
217 va = r600_resource_va(ctx->screen, (void *)shader->bo);
218 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
219 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
220 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
221
222 num_user_sgprs = SI_PS_NUM_USER_SGPR;
223 num_sgprs = shader->num_sgprs;
224 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
225 if ((num_user_sgprs + 1) > num_sgprs) {
226 /* Last 2 reserved SGPRs are used for VCC */
227 num_sgprs = num_user_sgprs + 1 + 2;
228 }
229 assert(num_sgprs <= 104);
230
231 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
232 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
233 S_00B028_SGPRS((num_sgprs - 1) / 8));
234 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
235 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
236 S_00B02C_USER_SGPR(num_user_sgprs));
237 if (rctx->b.chip_class >= CIK) {
238 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
239 S_00B01C_CU_EN(0xffff));
240 }
241
242 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
243
244 shader->cb0_is_integer = rctx->fb_cb0_is_integer;
245 shader->sprite_coord_enable = rctx->sprite_coord_enable;
246 si_pm4_bind_state(rctx, ps, shader->pm4);
247 }
248
249 /*
250 * Drawing
251 */
252
253 static unsigned si_conv_pipe_prim(unsigned pprim)
254 {
255 static const unsigned prim_conv[] = {
256 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
257 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
258 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
259 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
260 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
261 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
262 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
263 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
264 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
265 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
266 [PIPE_PRIM_LINES_ADJACENCY] = ~0,
267 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0,
268 [PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0,
269 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0
270 };
271 unsigned result = prim_conv[pprim];
272 if (result == ~0) {
273 R600_ERR("unsupported primitive type %d\n", pprim);
274 }
275 return result;
276 }
277
278 static bool si_update_draw_info_state(struct r600_context *rctx,
279 const struct pipe_draw_info *info)
280 {
281 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
282 struct si_shader *vs = &rctx->vs_shader->current->shader;
283 unsigned prim = si_conv_pipe_prim(info->mode);
284 unsigned ls_mask = 0;
285
286 if (pm4 == NULL)
287 return false;
288
289 if (prim == ~0) {
290 FREE(pm4);
291 return false;
292 }
293
294 if (rctx->b.chip_class >= CIK)
295 si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim);
296 else
297 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
298 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
299 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
300 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET,
301 info->indexed ? info->index_bias : info->start);
302 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
303 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
304 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_START_INSTANCE * 4,
305 info->start_instance);
306
307 if (prim == V_008958_DI_PT_LINELIST)
308 ls_mask = 1;
309 else if (prim == V_008958_DI_PT_LINESTRIP)
310 ls_mask = 2;
311 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
312 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
313 rctx->pa_sc_line_stipple);
314
315 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
316 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
317 S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
318 } else {
319 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
320 }
321 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
322 S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
323 S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs->clip_dist_write & 0x0F) != 0) |
324 S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs->clip_dist_write & 0xF0) != 0) |
325 S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write) |
326 (rctx->queued.named.rasterizer->clip_plane_enable &
327 vs->clip_dist_write));
328 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL,
329 rctx->queued.named.rasterizer->pa_cl_clip_cntl |
330 (vs->clip_dist_write ? 0 :
331 rctx->queued.named.rasterizer->clip_plane_enable & 0x3F));
332
333 si_pm4_set_state(rctx, draw_info, pm4);
334 return true;
335 }
336
337 static void si_update_spi_map(struct r600_context *rctx)
338 {
339 struct si_shader *ps = &rctx->ps_shader->current->shader;
340 struct si_shader *vs = &rctx->vs_shader->current->shader;
341 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
342 unsigned i, j, tmp;
343
344 for (i = 0; i < ps->ninput; i++) {
345 unsigned name = ps->input[i].name;
346 unsigned param_offset = ps->input[i].param_offset;
347
348 if (name == TGSI_SEMANTIC_POSITION)
349 /* Read from preloaded VGPRs, not parameters */
350 continue;
351
352 bcolor:
353 tmp = 0;
354
355 if (ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
356 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
357 rctx->ps_shader->current->key.ps.flatshade)) {
358 tmp |= S_028644_FLAT_SHADE(1);
359 }
360
361 if (name == TGSI_SEMANTIC_GENERIC &&
362 rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
363 tmp |= S_028644_PT_SPRITE_TEX(1);
364 }
365
366 for (j = 0; j < vs->noutput; j++) {
367 if (name == vs->output[j].name &&
368 ps->input[i].sid == vs->output[j].sid) {
369 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
370 break;
371 }
372 }
373
374 if (j == vs->noutput) {
375 /* No corresponding output found, load defaults into input */
376 tmp |= S_028644_OFFSET(0x20);
377 }
378
379 si_pm4_set_reg(pm4,
380 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
381 tmp);
382
383 if (name == TGSI_SEMANTIC_COLOR &&
384 rctx->ps_shader->current->key.ps.color_two_side) {
385 name = TGSI_SEMANTIC_BCOLOR;
386 param_offset++;
387 goto bcolor;
388 }
389 }
390
391 si_pm4_set_state(rctx, spi, pm4);
392 }
393
394 static void si_update_derived_state(struct r600_context *rctx)
395 {
396 struct pipe_context * ctx = (struct pipe_context*)rctx;
397 unsigned vs_dirty = 0, ps_dirty = 0;
398
399 if (!rctx->blitter->running) {
400 /* Flush depth textures which need to be flushed. */
401 for (int i = 0; i < SI_NUM_SHADERS; i++) {
402 if (rctx->samplers[i].depth_texture_mask) {
403 si_flush_depth_textures(rctx, &rctx->samplers[i]);
404 }
405 if (rctx->samplers[i].compressed_colortex_mask) {
406 r600_decompress_color_textures(rctx, &rctx->samplers[i]);
407 }
408 }
409 }
410
411 si_shader_select(ctx, rctx->vs_shader, &vs_dirty);
412
413 if (!rctx->vs_shader->current->pm4) {
414 si_pipe_shader_vs(ctx, rctx->vs_shader->current);
415 vs_dirty = 0;
416 }
417
418 if (vs_dirty) {
419 si_pm4_bind_state(rctx, vs, rctx->vs_shader->current->pm4);
420 }
421
422
423 si_shader_select(ctx, rctx->ps_shader, &ps_dirty);
424
425 if (!rctx->ps_shader->current->pm4) {
426 si_pipe_shader_ps(ctx, rctx->ps_shader->current);
427 ps_dirty = 0;
428 }
429 if (!rctx->ps_shader->current->bo) {
430 if (!rctx->dummy_pixel_shader->pm4)
431 si_pipe_shader_ps(ctx, rctx->dummy_pixel_shader);
432 else
433 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
434
435 ps_dirty = 0;
436 }
437 if (rctx->ps_shader->current->cb0_is_integer != rctx->fb_cb0_is_integer) {
438 si_pipe_shader_ps(ctx, rctx->ps_shader->current);
439 ps_dirty = 1;
440 }
441
442 if (ps_dirty) {
443 si_pm4_bind_state(rctx, ps, rctx->ps_shader->current->pm4);
444 }
445
446 if (si_pm4_state_changed(rctx, ps) || si_pm4_state_changed(rctx, vs)) {
447 /* XXX: Emitting the PS state even when only the VS changed
448 * fixes random failures with piglit glsl-max-varyings.
449 * Not sure why...
450 */
451 rctx->emitted.named.ps = NULL;
452 si_update_spi_map(rctx);
453 }
454 }
455
456 static void si_vertex_buffer_update(struct r600_context *rctx)
457 {
458 struct pipe_context *ctx = &rctx->b.b;
459 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
460 bool bound[PIPE_MAX_ATTRIBS] = {};
461 unsigned i, count;
462 uint64_t va;
463
464 si_pm4_inval_texture_cache(pm4);
465
466 /* bind vertex buffer once */
467 count = rctx->vertex_elements->count;
468 assert(count <= 256 / 4);
469
470 si_pm4_sh_data_begin(pm4);
471 for (i = 0 ; i < count; i++) {
472 struct pipe_vertex_element *ve = &rctx->vertex_elements->elements[i];
473 struct pipe_vertex_buffer *vb;
474 struct r600_resource *rbuffer;
475 unsigned offset;
476
477 if (ve->vertex_buffer_index >= rctx->nr_vertex_buffers)
478 continue;
479
480 vb = &rctx->vertex_buffer[ve->vertex_buffer_index];
481 rbuffer = (struct r600_resource*)vb->buffer;
482 if (rbuffer == NULL)
483 continue;
484
485 offset = 0;
486 offset += vb->buffer_offset;
487 offset += ve->src_offset;
488
489 va = r600_resource_va(ctx->screen, (void*)rbuffer);
490 va += offset;
491
492 /* Fill in T# buffer resource description */
493 si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF);
494 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
495 S_008F04_STRIDE(vb->stride)));
496 if (vb->stride)
497 /* Round up by rounding down and adding 1 */
498 si_pm4_sh_data_add(pm4,
499 (vb->buffer->width0 - offset -
500 util_format_get_blocksize(ve->src_format)) /
501 vb->stride + 1);
502 else
503 si_pm4_sh_data_add(pm4, vb->buffer->width0 - offset);
504 si_pm4_sh_data_add(pm4, rctx->vertex_elements->rsrc_word3[i]);
505
506 if (!bound[ve->vertex_buffer_index]) {
507 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
508 bound[ve->vertex_buffer_index] = true;
509 }
510 }
511 si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_VERTEX_BUFFER);
512 si_pm4_set_state(rctx, vertex_buffers, pm4);
513 }
514
515 static void si_state_draw(struct r600_context *rctx,
516 const struct pipe_draw_info *info,
517 const struct pipe_index_buffer *ib)
518 {
519 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
520
521 if (pm4 == NULL)
522 return;
523
524 /* queries need some special values
525 * (this is non-zero if any query is active) */
526 if (rctx->num_cs_dw_nontimer_queries_suspend) {
527 struct si_state_dsa *dsa = rctx->queued.named.dsa;
528
529 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
530 S_028004_PERFECT_ZPASS_COUNTS(1) |
531 S_028004_SAMPLE_RATE(rctx->fb_log_samples));
532 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
533 dsa->db_render_override |
534 S_02800C_NOOP_CULL_DISABLE(1));
535 }
536
537 /* draw packet */
538 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
539 if (ib->index_size == 4) {
540 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (R600_BIG_ENDIAN ?
541 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
542 } else {
543 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (R600_BIG_ENDIAN ?
544 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
545 }
546 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
547
548 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
549 si_pm4_cmd_add(pm4, info->instance_count);
550 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
551
552 if (info->indexed) {
553 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
554 rctx->index_buffer.index_size;
555 uint64_t va;
556 va = r600_resource_va(&rctx->screen->b.b, ib->buffer);
557 va += ib->offset;
558
559 si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ);
560 si_cmd_draw_index_2(pm4, max_size, va, info->count,
561 V_0287F0_DI_SRC_SEL_DMA,
562 rctx->predicate_drawing);
563 } else {
564 uint32_t initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
565 initiator |= S_0287F0_USE_OPAQUE(!!info->count_from_stream_output);
566 si_cmd_draw_index_auto(pm4, info->count, initiator, rctx->predicate_drawing);
567 }
568 si_pm4_set_state(rctx, draw, pm4);
569 }
570
571 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
572 {
573 struct r600_context *rctx = (struct r600_context *)ctx;
574 struct pipe_index_buffer ib = {};
575 uint32_t cp_coher_cntl, i;
576
577 if (!info->count && (info->indexed || !info->count_from_stream_output))
578 return;
579
580 if (!rctx->ps_shader || !rctx->vs_shader)
581 return;
582
583 si_update_derived_state(rctx);
584 si_vertex_buffer_update(rctx);
585
586 if (info->indexed) {
587 /* Initialize the index buffer struct. */
588 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
589 ib.user_buffer = rctx->index_buffer.user_buffer;
590 ib.index_size = rctx->index_buffer.index_size;
591 ib.offset = rctx->index_buffer.offset + info->start * ib.index_size;
592
593 /* Translate or upload, if needed. */
594 r600_translate_index_buffer(rctx, &ib, info->count);
595
596 if (ib.user_buffer && !ib.buffer) {
597 r600_upload_index_buffer(rctx, &ib, info->count);
598 }
599 }
600
601 rctx->vs_shader_so_strides = rctx->vs_shader->current->so_strides;
602
603 if (!si_update_draw_info_state(rctx, info))
604 return;
605
606 si_state_draw(rctx, info, &ib);
607
608 /* Cache flushing via CP_COHER_CNTL. */
609 cp_coher_cntl = si_pm4_sync_flags(rctx);
610
611 if (rctx->b.flags & R600_CONTEXT_INV_CONST_CACHE) {
612 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1) |
613 S_0085F0_SH_KCACHE_ACTION_ENA(1);
614 }
615
616 if (cp_coher_cntl) {
617 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
618
619 if (pm4 == NULL)
620 return;
621
622 si_cmd_surface_sync(pm4, cp_coher_cntl);
623 si_pm4_set_state(rctx, sync, pm4);
624 }
625
626 if (rctx->flush_and_inv_cb_meta) {
627 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
628
629 if (pm4 == NULL)
630 return;
631
632 si_cmd_flush_and_inv_cb_meta(pm4);
633 si_pm4_set_state(rctx, flush_and_inv_cb_meta, pm4);
634 rctx->flush_and_inv_cb_meta = false;
635 }
636
637 /* Emit states. */
638 rctx->pm4_dirty_cdwords += si_pm4_dirty_dw(rctx);
639
640 si_need_cs_space(rctx, 0, TRUE);
641
642 for (i = 0; i < SI_NUM_ATOMS(rctx); i++) {
643 if (rctx->atoms.array[i]->dirty) {
644 rctx->atoms.array[i]->emit(&rctx->b, rctx->atoms.array[i]);
645 rctx->atoms.array[i]->dirty = false;
646 }
647 }
648
649 si_pm4_emit_dirty(rctx);
650 rctx->pm4_dirty_cdwords = 0;
651
652 #if R600_TRACE_CS
653 if (rctx->screen->trace_bo) {
654 r600_trace_emit(rctx);
655 }
656 #endif
657
658 #if 0
659 /* Enable stream out if needed. */
660 if (rctx->streamout_start) {
661 r600_context_streamout_begin(rctx);
662 rctx->streamout_start = FALSE;
663 }
664 #endif
665
666 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY;
667
668 /* Set the depth buffer as dirty. */
669 if (rctx->framebuffer.zsbuf) {
670 struct pipe_surface *surf = rctx->framebuffer.zsbuf;
671 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
672
673 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
674 }
675 if (rctx->fb_compressed_cb_mask) {
676 struct pipe_surface *surf;
677 struct r600_texture *rtex;
678 unsigned mask = rctx->fb_compressed_cb_mask;
679
680 do {
681 unsigned i = u_bit_scan(&mask);
682 surf = rctx->framebuffer.cbufs[i];
683 rtex = (struct r600_texture*)surf->texture;
684
685 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
686 } while (mask);
687 }
688
689 pipe_resource_reference(&ib.buffer, NULL);
690 }