src/gallium/drivers/radeonsi/si_state_draw.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Christian König <christian.koenig@amd.com>
  25  */
  26
  27 #include "util/u_memory.h"
  28 #include "util/u_framebuffer.h"
  29 #include "util/u_blitter.h"
  30 #include "tgsi/tgsi_parse.h"
  31 #include "radeonsi_pipe.h"
  32 #include "si_state.h"
  33 #include "sid.h"
  34
  35 /*
  36  * Shaders
  37  */
  38
  39 static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
  40 {
  41         struct r600_context *rctx = (struct r600_context *)ctx;
  42         struct si_pm4_state *pm4;
  43         unsigned num_sgprs, num_user_sgprs;
  44         unsigned nparams, i;
  45         uint64_t va;
  46
  47         if (si_pipe_shader_create(ctx, shader))
  48                 return;
  49
  50         si_pm4_delete_state(rctx, vs, shader->pm4);
  51         pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
  52
  53         si_pm4_inval_shader_cache(pm4);
  54
  55         /* Certain attributes (position, psize, etc.) don't count as params.
  56          * VS is required to export at least one param and r600_shader_from_tgsi()
  57          * takes care of adding a dummy export.
  58          */
  59         for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
  60                 if (shader->shader.output[i].name != TGSI_SEMANTIC_POSITION)
  61                         nparams++;
  62         }
  63         if (nparams < 1)
  64                 nparams = 1;
  65
  66         si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
  67                        S_0286C4_VS_EXPORT_COUNT(nparams - 1));
  68
  69         si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
  70                        S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
  71                        S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
  72                        S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
  73                        S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE));
  74
  75         va = r600_resource_va(ctx->screen, (void *)shader->bo);
  76         si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
  77         si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
  78         si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
  79
  80         num_user_sgprs = 8;
  81         num_sgprs = shader->num_sgprs;
  82         if (num_user_sgprs > num_sgprs)
  83                 num_sgprs = num_user_sgprs;
  84         /* Last 2 reserved SGPRs are used for VCC */
  85         num_sgprs += 2;
  86         assert(num_sgprs <= 104);
  87
  88         si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
  89                        S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
  90                        S_00B128_SGPRS((num_sgprs - 1) / 8));
  91         si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
  92                        S_00B12C_USER_SGPR(num_user_sgprs));
  93
  94         si_pm4_bind_state(rctx, vs, shader->pm4);
  95 }
  96
  97 static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
  98 {
  99         struct r600_context *rctx = (struct r600_context *)ctx;
 100         struct si_pm4_state *pm4;
 101         unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
 102         unsigned num_sgprs, num_user_sgprs;
 103         int ninterp = 0;
 104         boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
 105         unsigned spi_baryc_cntl;
 106         uint64_t va;
 107
 108         if (si_pipe_shader_create(ctx, shader))
 109                 return;
 110
 111         si_pm4_delete_state(rctx, ps, shader->pm4);
 112         pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
 113
 114         si_pm4_inval_shader_cache(pm4);
 115
 116         db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
 117         for (i = 0; i < shader->shader.ninput; i++) {
 118                 ninterp++;
 119                 /* XXX: Flat shading hangs the GPU */
 120                 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
 121                     (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
 122                      rctx->queued.named.rasterizer->flatshade))
 123                         have_linear = TRUE;
 124                 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
 125                         have_linear = TRUE;
 126                 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
 127                         have_perspective = TRUE;
 128                 if (shader->shader.input[i].centroid)
 129                         have_centroid = TRUE;
 130         }
 131
 132         for (i = 0; i < shader->shader.noutput; i++) {
 133                 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
 134                         db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
 135                 if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
 136                         db_shader_control |= 0; // XXX OP_VAL or TEST_VAL?
 137         }
 138         if (shader->shader.uses_kill)
 139                 db_shader_control |= S_02880C_KILL_ENABLE(1);
 140
 141         exports_ps = 0;
 142         num_cout = 0;
 143         for (i = 0; i < shader->shader.noutput; i++) {
 144                 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
 145                     shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
 146                         exports_ps |= 1;
 147                 else if (shader->shader.output[i].name == TGSI_SEMANTIC_COLOR) {
 148                         if (shader->shader.fs_write_all)
 149                                 num_cout = shader->shader.nr_cbufs;
 150                         else
 151                                 num_cout++;
 152                 }
 153         }
 154         if (!exports_ps) {
 155                 /* always at least export 1 component per pixel */
 156                 exports_ps = 2;
 157         }
 158
 159         spi_ps_in_control = S_0286D8_NUM_INTERP(ninterp);
 160
 161         spi_baryc_cntl = 0;
 162         if (have_perspective)
 163                 spi_baryc_cntl |= have_centroid ?
 164                         S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1);
 165         if (have_linear)
 166                 spi_baryc_cntl |= have_centroid ?
 167                         S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1);
 168
 169         si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
 170         si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, shader->spi_ps_input_ena);
 171         si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, shader->spi_ps_input_ena);
 172         si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
 173
 174         /* XXX: Depends on Z buffer format? */
 175         si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, 0);
 176
 177         /* XXX: Depends on color buffer format? */
 178         si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
 179                        S_028714_COL0_EXPORT_FORMAT(V_028714_SPI_SHADER_32_ABGR));
 180
 181         va = r600_resource_va(ctx->screen, (void *)shader->bo);
 182         si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
 183         si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
 184         si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
 185
 186         num_user_sgprs = 6;
 187         num_sgprs = shader->num_sgprs;
 188         if (num_user_sgprs > num_sgprs)
 189                 num_sgprs = num_user_sgprs;
 190         /* Last 2 reserved SGPRs are used for VCC */
 191         num_sgprs += 2;
 192         assert(num_sgprs <= 104);
 193
 194         si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
 195                        S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
 196                        S_00B028_SGPRS((num_sgprs - 1) / 8));
 197         si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
 198                        S_00B02C_USER_SGPR(num_user_sgprs));
 199
 200         si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
 201
 202         shader->sprite_coord_enable = rctx->sprite_coord_enable;
 203         si_pm4_bind_state(rctx, ps, shader->pm4);
 204 }
 205
 206 /*
 207  * Drawing
 208  */
 209
 210 static unsigned si_conv_pipe_prim(unsigned pprim)
 211 {
 212         static const unsigned prim_conv[] = {
 213                 [PIPE_PRIM_POINTS]                      = V_008958_DI_PT_POINTLIST,
 214                 [PIPE_PRIM_LINES]                       = V_008958_DI_PT_LINELIST,
 215                 [PIPE_PRIM_LINE_LOOP]                   = V_008958_DI_PT_LINELOOP,
 216                 [PIPE_PRIM_LINE_STRIP]                  = V_008958_DI_PT_LINESTRIP,
 217                 [PIPE_PRIM_TRIANGLES]                   = V_008958_DI_PT_TRILIST,
 218                 [PIPE_PRIM_TRIANGLE_STRIP]              = V_008958_DI_PT_TRISTRIP,
 219                 [PIPE_PRIM_TRIANGLE_FAN]                = V_008958_DI_PT_TRIFAN,
 220                 [PIPE_PRIM_QUADS]                       = V_008958_DI_PT_QUADLIST,
 221                 [PIPE_PRIM_QUAD_STRIP]                  = V_008958_DI_PT_QUADSTRIP,
 222                 [PIPE_PRIM_POLYGON]                     = V_008958_DI_PT_POLYGON,
 223                 [PIPE_PRIM_LINES_ADJACENCY]             = ~0,
 224                 [PIPE_PRIM_LINE_STRIP_ADJACENCY]        = ~0,
 225                 [PIPE_PRIM_TRIANGLES_ADJACENCY]         = ~0,
 226                 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY]    = ~0
 227         };
 228         unsigned result = prim_conv[pprim];
 229         if (result == ~0) {
 230                 R600_ERR("unsupported primitive type %d\n", pprim);
 231         }
 232         return result;
 233 }
 234
 235 static bool si_update_draw_info_state(struct r600_context *rctx,
 236                                const struct pipe_draw_info *info)
 237 {
 238         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
 239         unsigned prim = si_conv_pipe_prim(info->mode);
 240         unsigned ls_mask = 0;
 241
 242         if (pm4 == NULL)
 243                 return false;
 244
 245         if (prim == ~0) {
 246                 FREE(pm4);
 247                 return false;
 248         }
 249
 250         si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
 251         si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
 252         si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
 253         si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, info->index_bias);
 254         si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
 255         si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
 256 #if 0
 257         si_pm4_set_reg(pm4, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
 258         si_pm4_set_reg(pm4, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance);
 259 #endif
 260
 261         if (prim == V_008958_DI_PT_LINELIST)
 262                 ls_mask = 1;
 263         else if (prim == V_008958_DI_PT_LINESTRIP)
 264                 ls_mask = 2;
 265         si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
 266                        S_028A0C_AUTO_RESET_CNTL(ls_mask) |
 267                        rctx->pa_sc_line_stipple);
 268
 269         if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
 270                 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
 271                                S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
 272         } else {
 273                 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
 274         }
 275         si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
 276                        prim == PIPE_PRIM_POINTS ? rctx->pa_cl_vs_out_cntl : 0
 277                        /*| (rctx->rasterizer->clip_plane_enable &
 278                        rctx->vs_shader->shader.clip_dist_write)*/);
 279         si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL, rctx->pa_cl_clip_cntl
 280                         /*| (rctx->vs_shader->shader.clip_dist_write ||
 281                         rctx->vs_shader->shader.vs_prohibit_ucps ?
 282                         0 : rctx->rasterizer->clip_plane_enable & 0x3F)*/);
 283
 284         si_pm4_set_state(rctx, draw_info, pm4);
 285         return true;
 286 }
 287
 288 static void si_update_alpha_ref(struct r600_context *rctx)
 289 {
 290 #if 0
 291         unsigned alpha_ref;
 292         struct r600_pipe_state rstate;
 293
 294         alpha_ref = rctx->alpha_ref;
 295         rstate.nregs = 0;
 296         if (rctx->export_16bpc)
 297                 alpha_ref &= ~0x1FFF;
 298         si_pm4_set_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref);
 299
 300         si_pm4_set_state(rctx, TODO, pm4);
 301         rctx->alpha_ref_dirty = false;
 302 #endif
 303 }
 304
 305 static void si_update_spi_map(struct r600_context *rctx)
 306 {
 307         struct si_shader *ps = &rctx->ps_shader->shader;
 308         struct si_shader *vs = &rctx->vs_shader->shader;
 309         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
 310         unsigned i, j, tmp;
 311
 312         for (i = 0; i < ps->ninput; i++) {
 313                 tmp = 0;
 314
 315 #if 0
 316                 /* XXX: Flat shading hangs the GPU */
 317                 if (ps->input[i].name == TGSI_SEMANTIC_POSITION ||
 318                     ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
 319                     (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
 320                      rctx->rasterizer && rctx->rasterizer->flatshade)) {
 321                         tmp |= S_028644_FLAT_SHADE(1);
 322                 }
 323 #endif
 324
 325                 if (ps->input[i].name == TGSI_SEMANTIC_GENERIC &&
 326                     rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
 327                         tmp |= S_028644_PT_SPRITE_TEX(1);
 328                 }
 329
 330                 for (j = 0; j < vs->noutput; j++) {
 331                         if (ps->input[i].name == vs->output[j].name &&
 332                             ps->input[i].sid == vs->output[j].sid) {
 333                                 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
 334                                 break;
 335                         }
 336                 }
 337
 338                 if (j == vs->noutput) {
 339                         /* No corresponding output found, load defaults into input */
 340                         tmp |= S_028644_OFFSET(0x20);
 341                 }
 342
 343                 si_pm4_set_reg(pm4, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp);
 344         }
 345
 346         si_pm4_set_state(rctx, spi, pm4);
 347 }
 348
 349 static void si_update_derived_state(struct r600_context *rctx)
 350 {
 351         struct pipe_context * ctx = (struct pipe_context*)rctx;
 352
 353         if (!rctx->blitter->running) {
 354                 if (rctx->have_depth_fb || rctx->have_depth_texture)
 355                         r600_flush_depth_textures(rctx);
 356         }
 357
 358         if ((rctx->ps_shader->shader.fs_write_all &&
 359              (rctx->ps_shader->shader.nr_cbufs != rctx->framebuffer.nr_cbufs)) ||
 360             (rctx->sprite_coord_enable &&
 361              (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable))) {
 362                 si_pipe_shader_destroy(&rctx->context, rctx->ps_shader);
 363         }
 364
 365         if (rctx->alpha_ref_dirty) {
 366                 si_update_alpha_ref(rctx);
 367         }
 368
 369         if (!rctx->vs_shader->bo) {
 370                 si_pipe_shader_vs(ctx, rctx->vs_shader);
 371         }
 372
 373         if (!rctx->ps_shader->bo) {
 374                 si_pipe_shader_ps(ctx, rctx->ps_shader);
 375         }
 376
 377         if (rctx->shader_dirty) {
 378                 si_update_spi_map(rctx);
 379                 rctx->shader_dirty = false;
 380         }
 381 }
 382
 383 static void si_vertex_buffer_update(struct r600_context *rctx)
 384 {
 385         struct pipe_context *ctx = &rctx->context;
 386         struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
 387         bool bound[PIPE_MAX_ATTRIBS] = {};
 388         struct si_resource *t_list_buffer;
 389         unsigned i, count;
 390         uint32_t *ptr;
 391         uint64_t va;
 392
 393         si_pm4_inval_vertex_cache(pm4);
 394
 395         /* bind vertex buffer once */
 396         count = rctx->vertex_elements->count;
 397         assert(count <= 256 / 4);
 398
 399         t_list_buffer = si_resource_create_custom(ctx->screen, PIPE_USAGE_IMMUTABLE,
 400                                                   4 * 4 * count);
 401         if (t_list_buffer == NULL) {
 402                 FREE(pm4);
 403                 return;
 404         }
 405         si_pm4_add_bo(pm4, t_list_buffer, RADEON_USAGE_READ);
 406
 407         ptr = (uint32_t*)rctx->ws->buffer_map(t_list_buffer->cs_buf,
 408                                               rctx->cs,
 409                                               PIPE_TRANSFER_WRITE);
 410
 411         for (i = 0 ; i < count; i++, ptr += 4) {
 412                 struct pipe_vertex_element *ve = &rctx->vertex_elements->elements[i];
 413                 struct pipe_vertex_buffer *vb;
 414                 struct si_resource *rbuffer;
 415                 unsigned offset;
 416
 417                 if (ve->vertex_buffer_index >= rctx->nr_vertex_buffers)
 418                         continue;
 419
 420                 vb = &rctx->vertex_buffer[ve->vertex_buffer_index];
 421                 rbuffer = (struct si_resource*)vb->buffer;
 422                 if (rbuffer == NULL)
 423                         continue;
 424
 425                 offset = 0;
 426                 offset += vb->buffer_offset;
 427                 offset += ve->src_offset;
 428
 429                 va = r600_resource_va(ctx->screen, (void*)rbuffer);
 430                 va += offset;
 431
 432                 /* Fill in T# buffer resource description */
 433                 ptr[0] = va & 0xFFFFFFFF;
 434                 ptr[1] = (S_008F04_BASE_ADDRESS_HI(va >> 32) |
 435                           S_008F04_STRIDE(vb->stride));
 436                 if (vb->stride > 0)
 437                         ptr[2] = (vb->buffer->width0 - offset) / vb->stride;
 438                 else
 439                         ptr[2] = vb->buffer->width0 - offset;
 440                 ptr[3] = rctx->vertex_elements->rsrc_word3[i];
 441
 442                 if (!bound[ve->vertex_buffer_index]) {
 443                         si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
 444                         bound[ve->vertex_buffer_index] = true;
 445                 }
 446         }
 447
 448         va = r600_resource_va(ctx->screen, (void*)t_list_buffer);
 449         si_pm4_set_reg(pm4, R_00B148_SPI_SHADER_USER_DATA_VS_6, va);
 450         si_pm4_set_reg(pm4, R_00B14C_SPI_SHADER_USER_DATA_VS_7, va >> 32);
 451         si_pm4_set_state(rctx, vertex_buffers, pm4);
 452 }
 453
 454 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 455 {
 456         struct r600_context *rctx = (struct r600_context *)ctx;
 457         struct si_state_dsa *dsa = rctx->queued.named.dsa;
 458         struct pipe_draw_info info = *dinfo;
 459         struct r600_draw rdraw = {};
 460         struct pipe_index_buffer ib = {};
 461         struct r600_atom *state = NULL, *next_state = NULL;
 462
 463         if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
 464             (info.indexed && !rctx->index_buffer.buffer)) {
 465                 return;
 466         }
 467
 468         if (!rctx->ps_shader || !rctx->vs_shader)
 469                 return;
 470
 471         si_update_derived_state(rctx);
 472         si_vertex_buffer_update(rctx);
 473
 474         rdraw.vgt_num_indices = info.count;
 475         rdraw.vgt_num_instances = info.instance_count;
 476
 477         if (info.indexed) {
 478                 /* Initialize the index buffer struct. */
 479                 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
 480                 ib.index_size = rctx->index_buffer.index_size;
 481                 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
 482
 483                 /* Translate or upload, if needed. */
 484                 r600_translate_index_buffer(rctx, &ib, info.count);
 485
 486                 if (ib.user_buffer) {
 487                         r600_upload_index_buffer(rctx, &ib, info.count);
 488                 }
 489
 490                 /* Initialize the r600_draw struct with index buffer info. */
 491                 if (ib.index_size == 4) {
 492                         rdraw.vgt_index_type = V_028A7C_VGT_INDEX_32 |
 493                                 (R600_BIG_ENDIAN ? V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
 494                 } else {
 495                         rdraw.vgt_index_type = V_028A7C_VGT_INDEX_16 |
 496                                 (R600_BIG_ENDIAN ? V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
 497                 }
 498                 rdraw.indices = (struct si_resource*)ib.buffer;
 499                 rdraw.indices_bo_offset = ib.offset;
 500                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA;
 501         } else {
 502                 info.index_bias = info.start;
 503                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
 504                 if (info.count_from_stream_output) {
 505                         rdraw.vgt_draw_initiator |= S_0287F0_USE_OPAQUE(1);
 506
 507                         r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
 508                 }
 509         }
 510
 511         rctx->vs_shader_so_strides = rctx->vs_shader->so_strides;
 512
 513         if (!si_update_draw_info_state(rctx, &info))
 514                 return;
 515
 516         rdraw.db_render_override = dsa->db_render_override;
 517         rdraw.db_render_control = dsa->db_render_control;
 518
 519         /* Emit states. */
 520         rctx->pm4_dirty_cdwords += si_pm4_dirty_dw(rctx);
 521
 522         r600_need_cs_space(rctx, 0, TRUE);
 523
 524         LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
 525                 r600_emit_atom(rctx, state);
 526         }
 527         si_pm4_emit_dirty(rctx);
 528         rctx->pm4_dirty_cdwords = 0;
 529
 530         /* Enable stream out if needed. */
 531         if (rctx->streamout_start) {
 532                 r600_context_streamout_begin(rctx);
 533                 rctx->streamout_start = FALSE;
 534         }
 535
 536         si_context_draw(rctx, &rdraw);
 537
 538         rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
 539
 540         if (rctx->framebuffer.zsbuf)
 541         {
 542                 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
 543                 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
 544         }
 545
 546         pipe_resource_reference(&ib.buffer, NULL);
 547 }