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radeonsi: skip draw calls with 0-sized index buffers
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32 #include "util/u_suballoc.h"
33
34 #include "ac_debug.h"
35
36 /* special primitive types */
37 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
38
39 static unsigned si_conv_pipe_prim(unsigned mode)
40 {
41 static const unsigned prim_conv[] = {
42 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
43 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
44 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
45 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
46 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
47 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
48 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
49 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
50 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
51 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
52 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
53 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
54 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
55 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
56 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
57 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
58 };
59 assert(mode < ARRAY_SIZE(prim_conv));
60 return prim_conv[mode];
61 }
62
63 /**
64 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
65 * LS.LDS_SIZE is shared by all 3 shader stages.
66 *
67 * The information about LDS and other non-compile-time parameters is then
68 * written to userdata SGPRs.
69 */
70 static void si_emit_derived_tess_state(struct si_context *sctx,
71 const struct pipe_draw_info *info,
72 unsigned *num_patches)
73 {
74 struct radeon_cmdbuf *cs = sctx->gfx_cs;
75 struct si_shader *ls_current;
76 struct si_shader_selector *ls;
77 /* The TES pointer will only be used for sctx->last_tcs.
78 * It would be wrong to think that TCS = TES. */
79 struct si_shader_selector *tcs =
80 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
81 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
82 bool has_primid_instancing_bug = sctx->chip_class == GFX6 &&
83 sctx->screen->info.max_se == 1;
84 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
85 unsigned num_tcs_input_cp = info->vertices_per_patch;
86 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
87 unsigned num_tcs_patch_outputs;
88 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
89 unsigned input_patch_size, output_patch_size, output_patch0_offset;
90 unsigned perpatch_output_offset, lds_size;
91 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
92 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
93
94 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
95 if (sctx->chip_class >= GFX9) {
96 if (sctx->tcs_shader.cso)
97 ls_current = sctx->tcs_shader.current;
98 else
99 ls_current = sctx->fixed_func_tcs_shader.current;
100
101 ls = ls_current->key.part.tcs.ls;
102 } else {
103 ls_current = sctx->vs_shader.current;
104 ls = sctx->vs_shader.cso;
105 }
106
107 if (sctx->last_ls == ls_current &&
108 sctx->last_tcs == tcs &&
109 sctx->last_tes_sh_base == tes_sh_base &&
110 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
111 (!has_primid_instancing_bug ||
112 (sctx->last_tess_uses_primid == tess_uses_primid))) {
113 *num_patches = sctx->last_num_patches;
114 return;
115 }
116
117 sctx->last_ls = ls_current;
118 sctx->last_tcs = tcs;
119 sctx->last_tes_sh_base = tes_sh_base;
120 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
121 sctx->last_tess_uses_primid = tess_uses_primid;
122
123 /* This calculates how shader inputs and outputs among VS, TCS, and TES
124 * are laid out in LDS. */
125 num_tcs_inputs = util_last_bit64(ls->outputs_written);
126
127 if (sctx->tcs_shader.cso) {
128 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
129 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
130 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
131 } else {
132 /* No TCS. Route varyings from LS to TES. */
133 num_tcs_outputs = num_tcs_inputs;
134 num_tcs_output_cp = num_tcs_input_cp;
135 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
136 }
137
138 input_vertex_size = ls->lshs_vertex_stride;
139 output_vertex_size = num_tcs_outputs * 16;
140
141 input_patch_size = num_tcs_input_cp * input_vertex_size;
142
143 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
144 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
145
146 /* Ensure that we only need one wave per SIMD so we don't need to check
147 * resource usage. Also ensures that the number of tcs in and out
148 * vertices per threadgroup are at most 256.
149 */
150 unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
151 *num_patches = 256 / max_verts_per_patch;
152
153 /* Make sure that the data fits in LDS. This assumes the shaders only
154 * use LDS for the inputs and outputs.
155 *
156 * While GFX7 can use 64K per threadgroup, there is a hang on Stoney
157 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
158 * uses 32K at most on all GCN chips.
159 */
160 hardware_lds_size = 32768;
161 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
162 output_patch_size));
163
164 /* Make sure the output data fits in the offchip buffer */
165 *num_patches = MIN2(*num_patches,
166 (sctx->screen->tess_offchip_block_dw_size * 4) /
167 output_patch_size);
168
169 /* Not necessary for correctness, but improves performance.
170 * The hardware can do more, but the radeonsi shader constant is
171 * limited to 6 bits.
172 */
173 *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */
174
175 /* When distributed tessellation is unsupported, switch between SEs
176 * at a higher frequency to compensate for it.
177 */
178 if (!sctx->screen->has_distributed_tess && sctx->screen->info.max_se > 1)
179 *num_patches = MIN2(*num_patches, 16); /* recommended */
180
181 /* Make sure that vector lanes are reasonably occupied. It probably
182 * doesn't matter much because this is LS-HS, and TES is likely to
183 * occupy significantly more CUs.
184 */
185 unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
186 unsigned wave_size = sctx->screen->ge_wave_size;
187
188 if (temp_verts_per_tg > wave_size && temp_verts_per_tg % wave_size < wave_size*3/4)
189 *num_patches = (temp_verts_per_tg & ~(wave_size - 1)) / max_verts_per_patch;
190
191 if (sctx->chip_class == GFX6) {
192 /* GFX6 bug workaround, related to power management. Limit LS-HS
193 * threadgroups to only one wave.
194 */
195 unsigned one_wave = wave_size / max_verts_per_patch;
196 *num_patches = MIN2(*num_patches, one_wave);
197 }
198
199 /* The VGT HS block increments the patch ID unconditionally
200 * within a single threadgroup. This results in incorrect
201 * patch IDs when instanced draws are used.
202 *
203 * The intended solution is to restrict threadgroups to
204 * a single instance by setting SWITCH_ON_EOI, which
205 * should cause IA to split instances up. However, this
206 * doesn't work correctly on GFX6 when there is no other
207 * SE to switch to.
208 */
209 if (has_primid_instancing_bug && tess_uses_primid)
210 *num_patches = 1;
211
212 sctx->last_num_patches = *num_patches;
213
214 output_patch0_offset = input_patch_size * *num_patches;
215 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
216
217 /* Compute userdata SGPRs. */
218 assert(((input_vertex_size / 4) & ~0xff) == 0);
219 assert(((output_vertex_size / 4) & ~0xff) == 0);
220 assert(((input_patch_size / 4) & ~0x1fff) == 0);
221 assert(((output_patch_size / 4) & ~0x1fff) == 0);
222 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
223 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
224 assert(num_tcs_input_cp <= 32);
225 assert(num_tcs_output_cp <= 32);
226
227 uint64_t ring_va = si_resource(sctx->tess_rings)->gpu_address;
228 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
229
230 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
231 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
232 tcs_out_layout = (output_patch_size / 4) |
233 (num_tcs_input_cp << 13) |
234 ring_va;
235 tcs_out_offsets = (output_patch0_offset / 16) |
236 ((perpatch_output_offset / 16) << 16);
237 offchip_layout = *num_patches |
238 (num_tcs_output_cp << 6) |
239 (pervertex_output_patch_size * *num_patches << 12);
240
241 /* Compute the LDS size. */
242 lds_size = output_patch0_offset + output_patch_size * *num_patches;
243
244 if (sctx->chip_class >= GFX7) {
245 assert(lds_size <= 65536);
246 lds_size = align(lds_size, 512) / 512;
247 } else {
248 assert(lds_size <= 32768);
249 lds_size = align(lds_size, 256) / 256;
250 }
251
252 /* Set SI_SGPR_VS_STATE_BITS. */
253 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
254 C_VS_STATE_LS_OUT_VERTEX_SIZE;
255 sctx->current_vs_state |= tcs_in_layout;
256
257 /* We should be able to support in-shader LDS use with LLVM >= 9
258 * by just adding the lds_sizes together, but it has never
259 * been tested. */
260 assert(ls_current->config.lds_size == 0);
261
262 if (sctx->chip_class >= GFX9) {
263 unsigned hs_rsrc2 = ls_current->config.rsrc2;
264
265 if (sctx->chip_class >= GFX10)
266 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(lds_size);
267 else
268 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(lds_size);
269
270 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
271
272 /* Set userdata SGPRs for merged LS-HS. */
273 radeon_set_sh_reg_seq(cs,
274 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
275 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
276 radeon_emit(cs, offchip_layout);
277 radeon_emit(cs, tcs_out_offsets);
278 radeon_emit(cs, tcs_out_layout);
279 } else {
280 unsigned ls_rsrc2 = ls_current->config.rsrc2;
281
282 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
283 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
284
285 /* Due to a hw bug, RSRC2_LS must be written twice with another
286 * LS register written in between. */
287 if (sctx->chip_class == GFX7 && sctx->family != CHIP_HAWAII)
288 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
289 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
290 radeon_emit(cs, ls_current->config.rsrc1);
291 radeon_emit(cs, ls_rsrc2);
292
293 /* Set userdata SGPRs for TCS. */
294 radeon_set_sh_reg_seq(cs,
295 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
296 radeon_emit(cs, offchip_layout);
297 radeon_emit(cs, tcs_out_offsets);
298 radeon_emit(cs, tcs_out_layout);
299 radeon_emit(cs, tcs_in_layout);
300 }
301
302 /* Set userdata SGPRs for TES. */
303 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
304 radeon_emit(cs, offchip_layout);
305 radeon_emit(cs, ring_va);
306
307 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
308 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
309 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
310
311 if (sctx->last_ls_hs_config != ls_hs_config) {
312 if (sctx->chip_class >= GFX7) {
313 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
314 ls_hs_config);
315 } else {
316 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
317 ls_hs_config);
318 }
319 sctx->last_ls_hs_config = ls_hs_config;
320 sctx->context_roll = true;
321 }
322 }
323
324 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info,
325 enum pipe_prim_type prim)
326 {
327 switch (prim) {
328 case PIPE_PRIM_PATCHES:
329 return info->count / info->vertices_per_patch;
330 case PIPE_PRIM_POLYGON:
331 return info->count >= 3;
332 case SI_PRIM_RECTANGLE_LIST:
333 return info->count / 3;
334 default:
335 return u_decomposed_prims_for_vertices(prim, info->count);
336 }
337 }
338
339 static unsigned
340 si_get_init_multi_vgt_param(struct si_screen *sscreen,
341 union si_vgt_param_key *key)
342 {
343 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
344 unsigned max_primgroup_in_wave = 2;
345
346 /* SWITCH_ON_EOP(0) is always preferable. */
347 bool wd_switch_on_eop = false;
348 bool ia_switch_on_eop = false;
349 bool ia_switch_on_eoi = false;
350 bool partial_vs_wave = false;
351 bool partial_es_wave = false;
352
353 if (key->u.uses_tess) {
354 /* SWITCH_ON_EOI must be set if PrimID is used. */
355 if (key->u.tess_uses_prim_id)
356 ia_switch_on_eoi = true;
357
358 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
359 if ((sscreen->info.family == CHIP_TAHITI ||
360 sscreen->info.family == CHIP_PITCAIRN ||
361 sscreen->info.family == CHIP_BONAIRE) &&
362 key->u.uses_gs)
363 partial_vs_wave = true;
364
365 /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
366 if (sscreen->has_distributed_tess) {
367 if (key->u.uses_gs) {
368 if (sscreen->info.chip_class == GFX8)
369 partial_es_wave = true;
370 } else {
371 partial_vs_wave = true;
372 }
373 }
374 }
375
376 /* This is a hardware requirement. */
377 if (key->u.line_stipple_enabled ||
378 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
379 ia_switch_on_eop = true;
380 wd_switch_on_eop = true;
381 }
382
383 if (sscreen->info.chip_class >= GFX7) {
384 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
385 * 4 shader engines. Set 1 to pass the assertion below.
386 * The other cases are hardware requirements.
387 *
388 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
389 * for points, line strips, and tri strips.
390 */
391 if (sscreen->info.max_se <= 2 ||
392 key->u.prim == PIPE_PRIM_POLYGON ||
393 key->u.prim == PIPE_PRIM_LINE_LOOP ||
394 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
395 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
396 (key->u.primitive_restart &&
397 (sscreen->info.family < CHIP_POLARIS10 ||
398 (key->u.prim != PIPE_PRIM_POINTS &&
399 key->u.prim != PIPE_PRIM_LINE_STRIP &&
400 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
401 key->u.count_from_stream_output)
402 wd_switch_on_eop = true;
403
404 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
405 * We don't know that for indirect drawing, so treat it as
406 * always problematic. */
407 if (sscreen->info.family == CHIP_HAWAII &&
408 key->u.uses_instancing)
409 wd_switch_on_eop = true;
410
411 /* Performance recommendation for 4 SE Gfx7-8 parts if
412 * instances are smaller than a primgroup.
413 * Assume indirect draws always use small instances.
414 * This is needed for good VS wave utilization.
415 */
416 if (sscreen->info.chip_class <= GFX8 &&
417 sscreen->info.max_se == 4 &&
418 key->u.multi_instances_smaller_than_primgroup)
419 wd_switch_on_eop = true;
420
421 /* Required on GFX7 and later. */
422 if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
423 ia_switch_on_eoi = true;
424
425 /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
426 * to work around a GS hang.
427 */
428 if (key->u.uses_gs &&
429 (sscreen->info.family == CHIP_TONGA ||
430 sscreen->info.family == CHIP_FIJI ||
431 sscreen->info.family == CHIP_POLARIS10 ||
432 sscreen->info.family == CHIP_POLARIS11 ||
433 sscreen->info.family == CHIP_POLARIS12 ||
434 sscreen->info.family == CHIP_VEGAM))
435 partial_vs_wave = true;
436
437 /* Required by Hawaii and, for some special cases, by GFX8. */
438 if (ia_switch_on_eoi &&
439 (sscreen->info.family == CHIP_HAWAII ||
440 (sscreen->info.chip_class == GFX8 &&
441 (key->u.uses_gs || max_primgroup_in_wave != 2))))
442 partial_vs_wave = true;
443
444 /* Instancing bug on Bonaire. */
445 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
446 key->u.uses_instancing)
447 partial_vs_wave = true;
448
449 /* This only applies to Polaris10 and later 4 SE chips.
450 * wd_switch_on_eop is already true on all other chips.
451 */
452 if (!wd_switch_on_eop && key->u.primitive_restart)
453 partial_vs_wave = true;
454
455 /* If the WD switch is false, the IA switch must be false too. */
456 assert(wd_switch_on_eop || !ia_switch_on_eop);
457 }
458
459 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
460 if (sscreen->info.chip_class <= GFX8 && ia_switch_on_eoi)
461 partial_es_wave = true;
462
463 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
464 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
465 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
466 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
467 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= GFX7 ? wd_switch_on_eop : 0) |
468 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
469 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == GFX8 ?
470 max_primgroup_in_wave : 0) |
471 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
472 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
473 }
474
475 static void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
476 {
477 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
478 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
479 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
480 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
481 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
482 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
483 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
484 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
485 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
486 union si_vgt_param_key key;
487
488 key.index = 0;
489 key.u.prim = prim;
490 key.u.uses_instancing = uses_instancing;
491 key.u.multi_instances_smaller_than_primgroup = multi_instances;
492 key.u.primitive_restart = primitive_restart;
493 key.u.count_from_stream_output = count_from_so;
494 key.u.line_stipple_enabled = line_stipple;
495 key.u.uses_tess = uses_tess;
496 key.u.tess_uses_prim_id = tess_uses_primid;
497 key.u.uses_gs = uses_gs;
498
499 sctx->ia_multi_vgt_param[key.index] =
500 si_get_init_multi_vgt_param(sctx->screen, &key);
501 }
502 }
503
504 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
505 const struct pipe_draw_info *info,
506 enum pipe_prim_type prim,
507 unsigned num_patches,
508 unsigned instance_count,
509 bool primitive_restart)
510 {
511 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
512 unsigned primgroup_size;
513 unsigned ia_multi_vgt_param;
514
515 if (sctx->tes_shader.cso) {
516 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
517 } else if (sctx->gs_shader.cso) {
518 primgroup_size = 64; /* recommended with a GS */
519 } else {
520 primgroup_size = 128; /* recommended without a GS and tess */
521 }
522
523 key.u.prim = prim;
524 key.u.uses_instancing = info->indirect || instance_count > 1;
525 key.u.multi_instances_smaller_than_primgroup =
526 info->indirect ||
527 (instance_count > 1 &&
528 (info->count_from_stream_output ||
529 si_num_prims_for_vertices(info, prim) < primgroup_size));
530 key.u.primitive_restart = primitive_restart;
531 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
532
533 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
534 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
535
536 if (sctx->gs_shader.cso) {
537 /* GS requirement. */
538 if (sctx->chip_class <= GFX8 &&
539 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
540 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
541
542 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
543 * The hw doc says all multi-SE chips are affected, but Vulkan
544 * only applies it to Hawaii. Do what Vulkan does.
545 */
546 if (sctx->family == CHIP_HAWAII &&
547 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
548 (info->indirect ||
549 (instance_count > 1 &&
550 (info->count_from_stream_output ||
551 si_num_prims_for_vertices(info, prim) <= 1))))
552 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
553 }
554
555 return ia_multi_vgt_param;
556 }
557
558 static unsigned si_conv_prim_to_gs_out(unsigned mode)
559 {
560 static const int prim_conv[] = {
561 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
562 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
563 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
564 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
565 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
566 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
567 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
568 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
569 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
570 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
571 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
572 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
573 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
574 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
575 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
576 [SI_PRIM_RECTANGLE_LIST] = V_028A6C_VGT_OUT_RECT_V0,
577 };
578 assert(mode < ARRAY_SIZE(prim_conv));
579
580 return prim_conv[mode];
581 }
582
583 /* rast_prim is the primitive type after GS. */
584 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
585 {
586 struct radeon_cmdbuf *cs = sctx->gfx_cs;
587 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
588 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
589
590 if (likely(rast_prim == sctx->last_rast_prim &&
591 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple &&
592 (sctx->chip_class <= GFX9 ||
593 rs->flatshade_first == sctx->last_flatshade_first)))
594 return;
595
596 if (util_prim_is_lines(rast_prim)) {
597 /* For lines, reset the stipple pattern at each primitive. Otherwise,
598 * reset the stipple pattern at each packet (line strips, line loops).
599 */
600 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
601 rs->pa_sc_line_stipple |
602 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
603 sctx->context_roll = true;
604 }
605
606 unsigned gs_out = si_conv_prim_to_gs_out(sctx->current_rast_prim);
607
608 if (rast_prim != sctx->last_rast_prim &&
609 (sctx->ngg || sctx->gs_shader.cso)) {
610 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
611 sctx->context_roll = true;
612
613 if (sctx->chip_class >= GFX10) {
614 sctx->current_vs_state &= C_VS_STATE_OUTPRIM;
615 sctx->current_vs_state |= S_VS_STATE_OUTPRIM(gs_out);
616 }
617 }
618
619 if (sctx->chip_class >= GFX10) {
620 unsigned vtx_index = rs->flatshade_first ? 0 : gs_out;
621 sctx->current_vs_state &= C_VS_STATE_PROVOKING_VTX_INDEX;
622 sctx->current_vs_state |= S_VS_STATE_PROVOKING_VTX_INDEX(vtx_index);
623 }
624
625 sctx->last_rast_prim = rast_prim;
626 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
627 sctx->last_flatshade_first = rs->flatshade_first;
628 }
629
630 static void si_emit_vs_state(struct si_context *sctx,
631 const struct pipe_draw_info *info)
632 {
633 sctx->current_vs_state &= C_VS_STATE_INDEXED;
634 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
635
636 if (sctx->num_vs_blit_sgprs) {
637 /* Re-emit the state after we leave u_blitter. */
638 sctx->last_vs_state = ~0;
639 return;
640 }
641
642 if (sctx->current_vs_state != sctx->last_vs_state) {
643 struct radeon_cmdbuf *cs = sctx->gfx_cs;
644
645 /* For the API vertex shader (VS_STATE_INDEXED, LS_OUT_*). */
646 radeon_set_sh_reg(cs,
647 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
648 SI_SGPR_VS_STATE_BITS * 4,
649 sctx->current_vs_state);
650
651 /* Set CLAMP_VERTEX_COLOR and OUTPRIM in the last stage
652 * before the rasterizer.
653 *
654 * For TES or the GS copy shader without NGG:
655 */
656 if (sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] !=
657 R_00B130_SPI_SHADER_USER_DATA_VS_0) {
658 radeon_set_sh_reg(cs,
659 R_00B130_SPI_SHADER_USER_DATA_VS_0 +
660 SI_SGPR_VS_STATE_BITS * 4,
661 sctx->current_vs_state);
662 }
663
664 /* For NGG: */
665 if (sctx->chip_class >= GFX10 &&
666 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] !=
667 R_00B230_SPI_SHADER_USER_DATA_GS_0) {
668 radeon_set_sh_reg(cs,
669 R_00B230_SPI_SHADER_USER_DATA_GS_0 +
670 SI_SGPR_VS_STATE_BITS * 4,
671 sctx->current_vs_state);
672 }
673
674 sctx->last_vs_state = sctx->current_vs_state;
675 }
676 }
677
678 static inline bool si_prim_restart_index_changed(struct si_context *sctx,
679 bool primitive_restart,
680 unsigned restart_index)
681 {
682 return primitive_restart &&
683 (restart_index != sctx->last_restart_index ||
684 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
685 }
686
687 static void si_emit_ia_multi_vgt_param(struct si_context *sctx,
688 const struct pipe_draw_info *info,
689 enum pipe_prim_type prim,
690 unsigned num_patches,
691 unsigned instance_count,
692 bool primitive_restart)
693 {
694 struct radeon_cmdbuf *cs = sctx->gfx_cs;
695 unsigned ia_multi_vgt_param;
696
697 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, prim, num_patches,
698 instance_count, primitive_restart);
699
700 /* Draw state. */
701 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
702 if (sctx->chip_class == GFX9)
703 radeon_set_uconfig_reg_idx(cs, sctx->screen,
704 R_030960_IA_MULTI_VGT_PARAM, 4,
705 ia_multi_vgt_param);
706 else if (sctx->chip_class >= GFX7)
707 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
708 else
709 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
710
711 sctx->last_multi_vgt_param = ia_multi_vgt_param;
712 }
713 }
714
715 /* GFX10 removed IA_MULTI_VGT_PARAM in exchange for GE_CNTL.
716 * We overload last_multi_vgt_param.
717 */
718 static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches)
719 {
720 unsigned ge_cntl;
721
722 if (sctx->ngg) {
723 ge_cntl = si_get_vs_state(sctx)->ge_cntl |
724 S_03096C_PACKET_TO_ONE_PA(sctx->ia_multi_vgt_param_key.u.line_stipple_enabled);
725 } else {
726 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
727 unsigned primgroup_size;
728 unsigned vertgroup_size;
729
730 if (sctx->tes_shader.cso) {
731 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
732 vertgroup_size = 0;
733 } else if (sctx->gs_shader.cso) {
734 unsigned vgt_gs_onchip_cntl = sctx->gs_shader.current->ctx_reg.gs.vgt_gs_onchip_cntl;
735 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
736 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
737 } else {
738 primgroup_size = 128; /* recommended without a GS and tess */
739 vertgroup_size = 0;
740 }
741
742 ge_cntl = S_03096C_PRIM_GRP_SIZE(primgroup_size) |
743 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
744 S_03096C_BREAK_WAVE_AT_EOI(key.u.uses_tess && key.u.tess_uses_prim_id) |
745 S_03096C_PACKET_TO_ONE_PA(key.u.line_stipple_enabled);
746 }
747
748 if (ge_cntl != sctx->last_multi_vgt_param) {
749 radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, ge_cntl);
750 sctx->last_multi_vgt_param = ge_cntl;
751 }
752 }
753
754 static void si_emit_draw_registers(struct si_context *sctx,
755 const struct pipe_draw_info *info,
756 enum pipe_prim_type prim,
757 unsigned num_patches,
758 unsigned instance_count,
759 bool primitive_restart)
760 {
761 struct radeon_cmdbuf *cs = sctx->gfx_cs;
762 unsigned vgt_prim = si_conv_pipe_prim(prim);
763
764 if (sctx->chip_class >= GFX10)
765 gfx10_emit_ge_cntl(sctx, num_patches);
766 else
767 si_emit_ia_multi_vgt_param(sctx, info, prim, num_patches,
768 instance_count, primitive_restart);
769
770 if (vgt_prim != sctx->last_prim) {
771 if (sctx->chip_class >= GFX10)
772 radeon_set_uconfig_reg(cs, R_030908_VGT_PRIMITIVE_TYPE, vgt_prim);
773 else if (sctx->chip_class >= GFX7)
774 radeon_set_uconfig_reg_idx(cs, sctx->screen,
775 R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
776 else
777 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);
778
779 sctx->last_prim = vgt_prim;
780 }
781
782 /* Primitive restart. */
783 if (primitive_restart != sctx->last_primitive_restart_en) {
784 if (sctx->chip_class >= GFX9)
785 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
786 primitive_restart);
787 else
788 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
789 primitive_restart);
790
791 sctx->last_primitive_restart_en = primitive_restart;
792
793 }
794 if (si_prim_restart_index_changed(sctx, primitive_restart, info->restart_index)) {
795 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
796 info->restart_index);
797 sctx->last_restart_index = info->restart_index;
798 sctx->context_roll = true;
799 }
800 }
801
802 static void si_emit_draw_packets(struct si_context *sctx,
803 const struct pipe_draw_info *info,
804 struct pipe_resource *indexbuf,
805 unsigned index_size,
806 unsigned index_offset,
807 unsigned instance_count,
808 bool dispatch_prim_discard_cs,
809 unsigned original_index_size)
810 {
811 struct pipe_draw_indirect_info *indirect = info->indirect;
812 struct radeon_cmdbuf *cs = sctx->gfx_cs;
813 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
814 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
815 uint32_t index_max_size = 0;
816 uint64_t index_va = 0;
817
818 if (info->count_from_stream_output) {
819 struct si_streamout_target *t =
820 (struct si_streamout_target*)info->count_from_stream_output;
821
822 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
823 t->stride_in_dw);
824 si_cp_copy_data(sctx, sctx->gfx_cs,
825 COPY_DATA_REG, NULL,
826 R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2,
827 COPY_DATA_SRC_MEM, t->buf_filled_size,
828 t->buf_filled_size_offset);
829 }
830
831 /* draw packet */
832 if (index_size) {
833 if (index_size != sctx->last_index_size) {
834 unsigned index_type;
835
836 /* index type */
837 switch (index_size) {
838 case 1:
839 index_type = V_028A7C_VGT_INDEX_8;
840 break;
841 case 2:
842 index_type = V_028A7C_VGT_INDEX_16 |
843 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
844 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
845 break;
846 case 4:
847 index_type = V_028A7C_VGT_INDEX_32 |
848 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
849 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
850 break;
851 default:
852 assert(!"unreachable");
853 return;
854 }
855
856 if (sctx->chip_class >= GFX9) {
857 radeon_set_uconfig_reg_idx(cs, sctx->screen,
858 R_03090C_VGT_INDEX_TYPE, 2,
859 index_type);
860 } else {
861 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
862 radeon_emit(cs, index_type);
863 }
864
865 sctx->last_index_size = index_size;
866 }
867
868 if (original_index_size) {
869 index_max_size = (indexbuf->width0 - index_offset) /
870 original_index_size;
871 /* Skip draw calls with 0-sized index buffers.
872 * They cause a hang on some chips, like Navi10-14.
873 */
874 if (!index_max_size)
875 return;
876
877 index_va = si_resource(indexbuf)->gpu_address + index_offset;
878
879 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
880 si_resource(indexbuf),
881 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
882 }
883 } else {
884 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
885 * so the state must be re-emitted before the next indexed draw.
886 */
887 if (sctx->chip_class >= GFX7)
888 sctx->last_index_size = -1;
889 }
890
891 if (indirect) {
892 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address;
893
894 assert(indirect_va % 8 == 0);
895
896 si_invalidate_draw_sh_constants(sctx);
897
898 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
899 radeon_emit(cs, 1);
900 radeon_emit(cs, indirect_va);
901 radeon_emit(cs, indirect_va >> 32);
902
903 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
904 si_resource(indirect->buffer),
905 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
906
907 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
908 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
909
910 assert(indirect->offset % 4 == 0);
911
912 if (index_size) {
913 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
914 radeon_emit(cs, index_va);
915 radeon_emit(cs, index_va >> 32);
916
917 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
918 radeon_emit(cs, index_max_size);
919 }
920
921 if (!sctx->screen->has_draw_indirect_multi) {
922 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
923 : PKT3_DRAW_INDIRECT,
924 3, render_cond_bit));
925 radeon_emit(cs, indirect->offset);
926 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
927 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
928 radeon_emit(cs, di_src_sel);
929 } else {
930 uint64_t count_va = 0;
931
932 if (indirect->indirect_draw_count) {
933 struct si_resource *params_buf =
934 si_resource(indirect->indirect_draw_count);
935
936 radeon_add_to_buffer_list(
937 sctx, sctx->gfx_cs, params_buf,
938 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
939
940 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
941 }
942
943 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
944 PKT3_DRAW_INDIRECT_MULTI,
945 8, render_cond_bit));
946 radeon_emit(cs, indirect->offset);
947 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
948 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
949 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
950 S_2C3_DRAW_INDEX_ENABLE(1) |
951 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
952 radeon_emit(cs, indirect->draw_count);
953 radeon_emit(cs, count_va);
954 radeon_emit(cs, count_va >> 32);
955 radeon_emit(cs, indirect->stride);
956 radeon_emit(cs, di_src_sel);
957 }
958 } else {
959 int base_vertex;
960
961 if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
962 sctx->last_instance_count != instance_count) {
963 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
964 radeon_emit(cs, instance_count);
965 sctx->last_instance_count = instance_count;
966 }
967
968 /* Base vertex and start instance. */
969 base_vertex = original_index_size ? info->index_bias : info->start;
970
971 if (sctx->num_vs_blit_sgprs) {
972 /* Re-emit draw constants after we leave u_blitter. */
973 si_invalidate_draw_sh_constants(sctx);
974
975 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
976 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
977 sctx->num_vs_blit_sgprs);
978 radeon_emit_array(cs, sctx->vs_blit_sh_data,
979 sctx->num_vs_blit_sgprs);
980 } else if (base_vertex != sctx->last_base_vertex ||
981 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
982 info->start_instance != sctx->last_start_instance ||
983 info->drawid != sctx->last_drawid ||
984 sh_base_reg != sctx->last_sh_base_reg) {
985 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
986 radeon_emit(cs, base_vertex);
987 radeon_emit(cs, info->start_instance);
988 radeon_emit(cs, info->drawid);
989
990 sctx->last_base_vertex = base_vertex;
991 sctx->last_start_instance = info->start_instance;
992 sctx->last_drawid = info->drawid;
993 sctx->last_sh_base_reg = sh_base_reg;
994 }
995
996 if (index_size) {
997 if (dispatch_prim_discard_cs) {
998 index_va += info->start * original_index_size;
999 index_max_size = MIN2(index_max_size, info->count);
1000
1001 si_dispatch_prim_discard_cs_and_draw(sctx, info,
1002 original_index_size,
1003 base_vertex,
1004 index_va, index_max_size);
1005 return;
1006 }
1007
1008 index_va += info->start * index_size;
1009
1010 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
1011 radeon_emit(cs, index_max_size);
1012 radeon_emit(cs, index_va);
1013 radeon_emit(cs, index_va >> 32);
1014 radeon_emit(cs, info->count);
1015 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
1016 } else {
1017 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
1018 radeon_emit(cs, info->count);
1019 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1020 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
1021 }
1022 }
1023 }
1024
1025 void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs,
1026 unsigned cp_coher_cntl)
1027 {
1028 bool compute_ib = !sctx->has_graphics ||
1029 cs == sctx->prim_discard_compute_cs;
1030
1031 assert(sctx->chip_class <= GFX9);
1032
1033 if (sctx->chip_class == GFX9 || compute_ib) {
1034 /* Flush caches and wait for the caches to assert idle. */
1035 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
1036 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1037 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1038 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1039 radeon_emit(cs, 0); /* CP_COHER_BASE */
1040 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1041 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1042 } else {
1043 /* ACQUIRE_MEM is only required on a compute ring. */
1044 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
1045 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1046 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1047 radeon_emit(cs, 0); /* CP_COHER_BASE */
1048 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1049 }
1050
1051 /* ACQUIRE_MEM has an implicit context roll if the current context
1052 * is busy. */
1053 if (!compute_ib)
1054 sctx->context_roll = true;
1055 }
1056
1057 void si_prim_discard_signal_next_compute_ib_start(struct si_context *sctx)
1058 {
1059 if (!si_compute_prim_discard_enabled(sctx))
1060 return;
1061
1062 if (!sctx->barrier_buf) {
1063 u_suballocator_alloc(sctx->allocator_zeroed_memory, 4, 4,
1064 &sctx->barrier_buf_offset,
1065 (struct pipe_resource**)&sctx->barrier_buf);
1066 }
1067
1068 /* Emit a placeholder to signal the next compute IB to start.
1069 * See si_compute_prim_discard.c for explanation.
1070 */
1071 uint32_t signal = 1;
1072 si_cp_write_data(sctx, sctx->barrier_buf, sctx->barrier_buf_offset,
1073 4, V_370_MEM, V_370_ME, &signal);
1074
1075 sctx->last_pkt3_write_data =
1076 &sctx->gfx_cs->current.buf[sctx->gfx_cs->current.cdw - 5];
1077
1078 /* Only the last occurence of WRITE_DATA will be executed.
1079 * The packet will be enabled in si_flush_gfx_cs.
1080 */
1081 *sctx->last_pkt3_write_data = PKT3(PKT3_NOP, 3, 0);
1082 }
1083
1084 void gfx10_emit_cache_flush(struct si_context *ctx)
1085 {
1086 struct radeon_cmdbuf *cs = ctx->gfx_cs;
1087 uint32_t gcr_cntl = 0;
1088 unsigned cb_db_event = 0;
1089 unsigned flags = ctx->flags;
1090
1091 if (!ctx->has_graphics) {
1092 /* Only process compute flags. */
1093 flags &= SI_CONTEXT_INV_ICACHE |
1094 SI_CONTEXT_INV_SCACHE |
1095 SI_CONTEXT_INV_VCACHE |
1096 SI_CONTEXT_INV_L2 |
1097 SI_CONTEXT_WB_L2 |
1098 SI_CONTEXT_INV_L2_METADATA |
1099 SI_CONTEXT_CS_PARTIAL_FLUSH;
1100 }
1101
1102 /* We don't need these. */
1103 assert(!(flags & (SI_CONTEXT_VGT_FLUSH |
1104 SI_CONTEXT_VGT_STREAMOUT_SYNC |
1105 SI_CONTEXT_FLUSH_AND_INV_DB_META)));
1106
1107 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1108 ctx->num_cb_cache_flushes++;
1109 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1110 ctx->num_db_cache_flushes++;
1111
1112 if (flags & SI_CONTEXT_INV_ICACHE)
1113 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
1114 if (flags & SI_CONTEXT_INV_SCACHE) {
1115 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
1116 * to FORWARD when both L1 and L2 are written out (WB or INV).
1117 */
1118 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
1119 }
1120 if (flags & SI_CONTEXT_INV_VCACHE)
1121 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
1122 if (flags & SI_CONTEXT_INV_L2) {
1123 /* Writeback and invalidate everything in L2. */
1124 gcr_cntl |= S_586_GL2_INV(1) | S_586_GLM_INV(1);
1125 ctx->num_L2_invalidates++;
1126 } else if (flags & SI_CONTEXT_WB_L2) {
1127 /* Writeback but do not invalidate. */
1128 gcr_cntl |= S_586_GL2_WB(1);
1129 }
1130 if (flags & SI_CONTEXT_INV_L2_METADATA)
1131 gcr_cntl |= S_586_GLM_INV(1);
1132
1133 if (flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1134 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1135 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1136 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1137 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
1138 EVENT_INDEX(0));
1139 }
1140 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1141 /* Flush HTILE. Will wait for idle later. */
1142 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1143 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
1144 EVENT_INDEX(0));
1145 }
1146
1147 /* First flush CB/DB, then L1/L2. */
1148 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
1149
1150 if ((flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) ==
1151 (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1152 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1153 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1154 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1155 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1156 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1157 } else {
1158 assert(0);
1159 }
1160 } else {
1161 /* Wait for graphics shaders to go idle if requested. */
1162 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1163 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1164 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1165 /* Only count explicit shader flushes, not implicit ones. */
1166 ctx->num_vs_flushes++;
1167 ctx->num_ps_flushes++;
1168 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1169 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1170 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1171 ctx->num_vs_flushes++;
1172 }
1173 }
1174
1175 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH && ctx->compute_is_busy) {
1176 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1177 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
1178 ctx->num_cs_flushes++;
1179 ctx->compute_is_busy = false;
1180 }
1181
1182 if (cb_db_event) {
1183 /* CB/DB flush and invalidate (or possibly just a wait for a
1184 * meta flush) via RELEASE_MEM.
1185 *
1186 * Combine this with other cache flushes when possible; this
1187 * requires affected shaders to be idle, so do it after the
1188 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1189 * implied).
1190 */
1191 uint64_t va;
1192
1193 /* Do the flush (enqueue the event and wait for it). */
1194 va = ctx->wait_mem_scratch->gpu_address;
1195 ctx->wait_mem_number++;
1196
1197 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1198 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
1199 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
1200 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
1201 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
1202 assert(G_586_GL2_US(gcr_cntl) == 0);
1203 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
1204 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
1205 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
1206 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
1207 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
1208
1209 gcr_cntl &= C_586_GLM_WB &
1210 C_586_GLM_INV &
1211 C_586_GLV_INV &
1212 C_586_GL1_INV &
1213 C_586_GL2_INV &
1214 C_586_GL2_WB; /* keep SEQ */
1215
1216 si_cp_release_mem(ctx, cs, cb_db_event,
1217 S_490_GLM_WB(glm_wb) |
1218 S_490_GLM_INV(glm_inv) |
1219 S_490_GLV_INV(glv_inv) |
1220 S_490_GL1_INV(gl1_inv) |
1221 S_490_GL2_INV(gl2_inv) |
1222 S_490_GL2_WB(gl2_wb) |
1223 S_490_SEQ(gcr_seq),
1224 EOP_DST_SEL_MEM,
1225 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1226 EOP_DATA_SEL_VALUE_32BIT,
1227 ctx->wait_mem_scratch, va,
1228 ctx->wait_mem_number, SI_NOT_QUERY);
1229 si_cp_wait_mem(ctx, ctx->gfx_cs, va, ctx->wait_mem_number, 0xffffffff,
1230 WAIT_REG_MEM_EQUAL);
1231 }
1232
1233 /* Ignore fields that only modify the behavior of other fields. */
1234 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1235 /* Flush caches and wait for the caches to assert idle.
1236 * The cache flush is executed in the ME, but the PFP waits
1237 * for completion.
1238 */
1239 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1240 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1241 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1242 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1243 radeon_emit(cs, 0); /* CP_COHER_BASE */
1244 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1245 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1246 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1247 } else if (cb_db_event ||
1248 (flags & (SI_CONTEXT_VS_PARTIAL_FLUSH |
1249 SI_CONTEXT_PS_PARTIAL_FLUSH |
1250 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1251 /* We need to ensure that PFP waits as well. */
1252 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1253 radeon_emit(cs, 0);
1254 }
1255
1256 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1257 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1258 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1259 EVENT_INDEX(0));
1260 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1261 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1262 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1263 EVENT_INDEX(0));
1264 }
1265
1266 ctx->flags = 0;
1267 }
1268
1269 void si_emit_cache_flush(struct si_context *sctx)
1270 {
1271 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1272 uint32_t flags = sctx->flags;
1273
1274 if (!sctx->has_graphics) {
1275 /* Only process compute flags. */
1276 flags &= SI_CONTEXT_INV_ICACHE |
1277 SI_CONTEXT_INV_SCACHE |
1278 SI_CONTEXT_INV_VCACHE |
1279 SI_CONTEXT_INV_L2 |
1280 SI_CONTEXT_WB_L2 |
1281 SI_CONTEXT_INV_L2_METADATA |
1282 SI_CONTEXT_CS_PARTIAL_FLUSH;
1283 }
1284
1285 uint32_t cp_coher_cntl = 0;
1286 const uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1287 SI_CONTEXT_FLUSH_AND_INV_DB);
1288 const bool is_barrier = flush_cb_db ||
1289 /* INV_ICACHE == beginning of gfx IB. Checking
1290 * INV_ICACHE fixes corruption for DeusExMD with
1291 * compute-based culling, but I don't know why.
1292 */
1293 flags & (SI_CONTEXT_INV_ICACHE |
1294 SI_CONTEXT_PS_PARTIAL_FLUSH |
1295 SI_CONTEXT_VS_PARTIAL_FLUSH) ||
1296 (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1297 sctx->compute_is_busy);
1298
1299 assert(sctx->chip_class <= GFX9);
1300
1301 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1302 sctx->num_cb_cache_flushes++;
1303 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1304 sctx->num_db_cache_flushes++;
1305
1306 /* GFX6 has a bug that it always flushes ICACHE and KCACHE if either
1307 * bit is set. An alternative way is to write SQC_CACHES, but that
1308 * doesn't seem to work reliably. Since the bug doesn't affect
1309 * correctness (it only does more work than necessary) and
1310 * the performance impact is likely negligible, there is no plan
1311 * to add a workaround for it.
1312 */
1313
1314 if (flags & SI_CONTEXT_INV_ICACHE)
1315 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1316 if (flags & SI_CONTEXT_INV_SCACHE)
1317 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1318
1319 if (sctx->chip_class <= GFX8) {
1320 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1321 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1322 S_0085F0_CB0_DEST_BASE_ENA(1) |
1323 S_0085F0_CB1_DEST_BASE_ENA(1) |
1324 S_0085F0_CB2_DEST_BASE_ENA(1) |
1325 S_0085F0_CB3_DEST_BASE_ENA(1) |
1326 S_0085F0_CB4_DEST_BASE_ENA(1) |
1327 S_0085F0_CB5_DEST_BASE_ENA(1) |
1328 S_0085F0_CB6_DEST_BASE_ENA(1) |
1329 S_0085F0_CB7_DEST_BASE_ENA(1);
1330
1331 /* Necessary for DCC */
1332 if (sctx->chip_class == GFX8)
1333 si_cp_release_mem(sctx, cs,
1334 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1335 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
1336 EOP_DATA_SEL_DISCARD, NULL,
1337 0, 0, SI_NOT_QUERY);
1338 }
1339 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1340 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1341 S_0085F0_DB_DEST_BASE_ENA(1);
1342 }
1343
1344 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1345 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
1346 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1347 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1348 }
1349 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
1350 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
1351 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
1352 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1353 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1354 }
1355
1356 /* Wait for shader engines to go idle.
1357 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
1358 * for everything including CB/DB cache flushes.
1359 */
1360 if (!flush_cb_db) {
1361 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1362 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1363 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1364 /* Only count explicit shader flushes, not implicit ones
1365 * done by SURFACE_SYNC.
1366 */
1367 sctx->num_vs_flushes++;
1368 sctx->num_ps_flushes++;
1369 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1370 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1371 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1372 sctx->num_vs_flushes++;
1373 }
1374 }
1375
1376 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1377 sctx->compute_is_busy) {
1378 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1379 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1380 sctx->num_cs_flushes++;
1381 sctx->compute_is_busy = false;
1382 }
1383
1384 /* VGT state synchronization. */
1385 if (flags & SI_CONTEXT_VGT_FLUSH) {
1386 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1387 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1388 }
1389 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
1390 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1391 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1392 }
1393
1394 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
1395 * wait for idle on GFX9. We have to use a TS event.
1396 */
1397 if (sctx->chip_class == GFX9 && flush_cb_db) {
1398 uint64_t va;
1399 unsigned tc_flags, cb_db_event;
1400
1401 /* Set the CB/DB flush event. */
1402 switch (flush_cb_db) {
1403 case SI_CONTEXT_FLUSH_AND_INV_CB:
1404 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1405 break;
1406 case SI_CONTEXT_FLUSH_AND_INV_DB:
1407 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1408 break;
1409 default:
1410 /* both CB & DB */
1411 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1412 }
1413
1414 /* These are the only allowed combinations. If you need to
1415 * do multiple operations at once, do them separately.
1416 * All operations that invalidate L2 also seem to invalidate
1417 * metadata. Volatile (VOL) and WC flushes are not listed here.
1418 *
1419 * TC | TC_WB = writeback & invalidate L2 & L1
1420 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1421 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1422 * TC | TC_NC = invalidate L2 for MTYPE == NC
1423 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1424 * TCL1 = invalidate L1
1425 */
1426 tc_flags = 0;
1427
1428 if (flags & SI_CONTEXT_INV_L2_METADATA) {
1429 tc_flags = EVENT_TC_ACTION_ENA |
1430 EVENT_TC_MD_ACTION_ENA;
1431 }
1432
1433 /* Ideally flush TC together with CB/DB. */
1434 if (flags & SI_CONTEXT_INV_L2) {
1435 /* Writeback and invalidate everything in L2 & L1. */
1436 tc_flags = EVENT_TC_ACTION_ENA |
1437 EVENT_TC_WB_ACTION_ENA;
1438
1439 /* Clear the flags. */
1440 flags &= ~(SI_CONTEXT_INV_L2 |
1441 SI_CONTEXT_WB_L2 |
1442 SI_CONTEXT_INV_VCACHE);
1443 sctx->num_L2_invalidates++;
1444 }
1445
1446 /* Do the flush (enqueue the event and wait for it). */
1447 va = sctx->wait_mem_scratch->gpu_address;
1448 sctx->wait_mem_number++;
1449
1450 si_cp_release_mem(sctx, cs, cb_db_event, tc_flags,
1451 EOP_DST_SEL_MEM,
1452 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1453 EOP_DATA_SEL_VALUE_32BIT,
1454 sctx->wait_mem_scratch, va,
1455 sctx->wait_mem_number, SI_NOT_QUERY);
1456 si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff,
1457 WAIT_REG_MEM_EQUAL);
1458 }
1459
1460 /* Make sure ME is idle (it executes most packets) before continuing.
1461 * This prevents read-after-write hazards between PFP and ME.
1462 */
1463 if (sctx->has_graphics &&
1464 (cp_coher_cntl ||
1465 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1466 SI_CONTEXT_INV_VCACHE |
1467 SI_CONTEXT_INV_L2 |
1468 SI_CONTEXT_WB_L2)))) {
1469 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1470 radeon_emit(cs, 0);
1471 }
1472
1473 /* GFX6-GFX8 only:
1474 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1475 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1476 *
1477 * cp_coher_cntl should contain all necessary flags except TC flags
1478 * at this point.
1479 *
1480 * GFX6-GFX7 don't support L2 write-back.
1481 */
1482 if (flags & SI_CONTEXT_INV_L2 ||
1483 (sctx->chip_class <= GFX7 &&
1484 (flags & SI_CONTEXT_WB_L2))) {
1485 /* Invalidate L1 & L2. (L1 is always invalidated on GFX6)
1486 * WB must be set on GFX8+ when TC_ACTION is set.
1487 */
1488 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1489 S_0085F0_TC_ACTION_ENA(1) |
1490 S_0085F0_TCL1_ACTION_ENA(1) |
1491 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= GFX8));
1492 cp_coher_cntl = 0;
1493 sctx->num_L2_invalidates++;
1494 } else {
1495 /* L1 invalidation and L2 writeback must be done separately,
1496 * because both operations can't be done together.
1497 */
1498 if (flags & SI_CONTEXT_WB_L2) {
1499 /* WB = write-back
1500 * NC = apply to non-coherent MTYPEs
1501 * (i.e. MTYPE <= 1, which is what we use everywhere)
1502 *
1503 * WB doesn't work without NC.
1504 */
1505 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1506 S_0301F0_TC_WB_ACTION_ENA(1) |
1507 S_0301F0_TC_NC_ACTION_ENA(1));
1508 cp_coher_cntl = 0;
1509 sctx->num_L2_writebacks++;
1510 }
1511 if (flags & SI_CONTEXT_INV_VCACHE) {
1512 /* Invalidate per-CU VMEM L1. */
1513 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1514 S_0085F0_TCL1_ACTION_ENA(1));
1515 cp_coher_cntl = 0;
1516 }
1517 }
1518
1519 /* If TC flushes haven't cleared this... */
1520 if (cp_coher_cntl)
1521 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl);
1522
1523 if (is_barrier)
1524 si_prim_discard_signal_next_compute_ib_start(sctx);
1525
1526 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1527 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1528 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1529 EVENT_INDEX(0));
1530 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1531 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1532 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1533 EVENT_INDEX(0));
1534 }
1535
1536 sctx->flags = 0;
1537 }
1538
1539 static void si_get_draw_start_count(struct si_context *sctx,
1540 const struct pipe_draw_info *info,
1541 unsigned *start, unsigned *count)
1542 {
1543 struct pipe_draw_indirect_info *indirect = info->indirect;
1544
1545 if (indirect) {
1546 unsigned indirect_count;
1547 struct pipe_transfer *transfer;
1548 unsigned begin, end;
1549 unsigned map_size;
1550 unsigned *data;
1551
1552 if (indirect->indirect_draw_count) {
1553 data = pipe_buffer_map_range(&sctx->b,
1554 indirect->indirect_draw_count,
1555 indirect->indirect_draw_count_offset,
1556 sizeof(unsigned),
1557 PIPE_TRANSFER_READ, &transfer);
1558
1559 indirect_count = *data;
1560
1561 pipe_buffer_unmap(&sctx->b, transfer);
1562 } else {
1563 indirect_count = indirect->draw_count;
1564 }
1565
1566 if (!indirect_count) {
1567 *start = *count = 0;
1568 return;
1569 }
1570
1571 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1572 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1573 indirect->offset, map_size,
1574 PIPE_TRANSFER_READ, &transfer);
1575
1576 begin = UINT_MAX;
1577 end = 0;
1578
1579 for (unsigned i = 0; i < indirect_count; ++i) {
1580 unsigned count = data[0];
1581 unsigned start = data[2];
1582
1583 if (count > 0) {
1584 begin = MIN2(begin, start);
1585 end = MAX2(end, start + count);
1586 }
1587
1588 data += indirect->stride / sizeof(unsigned);
1589 }
1590
1591 pipe_buffer_unmap(&sctx->b, transfer);
1592
1593 if (begin < end) {
1594 *start = begin;
1595 *count = end - begin;
1596 } else {
1597 *start = *count = 0;
1598 }
1599 } else {
1600 *start = info->start;
1601 *count = info->count;
1602 }
1603 }
1604
1605 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1606 enum pipe_prim_type prim, unsigned instance_count,
1607 bool primitive_restart, unsigned skip_atom_mask)
1608 {
1609 unsigned num_patches = 0;
1610
1611 si_emit_rasterizer_prim_state(sctx);
1612 if (sctx->tes_shader.cso)
1613 si_emit_derived_tess_state(sctx, info, &num_patches);
1614
1615 /* Emit state atoms. */
1616 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1617 while (mask)
1618 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1619
1620 sctx->dirty_atoms &= skip_atom_mask;
1621
1622 /* Emit states. */
1623 mask = sctx->dirty_states;
1624 while (mask) {
1625 unsigned i = u_bit_scan(&mask);
1626 struct si_pm4_state *state = sctx->queued.array[i];
1627
1628 if (!state || sctx->emitted.array[i] == state)
1629 continue;
1630
1631 si_pm4_emit(sctx, state);
1632 sctx->emitted.array[i] = state;
1633 }
1634 sctx->dirty_states = 0;
1635
1636 /* Emit draw states. */
1637 si_emit_vs_state(sctx, info);
1638 si_emit_draw_registers(sctx, info, prim, num_patches, instance_count,
1639 primitive_restart);
1640 }
1641
1642 static bool
1643 si_all_vs_resources_read_only(struct si_context *sctx,
1644 struct pipe_resource *indexbuf)
1645 {
1646 struct radeon_winsys *ws = sctx->ws;
1647 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1648
1649 /* Index buffer. */
1650 if (indexbuf &&
1651 ws->cs_is_buffer_referenced(cs, si_resource(indexbuf)->buf,
1652 RADEON_USAGE_WRITE))
1653 goto has_write_reference;
1654
1655 /* Vertex buffers. */
1656 struct si_vertex_elements *velems = sctx->vertex_elements;
1657 unsigned num_velems = velems->count;
1658
1659 for (unsigned i = 0; i < num_velems; i++) {
1660 if (!((1 << i) & velems->first_vb_use_mask))
1661 continue;
1662
1663 unsigned vb_index = velems->vertex_buffer_index[i];
1664 struct pipe_resource *res = sctx->vertex_buffer[vb_index].buffer.resource;
1665 if (!res)
1666 continue;
1667
1668 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1669 RADEON_USAGE_WRITE))
1670 goto has_write_reference;
1671 }
1672
1673 /* Constant and shader buffers. */
1674 struct si_descriptors *buffers =
1675 &sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_VERTEX)];
1676 for (unsigned i = 0; i < buffers->num_active_slots; i++) {
1677 unsigned index = buffers->first_active_slot + i;
1678 struct pipe_resource *res =
1679 sctx->const_and_shader_buffers[PIPE_SHADER_VERTEX].buffers[index];
1680 if (!res)
1681 continue;
1682
1683 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1684 RADEON_USAGE_WRITE))
1685 goto has_write_reference;
1686 }
1687
1688 /* Samplers. */
1689 struct si_shader_selector *vs = sctx->vs_shader.cso;
1690 if (vs->info.samplers_declared) {
1691 unsigned num_samplers = util_last_bit(vs->info.samplers_declared);
1692
1693 for (unsigned i = 0; i < num_samplers; i++) {
1694 struct pipe_sampler_view *view = sctx->samplers[PIPE_SHADER_VERTEX].views[i];
1695 if (!view)
1696 continue;
1697
1698 if (ws->cs_is_buffer_referenced(cs,
1699 si_resource(view->texture)->buf,
1700 RADEON_USAGE_WRITE))
1701 goto has_write_reference;
1702 }
1703 }
1704
1705 /* Images. */
1706 if (vs->info.images_declared) {
1707 unsigned num_images = util_last_bit(vs->info.images_declared);
1708
1709 for (unsigned i = 0; i < num_images; i++) {
1710 struct pipe_resource *res = sctx->images[PIPE_SHADER_VERTEX].views[i].resource;
1711 if (!res)
1712 continue;
1713
1714 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1715 RADEON_USAGE_WRITE))
1716 goto has_write_reference;
1717 }
1718 }
1719
1720 return true;
1721
1722 has_write_reference:
1723 /* If the current gfx IB has enough packets, flush it to remove write
1724 * references to buffers.
1725 */
1726 if (cs->prev_dw + cs->current.cdw > 2048) {
1727 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1728 assert(si_all_vs_resources_read_only(sctx, indexbuf));
1729 return true;
1730 }
1731 return false;
1732 }
1733
1734 static ALWAYS_INLINE bool pd_msg(const char *s)
1735 {
1736 if (SI_PRIM_DISCARD_DEBUG)
1737 printf("PD failed: %s\n", s);
1738 return false;
1739 }
1740
1741 static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1742 {
1743 struct si_context *sctx = (struct si_context *)ctx;
1744 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1745 struct pipe_resource *indexbuf = info->index.resource;
1746 unsigned dirty_tex_counter, dirty_buf_counter;
1747 enum pipe_prim_type rast_prim, prim = info->mode;
1748 unsigned index_size = info->index_size;
1749 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1750 unsigned instance_count = info->instance_count;
1751 bool primitive_restart = info->primitive_restart &&
1752 (!sctx->screen->options.prim_restart_tri_strips_only ||
1753 (prim != PIPE_PRIM_TRIANGLE_STRIP &&
1754 prim != PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY));
1755
1756 if (likely(!info->indirect)) {
1757 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
1758 * no workaround for indirect draws, but we can at least skip
1759 * direct draws.
1760 */
1761 if (unlikely(!instance_count))
1762 return;
1763
1764 /* Handle count == 0. */
1765 if (unlikely(!info->count &&
1766 (index_size || !info->count_from_stream_output)))
1767 return;
1768 }
1769
1770 if (unlikely(!sctx->vs_shader.cso ||
1771 !rs ||
1772 (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
1773 (!!sctx->tes_shader.cso != (prim == PIPE_PRIM_PATCHES)))) {
1774 assert(0);
1775 return;
1776 }
1777
1778 /* Recompute and re-emit the texture resource states if needed. */
1779 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1780 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1781 sctx->last_dirty_tex_counter = dirty_tex_counter;
1782 sctx->framebuffer.dirty_cbufs |=
1783 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1784 sctx->framebuffer.dirty_zsbuf = true;
1785 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1786 si_update_all_texture_descriptors(sctx);
1787 }
1788
1789 dirty_buf_counter = p_atomic_read(&sctx->screen->dirty_buf_counter);
1790 if (unlikely(dirty_buf_counter != sctx->last_dirty_buf_counter)) {
1791 sctx->last_dirty_buf_counter = dirty_buf_counter;
1792 /* Rebind all buffers unconditionally. */
1793 si_rebind_buffer(sctx, NULL);
1794 }
1795
1796 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1797
1798 /* Set the rasterization primitive type.
1799 *
1800 * This must be done after si_decompress_textures, which can call
1801 * draw_vbo recursively, and before si_update_shaders, which uses
1802 * current_rast_prim for this draw_vbo call. */
1803 if (sctx->gs_shader.cso) {
1804 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
1805 rast_prim = sctx->gs_shader.cso->rast_prim;
1806 } else if (sctx->tes_shader.cso) {
1807 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
1808 rast_prim = sctx->tes_shader.cso->rast_prim;
1809 } else if (util_rast_prim_is_triangles(prim)) {
1810 rast_prim = PIPE_PRIM_TRIANGLES;
1811 } else {
1812 /* Only possibilities, POINTS, LINE*, RECTANGLES */
1813 rast_prim = prim;
1814 }
1815
1816 if (rast_prim != sctx->current_rast_prim) {
1817 if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
1818 util_prim_is_points_or_lines(rast_prim))
1819 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1820
1821 sctx->current_rast_prim = rast_prim;
1822 sctx->do_update_shaders = true;
1823 }
1824
1825 if (sctx->tes_shader.cso &&
1826 sctx->screen->has_ls_vgpr_init_bug) {
1827 /* Determine whether the LS VGPR fix should be applied.
1828 *
1829 * It is only required when num input CPs > num output CPs,
1830 * which cannot happen with the fixed function TCS. We should
1831 * also update this bit when switching from TCS to fixed
1832 * function TCS.
1833 */
1834 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1835 bool ls_vgpr_fix =
1836 tcs &&
1837 info->vertices_per_patch >
1838 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1839
1840 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1841 sctx->ls_vgpr_fix = ls_vgpr_fix;
1842 sctx->do_update_shaders = true;
1843 }
1844 }
1845
1846 if (sctx->chip_class <= GFX9 && sctx->gs_shader.cso) {
1847 /* Determine whether the GS triangle strip adjacency fix should
1848 * be applied. Rotate every other triangle if
1849 * - triangle strips with adjacency are fed to the GS and
1850 * - primitive restart is disabled (the rotation doesn't help
1851 * when the restart occurs after an odd number of triangles).
1852 */
1853 bool gs_tri_strip_adj_fix =
1854 !sctx->tes_shader.cso &&
1855 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1856 !primitive_restart;
1857
1858 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1859 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1860 sctx->do_update_shaders = true;
1861 }
1862 }
1863
1864 if (index_size) {
1865 /* Translate or upload, if needed. */
1866 /* 8-bit indices are supported on GFX8. */
1867 if (sctx->chip_class <= GFX7 && index_size == 1) {
1868 unsigned start, count, start_offset, size, offset;
1869 void *ptr;
1870
1871 si_get_draw_start_count(sctx, info, &start, &count);
1872 start_offset = start * 2;
1873 size = count * 2;
1874
1875 indexbuf = NULL;
1876 u_upload_alloc(ctx->stream_uploader, start_offset,
1877 size,
1878 si_optimal_tcc_alignment(sctx, size),
1879 &offset, &indexbuf, &ptr);
1880 if (!indexbuf)
1881 return;
1882
1883 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1884 index_offset + start,
1885 count, ptr);
1886
1887 /* info->start will be added by the drawing code */
1888 index_offset = offset - start_offset;
1889 index_size = 2;
1890 } else if (info->has_user_indices) {
1891 unsigned start_offset;
1892
1893 assert(!info->indirect);
1894 start_offset = info->start * index_size;
1895
1896 indexbuf = NULL;
1897 u_upload_data(ctx->stream_uploader, start_offset,
1898 info->count * index_size,
1899 sctx->screen->info.tcc_cache_line_size,
1900 (char*)info->index.user + start_offset,
1901 &index_offset, &indexbuf);
1902 if (!indexbuf)
1903 return;
1904
1905 /* info->start will be added by the drawing code */
1906 index_offset -= start_offset;
1907 } else if (sctx->chip_class <= GFX7 &&
1908 si_resource(indexbuf)->TC_L2_dirty) {
1909 /* GFX8 reads index buffers through TC L2, so it doesn't
1910 * need this. */
1911 sctx->flags |= SI_CONTEXT_WB_L2;
1912 si_resource(indexbuf)->TC_L2_dirty = false;
1913 }
1914 }
1915
1916 bool dispatch_prim_discard_cs = false;
1917 bool prim_discard_cs_instancing = false;
1918 unsigned original_index_size = index_size;
1919 unsigned direct_count = 0;
1920
1921 if (info->indirect) {
1922 struct pipe_draw_indirect_info *indirect = info->indirect;
1923
1924 /* Add the buffer size for memory checking in need_cs_space. */
1925 si_context_add_resource_size(sctx, indirect->buffer);
1926
1927 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1928 if (sctx->chip_class <= GFX8) {
1929 if (si_resource(indirect->buffer)->TC_L2_dirty) {
1930 sctx->flags |= SI_CONTEXT_WB_L2;
1931 si_resource(indirect->buffer)->TC_L2_dirty = false;
1932 }
1933
1934 if (indirect->indirect_draw_count &&
1935 si_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1936 sctx->flags |= SI_CONTEXT_WB_L2;
1937 si_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1938 }
1939 }
1940 } else {
1941 /* Multiply by 3 for strips and fans to get an approximate vertex
1942 * count as triangles. */
1943 direct_count = info->count * instance_count *
1944 (prim == PIPE_PRIM_TRIANGLES ? 1 : 3);
1945 }
1946
1947 /* Determine if we can use the primitive discard compute shader. */
1948 if (si_compute_prim_discard_enabled(sctx) &&
1949 (direct_count > sctx->prim_discard_vertex_count_threshold ?
1950 (sctx->compute_num_verts_rejected += direct_count, true) : /* Add, then return true. */
1951 (sctx->compute_num_verts_ineligible += direct_count, false)) && /* Add, then return false. */
1952 (!info->count_from_stream_output || pd_msg("draw_opaque")) &&
1953 (primitive_restart ?
1954 /* Supported prim types with primitive restart: */
1955 (prim == PIPE_PRIM_TRIANGLE_STRIP || pd_msg("bad prim type with primitive restart")) &&
1956 /* Disallow instancing with primitive restart: */
1957 (instance_count == 1 || pd_msg("instance_count > 1 with primitive restart")) :
1958 /* Supported prim types without primitive restart + allow instancing: */
1959 (1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1960 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1961 (1 << PIPE_PRIM_TRIANGLE_FAN)) &&
1962 /* Instancing is limited to 16-bit indices, because InstanceID is packed into VertexID. */
1963 /* TODO: DrawArraysInstanced doesn't sometimes work, so it's disabled. */
1964 (instance_count == 1 ||
1965 (instance_count <= USHRT_MAX && index_size && index_size <= 2) ||
1966 pd_msg("instance_count too large or index_size == 4 or DrawArraysInstanced"))) &&
1967 (info->drawid == 0 || !sctx->vs_shader.cso->info.uses_drawid || pd_msg("draw_id > 0")) &&
1968 (!sctx->render_cond || pd_msg("render condition")) &&
1969 /* Forced enablement ignores pipeline statistics queries. */
1970 (sctx->screen->debug_flags & (DBG(PD) | DBG(ALWAYS_PD)) ||
1971 (!sctx->num_pipeline_stat_queries && !sctx->streamout.prims_gen_query_enabled) ||
1972 pd_msg("pipestat or primgen query")) &&
1973 (!sctx->vertex_elements->instance_divisor_is_fetched || pd_msg("loads instance divisors")) &&
1974 (!sctx->tes_shader.cso || pd_msg("uses tess")) &&
1975 (!sctx->gs_shader.cso || pd_msg("uses GS")) &&
1976 (!sctx->ps_shader.cso->info.uses_primid || pd_msg("PS uses PrimID")) &&
1977 #if SI_PRIM_DISCARD_DEBUG /* same as cso->prim_discard_cs_allowed */
1978 (!sctx->vs_shader.cso->info.uses_bindless_images || pd_msg("uses bindless images")) &&
1979 (!sctx->vs_shader.cso->info.uses_bindless_samplers || pd_msg("uses bindless samplers")) &&
1980 (!sctx->vs_shader.cso->info.writes_memory || pd_msg("writes memory")) &&
1981 (!sctx->vs_shader.cso->info.writes_viewport_index || pd_msg("writes viewport index")) &&
1982 !sctx->vs_shader.cso->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
1983 !sctx->vs_shader.cso->so.num_outputs &&
1984 #else
1985 (sctx->vs_shader.cso->prim_discard_cs_allowed || pd_msg("VS shader uses unsupported features")) &&
1986 #endif
1987 /* Check that all buffers are used for read only, because compute
1988 * dispatches can run ahead. */
1989 (si_all_vs_resources_read_only(sctx, index_size ? indexbuf : NULL) || pd_msg("write reference"))) {
1990 switch (si_prepare_prim_discard_or_split_draw(sctx, info, primitive_restart)) {
1991 case SI_PRIM_DISCARD_ENABLED:
1992 original_index_size = index_size;
1993 prim_discard_cs_instancing = instance_count > 1;
1994 dispatch_prim_discard_cs = true;
1995
1996 /* The compute shader changes/lowers the following: */
1997 prim = PIPE_PRIM_TRIANGLES;
1998 index_size = 4;
1999 instance_count = 1;
2000 primitive_restart = false;
2001 sctx->compute_num_verts_rejected -= direct_count;
2002 sctx->compute_num_verts_accepted += direct_count;
2003 break;
2004 case SI_PRIM_DISCARD_DISABLED:
2005 break;
2006 case SI_PRIM_DISCARD_DRAW_SPLIT:
2007 sctx->compute_num_verts_rejected -= direct_count;
2008 goto return_cleanup;
2009 }
2010 }
2011
2012 if (prim_discard_cs_instancing != sctx->prim_discard_cs_instancing) {
2013 sctx->prim_discard_cs_instancing = prim_discard_cs_instancing;
2014 sctx->do_update_shaders = true;
2015 }
2016
2017 if (sctx->do_update_shaders && !si_update_shaders(sctx))
2018 goto return_cleanup;
2019
2020 si_need_gfx_cs_space(sctx);
2021
2022 if (sctx->bo_list_add_all_gfx_resources)
2023 si_gfx_resources_add_all_to_bo_list(sctx);
2024
2025 /* Since we've called si_context_add_resource_size for vertex buffers,
2026 * this must be called after si_need_cs_space, because we must let
2027 * need_cs_space flush before we add buffers to the buffer list.
2028 */
2029 if (!si_upload_vertex_buffer_descriptors(sctx))
2030 goto return_cleanup;
2031
2032 /* Vega10/Raven scissor bug workaround. When any context register is
2033 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
2034 * registers must be written too.
2035 */
2036 bool has_gfx9_scissor_bug = sctx->screen->has_gfx9_scissor_bug;
2037 unsigned masked_atoms = 0;
2038
2039 if (has_gfx9_scissor_bug) {
2040 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
2041
2042 if (info->count_from_stream_output ||
2043 sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
2044 sctx->dirty_states & si_states_that_always_roll_context())
2045 sctx->context_roll = true;
2046 }
2047
2048 /* Use optimal packet order based on whether we need to sync the pipeline. */
2049 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
2050 SI_CONTEXT_FLUSH_AND_INV_DB |
2051 SI_CONTEXT_PS_PARTIAL_FLUSH |
2052 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
2053 /* If we have to wait for idle, set all states first, so that all
2054 * SET packets are processed in parallel with previous draw calls.
2055 * Then draw and prefetch at the end. This ensures that the time
2056 * the CUs are idle is very short.
2057 */
2058 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
2059 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
2060
2061 if (!si_upload_graphics_shader_descriptors(sctx))
2062 goto return_cleanup;
2063
2064 /* Emit all states except possibly render condition. */
2065 si_emit_all_states(sctx, info, prim, instance_count,
2066 primitive_restart, masked_atoms);
2067 sctx->emit_cache_flush(sctx);
2068 /* <-- CUs are idle here. */
2069
2070 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
2071 sctx->atoms.s.render_cond.emit(sctx);
2072
2073 if (has_gfx9_scissor_bug &&
2074 (sctx->context_roll ||
2075 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
2076 sctx->atoms.s.scissors.emit(sctx);
2077
2078 sctx->dirty_atoms = 0;
2079
2080 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
2081 instance_count, dispatch_prim_discard_cs,
2082 original_index_size);
2083 /* <-- CUs are busy here. */
2084
2085 /* Start prefetches after the draw has been started. Both will run
2086 * in parallel, but starting the draw first is more important.
2087 */
2088 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2089 cik_emit_prefetch_L2(sctx, false);
2090 } else {
2091 /* If we don't wait for idle, start prefetches first, then set
2092 * states, and draw at the end.
2093 */
2094 if (sctx->flags)
2095 sctx->emit_cache_flush(sctx);
2096
2097 /* Only prefetch the API VS and VBO descriptors. */
2098 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2099 cik_emit_prefetch_L2(sctx, true);
2100
2101 if (!si_upload_graphics_shader_descriptors(sctx))
2102 goto return_cleanup;
2103
2104 si_emit_all_states(sctx, info, prim, instance_count,
2105 primitive_restart, masked_atoms);
2106
2107 if (has_gfx9_scissor_bug &&
2108 (sctx->context_roll ||
2109 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
2110 sctx->atoms.s.scissors.emit(sctx);
2111
2112 sctx->dirty_atoms = 0;
2113
2114 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
2115 instance_count, dispatch_prim_discard_cs,
2116 original_index_size);
2117
2118 /* Prefetch the remaining shaders after the draw has been
2119 * started. */
2120 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2121 cik_emit_prefetch_L2(sctx, false);
2122 }
2123
2124 /* Clear the context roll flag after the draw call. */
2125 sctx->context_roll = false;
2126
2127 if (unlikely(sctx->current_saved_cs)) {
2128 si_trace_emit(sctx);
2129 si_log_draw_state(sctx, sctx->log);
2130 }
2131
2132 /* Workaround for a VGT hang when streamout is enabled.
2133 * It must be done after drawing. */
2134 if ((sctx->family == CHIP_HAWAII ||
2135 sctx->family == CHIP_TONGA ||
2136 sctx->family == CHIP_FIJI) &&
2137 si_get_strmout_en(sctx)) {
2138 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
2139 }
2140
2141 if (unlikely(sctx->decompression_enabled)) {
2142 sctx->num_decompress_calls++;
2143 } else {
2144 sctx->num_draw_calls++;
2145 if (sctx->framebuffer.state.nr_cbufs > 1)
2146 sctx->num_mrt_draw_calls++;
2147 if (primitive_restart)
2148 sctx->num_prim_restart_calls++;
2149 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
2150 sctx->num_spill_draw_calls++;
2151 }
2152
2153 return_cleanup:
2154 if (index_size && indexbuf != info->index.resource)
2155 pipe_resource_reference(&indexbuf, NULL);
2156 }
2157
2158 static void
2159 si_draw_rectangle(struct blitter_context *blitter,
2160 void *vertex_elements_cso,
2161 blitter_get_vs_func get_vs,
2162 int x1, int y1, int x2, int y2,
2163 float depth, unsigned num_instances,
2164 enum blitter_attrib_type type,
2165 const union blitter_attrib *attrib)
2166 {
2167 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
2168 struct si_context *sctx = (struct si_context*)pipe;
2169
2170 /* Pack position coordinates as signed int16. */
2171 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
2172 ((uint32_t)(y1 & 0xffff) << 16);
2173 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
2174 ((uint32_t)(y2 & 0xffff) << 16);
2175 sctx->vs_blit_sh_data[2] = fui(depth);
2176
2177 switch (type) {
2178 case UTIL_BLITTER_ATTRIB_COLOR:
2179 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
2180 sizeof(float)*4);
2181 break;
2182 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
2183 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
2184 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
2185 sizeof(attrib->texcoord));
2186 break;
2187 case UTIL_BLITTER_ATTRIB_NONE:;
2188 }
2189
2190 pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
2191
2192 struct pipe_draw_info info = {};
2193 info.mode = SI_PRIM_RECTANGLE_LIST;
2194 info.count = 3;
2195 info.instance_count = num_instances;
2196
2197 /* Don't set per-stage shader pointers for VS. */
2198 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
2199 sctx->vertex_buffer_pointer_dirty = false;
2200
2201 si_draw_vbo(pipe, &info);
2202 }
2203
2204 void si_trace_emit(struct si_context *sctx)
2205 {
2206 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2207 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
2208
2209 si_cp_write_data(sctx, sctx->current_saved_cs->trace_buf,
2210 0, 4, V_370_MEM, V_370_ME, &trace_id);
2211
2212 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2213 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
2214
2215 if (sctx->log)
2216 u_log_flush(sctx->log);
2217 }
2218
2219 void si_init_draw_functions(struct si_context *sctx)
2220 {
2221 sctx->b.draw_vbo = si_draw_vbo;
2222
2223 sctx->blitter->draw_rectangle = si_draw_rectangle;
2224
2225 si_init_ia_multi_vgt_param_table(sctx);
2226 }