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radeonsi: Don't match TGSI_SEMANTIC_POSITION fs inputs to vs outputs
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "radeonsi_pipe.h"
32 #include "radeonsi_shader.h"
33 #include "si_state.h"
34 #include "sid.h"
35
36 /*
37 * Shaders
38 */
39
40 static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
41 {
42 struct r600_context *rctx = (struct r600_context *)ctx;
43 struct si_pm4_state *pm4;
44 unsigned num_sgprs, num_user_sgprs;
45 unsigned nparams, i;
46 uint64_t va;
47
48 si_pm4_delete_state(rctx, vs, shader->pm4);
49 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
50
51 si_pm4_inval_shader_cache(pm4);
52
53 /* Certain attributes (position, psize, etc.) don't count as params.
54 * VS is required to export at least one param and r600_shader_from_tgsi()
55 * takes care of adding a dummy export.
56 */
57 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
58 if (shader->shader.output[i].name != TGSI_SEMANTIC_POSITION)
59 nparams++;
60 }
61 if (nparams < 1)
62 nparams = 1;
63
64 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
65 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
66
67 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
68 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
69 S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
70 S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
71 S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE));
72
73 va = r600_resource_va(ctx->screen, (void *)shader->bo);
74 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
75 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
76 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
77
78 num_user_sgprs = SI_VS_NUM_USER_SGPR;
79 num_sgprs = shader->num_sgprs;
80 if (num_user_sgprs > num_sgprs)
81 num_sgprs = num_user_sgprs;
82 /* Last 2 reserved SGPRs are used for VCC */
83 num_sgprs += 2;
84 assert(num_sgprs <= 104);
85
86 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
87 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
88 S_00B128_SGPRS((num_sgprs - 1) / 8));
89 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
90 S_00B12C_USER_SGPR(num_user_sgprs));
91
92 si_pm4_bind_state(rctx, vs, shader->pm4);
93 }
94
95 static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
96 {
97 struct r600_context *rctx = (struct r600_context *)ctx;
98 struct si_pm4_state *pm4;
99 unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
100 unsigned num_sgprs, num_user_sgprs;
101 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
102 unsigned fragcoord_interp_mode = 0;
103 unsigned spi_baryc_cntl, spi_ps_input_ena, spi_shader_z_format;
104 uint64_t va;
105
106 si_pm4_delete_state(rctx, ps, shader->pm4);
107 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
108
109 si_pm4_inval_shader_cache(pm4);
110
111 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
112 for (i = 0; i < shader->shader.ninput; i++) {
113 switch (shader->shader.input[i].name) {
114 case TGSI_SEMANTIC_POSITION:
115 if (shader->shader.input[i].centroid) {
116 /* fragcoord_interp_mode will be written to
117 * SPI_BARYC_CNTL.POS_FLOAT_LOCATION
118 * Possible vaules:
119 * 0 -> Position = pixel center (default)
120 * 1 -> Position = pixel centroid
121 * 2 -> Position = iterated sample number XXX:
122 * What does this mean?
123 */
124 fragcoord_interp_mode = 1;
125 }
126 /* Fall through */
127 case TGSI_SEMANTIC_FACE:
128 continue;
129 }
130
131 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
132 have_linear = TRUE;
133 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
134 have_perspective = TRUE;
135 if (shader->shader.input[i].centroid)
136 have_centroid = TRUE;
137 }
138
139 for (i = 0; i < shader->shader.noutput; i++) {
140 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
141 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
142 if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
143 db_shader_control |= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
144 }
145 if (shader->shader.uses_kill || shader->key.alpha_func != PIPE_FUNC_ALWAYS)
146 db_shader_control |= S_02880C_KILL_ENABLE(1);
147
148 exports_ps = 0;
149 num_cout = 0;
150 for (i = 0; i < shader->shader.noutput; i++) {
151 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
152 shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
153 exports_ps |= 1;
154 else if (shader->shader.output[i].name == TGSI_SEMANTIC_COLOR) {
155 if (shader->shader.fs_write_all)
156 num_cout = shader->shader.nr_cbufs;
157 else
158 num_cout++;
159 }
160 }
161 if (!exports_ps) {
162 /* always at least export 1 component per pixel */
163 exports_ps = 2;
164 }
165
166 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.ninterp);
167
168 spi_baryc_cntl = 0;
169 if (have_perspective)
170 spi_baryc_cntl |= have_centroid ?
171 S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1);
172 if (have_linear)
173 spi_baryc_cntl |= have_centroid ?
174 S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1);
175 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(fragcoord_interp_mode);
176
177 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
178 spi_ps_input_ena = shader->spi_ps_input_ena;
179 /* we need to enable at least one of them, otherwise we hang the GPU */
180 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
181 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
182 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
183 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
184 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
185 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
186 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
187 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
188
189 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
190 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
191 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
192
193 if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control))
194 spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
195 else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control))
196 spi_shader_z_format = V_028710_SPI_SHADER_32_R;
197 else
198 spi_shader_z_format = 0;
199 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, spi_shader_z_format);
200 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
201 shader->spi_shader_col_format);
202
203 va = r600_resource_va(ctx->screen, (void *)shader->bo);
204 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
205 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
206 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
207
208 num_user_sgprs = SI_PS_NUM_USER_SGPR;
209 num_sgprs = shader->num_sgprs;
210 if (num_user_sgprs > num_sgprs)
211 num_sgprs = num_user_sgprs;
212 /* Last 2 reserved SGPRs are used for VCC */
213 num_sgprs += 2;
214 assert(num_sgprs <= 104);
215
216 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
217 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
218 S_00B028_SGPRS((num_sgprs - 1) / 8));
219 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
220 S_00B02C_USER_SGPR(num_user_sgprs));
221
222 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
223
224 shader->sprite_coord_enable = rctx->sprite_coord_enable;
225 si_pm4_bind_state(rctx, ps, shader->pm4);
226 }
227
228 /*
229 * Drawing
230 */
231
232 static unsigned si_conv_pipe_prim(unsigned pprim)
233 {
234 static const unsigned prim_conv[] = {
235 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
236 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
237 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
238 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
239 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
240 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
241 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
242 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
243 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
244 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
245 [PIPE_PRIM_LINES_ADJACENCY] = ~0,
246 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0,
247 [PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0,
248 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0
249 };
250 unsigned result = prim_conv[pprim];
251 if (result == ~0) {
252 R600_ERR("unsupported primitive type %d\n", pprim);
253 }
254 return result;
255 }
256
257 static bool si_update_draw_info_state(struct r600_context *rctx,
258 const struct pipe_draw_info *info)
259 {
260 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
261 unsigned prim = si_conv_pipe_prim(info->mode);
262 unsigned ls_mask = 0;
263
264 if (pm4 == NULL)
265 return false;
266
267 if (prim == ~0) {
268 FREE(pm4);
269 return false;
270 }
271
272 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
273 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
274 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
275 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET,
276 info->indexed ? info->index_bias : info->start);
277 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
278 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
279 #if 0
280 si_pm4_set_reg(pm4, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
281 si_pm4_set_reg(pm4, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance);
282 #endif
283
284 if (prim == V_008958_DI_PT_LINELIST)
285 ls_mask = 1;
286 else if (prim == V_008958_DI_PT_LINESTRIP)
287 ls_mask = 2;
288 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
289 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
290 rctx->pa_sc_line_stipple);
291
292 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
293 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
294 S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
295 } else {
296 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
297 }
298 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
299 prim == PIPE_PRIM_POINTS ? rctx->pa_cl_vs_out_cntl : 0
300 /*| (rctx->rasterizer->clip_plane_enable &
301 rctx->vs_shader->shader.clip_dist_write)*/);
302 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL, rctx->pa_cl_clip_cntl
303 /*| (rctx->vs_shader->shader.clip_dist_write ||
304 rctx->vs_shader->shader.vs_prohibit_ucps ?
305 0 : rctx->rasterizer->clip_plane_enable & 0x3F)*/);
306
307 si_pm4_set_state(rctx, draw_info, pm4);
308 return true;
309 }
310
311 static void si_update_spi_map(struct r600_context *rctx)
312 {
313 struct si_shader *ps = &rctx->ps_shader->current->shader;
314 struct si_shader *vs = &rctx->vs_shader->current->shader;
315 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
316 unsigned i, j, tmp;
317
318 for (i = 0; i < ps->ninput; i++) {
319 unsigned name = ps->input[i].name;
320 unsigned param_offset = ps->input[i].param_offset;
321
322 if (name == TGSI_SEMANTIC_POSITION)
323 /* Read from preloaded VGPRs, not parameters */
324 continue;
325
326 bcolor:
327 tmp = 0;
328
329 if (ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
330 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
331 rctx->ps_shader->current->key.flatshade)) {
332 tmp |= S_028644_FLAT_SHADE(1);
333 }
334
335 if (name == TGSI_SEMANTIC_GENERIC &&
336 rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
337 tmp |= S_028644_PT_SPRITE_TEX(1);
338 }
339
340 for (j = 0; j < vs->noutput; j++) {
341 if (name == vs->output[j].name &&
342 ps->input[i].sid == vs->output[j].sid) {
343 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
344 break;
345 }
346 }
347
348 if (j == vs->noutput) {
349 /* No corresponding output found, load defaults into input */
350 tmp |= S_028644_OFFSET(0x20);
351 }
352
353 si_pm4_set_reg(pm4,
354 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
355 tmp);
356
357 if (name == TGSI_SEMANTIC_COLOR &&
358 rctx->ps_shader->current->key.color_two_side) {
359 name = TGSI_SEMANTIC_BCOLOR;
360 param_offset++;
361 goto bcolor;
362 }
363 }
364
365 si_pm4_set_state(rctx, spi, pm4);
366 }
367
368 static void si_update_derived_state(struct r600_context *rctx)
369 {
370 struct pipe_context * ctx = (struct pipe_context*)rctx;
371 unsigned ps_dirty = 0;
372
373 if (!rctx->blitter->running) {
374 /* Flush depth textures which need to be flushed. */
375 if (rctx->vs_samplers.depth_texture_mask) {
376 si_flush_depth_textures(rctx, &rctx->vs_samplers);
377 }
378 if (rctx->ps_samplers.depth_texture_mask) {
379 si_flush_depth_textures(rctx, &rctx->ps_samplers);
380 }
381 }
382
383 si_shader_select(ctx, rctx->ps_shader, &ps_dirty);
384
385 if (!rctx->vs_shader->current->pm4) {
386 si_pipe_shader_vs(ctx, rctx->vs_shader->current);
387 }
388
389 if (!rctx->ps_shader->current->pm4) {
390 si_pipe_shader_ps(ctx, rctx->ps_shader->current);
391 ps_dirty = 0;
392 }
393 if (!rctx->ps_shader->current->bo) {
394 if (!rctx->dummy_pixel_shader->pm4)
395 si_pipe_shader_ps(ctx, rctx->dummy_pixel_shader);
396 else
397 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
398
399 ps_dirty = 0;
400 }
401
402 if (ps_dirty) {
403 si_pm4_bind_state(rctx, ps, rctx->ps_shader->current->pm4);
404 }
405
406 if (si_pm4_state_changed(rctx, ps) || si_pm4_state_changed(rctx, vs)) {
407 si_update_spi_map(rctx);
408 }
409 }
410
411 static void si_vertex_buffer_update(struct r600_context *rctx)
412 {
413 struct pipe_context *ctx = &rctx->context;
414 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
415 bool bound[PIPE_MAX_ATTRIBS] = {};
416 unsigned i, count;
417 uint64_t va;
418
419 si_pm4_inval_vertex_cache(pm4);
420
421 /* bind vertex buffer once */
422 count = rctx->vertex_elements->count;
423 assert(count <= 256 / 4);
424
425 si_pm4_sh_data_begin(pm4);
426 for (i = 0 ; i < count; i++) {
427 struct pipe_vertex_element *ve = &rctx->vertex_elements->elements[i];
428 struct pipe_vertex_buffer *vb;
429 struct si_resource *rbuffer;
430 unsigned offset;
431
432 if (ve->vertex_buffer_index >= rctx->nr_vertex_buffers)
433 continue;
434
435 vb = &rctx->vertex_buffer[ve->vertex_buffer_index];
436 rbuffer = (struct si_resource*)vb->buffer;
437 if (rbuffer == NULL)
438 continue;
439
440 offset = 0;
441 offset += vb->buffer_offset;
442 offset += ve->src_offset;
443
444 va = r600_resource_va(ctx->screen, (void*)rbuffer);
445 va += offset;
446
447 /* Fill in T# buffer resource description */
448 si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF);
449 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
450 S_008F04_STRIDE(vb->stride)));
451 si_pm4_sh_data_add(pm4, (vb->buffer->width0 - vb->buffer_offset) /
452 MAX2(vb->stride, 1));
453 si_pm4_sh_data_add(pm4, rctx->vertex_elements->rsrc_word3[i]);
454
455 if (!bound[ve->vertex_buffer_index]) {
456 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
457 bound[ve->vertex_buffer_index] = true;
458 }
459 }
460 si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_VERTEX_BUFFER);
461 si_pm4_set_state(rctx, vertex_buffers, pm4);
462 }
463
464 static void si_state_draw(struct r600_context *rctx,
465 const struct pipe_draw_info *info,
466 const struct pipe_index_buffer *ib)
467 {
468 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
469
470 /* queries need some special values
471 * (this is non-zero if any query is active) */
472 if (rctx->num_cs_dw_queries_suspend) {
473 struct si_state_dsa *dsa = rctx->queued.named.dsa;
474
475 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
476 S_028004_PERFECT_ZPASS_COUNTS(1));
477 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
478 dsa->db_render_override |
479 S_02800C_NOOP_CULL_DISABLE(1));
480 }
481
482 /* draw packet */
483 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
484 if (ib->index_size == 4) {
485 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (R600_BIG_ENDIAN ?
486 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
487 } else {
488 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (R600_BIG_ENDIAN ?
489 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
490 }
491 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
492
493 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
494 si_pm4_cmd_add(pm4, info->instance_count);
495 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
496
497 if (info->indexed) {
498 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
499 rctx->index_buffer.index_size;
500 uint64_t va;
501 va = r600_resource_va(&rctx->screen->screen, ib->buffer);
502 va += ib->offset;
503
504 si_pm4_add_bo(pm4, (struct si_resource *)ib->buffer, RADEON_USAGE_READ);
505 si_cmd_draw_index_2(pm4, max_size, va, info->count,
506 V_0287F0_DI_SRC_SEL_DMA,
507 rctx->predicate_drawing);
508 } else {
509 uint32_t initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
510 initiator |= S_0287F0_USE_OPAQUE(!!info->count_from_stream_output);
511 si_cmd_draw_index_auto(pm4, info->count, initiator, rctx->predicate_drawing);
512 }
513 si_pm4_set_state(rctx, draw, pm4);
514 }
515
516 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
517 {
518 struct r600_context *rctx = (struct r600_context *)ctx;
519 struct pipe_index_buffer ib = {};
520 uint32_t cp_coher_cntl;
521
522 if (!info->count && (info->indexed || !info->count_from_stream_output))
523 return;
524
525 if (!rctx->ps_shader || !rctx->vs_shader)
526 return;
527
528 si_update_derived_state(rctx);
529 si_vertex_buffer_update(rctx);
530
531 if (info->indexed) {
532 /* Initialize the index buffer struct. */
533 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
534 ib.user_buffer = rctx->index_buffer.user_buffer;
535 ib.index_size = rctx->index_buffer.index_size;
536 ib.offset = rctx->index_buffer.offset + info->start * ib.index_size;
537
538 /* Translate or upload, if needed. */
539 r600_translate_index_buffer(rctx, &ib, info->count);
540
541 if (ib.user_buffer && !ib.buffer) {
542 r600_upload_index_buffer(rctx, &ib, info->count);
543 }
544
545 } else if (info->count_from_stream_output) {
546 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info->count_from_stream_output);
547 }
548
549 rctx->vs_shader_so_strides = rctx->vs_shader->current->so_strides;
550
551 if (!si_update_draw_info_state(rctx, info))
552 return;
553
554 si_state_draw(rctx, info, &ib);
555
556 cp_coher_cntl = si_pm4_sync_flags(rctx);
557 if (cp_coher_cntl) {
558 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
559 si_cmd_surface_sync(pm4, cp_coher_cntl);
560 si_pm4_set_state(rctx, sync, pm4);
561 }
562
563 /* Emit states. */
564 rctx->pm4_dirty_cdwords += si_pm4_dirty_dw(rctx);
565
566 si_need_cs_space(rctx, 0, TRUE);
567
568 si_pm4_emit_dirty(rctx);
569 rctx->pm4_dirty_cdwords = 0;
570
571 #if 0
572 /* Enable stream out if needed. */
573 if (rctx->streamout_start) {
574 r600_context_streamout_begin(rctx);
575 rctx->streamout_start = FALSE;
576 }
577 #endif
578
579
580 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY;
581
582 /* Set the depth buffer as dirty. */
583 if (rctx->framebuffer.zsbuf) {
584 struct pipe_surface *surf = rctx->framebuffer.zsbuf;
585 struct r600_resource_texture *rtex = (struct r600_resource_texture *)surf->texture;
586
587 rtex->dirty_db_mask |= 1 << surf->u.tex.level;
588 }
589
590 pipe_resource_reference(&ib.buffer, NULL);
591 }