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radeonsi: Better indexing of parameters in the pixel shader.
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "radeonsi_pipe.h"
32 #include "radeonsi_shader.h"
33 #include "si_state.h"
34 #include "sid.h"
35
36 /*
37 * Shaders
38 */
39
40 static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
41 {
42 struct r600_context *rctx = (struct r600_context *)ctx;
43 struct si_pm4_state *pm4;
44 unsigned num_sgprs, num_user_sgprs;
45 unsigned nparams, i;
46 uint64_t va;
47
48 if (si_pipe_shader_create(ctx, shader))
49 return;
50
51 si_pm4_delete_state(rctx, vs, shader->pm4);
52 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
53
54 si_pm4_inval_shader_cache(pm4);
55
56 /* Certain attributes (position, psize, etc.) don't count as params.
57 * VS is required to export at least one param and r600_shader_from_tgsi()
58 * takes care of adding a dummy export.
59 */
60 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
61 if (shader->shader.output[i].name != TGSI_SEMANTIC_POSITION)
62 nparams++;
63 }
64 if (nparams < 1)
65 nparams = 1;
66
67 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
68 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
69
70 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
71 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
72 S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
73 S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
74 S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE));
75
76 va = r600_resource_va(ctx->screen, (void *)shader->bo);
77 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
78 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
79 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
80
81 num_user_sgprs = SI_VS_NUM_USER_SGPR;
82 num_sgprs = shader->num_sgprs;
83 if (num_user_sgprs > num_sgprs)
84 num_sgprs = num_user_sgprs;
85 /* Last 2 reserved SGPRs are used for VCC */
86 num_sgprs += 2;
87 assert(num_sgprs <= 104);
88
89 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
90 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
91 S_00B128_SGPRS((num_sgprs - 1) / 8));
92 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
93 S_00B12C_USER_SGPR(num_user_sgprs));
94
95 si_pm4_bind_state(rctx, vs, shader->pm4);
96 }
97
98 static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
99 {
100 struct r600_context *rctx = (struct r600_context *)ctx;
101 struct si_pm4_state *pm4;
102 unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
103 unsigned num_sgprs, num_user_sgprs;
104 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
105 unsigned fragcoord_interp_mode = 0;
106 unsigned spi_baryc_cntl, spi_ps_input_ena;
107 uint64_t va;
108
109 if (si_pipe_shader_create(ctx, shader))
110 return;
111
112 si_pm4_delete_state(rctx, ps, shader->pm4);
113 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
114
115 si_pm4_inval_shader_cache(pm4);
116
117 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
118 for (i = 0; i < shader->shader.ninput; i++) {
119 if (shader->shader.input[i].name == TGSI_SEMANTIC_POSITION) {
120 if (shader->shader.input[i].centroid) {
121 /* fragcoord_interp_mode will be written to
122 * SPI_BARYC_CNTL.POS_FLOAT_LOCATION
123 * Possible vaules:
124 * 0 -> Position = pixel center (default)
125 * 1 -> Position = pixel centroid
126 * 2 -> Position = iterated sample number XXX:
127 * What does this mean?
128 */
129 fragcoord_interp_mode = 1;
130 }
131 continue;
132 }
133
134 /* XXX: Flat shading hangs the GPU */
135 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
136 (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
137 rctx->queued.named.rasterizer->flatshade))
138 have_linear = TRUE;
139 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
140 have_linear = TRUE;
141 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
142 have_perspective = TRUE;
143 if (shader->shader.input[i].centroid)
144 have_centroid = TRUE;
145 }
146
147 for (i = 0; i < shader->shader.noutput; i++) {
148 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
149 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
150 if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
151 db_shader_control |= 0; // XXX OP_VAL or TEST_VAL?
152 }
153 if (shader->shader.uses_kill)
154 db_shader_control |= S_02880C_KILL_ENABLE(1);
155
156 exports_ps = 0;
157 num_cout = 0;
158 for (i = 0; i < shader->shader.noutput; i++) {
159 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
160 shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
161 exports_ps |= 1;
162 else if (shader->shader.output[i].name == TGSI_SEMANTIC_COLOR) {
163 if (shader->shader.fs_write_all)
164 num_cout = shader->shader.nr_cbufs;
165 else
166 num_cout++;
167 }
168 }
169 if (!exports_ps) {
170 /* always at least export 1 component per pixel */
171 exports_ps = 2;
172 }
173
174 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.ninterp);
175
176 spi_baryc_cntl = 0;
177 if (have_perspective)
178 spi_baryc_cntl |= have_centroid ?
179 S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1);
180 if (have_linear)
181 spi_baryc_cntl |= have_centroid ?
182 S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1);
183 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(fragcoord_interp_mode);
184
185 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
186 spi_ps_input_ena = shader->spi_ps_input_ena;
187 /* we need to enable at least one of them, otherwise we hang the GPU */
188 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
189 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
190 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
191 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
192 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
193 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
194 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
195 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
196
197 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
198 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
199 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
200
201 /* XXX: Depends on Z buffer format? */
202 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, 0);
203
204 va = r600_resource_va(ctx->screen, (void *)shader->bo);
205 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
206 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
207 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
208
209 num_user_sgprs = SI_PS_NUM_USER_SGPR;
210 num_sgprs = shader->num_sgprs;
211 if (num_user_sgprs > num_sgprs)
212 num_sgprs = num_user_sgprs;
213 /* Last 2 reserved SGPRs are used for VCC */
214 num_sgprs += 2;
215 assert(num_sgprs <= 104);
216
217 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
218 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
219 S_00B028_SGPRS((num_sgprs - 1) / 8));
220 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
221 S_00B02C_USER_SGPR(num_user_sgprs));
222
223 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
224
225 shader->sprite_coord_enable = rctx->sprite_coord_enable;
226 si_pm4_bind_state(rctx, ps, shader->pm4);
227 }
228
229 /*
230 * Drawing
231 */
232
233 static unsigned si_conv_pipe_prim(unsigned pprim)
234 {
235 static const unsigned prim_conv[] = {
236 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
237 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
238 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
239 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
240 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
241 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
242 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
243 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
244 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
245 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
246 [PIPE_PRIM_LINES_ADJACENCY] = ~0,
247 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0,
248 [PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0,
249 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0
250 };
251 unsigned result = prim_conv[pprim];
252 if (result == ~0) {
253 R600_ERR("unsupported primitive type %d\n", pprim);
254 }
255 return result;
256 }
257
258 static bool si_update_draw_info_state(struct r600_context *rctx,
259 const struct pipe_draw_info *info)
260 {
261 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
262 unsigned prim = si_conv_pipe_prim(info->mode);
263 unsigned ls_mask = 0;
264
265 if (pm4 == NULL)
266 return false;
267
268 if (prim == ~0) {
269 FREE(pm4);
270 return false;
271 }
272
273 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
274 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
275 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
276 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET,
277 info->indexed ? info->index_bias : info->start);
278 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
279 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
280 #if 0
281 si_pm4_set_reg(pm4, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
282 si_pm4_set_reg(pm4, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance);
283 #endif
284
285 if (prim == V_008958_DI_PT_LINELIST)
286 ls_mask = 1;
287 else if (prim == V_008958_DI_PT_LINESTRIP)
288 ls_mask = 2;
289 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
290 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
291 rctx->pa_sc_line_stipple);
292
293 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
294 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
295 S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
296 } else {
297 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
298 }
299 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
300 prim == PIPE_PRIM_POINTS ? rctx->pa_cl_vs_out_cntl : 0
301 /*| (rctx->rasterizer->clip_plane_enable &
302 rctx->vs_shader->shader.clip_dist_write)*/);
303 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL, rctx->pa_cl_clip_cntl
304 /*| (rctx->vs_shader->shader.clip_dist_write ||
305 rctx->vs_shader->shader.vs_prohibit_ucps ?
306 0 : rctx->rasterizer->clip_plane_enable & 0x3F)*/);
307
308 si_pm4_set_state(rctx, draw_info, pm4);
309 return true;
310 }
311
312 static void si_update_alpha_ref(struct r600_context *rctx)
313 {
314 #if 0
315 unsigned alpha_ref;
316 struct r600_pipe_state rstate;
317
318 alpha_ref = rctx->alpha_ref;
319 rstate.nregs = 0;
320 if (rctx->export_16bpc)
321 alpha_ref &= ~0x1FFF;
322 si_pm4_set_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref);
323
324 si_pm4_set_state(rctx, TODO, pm4);
325 rctx->alpha_ref_dirty = false;
326 #endif
327 }
328
329 static void si_update_spi_map(struct r600_context *rctx)
330 {
331 struct si_shader *ps = &rctx->ps_shader->current->shader;
332 struct si_shader *vs = &rctx->vs_shader->current->shader;
333 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
334 unsigned i, j, tmp;
335
336 for (i = 0; i < ps->ninput; i++) {
337 tmp = 0;
338
339 #if 0
340 /* XXX: Flat shading hangs the GPU */
341 if (ps->input[i].name == TGSI_SEMANTIC_POSITION ||
342 ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
343 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
344 rctx->rasterizer && rctx->rasterizer->flatshade)) {
345 tmp |= S_028644_FLAT_SHADE(1);
346 }
347 #endif
348
349 if (ps->input[i].name == TGSI_SEMANTIC_GENERIC &&
350 rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
351 tmp |= S_028644_PT_SPRITE_TEX(1);
352 }
353
354 for (j = 0; j < vs->noutput; j++) {
355 if (ps->input[i].name == vs->output[j].name &&
356 ps->input[i].sid == vs->output[j].sid) {
357 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
358 break;
359 }
360 }
361
362 if (j == vs->noutput) {
363 /* No corresponding output found, load defaults into input */
364 tmp |= S_028644_OFFSET(0x20);
365 }
366
367 si_pm4_set_reg(pm4,
368 R_028644_SPI_PS_INPUT_CNTL_0 + ps->input[i].param_offset * 4,
369 tmp);
370 }
371
372 si_pm4_set_state(rctx, spi, pm4);
373 }
374
375 static void si_update_derived_state(struct r600_context *rctx)
376 {
377 struct pipe_context * ctx = (struct pipe_context*)rctx;
378 unsigned ps_dirty = 0;
379
380 if (!rctx->blitter->running) {
381 if (rctx->have_depth_fb || rctx->have_depth_texture)
382 si_flush_depth_textures(rctx);
383 }
384
385 si_shader_select(ctx, rctx->ps_shader, &ps_dirty);
386
387 if (rctx->alpha_ref_dirty) {
388 si_update_alpha_ref(rctx);
389 }
390
391 if (!rctx->vs_shader->current->pm4) {
392 si_pipe_shader_vs(ctx, rctx->vs_shader->current);
393 }
394
395 if (!rctx->ps_shader->current->pm4) {
396 si_pipe_shader_ps(ctx, rctx->ps_shader->current);
397 ps_dirty = 0;
398 }
399 if (!rctx->ps_shader->current->bo) {
400 if (!rctx->dummy_pixel_shader->pm4)
401 si_pipe_shader_ps(ctx, rctx->dummy_pixel_shader);
402 else
403 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
404
405 ps_dirty = 0;
406 }
407
408 if (ps_dirty) {
409 si_pm4_bind_state(rctx, ps, rctx->ps_shader->current->pm4);
410 }
411
412 if (si_pm4_state_changed(rctx, ps) || si_pm4_state_changed(rctx, vs)) {
413 si_update_spi_map(rctx);
414 }
415 }
416
417 static void si_vertex_buffer_update(struct r600_context *rctx)
418 {
419 struct pipe_context *ctx = &rctx->context;
420 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
421 bool bound[PIPE_MAX_ATTRIBS] = {};
422 unsigned i, count;
423 uint64_t va;
424
425 si_pm4_inval_vertex_cache(pm4);
426
427 /* bind vertex buffer once */
428 count = rctx->vertex_elements->count;
429 assert(count <= 256 / 4);
430
431 si_pm4_sh_data_begin(pm4);
432 for (i = 0 ; i < count; i++) {
433 struct pipe_vertex_element *ve = &rctx->vertex_elements->elements[i];
434 struct pipe_vertex_buffer *vb;
435 struct si_resource *rbuffer;
436 unsigned offset;
437
438 if (ve->vertex_buffer_index >= rctx->nr_vertex_buffers)
439 continue;
440
441 vb = &rctx->vertex_buffer[ve->vertex_buffer_index];
442 rbuffer = (struct si_resource*)vb->buffer;
443 if (rbuffer == NULL)
444 continue;
445
446 offset = 0;
447 offset += vb->buffer_offset;
448 offset += ve->src_offset;
449
450 va = r600_resource_va(ctx->screen, (void*)rbuffer);
451 va += offset;
452
453 /* Fill in T# buffer resource description */
454 si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF);
455 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
456 S_008F04_STRIDE(vb->stride)));
457 si_pm4_sh_data_add(pm4, (vb->buffer->width0 - vb->buffer_offset) /
458 MAX2(vb->stride, 1));
459 si_pm4_sh_data_add(pm4, rctx->vertex_elements->rsrc_word3[i]);
460
461 if (!bound[ve->vertex_buffer_index]) {
462 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
463 bound[ve->vertex_buffer_index] = true;
464 }
465 }
466 si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_VERTEX_BUFFER);
467 si_pm4_set_state(rctx, vertex_buffers, pm4);
468 }
469
470 static void si_state_draw(struct r600_context *rctx,
471 const struct pipe_draw_info *info,
472 const struct pipe_index_buffer *ib)
473 {
474 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
475
476 /* queries need some special values
477 * (this is non-zero if any query is active) */
478 if (rctx->num_cs_dw_queries_suspend) {
479 struct si_state_dsa *dsa = rctx->queued.named.dsa;
480
481 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
482 S_028004_PERFECT_ZPASS_COUNTS(1));
483 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
484 dsa->db_render_override |
485 S_02800C_NOOP_CULL_DISABLE(1));
486 }
487
488 /* draw packet */
489 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
490 if (ib->index_size == 4) {
491 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (R600_BIG_ENDIAN ?
492 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
493 } else {
494 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (R600_BIG_ENDIAN ?
495 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
496 }
497 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
498
499 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
500 si_pm4_cmd_add(pm4, info->instance_count);
501 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
502
503 if (info->indexed) {
504 uint32_t max_size = (ib->buffer->width0 - ib->offset) /
505 rctx->index_buffer.index_size;
506 uint64_t va;
507 va = r600_resource_va(&rctx->screen->screen, ib->buffer);
508 va += ib->offset;
509
510 si_pm4_add_bo(pm4, (struct si_resource *)ib->buffer, RADEON_USAGE_READ);
511 si_cmd_draw_index_2(pm4, max_size, va, info->count,
512 V_0287F0_DI_SRC_SEL_DMA,
513 rctx->predicate_drawing);
514 } else {
515 uint32_t initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
516 initiator |= S_0287F0_USE_OPAQUE(!!info->count_from_stream_output);
517 si_cmd_draw_index_auto(pm4, info->count, initiator, rctx->predicate_drawing);
518 }
519 si_pm4_set_state(rctx, draw, pm4);
520 }
521
522 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
523 {
524 struct r600_context *rctx = (struct r600_context *)ctx;
525 struct pipe_index_buffer ib = {};
526 uint32_t cp_coher_cntl;
527
528 if ((!info->count && (info->indexed || !info->count_from_stream_output)) ||
529 (info->indexed && !rctx->index_buffer.buffer)) {
530 return;
531 }
532
533 if (!rctx->ps_shader || !rctx->vs_shader)
534 return;
535
536 si_update_derived_state(rctx);
537 si_vertex_buffer_update(rctx);
538
539 if (info->indexed) {
540 /* Initialize the index buffer struct. */
541 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
542 ib.index_size = rctx->index_buffer.index_size;
543 ib.offset = rctx->index_buffer.offset + info->start * ib.index_size;
544
545 /* Translate or upload, if needed. */
546 r600_translate_index_buffer(rctx, &ib, info->count);
547
548 if (ib.user_buffer) {
549 r600_upload_index_buffer(rctx, &ib, info->count);
550 }
551
552 } else if (info->count_from_stream_output) {
553 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info->count_from_stream_output);
554 }
555
556 rctx->vs_shader_so_strides = rctx->vs_shader->current->so_strides;
557
558 if (!si_update_draw_info_state(rctx, info))
559 return;
560
561 si_state_draw(rctx, info, &ib);
562
563 cp_coher_cntl = si_pm4_sync_flags(rctx);
564 if (cp_coher_cntl) {
565 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
566 si_cmd_surface_sync(pm4, cp_coher_cntl);
567 si_pm4_set_state(rctx, sync, pm4);
568 }
569
570 /* Emit states. */
571 rctx->pm4_dirty_cdwords += si_pm4_dirty_dw(rctx);
572
573 si_need_cs_space(rctx, 0, TRUE);
574
575 si_pm4_emit_dirty(rctx);
576 rctx->pm4_dirty_cdwords = 0;
577
578 #if 0
579 /* Enable stream out if needed. */
580 if (rctx->streamout_start) {
581 r600_context_streamout_begin(rctx);
582 rctx->streamout_start = FALSE;
583 }
584 #endif
585
586
587 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY;
588
589 if (rctx->framebuffer.zsbuf)
590 {
591 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
592 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
593 }
594
595 pipe_resource_reference(&ib.buffer, NULL);
596 }