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radeonsi: remove useless variable si_context::pm4_dirty_cdwords
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "radeon/r600_cs.h"
30 #include "sid.h"
31
32 #include "util/u_format.h"
33 #include "util/u_index_modify.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36 #include "util/u_upload_mgr.h"
37
38 /*
39 * Shaders
40 */
41
42 static void si_shader_es(struct si_shader *shader)
43 {
44 struct si_pm4_state *pm4;
45 unsigned num_sgprs, num_user_sgprs;
46 unsigned vgpr_comp_cnt;
47 uint64_t va;
48
49 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
50
51 if (pm4 == NULL)
52 return;
53
54 va = shader->bo->gpu_address;
55 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
56
57 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
58
59 num_user_sgprs = SI_VS_NUM_USER_SGPR;
60 num_sgprs = shader->num_sgprs;
61 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
62 if ((num_user_sgprs + 1) > num_sgprs) {
63 /* Last 2 reserved SGPRs are used for VCC */
64 num_sgprs = num_user_sgprs + 1 + 2;
65 }
66 assert(num_sgprs <= 104);
67
68 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
69 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
70 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
71 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
72 S_00B328_SGPRS((num_sgprs - 1) / 8) |
73 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt));
74 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
75 S_00B32C_USER_SGPR(num_user_sgprs));
76 }
77
78 static void si_shader_gs(struct si_shader *shader)
79 {
80 unsigned gs_vert_itemsize = shader->selector->info.num_outputs * (16 >> 2);
81 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
82 unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
83 unsigned cut_mode;
84 struct si_pm4_state *pm4;
85 unsigned num_sgprs, num_user_sgprs;
86 uint64_t va;
87
88 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
89 assert(gsvs_itemsize < (1 << 15));
90
91 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
92
93 if (pm4 == NULL)
94 return;
95
96 if (gs_max_vert_out <= 128) {
97 cut_mode = V_028A40_GS_CUT_128;
98 } else if (gs_max_vert_out <= 256) {
99 cut_mode = V_028A40_GS_CUT_256;
100 } else if (gs_max_vert_out <= 512) {
101 cut_mode = V_028A40_GS_CUT_512;
102 } else {
103 assert(gs_max_vert_out <= 1024);
104 cut_mode = V_028A40_GS_CUT_1024;
105 }
106
107 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
108 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
109 S_028A40_CUT_MODE(cut_mode)|
110 S_028A40_ES_WRITE_OPTIMIZE(1) |
111 S_028A40_GS_WRITE_OPTIMIZE(1));
112
113 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
114 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize);
115 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize);
116
117 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
118 util_bitcount64(shader->selector->gs_used_inputs) * (16 >> 2));
119 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
120
121 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
122
123 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
124
125 va = shader->bo->gpu_address;
126 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
127 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
128 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
129
130 num_user_sgprs = SI_GS_NUM_USER_SGPR;
131 num_sgprs = shader->num_sgprs;
132 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
133 if ((num_user_sgprs + 2) > num_sgprs) {
134 /* Last 2 reserved SGPRs are used for VCC */
135 num_sgprs = num_user_sgprs + 2 + 2;
136 }
137 assert(num_sgprs <= 104);
138
139 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
140 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
141 S_00B228_SGPRS((num_sgprs - 1) / 8));
142 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
143 S_00B22C_USER_SGPR(num_user_sgprs));
144 }
145
146 static void si_shader_vs(struct si_shader *shader)
147 {
148 struct tgsi_shader_info *info = &shader->selector->info;
149 struct si_pm4_state *pm4;
150 unsigned num_sgprs, num_user_sgprs;
151 unsigned nparams, i, vgpr_comp_cnt;
152 uint64_t va;
153 unsigned window_space =
154 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
155
156 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
157
158 if (pm4 == NULL)
159 return;
160
161 va = shader->bo->gpu_address;
162 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
163
164 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
165
166 if (shader->is_gs_copy_shader)
167 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
168 else
169 num_user_sgprs = SI_VS_NUM_USER_SGPR;
170
171 num_sgprs = shader->num_sgprs;
172 if (num_user_sgprs > num_sgprs) {
173 /* Last 2 reserved SGPRs are used for VCC */
174 num_sgprs = num_user_sgprs + 2;
175 }
176 assert(num_sgprs <= 104);
177
178 /* Certain attributes (position, psize, etc.) don't count as params.
179 * VS is required to export at least one param and r600_shader_from_tgsi()
180 * takes care of adding a dummy export.
181 */
182 for (nparams = 0, i = 0 ; i < info->num_outputs; i++) {
183 switch (info->output_semantic_name[i]) {
184 case TGSI_SEMANTIC_CLIPVERTEX:
185 case TGSI_SEMANTIC_POSITION:
186 case TGSI_SEMANTIC_PSIZE:
187 break;
188 default:
189 nparams++;
190 }
191 }
192 if (nparams < 1)
193 nparams = 1;
194
195 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
196 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
197
198 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
199 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
200 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
201 V_02870C_SPI_SHADER_4COMP :
202 V_02870C_SPI_SHADER_NONE) |
203 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
204 V_02870C_SPI_SHADER_4COMP :
205 V_02870C_SPI_SHADER_NONE) |
206 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
207 V_02870C_SPI_SHADER_4COMP :
208 V_02870C_SPI_SHADER_NONE));
209
210 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
211 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
212 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
213 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
214 S_00B128_SGPRS((num_sgprs - 1) / 8) |
215 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
216 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
217 S_00B12C_USER_SGPR(num_user_sgprs) |
218 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
219 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
220 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
221 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
222 S_00B12C_SO_EN(!!shader->selector->so.num_outputs));
223 if (window_space)
224 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
225 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
226 else
227 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
228 S_028818_VTX_W0_FMT(1) |
229 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
230 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
231 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
232 }
233
234 static void si_shader_ps(struct si_shader *shader)
235 {
236 struct tgsi_shader_info *info = &shader->selector->info;
237 struct si_pm4_state *pm4;
238 unsigned i, spi_ps_in_control;
239 unsigned num_sgprs, num_user_sgprs;
240 unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
241 uint64_t va;
242
243 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
244
245 if (pm4 == NULL)
246 return;
247
248 for (i = 0; i < info->num_inputs; i++) {
249 switch (info->input_semantic_name[i]) {
250 case TGSI_SEMANTIC_POSITION:
251 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
252 * Possible vaules:
253 * 0 -> Position = pixel center (default)
254 * 1 -> Position = pixel centroid
255 * 2 -> Position = at sample position
256 */
257 switch (info->input_interpolate_loc[i]) {
258 case TGSI_INTERPOLATE_LOC_CENTROID:
259 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
260 break;
261 case TGSI_INTERPOLATE_LOC_SAMPLE:
262 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
263 break;
264 }
265
266 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
267 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
268 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
269 break;
270 }
271 }
272
273 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
274 S_0286D8_BC_OPTIMIZE_DISABLE(1);
275
276 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
277 spi_ps_input_ena = shader->spi_ps_input_ena;
278 /* we need to enable at least one of them, otherwise we hang the GPU */
279 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
280 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
281 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
282 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
283 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
284 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
285 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
286 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
287
288 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
289 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
290 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
291
292 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
293 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
294 shader->spi_shader_col_format);
295 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
296
297 va = shader->bo->gpu_address;
298 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
299 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
300 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
301
302 num_user_sgprs = SI_PS_NUM_USER_SGPR;
303 num_sgprs = shader->num_sgprs;
304 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
305 if ((num_user_sgprs + 1) > num_sgprs) {
306 /* Last 2 reserved SGPRs are used for VCC */
307 num_sgprs = num_user_sgprs + 1 + 2;
308 }
309 assert(num_sgprs <= 104);
310
311 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
312 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
313 S_00B028_SGPRS((num_sgprs - 1) / 8));
314 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
315 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
316 S_00B02C_USER_SGPR(num_user_sgprs));
317 }
318
319 void si_shader_init_pm4_state(struct si_shader *shader)
320 {
321 switch (shader->selector->type) {
322 case PIPE_SHADER_VERTEX:
323 if (shader->key.vs.as_es)
324 si_shader_es(shader);
325 else
326 si_shader_vs(shader);
327 break;
328 case PIPE_SHADER_GEOMETRY:
329 si_shader_gs(shader);
330 si_shader_vs(shader->gs_copy_shader);
331 break;
332 case PIPE_SHADER_FRAGMENT:
333 si_shader_ps(shader);
334 break;
335 default:
336 assert(0);
337 }
338 }
339
340 /*
341 * Drawing
342 */
343
344 static unsigned si_conv_pipe_prim(unsigned pprim)
345 {
346 static const unsigned prim_conv[] = {
347 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
348 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
349 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
350 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
351 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
352 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
353 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
354 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
355 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
356 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
357 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
358 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
359 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
360 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
361 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
362 };
363 unsigned result = prim_conv[pprim];
364 if (result == ~0) {
365 R600_ERR("unsupported primitive type %d\n", pprim);
366 }
367 return result;
368 }
369
370 static unsigned si_conv_prim_to_gs_out(unsigned mode)
371 {
372 static const int prim_conv[] = {
373 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
374 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
375 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
376 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
377 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
378 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
379 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
380 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
381 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
382 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
383 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
384 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
385 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
386 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
387 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
388 };
389 assert(mode < Elements(prim_conv));
390
391 return prim_conv[mode];
392 }
393
394 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
395 const struct pipe_draw_info *info)
396 {
397 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
398 unsigned prim = info->mode;
399 unsigned primgroup_size = 128; /* recommended without a GS */
400
401 /* SWITCH_ON_EOP(0) is always preferable. */
402 bool wd_switch_on_eop = false;
403 bool ia_switch_on_eop = false;
404 bool partial_vs_wave = false;
405
406 if (sctx->gs_shader)
407 primgroup_size = 64; /* recommended with a GS */
408
409 /* This is a hardware requirement. */
410 if ((rs && rs->line_stipple_enable) ||
411 (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
412 ia_switch_on_eop = true;
413 wd_switch_on_eop = true;
414 }
415
416 if (sctx->b.streamout.streamout_enabled ||
417 sctx->b.streamout.prims_gen_query_enabled)
418 partial_vs_wave = true;
419
420 if (sctx->b.chip_class >= CIK) {
421 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
422 * 4 shader engines. Set 1 to pass the assertion below.
423 * The other cases are hardware requirements. */
424 if (sctx->b.screen->info.max_se < 4 ||
425 prim == PIPE_PRIM_POLYGON ||
426 prim == PIPE_PRIM_LINE_LOOP ||
427 prim == PIPE_PRIM_TRIANGLE_FAN ||
428 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
429 info->primitive_restart)
430 wd_switch_on_eop = true;
431
432 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
433 * We don't know that for indirect drawing, so treat it as
434 * always problematic. */
435 if (sctx->b.family == CHIP_HAWAII &&
436 (info->indirect || info->instance_count > 1))
437 wd_switch_on_eop = true;
438
439 /* If the WD switch is false, the IA switch must be false too. */
440 assert(wd_switch_on_eop || !ia_switch_on_eop);
441 }
442
443 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
444 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
445 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
446 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0);
447 }
448
449 static bool si_update_draw_info_state(struct si_context *sctx,
450 const struct pipe_draw_info *info,
451 const struct pipe_index_buffer *ib)
452 {
453 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
454 struct si_shader *vs = si_get_vs_state(sctx);
455 unsigned window_space =
456 vs->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
457 unsigned prim = si_conv_pipe_prim(info->mode);
458 unsigned gs_out_prim =
459 si_conv_prim_to_gs_out(sctx->gs_shader ?
460 sctx->gs_shader->gs_output_prim :
461 info->mode);
462 unsigned ls_mask = 0;
463 unsigned ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info);
464
465 if (pm4 == NULL)
466 return false;
467
468 if (prim == ~0) {
469 FREE(pm4);
470 return false;
471 }
472
473 if (sctx->b.chip_class >= CIK) {
474 si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
475 ib->index_size == 4 ? 0xFC000000 : 0xFC00);
476
477 si_pm4_cmd_begin(pm4, PKT3_DRAW_PREAMBLE);
478 si_pm4_cmd_add(pm4, prim); /* VGT_PRIMITIVE_TYPE */
479 si_pm4_cmd_add(pm4, ia_multi_vgt_param); /* IA_MULTI_VGT_PARAM */
480 si_pm4_cmd_add(pm4, 0); /* VGT_LS_HS_CONFIG */
481 si_pm4_cmd_end(pm4, false);
482 } else {
483 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
484 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
485 }
486
487 si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
488 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
489 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
490
491 if (prim == V_008958_DI_PT_LINELIST)
492 ls_mask = 1;
493 else if (prim == V_008958_DI_PT_LINESTRIP)
494 ls_mask = 2;
495 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
496 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
497 sctx->pa_sc_line_stipple);
498
499 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
500 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
501 S_028814_PROVOKING_VTX_LAST(1) | sctx->pa_su_sc_mode_cntl);
502 } else {
503 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, sctx->pa_su_sc_mode_cntl);
504 }
505 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
506 S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
507 S_02881C_USE_VTX_EDGE_FLAG(vs->vs_out_edgeflag) |
508 S_02881C_USE_VTX_RENDER_TARGET_INDX(vs->vs_out_layer) |
509 S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs->clip_dist_write & 0x0F) != 0) |
510 S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs->clip_dist_write & 0xF0) != 0) |
511 S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write) |
512 (sctx->queued.named.rasterizer->clip_plane_enable &
513 vs->clip_dist_write));
514 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL,
515 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
516 (vs->clip_dist_write ? 0 :
517 sctx->queued.named.rasterizer->clip_plane_enable & 0x3F) |
518 S_028810_CLIP_DISABLE(window_space));
519
520 si_pm4_set_state(sctx, draw_info, pm4);
521 return true;
522 }
523
524 static void si_update_spi_map(struct si_context *sctx)
525 {
526 struct si_shader *ps = sctx->ps_shader->current;
527 struct si_shader *vs = si_get_vs_state(sctx);
528 struct tgsi_shader_info *psinfo = &ps->selector->info;
529 struct tgsi_shader_info *vsinfo = &vs->selector->info;
530 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
531 unsigned i, j, tmp;
532
533 for (i = 0; i < psinfo->num_inputs; i++) {
534 unsigned name = psinfo->input_semantic_name[i];
535 unsigned index = psinfo->input_semantic_index[i];
536 unsigned interpolate = psinfo->input_interpolate[i];
537 unsigned param_offset = ps->ps_input_param_offset[i];
538
539 if (name == TGSI_SEMANTIC_POSITION)
540 /* Read from preloaded VGPRs, not parameters */
541 continue;
542
543 bcolor:
544 tmp = 0;
545
546 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
547 (interpolate == TGSI_INTERPOLATE_COLOR &&
548 ps->key.ps.flatshade)) {
549 tmp |= S_028644_FLAT_SHADE(1);
550 }
551
552 if (name == TGSI_SEMANTIC_GENERIC &&
553 sctx->sprite_coord_enable & (1 << index)) {
554 tmp |= S_028644_PT_SPRITE_TEX(1);
555 }
556
557 for (j = 0; j < vsinfo->num_outputs; j++) {
558 if (name == vsinfo->output_semantic_name[j] &&
559 index == vsinfo->output_semantic_index[j]) {
560 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
561 break;
562 }
563 }
564
565 if (j == vsinfo->num_outputs) {
566 /* No corresponding output found, load defaults into input */
567 tmp |= S_028644_OFFSET(0x20);
568 }
569
570 si_pm4_set_reg(pm4,
571 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
572 tmp);
573
574 if (name == TGSI_SEMANTIC_COLOR &&
575 ps->key.ps.color_two_side) {
576 name = TGSI_SEMANTIC_BCOLOR;
577 param_offset++;
578 goto bcolor;
579 }
580 }
581
582 si_pm4_set_state(sctx, spi, pm4);
583 }
584
585 /* Initialize state related to ESGS / GSVS ring buffers */
586 static void si_init_gs_rings(struct si_context *sctx)
587 {
588 unsigned esgs_ring_size = 128 * 1024;
589 unsigned gsvs_ring_size = 64 * 1024 * 1024;
590
591 assert(!sctx->gs_rings);
592 sctx->gs_rings = CALLOC_STRUCT(si_pm4_state);
593
594 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
595 PIPE_USAGE_DEFAULT, esgs_ring_size);
596
597 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
598 PIPE_USAGE_DEFAULT, gsvs_ring_size);
599
600 if (sctx->b.chip_class >= CIK) {
601 si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
602 esgs_ring_size / 256);
603 si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
604 gsvs_ring_size / 256);
605 } else {
606 si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
607 esgs_ring_size / 256);
608 si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
609 gsvs_ring_size / 256);
610 }
611
612 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
613 sctx->esgs_ring, 0, esgs_ring_size,
614 true, true, 4, 64);
615 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
616 sctx->esgs_ring, 0, esgs_ring_size,
617 false, false, 0, 0);
618 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
619 sctx->gsvs_ring, 0, gsvs_ring_size,
620 false, false, 0, 0);
621 }
622
623 static void si_update_derived_state(struct si_context *sctx)
624 {
625 struct pipe_context * ctx = (struct pipe_context*)sctx;
626
627 if (!sctx->blitter->running) {
628 /* Flush depth textures which need to be flushed. */
629 for (int i = 0; i < SI_NUM_SHADERS; i++) {
630 if (sctx->samplers[i].depth_texture_mask) {
631 si_flush_depth_textures(sctx, &sctx->samplers[i]);
632 }
633 if (sctx->samplers[i].compressed_colortex_mask) {
634 si_decompress_color_textures(sctx, &sctx->samplers[i]);
635 }
636 }
637 }
638
639 if (sctx->gs_shader) {
640 si_shader_select(ctx, sctx->gs_shader);
641 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
642 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
643
644 sctx->b.streamout.stride_in_dw = sctx->gs_shader->so.stride;
645
646 si_shader_select(ctx, sctx->vs_shader);
647 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
648
649 if (!sctx->gs_rings)
650 si_init_gs_rings(sctx);
651 if (sctx->emitted.named.gs_rings != sctx->gs_rings)
652 sctx->b.flags |= R600_CONTEXT_VGT_FLUSH;
653 si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
654
655 si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
656 sctx->gsvs_ring,
657 sctx->gs_shader->gs_max_out_vertices *
658 sctx->gs_shader->info.num_outputs * 16,
659 64, true, true, 4, 16);
660
661 if (!sctx->gs_on) {
662 sctx->gs_on = CALLOC_STRUCT(si_pm4_state);
663
664 si_pm4_set_reg(sctx->gs_on, R_028B54_VGT_SHADER_STAGES_EN,
665 S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
666 S_028B54_GS_EN(1) |
667 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER));
668 }
669 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_on);
670 } else {
671 si_shader_select(ctx, sctx->vs_shader);
672 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
673
674 sctx->b.streamout.stride_in_dw = sctx->vs_shader->so.stride;
675
676 if (!sctx->gs_off) {
677 sctx->gs_off = CALLOC_STRUCT(si_pm4_state);
678
679 si_pm4_set_reg(sctx->gs_off, R_028A40_VGT_GS_MODE, 0);
680 si_pm4_set_reg(sctx->gs_off, R_028B54_VGT_SHADER_STAGES_EN, 0);
681 }
682 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_off);
683 si_pm4_bind_state(sctx, gs_rings, NULL);
684 si_pm4_bind_state(sctx, gs, NULL);
685 si_pm4_bind_state(sctx, es, NULL);
686 }
687
688 si_shader_select(ctx, sctx->ps_shader);
689
690 if (!sctx->ps_shader->current) {
691 struct si_shader_selector *sel;
692
693 /* use a dummy shader if compiling the shader (variant) failed */
694 si_make_dummy_ps(sctx);
695 sel = sctx->dummy_pixel_shader;
696 si_shader_select(ctx, sel);
697 sctx->ps_shader->current = sel->current;
698 }
699
700 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
701
702 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs))
703 si_update_spi_map(sctx);
704
705 if (sctx->ps_db_shader_control != sctx->ps_shader->current->db_shader_control) {
706 sctx->ps_db_shader_control = sctx->ps_shader->current->db_shader_control;
707 sctx->db_render_state.dirty = true;
708 }
709 }
710
711 static void si_emit_draw_packets(struct si_context *sctx,
712 const struct pipe_draw_info *info,
713 const struct pipe_index_buffer *ib)
714 {
715 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
716 unsigned sh_base_reg = (sctx->gs_shader ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
717 R_00B130_SPI_SHADER_USER_DATA_VS_0);
718
719 if (info->count_from_stream_output) {
720 struct r600_so_target *t =
721 (struct r600_so_target*)info->count_from_stream_output;
722 uint64_t va = t->buf_filled_size->gpu_address +
723 t->buf_filled_size_offset;
724
725 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
726 t->stride_in_dw);
727
728 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
729 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
730 COPY_DATA_DST_SEL(COPY_DATA_REG) |
731 COPY_DATA_WR_CONFIRM);
732 radeon_emit(cs, va); /* src address lo */
733 radeon_emit(cs, va >> 32); /* src address hi */
734 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
735 radeon_emit(cs, 0); /* unused */
736
737 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
738 t->buf_filled_size, RADEON_USAGE_READ,
739 RADEON_PRIO_MIN);
740 }
741
742 /* draw packet */
743 if (info->indexed) {
744 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
745
746 if (ib->index_size == 4) {
747 radeon_emit(cs, V_028A7C_VGT_INDEX_32 | (SI_BIG_ENDIAN ?
748 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
749 } else {
750 radeon_emit(cs, V_028A7C_VGT_INDEX_16 | (SI_BIG_ENDIAN ?
751 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
752 }
753 }
754
755 if (!info->indirect) {
756 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
757 radeon_emit(cs, info->instance_count);
758
759 si_write_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
760 radeon_emit(cs, info->indexed ? info->index_bias : info->start);
761 radeon_emit(cs, info->start_instance);
762 } else {
763 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
764 (struct r600_resource *)info->indirect,
765 RADEON_USAGE_READ, RADEON_PRIO_MIN);
766 }
767
768 if (info->indexed) {
769 uint32_t index_max_size = (ib->buffer->width0 - ib->offset) /
770 ib->index_size;
771 uint64_t index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
772
773 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
774 (struct r600_resource *)ib->buffer,
775 RADEON_USAGE_READ, RADEON_PRIO_MIN);
776
777 if (info->indirect) {
778 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
779
780 assert(indirect_va % 8 == 0);
781 assert(index_va % 2 == 0);
782 assert(info->indirect_offset % 4 == 0);
783
784 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
785 radeon_emit(cs, 1);
786 radeon_emit(cs, indirect_va);
787 radeon_emit(cs, indirect_va >> 32);
788
789 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
790 radeon_emit(cs, index_va);
791 radeon_emit(cs, index_va >> 32);
792
793 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
794 radeon_emit(cs, index_max_size);
795
796 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT, 3, sctx->b.predicate_drawing));
797 radeon_emit(cs, info->indirect_offset);
798 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
799 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
800 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
801 } else {
802 index_va += info->start * ib->index_size;
803
804 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, sctx->b.predicate_drawing));
805 radeon_emit(cs, index_max_size);
806 radeon_emit(cs, index_va);
807 radeon_emit(cs, (index_va >> 32UL) & 0xFF);
808 radeon_emit(cs, info->count);
809 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
810 }
811 } else {
812 if (info->indirect) {
813 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
814
815 assert(indirect_va % 8 == 0);
816 assert(info->indirect_offset % 4 == 0);
817
818 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
819 radeon_emit(cs, 1);
820 radeon_emit(cs, indirect_va);
821 radeon_emit(cs, indirect_va >> 32);
822
823 radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, sctx->b.predicate_drawing));
824 radeon_emit(cs, info->indirect_offset);
825 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
826 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
827 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
828 } else {
829 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, sctx->b.predicate_drawing));
830 radeon_emit(cs, info->count);
831 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
832 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
833 }
834 }
835 }
836
837 void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom)
838 {
839 struct radeon_winsys_cs *cs = sctx->rings.gfx.cs;
840 uint32_t cp_coher_cntl = 0;
841 uint32_t compute =
842 PKT3_SHADER_TYPE_S(!!(sctx->flags & R600_CONTEXT_FLAG_COMPUTE));
843
844 /* XXX SI flushes both ICACHE and KCACHE if either flag is set.
845 * XXX CIK shouldn't have this issue. Test CIK before separating the flags
846 * XXX to ensure there is no regression. Also find out if there is another
847 * XXX way to flush either ICACHE or KCACHE but not both for SI. */
848 if (sctx->flags & (R600_CONTEXT_INV_SHADER_CACHE |
849 R600_CONTEXT_INV_CONST_CACHE)) {
850 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1) |
851 S_0085F0_SH_KCACHE_ACTION_ENA(1);
852 }
853 if (sctx->flags & (R600_CONTEXT_INV_TEX_CACHE |
854 R600_CONTEXT_STREAMOUT_FLUSH)) {
855 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1) |
856 S_0085F0_TCL1_ACTION_ENA(1);
857 }
858 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB) {
859 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
860 S_0085F0_CB0_DEST_BASE_ENA(1) |
861 S_0085F0_CB1_DEST_BASE_ENA(1) |
862 S_0085F0_CB2_DEST_BASE_ENA(1) |
863 S_0085F0_CB3_DEST_BASE_ENA(1) |
864 S_0085F0_CB4_DEST_BASE_ENA(1) |
865 S_0085F0_CB5_DEST_BASE_ENA(1) |
866 S_0085F0_CB6_DEST_BASE_ENA(1) |
867 S_0085F0_CB7_DEST_BASE_ENA(1);
868 }
869 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB) {
870 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
871 S_0085F0_DB_DEST_BASE_ENA(1);
872 }
873
874 if (cp_coher_cntl) {
875 if (sctx->chip_class >= CIK) {
876 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) | compute);
877 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
878 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
879 radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */
880 radeon_emit(cs, 0); /* CP_COHER_BASE */
881 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
882 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
883 } else {
884 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0) | compute);
885 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
886 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
887 radeon_emit(cs, 0); /* CP_COHER_BASE */
888 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
889 }
890 }
891
892 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META) {
893 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
894 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
895 }
896 if (sctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB_META) {
897 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
898 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
899 }
900 if (sctx->flags & R600_CONTEXT_FLUSH_WITH_INV_L2) {
901 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
902 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH) | EVENT_INDEX(7) |
903 EVENT_WRITE_INV_L2);
904 }
905
906 if (sctx->flags & (R600_CONTEXT_WAIT_3D_IDLE |
907 R600_CONTEXT_PS_PARTIAL_FLUSH)) {
908 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
909 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
910 } else if (sctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
911 /* Needed if streamout buffers are going to be used as a source. */
912 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
913 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
914 }
915
916 if (sctx->flags & R600_CONTEXT_CS_PARTIAL_FLUSH) {
917 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
918 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
919 }
920
921 if (sctx->flags & R600_CONTEXT_VGT_FLUSH) {
922 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
923 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
924 }
925 if (sctx->flags & R600_CONTEXT_VGT_STREAMOUT_SYNC) {
926 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute);
927 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
928 }
929
930 sctx->flags = 0;
931 }
932
933 const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 21 }; /* number of CS dwords */
934
935 static void si_get_draw_start_count(struct si_context *sctx,
936 const struct pipe_draw_info *info,
937 unsigned *start, unsigned *count)
938 {
939 if (info->indirect) {
940 struct r600_resource *indirect =
941 (struct r600_resource*)info->indirect;
942 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
943 indirect, PIPE_TRANSFER_READ);
944 data += info->indirect_offset/sizeof(int);
945 *start = data[2];
946 *count = data[0];
947 } else {
948 *start = info->start;
949 *count = info->count;
950 }
951 }
952
953 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
954 {
955 struct si_context *sctx = (struct si_context *)ctx;
956 struct pipe_index_buffer ib = {};
957 uint32_t i;
958
959 if (!info->count && !info->indirect &&
960 (info->indexed || !info->count_from_stream_output))
961 return;
962
963 if (!sctx->ps_shader || !sctx->vs_shader)
964 return;
965
966 si_update_derived_state(sctx);
967
968 if (sctx->vertex_buffers_dirty) {
969 si_update_vertex_buffers(sctx);
970 sctx->vertex_buffers_dirty = false;
971 }
972
973 if (info->indexed) {
974 /* Initialize the index buffer struct. */
975 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
976 ib.user_buffer = sctx->index_buffer.user_buffer;
977 ib.index_size = sctx->index_buffer.index_size;
978 ib.offset = sctx->index_buffer.offset;
979
980 /* Translate or upload, if needed. */
981 if (ib.index_size == 1) {
982 struct pipe_resource *out_buffer = NULL;
983 unsigned out_offset, start, count, start_offset;
984 void *ptr;
985
986 si_get_draw_start_count(sctx, info, &start, &count);
987 start_offset = start * ib.index_size;
988
989 u_upload_alloc(sctx->b.uploader, start_offset, count * 2,
990 &out_offset, &out_buffer, &ptr);
991
992 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
993 ib.offset + start_offset,
994 count, ptr);
995
996 pipe_resource_reference(&ib.buffer, NULL);
997 ib.user_buffer = NULL;
998 ib.buffer = out_buffer;
999 /* info->start will be added by the drawing code */
1000 ib.offset = out_offset - start_offset;
1001 ib.index_size = 2;
1002 } else if (ib.user_buffer && !ib.buffer) {
1003 unsigned start, count, start_offset;
1004
1005 si_get_draw_start_count(sctx, info, &start, &count);
1006 start_offset = start * ib.index_size;
1007
1008 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
1009 (char*)ib.user_buffer + start_offset,
1010 &ib.offset, &ib.buffer);
1011 /* info->start will be added by the drawing code */
1012 ib.offset -= start_offset;
1013 }
1014 }
1015
1016 if (!si_update_draw_info_state(sctx, info, &ib))
1017 return;
1018
1019 /* Check flush flags. */
1020 if (sctx->b.flags)
1021 sctx->atoms.s.cache_flush->dirty = true;
1022
1023 si_need_cs_space(sctx, 0, TRUE);
1024
1025 /* Emit states. */
1026 for (i = 0; i < SI_NUM_ATOMS(sctx); i++) {
1027 if (sctx->atoms.array[i]->dirty) {
1028 sctx->atoms.array[i]->emit(&sctx->b, sctx->atoms.array[i]);
1029 sctx->atoms.array[i]->dirty = false;
1030 }
1031 }
1032
1033 si_pm4_emit_dirty(sctx);
1034 si_emit_draw_packets(sctx, info, &ib);
1035
1036 #if SI_TRACE_CS
1037 if (sctx->screen->b.trace_bo) {
1038 si_trace_emit(sctx);
1039 }
1040 #endif
1041
1042 /* Workaround for a VGT hang when streamout is enabled.
1043 * It must be done after drawing. */
1044 if (sctx->b.family == CHIP_HAWAII &&
1045 (sctx->b.streamout.streamout_enabled ||
1046 sctx->b.streamout.prims_gen_query_enabled)) {
1047 sctx->b.flags |= R600_CONTEXT_VGT_STREAMOUT_SYNC;
1048 }
1049
1050 /* Set the depth buffer as dirty. */
1051 if (sctx->framebuffer.state.zsbuf) {
1052 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1053 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1054
1055 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1056 }
1057 if (sctx->framebuffer.compressed_cb_mask) {
1058 struct pipe_surface *surf;
1059 struct r600_texture *rtex;
1060 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1061
1062 do {
1063 unsigned i = u_bit_scan(&mask);
1064 surf = sctx->framebuffer.state.cbufs[i];
1065 rtex = (struct r600_texture*)surf->texture;
1066
1067 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1068 } while (mask);
1069 }
1070
1071 pipe_resource_reference(&ib.buffer, NULL);
1072 sctx->b.num_draw_calls++;
1073 }
1074
1075 #if SI_TRACE_CS
1076 void si_trace_emit(struct si_context *sctx)
1077 {
1078 struct si_screen *sscreen = sctx->screen;
1079 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
1080 uint64_t va;
1081
1082 va = sscreen->b.trace_bo->gpu_address;
1083 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, sscreen->b.trace_bo,
1084 RADEON_USAGE_READWRITE, RADEON_PRIO_MIN);
1085 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1086 radeon_emit(cs, PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_MEM_SYNC) |
1087 PKT3_WRITE_DATA_WR_CONFIRM |
1088 PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME));
1089 radeon_emit(cs, va & 0xFFFFFFFFUL);
1090 radeon_emit(cs, (va >> 32UL) & 0xFFFFFFFFUL);
1091 radeon_emit(cs, cs->cdw);
1092 radeon_emit(cs, sscreen->b.cs_count);
1093 }
1094 #endif