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radeonsi: use pipe_draw_info::prim and primitive_restart indirectly
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32
33 #include "ac_debug.h"
34
35 /* special primitive types */
36 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
37
38 static unsigned si_conv_pipe_prim(unsigned mode)
39 {
40 static const unsigned prim_conv[] = {
41 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
42 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
43 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
44 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
45 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
46 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
47 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
48 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
49 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
50 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
51 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
55 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
56 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
57 };
58 assert(mode < ARRAY_SIZE(prim_conv));
59 return prim_conv[mode];
60 }
61
62 /**
63 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
64 * LS.LDS_SIZE is shared by all 3 shader stages.
65 *
66 * The information about LDS and other non-compile-time parameters is then
67 * written to userdata SGPRs.
68 */
69 static void si_emit_derived_tess_state(struct si_context *sctx,
70 const struct pipe_draw_info *info,
71 unsigned *num_patches)
72 {
73 struct radeon_cmdbuf *cs = sctx->gfx_cs;
74 struct si_shader *ls_current;
75 struct si_shader_selector *ls;
76 /* The TES pointer will only be used for sctx->last_tcs.
77 * It would be wrong to think that TCS = TES. */
78 struct si_shader_selector *tcs =
79 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
80 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
81 bool has_primid_instancing_bug = sctx->chip_class == GFX6 &&
82 sctx->screen->info.max_se == 1;
83 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
84 unsigned num_tcs_input_cp = info->vertices_per_patch;
85 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
86 unsigned num_tcs_patch_outputs;
87 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
88 unsigned input_patch_size, output_patch_size, output_patch0_offset;
89 unsigned perpatch_output_offset, lds_size;
90 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
91 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
92
93 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
94 if (sctx->chip_class >= GFX9) {
95 if (sctx->tcs_shader.cso)
96 ls_current = sctx->tcs_shader.current;
97 else
98 ls_current = sctx->fixed_func_tcs_shader.current;
99
100 ls = ls_current->key.part.tcs.ls;
101 } else {
102 ls_current = sctx->vs_shader.current;
103 ls = sctx->vs_shader.cso;
104 }
105
106 if (sctx->last_ls == ls_current &&
107 sctx->last_tcs == tcs &&
108 sctx->last_tes_sh_base == tes_sh_base &&
109 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
110 (!has_primid_instancing_bug ||
111 (sctx->last_tess_uses_primid == tess_uses_primid))) {
112 *num_patches = sctx->last_num_patches;
113 return;
114 }
115
116 sctx->last_ls = ls_current;
117 sctx->last_tcs = tcs;
118 sctx->last_tes_sh_base = tes_sh_base;
119 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
120 sctx->last_tess_uses_primid = tess_uses_primid;
121
122 /* This calculates how shader inputs and outputs among VS, TCS, and TES
123 * are laid out in LDS. */
124 num_tcs_inputs = util_last_bit64(ls->outputs_written);
125
126 if (sctx->tcs_shader.cso) {
127 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
128 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
129 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
130 } else {
131 /* No TCS. Route varyings from LS to TES. */
132 num_tcs_outputs = num_tcs_inputs;
133 num_tcs_output_cp = num_tcs_input_cp;
134 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
135 }
136
137 input_vertex_size = ls->lshs_vertex_stride;
138 output_vertex_size = num_tcs_outputs * 16;
139
140 input_patch_size = num_tcs_input_cp * input_vertex_size;
141
142 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
143 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
144
145 /* Ensure that we only need one wave per SIMD so we don't need to check
146 * resource usage. Also ensures that the number of tcs in and out
147 * vertices per threadgroup are at most 256.
148 */
149 unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
150 *num_patches = 256 / max_verts_per_patch;
151
152 /* Make sure that the data fits in LDS. This assumes the shaders only
153 * use LDS for the inputs and outputs.
154 *
155 * While GFX7 can use 64K per threadgroup, there is a hang on Stoney
156 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
157 * uses 32K at most on all GCN chips.
158 */
159 hardware_lds_size = 32768;
160 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
161 output_patch_size));
162
163 /* Make sure the output data fits in the offchip buffer */
164 *num_patches = MIN2(*num_patches,
165 (sctx->screen->tess_offchip_block_dw_size * 4) /
166 output_patch_size);
167
168 /* Not necessary for correctness, but improves performance.
169 * The hardware can do more, but the radeonsi shader constant is
170 * limited to 6 bits.
171 */
172 *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */
173
174 /* When distributed tessellation is unsupported, switch between SEs
175 * at a higher frequency to compensate for it.
176 */
177 if (!sctx->screen->has_distributed_tess && sctx->screen->info.max_se > 1)
178 *num_patches = MIN2(*num_patches, 16); /* recommended */
179
180 /* Make sure that vector lanes are reasonably occupied. It probably
181 * doesn't matter much because this is LS-HS, and TES is likely to
182 * occupy significantly more CUs.
183 */
184 unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
185 if (temp_verts_per_tg > 64 && temp_verts_per_tg % 64 < 48)
186 *num_patches = (temp_verts_per_tg & ~63) / max_verts_per_patch;
187
188 if (sctx->chip_class == GFX6) {
189 /* GFX6 bug workaround, related to power management. Limit LS-HS
190 * threadgroups to only one wave.
191 */
192 unsigned one_wave = 64 / max_verts_per_patch;
193 *num_patches = MIN2(*num_patches, one_wave);
194 }
195
196 /* The VGT HS block increments the patch ID unconditionally
197 * within a single threadgroup. This results in incorrect
198 * patch IDs when instanced draws are used.
199 *
200 * The intended solution is to restrict threadgroups to
201 * a single instance by setting SWITCH_ON_EOI, which
202 * should cause IA to split instances up. However, this
203 * doesn't work correctly on GFX6 when there is no other
204 * SE to switch to.
205 */
206 if (has_primid_instancing_bug && tess_uses_primid)
207 *num_patches = 1;
208
209 sctx->last_num_patches = *num_patches;
210
211 output_patch0_offset = input_patch_size * *num_patches;
212 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
213
214 /* Compute userdata SGPRs. */
215 assert(((input_vertex_size / 4) & ~0xff) == 0);
216 assert(((output_vertex_size / 4) & ~0xff) == 0);
217 assert(((input_patch_size / 4) & ~0x1fff) == 0);
218 assert(((output_patch_size / 4) & ~0x1fff) == 0);
219 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
220 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
221 assert(num_tcs_input_cp <= 32);
222 assert(num_tcs_output_cp <= 32);
223
224 uint64_t ring_va = si_resource(sctx->tess_rings)->gpu_address;
225 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
226
227 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
228 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
229 tcs_out_layout = (output_patch_size / 4) |
230 (num_tcs_input_cp << 13) |
231 ring_va;
232 tcs_out_offsets = (output_patch0_offset / 16) |
233 ((perpatch_output_offset / 16) << 16);
234 offchip_layout = *num_patches |
235 (num_tcs_output_cp << 6) |
236 (pervertex_output_patch_size * *num_patches << 12);
237
238 /* Compute the LDS size. */
239 lds_size = output_patch0_offset + output_patch_size * *num_patches;
240
241 if (sctx->chip_class >= GFX7) {
242 assert(lds_size <= 65536);
243 lds_size = align(lds_size, 512) / 512;
244 } else {
245 assert(lds_size <= 32768);
246 lds_size = align(lds_size, 256) / 256;
247 }
248
249 /* Set SI_SGPR_VS_STATE_BITS. */
250 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
251 C_VS_STATE_LS_OUT_VERTEX_SIZE;
252 sctx->current_vs_state |= tcs_in_layout;
253
254 if (sctx->chip_class >= GFX9) {
255 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
256 S_00B42C_LDS_SIZE(lds_size);
257
258 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
259
260 /* Set userdata SGPRs for merged LS-HS. */
261 radeon_set_sh_reg_seq(cs,
262 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
263 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
264 radeon_emit(cs, offchip_layout);
265 radeon_emit(cs, tcs_out_offsets);
266 radeon_emit(cs, tcs_out_layout);
267 } else {
268 unsigned ls_rsrc2 = ls_current->config.rsrc2;
269
270 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
271 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
272
273 /* Due to a hw bug, RSRC2_LS must be written twice with another
274 * LS register written in between. */
275 if (sctx->chip_class == GFX7 && sctx->family != CHIP_HAWAII)
276 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
277 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
278 radeon_emit(cs, ls_current->config.rsrc1);
279 radeon_emit(cs, ls_rsrc2);
280
281 /* Set userdata SGPRs for TCS. */
282 radeon_set_sh_reg_seq(cs,
283 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
284 radeon_emit(cs, offchip_layout);
285 radeon_emit(cs, tcs_out_offsets);
286 radeon_emit(cs, tcs_out_layout);
287 radeon_emit(cs, tcs_in_layout);
288 }
289
290 /* Set userdata SGPRs for TES. */
291 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
292 radeon_emit(cs, offchip_layout);
293 radeon_emit(cs, ring_va);
294
295 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
296 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
297 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
298
299 if (sctx->last_ls_hs_config != ls_hs_config) {
300 if (sctx->chip_class >= GFX7) {
301 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
302 ls_hs_config);
303 } else {
304 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
305 ls_hs_config);
306 }
307 sctx->last_ls_hs_config = ls_hs_config;
308 sctx->context_roll = true;
309 }
310 }
311
312 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info,
313 enum pipe_prim_type prim)
314 {
315 switch (prim) {
316 case PIPE_PRIM_PATCHES:
317 return info->count / info->vertices_per_patch;
318 case PIPE_PRIM_POLYGON:
319 return info->count >= 3;
320 case SI_PRIM_RECTANGLE_LIST:
321 return info->count / 3;
322 default:
323 return u_decomposed_prims_for_vertices(prim, info->count);
324 }
325 }
326
327 static unsigned
328 si_get_init_multi_vgt_param(struct si_screen *sscreen,
329 union si_vgt_param_key *key)
330 {
331 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
332 unsigned max_primgroup_in_wave = 2;
333
334 /* SWITCH_ON_EOP(0) is always preferable. */
335 bool wd_switch_on_eop = false;
336 bool ia_switch_on_eop = false;
337 bool ia_switch_on_eoi = false;
338 bool partial_vs_wave = false;
339 bool partial_es_wave = false;
340
341 if (key->u.uses_tess) {
342 /* SWITCH_ON_EOI must be set if PrimID is used. */
343 if (key->u.tess_uses_prim_id)
344 ia_switch_on_eoi = true;
345
346 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
347 if ((sscreen->info.family == CHIP_TAHITI ||
348 sscreen->info.family == CHIP_PITCAIRN ||
349 sscreen->info.family == CHIP_BONAIRE) &&
350 key->u.uses_gs)
351 partial_vs_wave = true;
352
353 /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
354 if (sscreen->has_distributed_tess) {
355 if (key->u.uses_gs) {
356 if (sscreen->info.chip_class == GFX8)
357 partial_es_wave = true;
358 } else {
359 partial_vs_wave = true;
360 }
361 }
362 }
363
364 /* This is a hardware requirement. */
365 if (key->u.line_stipple_enabled ||
366 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
367 ia_switch_on_eop = true;
368 wd_switch_on_eop = true;
369 }
370
371 if (sscreen->info.chip_class >= GFX7) {
372 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
373 * 4 shader engines. Set 1 to pass the assertion below.
374 * The other cases are hardware requirements.
375 *
376 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
377 * for points, line strips, and tri strips.
378 */
379 if (sscreen->info.max_se <= 2 ||
380 key->u.prim == PIPE_PRIM_POLYGON ||
381 key->u.prim == PIPE_PRIM_LINE_LOOP ||
382 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
383 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
384 (key->u.primitive_restart &&
385 (sscreen->info.family < CHIP_POLARIS10 ||
386 (key->u.prim != PIPE_PRIM_POINTS &&
387 key->u.prim != PIPE_PRIM_LINE_STRIP &&
388 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
389 key->u.count_from_stream_output)
390 wd_switch_on_eop = true;
391
392 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
393 * We don't know that for indirect drawing, so treat it as
394 * always problematic. */
395 if (sscreen->info.family == CHIP_HAWAII &&
396 key->u.uses_instancing)
397 wd_switch_on_eop = true;
398
399 /* Performance recommendation for 4 SE Gfx7-8 parts if
400 * instances are smaller than a primgroup.
401 * Assume indirect draws always use small instances.
402 * This is needed for good VS wave utilization.
403 */
404 if (sscreen->info.chip_class <= GFX8 &&
405 sscreen->info.max_se == 4 &&
406 key->u.multi_instances_smaller_than_primgroup)
407 wd_switch_on_eop = true;
408
409 /* Required on GFX7 and later. */
410 if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
411 ia_switch_on_eoi = true;
412
413 /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
414 * to work around a GS hang.
415 */
416 if (key->u.uses_gs &&
417 (sscreen->info.family == CHIP_TONGA ||
418 sscreen->info.family == CHIP_FIJI ||
419 sscreen->info.family == CHIP_POLARIS10 ||
420 sscreen->info.family == CHIP_POLARIS11 ||
421 sscreen->info.family == CHIP_POLARIS12 ||
422 sscreen->info.family == CHIP_VEGAM))
423 partial_vs_wave = true;
424
425 /* Required by Hawaii and, for some special cases, by GFX8. */
426 if (ia_switch_on_eoi &&
427 (sscreen->info.family == CHIP_HAWAII ||
428 (sscreen->info.chip_class == GFX8 &&
429 (key->u.uses_gs || max_primgroup_in_wave != 2))))
430 partial_vs_wave = true;
431
432 /* Instancing bug on Bonaire. */
433 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
434 key->u.uses_instancing)
435 partial_vs_wave = true;
436
437 /* This only applies to Polaris10 and later 4 SE chips.
438 * wd_switch_on_eop is already true on all other chips.
439 */
440 if (!wd_switch_on_eop && key->u.primitive_restart)
441 partial_vs_wave = true;
442
443 /* If the WD switch is false, the IA switch must be false too. */
444 assert(wd_switch_on_eop || !ia_switch_on_eop);
445 }
446
447 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
448 if (sscreen->info.chip_class <= GFX8 && ia_switch_on_eoi)
449 partial_es_wave = true;
450
451 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
452 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
453 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
454 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
455 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= GFX7 ? wd_switch_on_eop : 0) |
456 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
457 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == GFX8 ?
458 max_primgroup_in_wave : 0) |
459 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
460 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
461 }
462
463 static void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
464 {
465 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
466 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
467 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
468 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
469 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
470 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
471 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
472 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
473 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
474 union si_vgt_param_key key;
475
476 key.index = 0;
477 key.u.prim = prim;
478 key.u.uses_instancing = uses_instancing;
479 key.u.multi_instances_smaller_than_primgroup = multi_instances;
480 key.u.primitive_restart = primitive_restart;
481 key.u.count_from_stream_output = count_from_so;
482 key.u.line_stipple_enabled = line_stipple;
483 key.u.uses_tess = uses_tess;
484 key.u.tess_uses_prim_id = tess_uses_primid;
485 key.u.uses_gs = uses_gs;
486
487 sctx->ia_multi_vgt_param[key.index] =
488 si_get_init_multi_vgt_param(sctx->screen, &key);
489 }
490 }
491
492 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
493 const struct pipe_draw_info *info,
494 enum pipe_prim_type prim,
495 unsigned num_patches,
496 bool primitive_restart)
497 {
498 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
499 unsigned primgroup_size;
500 unsigned ia_multi_vgt_param;
501
502 if (sctx->tes_shader.cso) {
503 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
504 } else if (sctx->gs_shader.cso) {
505 primgroup_size = 64; /* recommended with a GS */
506 } else {
507 primgroup_size = 128; /* recommended without a GS and tess */
508 }
509
510 key.u.prim = prim;
511 key.u.uses_instancing = info->indirect || info->instance_count > 1;
512 key.u.multi_instances_smaller_than_primgroup =
513 info->indirect ||
514 (info->instance_count > 1 &&
515 (info->count_from_stream_output ||
516 si_num_prims_for_vertices(info, prim) < primgroup_size));
517 key.u.primitive_restart = primitive_restart;
518 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
519
520 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
521 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
522
523 if (sctx->gs_shader.cso) {
524 /* GS requirement. */
525 if (sctx->chip_class <= GFX8 &&
526 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
527 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
528
529 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
530 * The hw doc says all multi-SE chips are affected, but Vulkan
531 * only applies it to Hawaii. Do what Vulkan does.
532 */
533 if (sctx->family == CHIP_HAWAII &&
534 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
535 (info->indirect ||
536 (info->instance_count > 1 &&
537 (info->count_from_stream_output ||
538 si_num_prims_for_vertices(info, prim) <= 1))))
539 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
540 }
541
542 return ia_multi_vgt_param;
543 }
544
545 /* rast_prim is the primitive type after GS. */
546 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
547 {
548 struct radeon_cmdbuf *cs = sctx->gfx_cs;
549 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
550 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
551
552 /* Skip this if not rendering lines. */
553 if (!util_prim_is_lines(rast_prim))
554 return;
555
556 if (rast_prim == sctx->last_rast_prim &&
557 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
558 return;
559
560 /* For lines, reset the stipple pattern at each primitive. Otherwise,
561 * reset the stipple pattern at each packet (line strips, line loops).
562 */
563 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
564 rs->pa_sc_line_stipple |
565 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
566
567 sctx->last_rast_prim = rast_prim;
568 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
569 sctx->context_roll = true;
570 }
571
572 static void si_emit_vs_state(struct si_context *sctx,
573 const struct pipe_draw_info *info)
574 {
575 sctx->current_vs_state &= C_VS_STATE_INDEXED;
576 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
577
578 if (sctx->num_vs_blit_sgprs) {
579 /* Re-emit the state after we leave u_blitter. */
580 sctx->last_vs_state = ~0;
581 return;
582 }
583
584 if (sctx->current_vs_state != sctx->last_vs_state) {
585 struct radeon_cmdbuf *cs = sctx->gfx_cs;
586
587 /* For the API vertex shader (VS_STATE_INDEXED). */
588 radeon_set_sh_reg(cs,
589 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
590 SI_SGPR_VS_STATE_BITS * 4,
591 sctx->current_vs_state);
592
593 /* For vertex color clamping, which is done in the last stage
594 * before the rasterizer. */
595 if (sctx->gs_shader.cso || sctx->tes_shader.cso) {
596 /* GS copy shader or TES if GS is missing. */
597 radeon_set_sh_reg(cs,
598 R_00B130_SPI_SHADER_USER_DATA_VS_0 +
599 SI_SGPR_VS_STATE_BITS * 4,
600 sctx->current_vs_state);
601 }
602
603 sctx->last_vs_state = sctx->current_vs_state;
604 }
605 }
606
607 static inline bool si_prim_restart_index_changed(struct si_context *sctx,
608 bool primitive_restart,
609 unsigned restart_index)
610 {
611 return primitive_restart &&
612 (restart_index != sctx->last_restart_index ||
613 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
614 }
615
616 static void si_emit_draw_registers(struct si_context *sctx,
617 const struct pipe_draw_info *info,
618 enum pipe_prim_type prim,
619 unsigned num_patches,
620 bool primitive_restart)
621 {
622 struct radeon_cmdbuf *cs = sctx->gfx_cs;
623 unsigned vgt_prim = si_conv_pipe_prim(prim);
624 unsigned ia_multi_vgt_param;
625
626 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, prim, num_patches,
627 primitive_restart);
628
629 /* Draw state. */
630 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
631 if (sctx->chip_class >= GFX9)
632 radeon_set_uconfig_reg_idx(cs, sctx->screen,
633 R_030960_IA_MULTI_VGT_PARAM, 4,
634 ia_multi_vgt_param);
635 else if (sctx->chip_class >= GFX7)
636 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
637 else
638 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
639
640 sctx->last_multi_vgt_param = ia_multi_vgt_param;
641 }
642 if (vgt_prim != sctx->last_prim) {
643 if (sctx->chip_class >= GFX7)
644 radeon_set_uconfig_reg_idx(cs, sctx->screen,
645 R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
646 else
647 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);
648
649 sctx->last_prim = vgt_prim;
650 }
651
652 /* Primitive restart. */
653 if (primitive_restart != sctx->last_primitive_restart_en) {
654 if (sctx->chip_class >= GFX9)
655 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
656 primitive_restart);
657 else
658 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
659 primitive_restart);
660
661 sctx->last_primitive_restart_en = primitive_restart;
662
663 }
664 if (si_prim_restart_index_changed(sctx, primitive_restart, info->restart_index)) {
665 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
666 info->restart_index);
667 sctx->last_restart_index = info->restart_index;
668 sctx->context_roll = true;
669 }
670 }
671
672 static void si_emit_draw_packets(struct si_context *sctx,
673 const struct pipe_draw_info *info,
674 struct pipe_resource *indexbuf,
675 unsigned index_size,
676 unsigned index_offset)
677 {
678 struct pipe_draw_indirect_info *indirect = info->indirect;
679 struct radeon_cmdbuf *cs = sctx->gfx_cs;
680 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
681 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
682 uint32_t index_max_size = 0;
683 uint64_t index_va = 0;
684
685 if (info->count_from_stream_output) {
686 struct si_streamout_target *t =
687 (struct si_streamout_target*)info->count_from_stream_output;
688
689 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
690 t->stride_in_dw);
691 si_cp_copy_data(sctx, sctx->gfx_cs,
692 COPY_DATA_REG, NULL,
693 R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2,
694 COPY_DATA_SRC_MEM, t->buf_filled_size,
695 t->buf_filled_size_offset);
696 }
697
698 /* draw packet */
699 if (index_size) {
700 if (index_size != sctx->last_index_size) {
701 unsigned index_type;
702
703 /* index type */
704 switch (index_size) {
705 case 1:
706 index_type = V_028A7C_VGT_INDEX_8;
707 break;
708 case 2:
709 index_type = V_028A7C_VGT_INDEX_16 |
710 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
711 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
712 break;
713 case 4:
714 index_type = V_028A7C_VGT_INDEX_32 |
715 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
716 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
717 break;
718 default:
719 assert(!"unreachable");
720 return;
721 }
722
723 if (sctx->chip_class >= GFX9) {
724 radeon_set_uconfig_reg_idx(cs, sctx->screen,
725 R_03090C_VGT_INDEX_TYPE, 2,
726 index_type);
727 } else {
728 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
729 radeon_emit(cs, index_type);
730 }
731
732 sctx->last_index_size = index_size;
733 }
734
735 index_max_size = (indexbuf->width0 - index_offset) /
736 index_size;
737 index_va = si_resource(indexbuf)->gpu_address + index_offset;
738
739 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
740 si_resource(indexbuf),
741 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
742 } else {
743 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
744 * so the state must be re-emitted before the next indexed draw.
745 */
746 if (sctx->chip_class >= GFX7)
747 sctx->last_index_size = -1;
748 }
749
750 if (indirect) {
751 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address;
752
753 assert(indirect_va % 8 == 0);
754
755 si_invalidate_draw_sh_constants(sctx);
756
757 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
758 radeon_emit(cs, 1);
759 radeon_emit(cs, indirect_va);
760 radeon_emit(cs, indirect_va >> 32);
761
762 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
763 si_resource(indirect->buffer),
764 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
765
766 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
767 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
768
769 assert(indirect->offset % 4 == 0);
770
771 if (index_size) {
772 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
773 radeon_emit(cs, index_va);
774 radeon_emit(cs, index_va >> 32);
775
776 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
777 radeon_emit(cs, index_max_size);
778 }
779
780 if (!sctx->screen->has_draw_indirect_multi) {
781 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
782 : PKT3_DRAW_INDIRECT,
783 3, render_cond_bit));
784 radeon_emit(cs, indirect->offset);
785 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
786 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
787 radeon_emit(cs, di_src_sel);
788 } else {
789 uint64_t count_va = 0;
790
791 if (indirect->indirect_draw_count) {
792 struct si_resource *params_buf =
793 si_resource(indirect->indirect_draw_count);
794
795 radeon_add_to_buffer_list(
796 sctx, sctx->gfx_cs, params_buf,
797 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
798
799 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
800 }
801
802 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
803 PKT3_DRAW_INDIRECT_MULTI,
804 8, render_cond_bit));
805 radeon_emit(cs, indirect->offset);
806 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
807 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
808 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
809 S_2C3_DRAW_INDEX_ENABLE(1) |
810 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
811 radeon_emit(cs, indirect->draw_count);
812 radeon_emit(cs, count_va);
813 radeon_emit(cs, count_va >> 32);
814 radeon_emit(cs, indirect->stride);
815 radeon_emit(cs, di_src_sel);
816 }
817 } else {
818 unsigned instance_count = info->instance_count;
819 int base_vertex;
820
821 if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
822 sctx->last_instance_count != instance_count) {
823 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
824 radeon_emit(cs, instance_count);
825 sctx->last_instance_count = instance_count;
826 }
827
828 /* Base vertex and start instance. */
829 base_vertex = index_size ? info->index_bias : info->start;
830
831 if (sctx->num_vs_blit_sgprs) {
832 /* Re-emit draw constants after we leave u_blitter. */
833 si_invalidate_draw_sh_constants(sctx);
834
835 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
836 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
837 sctx->num_vs_blit_sgprs);
838 radeon_emit_array(cs, sctx->vs_blit_sh_data,
839 sctx->num_vs_blit_sgprs);
840 } else if (base_vertex != sctx->last_base_vertex ||
841 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
842 info->start_instance != sctx->last_start_instance ||
843 info->drawid != sctx->last_drawid ||
844 sh_base_reg != sctx->last_sh_base_reg) {
845 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
846 radeon_emit(cs, base_vertex);
847 radeon_emit(cs, info->start_instance);
848 radeon_emit(cs, info->drawid);
849
850 sctx->last_base_vertex = base_vertex;
851 sctx->last_start_instance = info->start_instance;
852 sctx->last_drawid = info->drawid;
853 sctx->last_sh_base_reg = sh_base_reg;
854 }
855
856 if (index_size) {
857 index_va += info->start * index_size;
858
859 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
860 radeon_emit(cs, index_max_size);
861 radeon_emit(cs, index_va);
862 radeon_emit(cs, index_va >> 32);
863 radeon_emit(cs, info->count);
864 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
865 } else {
866 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
867 radeon_emit(cs, info->count);
868 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
869 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
870 }
871 }
872 }
873
874 static void si_emit_surface_sync(struct si_context *sctx,
875 unsigned cp_coher_cntl)
876 {
877 struct radeon_cmdbuf *cs = sctx->gfx_cs;
878
879 if (sctx->chip_class >= GFX9 || !sctx->has_graphics) {
880 /* Flush caches and wait for the caches to assert idle. */
881 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
882 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
883 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
884 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
885 radeon_emit(cs, 0); /* CP_COHER_BASE */
886 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
887 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
888 } else {
889 /* ACQUIRE_MEM is only required on a compute ring. */
890 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
891 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
892 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
893 radeon_emit(cs, 0); /* CP_COHER_BASE */
894 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
895 }
896
897 /* ACQUIRE_MEM has an implicit context roll if the current context
898 * is busy. */
899 if (sctx->has_graphics)
900 sctx->context_roll = true;
901 }
902
903 void si_emit_cache_flush(struct si_context *sctx)
904 {
905 struct radeon_cmdbuf *cs = sctx->gfx_cs;
906 uint32_t flags = sctx->flags;
907
908 if (!sctx->has_graphics) {
909 /* Only process compute flags. */
910 flags &= SI_CONTEXT_INV_ICACHE |
911 SI_CONTEXT_INV_SMEM_L1 |
912 SI_CONTEXT_INV_VMEM_L1 |
913 SI_CONTEXT_INV_GLOBAL_L2 |
914 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
915 SI_CONTEXT_INV_L2_METADATA |
916 SI_CONTEXT_CS_PARTIAL_FLUSH;
917 }
918
919 uint32_t cp_coher_cntl = 0;
920 uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
921 SI_CONTEXT_FLUSH_AND_INV_DB);
922
923 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
924 sctx->num_cb_cache_flushes++;
925 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
926 sctx->num_db_cache_flushes++;
927
928 /* GFX6 has a bug that it always flushes ICACHE and KCACHE if either
929 * bit is set. An alternative way is to write SQC_CACHES, but that
930 * doesn't seem to work reliably. Since the bug doesn't affect
931 * correctness (it only does more work than necessary) and
932 * the performance impact is likely negligible, there is no plan
933 * to add a workaround for it.
934 */
935
936 if (flags & SI_CONTEXT_INV_ICACHE)
937 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
938 if (flags & SI_CONTEXT_INV_SMEM_L1)
939 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
940
941 if (sctx->chip_class <= GFX8) {
942 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
943 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
944 S_0085F0_CB0_DEST_BASE_ENA(1) |
945 S_0085F0_CB1_DEST_BASE_ENA(1) |
946 S_0085F0_CB2_DEST_BASE_ENA(1) |
947 S_0085F0_CB3_DEST_BASE_ENA(1) |
948 S_0085F0_CB4_DEST_BASE_ENA(1) |
949 S_0085F0_CB5_DEST_BASE_ENA(1) |
950 S_0085F0_CB6_DEST_BASE_ENA(1) |
951 S_0085F0_CB7_DEST_BASE_ENA(1);
952
953 /* Necessary for DCC */
954 if (sctx->chip_class == GFX8)
955 si_cp_release_mem(sctx, cs,
956 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
957 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
958 EOP_DATA_SEL_DISCARD, NULL,
959 0, 0, SI_NOT_QUERY);
960 }
961 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
962 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
963 S_0085F0_DB_DEST_BASE_ENA(1);
964 }
965
966 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
967 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
968 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
969 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
970 }
971 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
972 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
973 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
974 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
975 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
976 }
977
978 /* Wait for shader engines to go idle.
979 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
980 * for everything including CB/DB cache flushes.
981 */
982 if (!flush_cb_db) {
983 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
984 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
985 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
986 /* Only count explicit shader flushes, not implicit ones
987 * done by SURFACE_SYNC.
988 */
989 sctx->num_vs_flushes++;
990 sctx->num_ps_flushes++;
991 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
992 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
993 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
994 sctx->num_vs_flushes++;
995 }
996 }
997
998 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
999 sctx->compute_is_busy) {
1000 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1001 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1002 sctx->num_cs_flushes++;
1003 sctx->compute_is_busy = false;
1004 }
1005
1006 /* VGT state synchronization. */
1007 if (flags & SI_CONTEXT_VGT_FLUSH) {
1008 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1009 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1010 }
1011 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
1012 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1013 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1014 }
1015
1016 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
1017 * wait for idle on GFX9. We have to use a TS event.
1018 */
1019 if (sctx->chip_class >= GFX9 && flush_cb_db) {
1020 uint64_t va;
1021 unsigned tc_flags, cb_db_event;
1022
1023 /* Set the CB/DB flush event. */
1024 switch (flush_cb_db) {
1025 case SI_CONTEXT_FLUSH_AND_INV_CB:
1026 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1027 break;
1028 case SI_CONTEXT_FLUSH_AND_INV_DB:
1029 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1030 break;
1031 default:
1032 /* both CB & DB */
1033 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1034 }
1035
1036 /* These are the only allowed combinations. If you need to
1037 * do multiple operations at once, do them separately.
1038 * All operations that invalidate L2 also seem to invalidate
1039 * metadata. Volatile (VOL) and WC flushes are not listed here.
1040 *
1041 * TC | TC_WB = writeback & invalidate L2 & L1
1042 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1043 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1044 * TC | TC_NC = invalidate L2 for MTYPE == NC
1045 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1046 * TCL1 = invalidate L1
1047 */
1048 tc_flags = 0;
1049
1050 if (flags & SI_CONTEXT_INV_L2_METADATA) {
1051 tc_flags = EVENT_TC_ACTION_ENA |
1052 EVENT_TC_MD_ACTION_ENA;
1053 }
1054
1055 /* Ideally flush TC together with CB/DB. */
1056 if (flags & SI_CONTEXT_INV_GLOBAL_L2) {
1057 /* Writeback and invalidate everything in L2 & L1. */
1058 tc_flags = EVENT_TC_ACTION_ENA |
1059 EVENT_TC_WB_ACTION_ENA;
1060
1061 /* Clear the flags. */
1062 flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
1063 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
1064 SI_CONTEXT_INV_VMEM_L1);
1065 sctx->num_L2_invalidates++;
1066 }
1067
1068 /* Do the flush (enqueue the event and wait for it). */
1069 va = sctx->wait_mem_scratch->gpu_address;
1070 sctx->wait_mem_number++;
1071
1072 si_cp_release_mem(sctx, cs, cb_db_event, tc_flags,
1073 EOP_DST_SEL_MEM,
1074 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1075 EOP_DATA_SEL_VALUE_32BIT,
1076 sctx->wait_mem_scratch, va,
1077 sctx->wait_mem_number, SI_NOT_QUERY);
1078 si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff,
1079 WAIT_REG_MEM_EQUAL);
1080 }
1081
1082 /* Make sure ME is idle (it executes most packets) before continuing.
1083 * This prevents read-after-write hazards between PFP and ME.
1084 */
1085 if (sctx->has_graphics &&
1086 (cp_coher_cntl ||
1087 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1088 SI_CONTEXT_INV_VMEM_L1 |
1089 SI_CONTEXT_INV_GLOBAL_L2 |
1090 SI_CONTEXT_WRITEBACK_GLOBAL_L2)))) {
1091 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1092 radeon_emit(cs, 0);
1093 }
1094
1095 /* GFX6-GFX8 only:
1096 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1097 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1098 *
1099 * cp_coher_cntl should contain all necessary flags except TC flags
1100 * at this point.
1101 *
1102 * GFX6-GFX7 don't support L2 write-back.
1103 */
1104 if (flags & SI_CONTEXT_INV_GLOBAL_L2 ||
1105 (sctx->chip_class <= GFX7 &&
1106 (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1107 /* Invalidate L1 & L2. (L1 is always invalidated on GFX6)
1108 * WB must be set on GFX8+ when TC_ACTION is set.
1109 */
1110 si_emit_surface_sync(sctx, cp_coher_cntl |
1111 S_0085F0_TC_ACTION_ENA(1) |
1112 S_0085F0_TCL1_ACTION_ENA(1) |
1113 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= GFX8));
1114 cp_coher_cntl = 0;
1115 sctx->num_L2_invalidates++;
1116 } else {
1117 /* L1 invalidation and L2 writeback must be done separately,
1118 * because both operations can't be done together.
1119 */
1120 if (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
1121 /* WB = write-back
1122 * NC = apply to non-coherent MTYPEs
1123 * (i.e. MTYPE <= 1, which is what we use everywhere)
1124 *
1125 * WB doesn't work without NC.
1126 */
1127 si_emit_surface_sync(sctx, cp_coher_cntl |
1128 S_0301F0_TC_WB_ACTION_ENA(1) |
1129 S_0301F0_TC_NC_ACTION_ENA(1));
1130 cp_coher_cntl = 0;
1131 sctx->num_L2_writebacks++;
1132 }
1133 if (flags & SI_CONTEXT_INV_VMEM_L1) {
1134 /* Invalidate per-CU VMEM L1. */
1135 si_emit_surface_sync(sctx, cp_coher_cntl |
1136 S_0085F0_TCL1_ACTION_ENA(1));
1137 cp_coher_cntl = 0;
1138 }
1139 }
1140
1141 /* If TC flushes haven't cleared this... */
1142 if (cp_coher_cntl)
1143 si_emit_surface_sync(sctx, cp_coher_cntl);
1144
1145 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1146 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1147 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1148 EVENT_INDEX(0));
1149 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1150 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1151 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1152 EVENT_INDEX(0));
1153 }
1154
1155 sctx->flags = 0;
1156 }
1157
1158 static void si_get_draw_start_count(struct si_context *sctx,
1159 const struct pipe_draw_info *info,
1160 unsigned *start, unsigned *count)
1161 {
1162 struct pipe_draw_indirect_info *indirect = info->indirect;
1163
1164 if (indirect) {
1165 unsigned indirect_count;
1166 struct pipe_transfer *transfer;
1167 unsigned begin, end;
1168 unsigned map_size;
1169 unsigned *data;
1170
1171 if (indirect->indirect_draw_count) {
1172 data = pipe_buffer_map_range(&sctx->b,
1173 indirect->indirect_draw_count,
1174 indirect->indirect_draw_count_offset,
1175 sizeof(unsigned),
1176 PIPE_TRANSFER_READ, &transfer);
1177
1178 indirect_count = *data;
1179
1180 pipe_buffer_unmap(&sctx->b, transfer);
1181 } else {
1182 indirect_count = indirect->draw_count;
1183 }
1184
1185 if (!indirect_count) {
1186 *start = *count = 0;
1187 return;
1188 }
1189
1190 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1191 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1192 indirect->offset, map_size,
1193 PIPE_TRANSFER_READ, &transfer);
1194
1195 begin = UINT_MAX;
1196 end = 0;
1197
1198 for (unsigned i = 0; i < indirect_count; ++i) {
1199 unsigned count = data[0];
1200 unsigned start = data[2];
1201
1202 if (count > 0) {
1203 begin = MIN2(begin, start);
1204 end = MAX2(end, start + count);
1205 }
1206
1207 data += indirect->stride / sizeof(unsigned);
1208 }
1209
1210 pipe_buffer_unmap(&sctx->b, transfer);
1211
1212 if (begin < end) {
1213 *start = begin;
1214 *count = end - begin;
1215 } else {
1216 *start = *count = 0;
1217 }
1218 } else {
1219 *start = info->start;
1220 *count = info->count;
1221 }
1222 }
1223
1224 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1225 enum pipe_prim_type prim, bool primitive_restart,
1226 unsigned skip_atom_mask)
1227 {
1228 unsigned num_patches = 0;
1229
1230 si_emit_rasterizer_prim_state(sctx);
1231 if (sctx->tes_shader.cso)
1232 si_emit_derived_tess_state(sctx, info, &num_patches);
1233
1234 /* Emit state atoms. */
1235 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1236 while (mask)
1237 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1238
1239 sctx->dirty_atoms &= skip_atom_mask;
1240
1241 /* Emit states. */
1242 mask = sctx->dirty_states;
1243 while (mask) {
1244 unsigned i = u_bit_scan(&mask);
1245 struct si_pm4_state *state = sctx->queued.array[i];
1246
1247 if (!state || sctx->emitted.array[i] == state)
1248 continue;
1249
1250 si_pm4_emit(sctx, state);
1251 sctx->emitted.array[i] = state;
1252 }
1253 sctx->dirty_states = 0;
1254
1255 /* Emit draw states. */
1256 si_emit_vs_state(sctx, info);
1257 si_emit_draw_registers(sctx, info, prim, num_patches, primitive_restart);
1258 }
1259
1260 static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1261 {
1262 struct si_context *sctx = (struct si_context *)ctx;
1263 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1264 struct pipe_resource *indexbuf = info->index.resource;
1265 unsigned dirty_tex_counter;
1266 enum pipe_prim_type rast_prim, prim = info->mode;
1267 unsigned index_size = info->index_size;
1268 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1269 bool primitive_restart = info->primitive_restart;
1270
1271 if (likely(!info->indirect)) {
1272 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
1273 * no workaround for indirect draws, but we can at least skip
1274 * direct draws.
1275 */
1276 if (unlikely(!info->instance_count))
1277 return;
1278
1279 /* Handle count == 0. */
1280 if (unlikely(!info->count &&
1281 (index_size || !info->count_from_stream_output)))
1282 return;
1283 }
1284
1285 if (unlikely(!sctx->vs_shader.cso ||
1286 !rs ||
1287 (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
1288 (!!sctx->tes_shader.cso != (prim == PIPE_PRIM_PATCHES)))) {
1289 assert(0);
1290 return;
1291 }
1292
1293 /* Recompute and re-emit the texture resource states if needed. */
1294 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1295 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1296 sctx->last_dirty_tex_counter = dirty_tex_counter;
1297 sctx->framebuffer.dirty_cbufs |=
1298 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1299 sctx->framebuffer.dirty_zsbuf = true;
1300 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1301 si_update_all_texture_descriptors(sctx);
1302 }
1303
1304 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1305
1306 /* Set the rasterization primitive type.
1307 *
1308 * This must be done after si_decompress_textures, which can call
1309 * draw_vbo recursively, and before si_update_shaders, which uses
1310 * current_rast_prim for this draw_vbo call. */
1311 if (sctx->gs_shader.cso)
1312 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1313 else if (sctx->tes_shader.cso) {
1314 if (sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1315 rast_prim = PIPE_PRIM_POINTS;
1316 else
1317 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1318 } else
1319 rast_prim = prim;
1320
1321 if (rast_prim != sctx->current_rast_prim) {
1322 if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
1323 util_prim_is_points_or_lines(rast_prim))
1324 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1325
1326 sctx->current_rast_prim = rast_prim;
1327 sctx->do_update_shaders = true;
1328 }
1329
1330 if (sctx->tes_shader.cso &&
1331 sctx->screen->has_ls_vgpr_init_bug) {
1332 /* Determine whether the LS VGPR fix should be applied.
1333 *
1334 * It is only required when num input CPs > num output CPs,
1335 * which cannot happen with the fixed function TCS. We should
1336 * also update this bit when switching from TCS to fixed
1337 * function TCS.
1338 */
1339 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1340 bool ls_vgpr_fix =
1341 tcs &&
1342 info->vertices_per_patch >
1343 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1344
1345 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1346 sctx->ls_vgpr_fix = ls_vgpr_fix;
1347 sctx->do_update_shaders = true;
1348 }
1349 }
1350
1351 if (sctx->gs_shader.cso) {
1352 /* Determine whether the GS triangle strip adjacency fix should
1353 * be applied. Rotate every other triangle if
1354 * - triangle strips with adjacency are fed to the GS and
1355 * - primitive restart is disabled (the rotation doesn't help
1356 * when the restart occurs after an odd number of triangles).
1357 */
1358 bool gs_tri_strip_adj_fix =
1359 !sctx->tes_shader.cso &&
1360 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1361 !info->primitive_restart;
1362
1363 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1364 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1365 sctx->do_update_shaders = true;
1366 }
1367 }
1368
1369 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1370 goto return_cleanup;
1371
1372 if (index_size) {
1373 /* Translate or upload, if needed. */
1374 /* 8-bit indices are supported on GFX8. */
1375 if (sctx->chip_class <= GFX7 && index_size == 1) {
1376 unsigned start, count, start_offset, size, offset;
1377 void *ptr;
1378
1379 si_get_draw_start_count(sctx, info, &start, &count);
1380 start_offset = start * 2;
1381 size = count * 2;
1382
1383 indexbuf = NULL;
1384 u_upload_alloc(ctx->stream_uploader, start_offset,
1385 size,
1386 si_optimal_tcc_alignment(sctx, size),
1387 &offset, &indexbuf, &ptr);
1388 if (!indexbuf)
1389 return;
1390
1391 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1392 index_offset + start,
1393 count, ptr);
1394
1395 /* info->start will be added by the drawing code */
1396 index_offset = offset - start_offset;
1397 index_size = 2;
1398 } else if (info->has_user_indices) {
1399 unsigned start_offset;
1400
1401 assert(!info->indirect);
1402 start_offset = info->start * index_size;
1403
1404 indexbuf = NULL;
1405 u_upload_data(ctx->stream_uploader, start_offset,
1406 info->count * index_size,
1407 sctx->screen->info.tcc_cache_line_size,
1408 (char*)info->index.user + start_offset,
1409 &index_offset, &indexbuf);
1410 if (!indexbuf)
1411 return;
1412
1413 /* info->start will be added by the drawing code */
1414 index_offset -= start_offset;
1415 } else if (sctx->chip_class <= GFX7 &&
1416 si_resource(indexbuf)->TC_L2_dirty) {
1417 /* GFX8 reads index buffers through TC L2, so it doesn't
1418 * need this. */
1419 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1420 si_resource(indexbuf)->TC_L2_dirty = false;
1421 }
1422 }
1423
1424 if (info->indirect) {
1425 struct pipe_draw_indirect_info *indirect = info->indirect;
1426
1427 /* Add the buffer size for memory checking in need_cs_space. */
1428 si_context_add_resource_size(sctx, indirect->buffer);
1429
1430 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1431 if (sctx->chip_class <= GFX8) {
1432 if (si_resource(indirect->buffer)->TC_L2_dirty) {
1433 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1434 si_resource(indirect->buffer)->TC_L2_dirty = false;
1435 }
1436
1437 if (indirect->indirect_draw_count &&
1438 si_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1439 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1440 si_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1441 }
1442 }
1443 }
1444
1445 si_need_gfx_cs_space(sctx);
1446
1447 if (sctx->bo_list_add_all_gfx_resources)
1448 si_gfx_resources_add_all_to_bo_list(sctx);
1449
1450 /* Since we've called si_context_add_resource_size for vertex buffers,
1451 * this must be called after si_need_cs_space, because we must let
1452 * need_cs_space flush before we add buffers to the buffer list.
1453 */
1454 if (!si_upload_vertex_buffer_descriptors(sctx))
1455 goto return_cleanup;
1456
1457 /* Vega10/Raven scissor bug workaround. When any context register is
1458 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
1459 * registers must be written too.
1460 */
1461 bool has_gfx9_scissor_bug = sctx->screen->has_gfx9_scissor_bug;
1462 unsigned masked_atoms = 0;
1463
1464 if (has_gfx9_scissor_bug) {
1465 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
1466
1467 if (info->count_from_stream_output ||
1468 sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
1469 sctx->dirty_states & si_states_that_always_roll_context())
1470 sctx->context_roll = true;
1471 }
1472
1473 /* Use optimal packet order based on whether we need to sync the pipeline. */
1474 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1475 SI_CONTEXT_FLUSH_AND_INV_DB |
1476 SI_CONTEXT_PS_PARTIAL_FLUSH |
1477 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1478 /* If we have to wait for idle, set all states first, so that all
1479 * SET packets are processed in parallel with previous draw calls.
1480 * Then draw and prefetch at the end. This ensures that the time
1481 * the CUs are idle is very short.
1482 */
1483 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
1484 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
1485
1486 if (!si_upload_graphics_shader_descriptors(sctx))
1487 goto return_cleanup;
1488
1489 /* Emit all states except possibly render condition. */
1490 si_emit_all_states(sctx, info, prim, primitive_restart, masked_atoms);
1491 si_emit_cache_flush(sctx);
1492 /* <-- CUs are idle here. */
1493
1494 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
1495 sctx->atoms.s.render_cond.emit(sctx);
1496
1497 if (has_gfx9_scissor_bug &&
1498 (sctx->context_roll ||
1499 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
1500 sctx->atoms.s.scissors.emit(sctx);
1501
1502 sctx->dirty_atoms = 0;
1503
1504 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1505 /* <-- CUs are busy here. */
1506
1507 /* Start prefetches after the draw has been started. Both will run
1508 * in parallel, but starting the draw first is more important.
1509 */
1510 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
1511 cik_emit_prefetch_L2(sctx, false);
1512 } else {
1513 /* If we don't wait for idle, start prefetches first, then set
1514 * states, and draw at the end.
1515 */
1516 if (sctx->flags)
1517 si_emit_cache_flush(sctx);
1518
1519 /* Only prefetch the API VS and VBO descriptors. */
1520 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
1521 cik_emit_prefetch_L2(sctx, true);
1522
1523 if (!si_upload_graphics_shader_descriptors(sctx))
1524 return;
1525
1526 si_emit_all_states(sctx, info, prim, primitive_restart, masked_atoms);
1527
1528 if (has_gfx9_scissor_bug &&
1529 (sctx->context_roll ||
1530 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
1531 sctx->atoms.s.scissors.emit(sctx);
1532
1533 sctx->dirty_atoms = 0;
1534
1535 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1536
1537 /* Prefetch the remaining shaders after the draw has been
1538 * started. */
1539 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
1540 cik_emit_prefetch_L2(sctx, false);
1541 }
1542
1543 /* Clear the context roll flag after the draw call. */
1544 sctx->context_roll = false;
1545
1546 if (unlikely(sctx->current_saved_cs)) {
1547 si_trace_emit(sctx);
1548 si_log_draw_state(sctx, sctx->log);
1549 }
1550
1551 /* Workaround for a VGT hang when streamout is enabled.
1552 * It must be done after drawing. */
1553 if ((sctx->family == CHIP_HAWAII ||
1554 sctx->family == CHIP_TONGA ||
1555 sctx->family == CHIP_FIJI) &&
1556 si_get_strmout_en(sctx)) {
1557 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1558 }
1559
1560 if (unlikely(sctx->decompression_enabled)) {
1561 sctx->num_decompress_calls++;
1562 } else {
1563 sctx->num_draw_calls++;
1564 if (sctx->framebuffer.state.nr_cbufs > 1)
1565 sctx->num_mrt_draw_calls++;
1566 if (primitive_restart)
1567 sctx->num_prim_restart_calls++;
1568 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1569 sctx->num_spill_draw_calls++;
1570 }
1571
1572 return_cleanup:
1573 if (index_size && indexbuf != info->index.resource)
1574 pipe_resource_reference(&indexbuf, NULL);
1575 }
1576
1577 static void
1578 si_draw_rectangle(struct blitter_context *blitter,
1579 void *vertex_elements_cso,
1580 blitter_get_vs_func get_vs,
1581 int x1, int y1, int x2, int y2,
1582 float depth, unsigned num_instances,
1583 enum blitter_attrib_type type,
1584 const union blitter_attrib *attrib)
1585 {
1586 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
1587 struct si_context *sctx = (struct si_context*)pipe;
1588
1589 /* Pack position coordinates as signed int16. */
1590 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
1591 ((uint32_t)(y1 & 0xffff) << 16);
1592 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
1593 ((uint32_t)(y2 & 0xffff) << 16);
1594 sctx->vs_blit_sh_data[2] = fui(depth);
1595
1596 switch (type) {
1597 case UTIL_BLITTER_ATTRIB_COLOR:
1598 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
1599 sizeof(float)*4);
1600 break;
1601 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
1602 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
1603 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
1604 sizeof(attrib->texcoord));
1605 break;
1606 case UTIL_BLITTER_ATTRIB_NONE:;
1607 }
1608
1609 pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
1610
1611 struct pipe_draw_info info = {};
1612 info.mode = SI_PRIM_RECTANGLE_LIST;
1613 info.count = 3;
1614 info.instance_count = num_instances;
1615
1616 /* Don't set per-stage shader pointers for VS. */
1617 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
1618 sctx->vertex_buffer_pointer_dirty = false;
1619
1620 si_draw_vbo(pipe, &info);
1621 }
1622
1623 void si_trace_emit(struct si_context *sctx)
1624 {
1625 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1626 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
1627
1628 si_cp_write_data(sctx, sctx->current_saved_cs->trace_buf,
1629 0, 4, V_370_MEM, V_370_ME, &trace_id);
1630
1631 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1632 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
1633
1634 if (sctx->log)
1635 u_log_flush(sctx->log);
1636 }
1637
1638 void si_init_draw_functions(struct si_context *sctx)
1639 {
1640 sctx->b.draw_vbo = si_draw_vbo;
1641
1642 sctx->blitter->draw_rectangle = si_draw_rectangle;
1643
1644 si_init_ia_multi_vgt_param_table(sctx);
1645 }