2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "radeonsi_pipe.h"
32 #include "radeonsi_shader.h"
40 static void si_pipe_shader_vs(struct pipe_context
*ctx
, struct si_pipe_shader
*shader
)
42 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
43 struct si_pm4_state
*pm4
;
44 unsigned num_sgprs
, num_user_sgprs
;
45 unsigned nparams
, i
, vgpr_comp_cnt
;
48 si_pm4_delete_state(rctx
, vs
, shader
->pm4
);
49 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
51 si_pm4_inval_shader_cache(pm4
);
53 /* Certain attributes (position, psize, etc.) don't count as params.
54 * VS is required to export at least one param and r600_shader_from_tgsi()
55 * takes care of adding a dummy export.
57 for (nparams
= 0, i
= 0 ; i
< shader
->shader
.noutput
; i
++) {
58 switch (shader
->shader
.output
[i
].name
) {
59 case TGSI_SEMANTIC_POSITION
:
60 case TGSI_SEMANTIC_PSIZE
:
69 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
70 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
72 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
73 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
74 S_02870C_POS1_EXPORT_FORMAT(shader
->shader
.vs_out_misc_write
?
75 V_02870C_SPI_SHADER_4COMP
:
76 V_02870C_SPI_SHADER_NONE
) |
77 S_02870C_POS2_EXPORT_FORMAT((shader
->shader
.clip_dist_write
& 0x0F) ?
78 V_02870C_SPI_SHADER_4COMP
:
79 V_02870C_SPI_SHADER_NONE
) |
80 S_02870C_POS3_EXPORT_FORMAT((shader
->shader
.clip_dist_write
& 0xF0) ?
81 V_02870C_SPI_SHADER_4COMP
:
82 V_02870C_SPI_SHADER_NONE
));
84 va
= r600_resource_va(ctx
->screen
, (void *)shader
->bo
);
85 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
);
86 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
87 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, va
>> 40);
89 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
90 num_sgprs
= shader
->num_sgprs
;
91 if (num_user_sgprs
> num_sgprs
)
92 num_sgprs
= num_user_sgprs
;
93 /* Last 2 reserved SGPRs are used for VCC */
95 assert(num_sgprs
<= 104);
97 vgpr_comp_cnt
= shader
->shader
.uses_instanceid
? 3 : 0;
99 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
100 S_00B128_VGPRS((shader
->num_vgprs
- 1) / 4) |
101 S_00B128_SGPRS((num_sgprs
- 1) / 8) |
102 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
));
103 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
104 S_00B12C_USER_SGPR(num_user_sgprs
));
106 si_pm4_bind_state(rctx
, vs
, shader
->pm4
);
109 static void si_pipe_shader_ps(struct pipe_context
*ctx
, struct si_pipe_shader
*shader
)
111 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
112 struct si_pm4_state
*pm4
;
113 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control
, db_shader_control
;
114 unsigned num_sgprs
, num_user_sgprs
;
115 boolean have_linear
= FALSE
, have_centroid
= FALSE
, have_perspective
= FALSE
;
116 unsigned fragcoord_interp_mode
= 0;
117 unsigned spi_baryc_cntl
, spi_ps_input_ena
, spi_shader_z_format
;
120 si_pm4_delete_state(rctx
, ps
, shader
->pm4
);
121 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
123 si_pm4_inval_shader_cache(pm4
);
125 db_shader_control
= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
126 for (i
= 0; i
< shader
->shader
.ninput
; i
++) {
127 switch (shader
->shader
.input
[i
].name
) {
128 case TGSI_SEMANTIC_POSITION
:
129 if (shader
->shader
.input
[i
].centroid
) {
130 /* fragcoord_interp_mode will be written to
131 * SPI_BARYC_CNTL.POS_FLOAT_LOCATION
133 * 0 -> Position = pixel center (default)
134 * 1 -> Position = pixel centroid
135 * 2 -> Position = iterated sample number XXX:
136 * What does this mean?
138 fragcoord_interp_mode
= 1;
141 case TGSI_SEMANTIC_FACE
:
145 if (shader
->shader
.input
[i
].interpolate
== TGSI_INTERPOLATE_LINEAR
)
147 if (shader
->shader
.input
[i
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
148 have_perspective
= TRUE
;
149 if (shader
->shader
.input
[i
].centroid
)
150 have_centroid
= TRUE
;
153 for (i
= 0; i
< shader
->shader
.noutput
; i
++) {
154 if (shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_POSITION
)
155 db_shader_control
|= S_02880C_Z_EXPORT_ENABLE(1);
156 if (shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
157 db_shader_control
|= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
159 if (shader
->shader
.uses_kill
|| shader
->key
.ps
.alpha_func
!= PIPE_FUNC_ALWAYS
)
160 db_shader_control
|= S_02880C_KILL_ENABLE(1);
164 for (i
= 0; i
< shader
->shader
.noutput
; i
++) {
165 if (shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_POSITION
||
166 shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
168 else if (shader
->shader
.output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
169 if (shader
->shader
.fs_write_all
)
170 num_cout
= shader
->shader
.nr_cbufs
;
176 /* always at least export 1 component per pixel */
180 spi_ps_in_control
= S_0286D8_NUM_INTERP(shader
->shader
.ninterp
);
183 if (have_perspective
)
184 spi_baryc_cntl
|= have_centroid
?
185 S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1);
187 spi_baryc_cntl
|= have_centroid
?
188 S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1);
189 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(fragcoord_interp_mode
);
191 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
192 spi_ps_input_ena
= shader
->spi_ps_input_ena
;
193 /* we need to enable at least one of them, otherwise we hang the GPU */
194 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena
) ||
195 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) ||
196 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) ||
197 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena
) ||
198 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena
) ||
199 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
) ||
200 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
) ||
201 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena
));
203 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, spi_ps_input_ena
);
204 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
, spi_ps_input_ena
);
205 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
207 if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control
))
208 spi_shader_z_format
= V_028710_SPI_SHADER_32_GR
;
209 else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control
))
210 spi_shader_z_format
= V_028710_SPI_SHADER_32_R
;
212 spi_shader_z_format
= 0;
213 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
, spi_shader_z_format
);
214 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
,
215 shader
->spi_shader_col_format
);
216 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, shader
->cb_shader_mask
);
218 va
= r600_resource_va(ctx
->screen
, (void *)shader
->bo
);
219 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
);
220 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
221 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, va
>> 40);
223 num_user_sgprs
= SI_PS_NUM_USER_SGPR
;
224 num_sgprs
= shader
->num_sgprs
;
225 if (num_user_sgprs
> num_sgprs
)
226 num_sgprs
= num_user_sgprs
;
227 /* Last 2 reserved SGPRs are used for VCC */
229 assert(num_sgprs
<= 104);
231 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
232 S_00B028_VGPRS((shader
->num_vgprs
- 1) / 4) |
233 S_00B028_SGPRS((num_sgprs
- 1) / 8));
234 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
235 S_00B02C_USER_SGPR(num_user_sgprs
));
237 si_pm4_set_reg(pm4
, R_02880C_DB_SHADER_CONTROL
, db_shader_control
);
239 shader
->sprite_coord_enable
= rctx
->sprite_coord_enable
;
240 si_pm4_bind_state(rctx
, ps
, shader
->pm4
);
247 static unsigned si_conv_pipe_prim(unsigned pprim
)
249 static const unsigned prim_conv
[] = {
250 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
251 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
252 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
253 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
254 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
255 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
256 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
257 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
258 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
259 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
260 [PIPE_PRIM_LINES_ADJACENCY
] = ~0,
261 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = ~0,
262 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = ~0,
263 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = ~0
265 unsigned result
= prim_conv
[pprim
];
267 R600_ERR("unsupported primitive type %d\n", pprim
);
272 static bool si_update_draw_info_state(struct r600_context
*rctx
,
273 const struct pipe_draw_info
*info
)
275 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
276 struct si_shader
*vs
= &rctx
->vs_shader
->current
->shader
;
277 unsigned prim
= si_conv_pipe_prim(info
->mode
);
278 unsigned ls_mask
= 0;
288 si_pm4_set_reg(pm4
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
289 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
290 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
291 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
,
292 info
->indexed
? info
->index_bias
: info
->start
);
293 si_pm4_set_reg(pm4
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
, info
->restart_index
);
294 si_pm4_set_reg(pm4
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, info
->primitive_restart
);
295 si_pm4_set_reg(pm4
, R_00B130_SPI_SHADER_USER_DATA_VS_0
+ SI_SGPR_START_INSTANCE
* 4,
296 info
->start_instance
);
298 if (prim
== V_008958_DI_PT_LINELIST
)
300 else if (prim
== V_008958_DI_PT_LINESTRIP
)
302 si_pm4_set_reg(pm4
, R_028A0C_PA_SC_LINE_STIPPLE
,
303 S_028A0C_AUTO_RESET_CNTL(ls_mask
) |
304 rctx
->pa_sc_line_stipple
);
306 if (info
->mode
== PIPE_PRIM_QUADS
|| info
->mode
== PIPE_PRIM_QUAD_STRIP
|| info
->mode
== PIPE_PRIM_POLYGON
) {
307 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
308 S_028814_PROVOKING_VTX_LAST(1) | rctx
->pa_su_sc_mode_cntl
);
310 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
, rctx
->pa_su_sc_mode_cntl
);
312 si_pm4_set_reg(pm4
, R_02881C_PA_CL_VS_OUT_CNTL
,
313 S_02881C_USE_VTX_POINT_SIZE(vs
->vs_out_point_size
) |
314 S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs
->clip_dist_write
& 0x0F) != 0) |
315 S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs
->clip_dist_write
& 0xF0) != 0) |
316 S_02881C_VS_OUT_MISC_VEC_ENA(vs
->vs_out_misc_write
) |
317 (rctx
->queued
.named
.rasterizer
->clip_plane_enable
&
318 vs
->clip_dist_write
));
319 si_pm4_set_reg(pm4
, R_028810_PA_CL_CLIP_CNTL
,
320 rctx
->queued
.named
.rasterizer
->pa_cl_clip_cntl
|
321 (vs
->clip_dist_write
? 0 :
322 rctx
->queued
.named
.rasterizer
->clip_plane_enable
& 0x3F));
324 si_pm4_set_state(rctx
, draw_info
, pm4
);
328 static void si_update_spi_map(struct r600_context
*rctx
)
330 struct si_shader
*ps
= &rctx
->ps_shader
->current
->shader
;
331 struct si_shader
*vs
= &rctx
->vs_shader
->current
->shader
;
332 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
335 for (i
= 0; i
< ps
->ninput
; i
++) {
336 unsigned name
= ps
->input
[i
].name
;
337 unsigned param_offset
= ps
->input
[i
].param_offset
;
339 if (name
== TGSI_SEMANTIC_POSITION
)
340 /* Read from preloaded VGPRs, not parameters */
346 if (ps
->input
[i
].interpolate
== TGSI_INTERPOLATE_CONSTANT
||
347 (ps
->input
[i
].interpolate
== TGSI_INTERPOLATE_COLOR
&&
348 rctx
->ps_shader
->current
->key
.ps
.flatshade
)) {
349 tmp
|= S_028644_FLAT_SHADE(1);
352 if (name
== TGSI_SEMANTIC_GENERIC
&&
353 rctx
->sprite_coord_enable
& (1 << ps
->input
[i
].sid
)) {
354 tmp
|= S_028644_PT_SPRITE_TEX(1);
357 for (j
= 0; j
< vs
->noutput
; j
++) {
358 if (name
== vs
->output
[j
].name
&&
359 ps
->input
[i
].sid
== vs
->output
[j
].sid
) {
360 tmp
|= S_028644_OFFSET(vs
->output
[j
].param_offset
);
365 if (j
== vs
->noutput
) {
366 /* No corresponding output found, load defaults into input */
367 tmp
|= S_028644_OFFSET(0x20);
371 R_028644_SPI_PS_INPUT_CNTL_0
+ param_offset
* 4,
374 if (name
== TGSI_SEMANTIC_COLOR
&&
375 rctx
->ps_shader
->current
->key
.ps
.color_two_side
) {
376 name
= TGSI_SEMANTIC_BCOLOR
;
382 si_pm4_set_state(rctx
, spi
, pm4
);
385 static void si_update_derived_state(struct r600_context
*rctx
)
387 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
388 unsigned vs_dirty
= 0, ps_dirty
= 0;
390 if (!rctx
->blitter
->running
) {
391 /* Flush depth textures which need to be flushed. */
392 if (rctx
->vs_samplers
.depth_texture_mask
) {
393 si_flush_depth_textures(rctx
, &rctx
->vs_samplers
);
395 if (rctx
->ps_samplers
.depth_texture_mask
) {
396 si_flush_depth_textures(rctx
, &rctx
->ps_samplers
);
400 si_shader_select(ctx
, rctx
->vs_shader
, &vs_dirty
);
402 if (!rctx
->vs_shader
->current
->pm4
) {
403 si_pipe_shader_vs(ctx
, rctx
->vs_shader
->current
);
408 si_pm4_bind_state(rctx
, vs
, rctx
->vs_shader
->current
->pm4
);
412 si_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
414 if (!rctx
->ps_shader
->current
->pm4
) {
415 si_pipe_shader_ps(ctx
, rctx
->ps_shader
->current
);
418 if (!rctx
->ps_shader
->current
->bo
) {
419 if (!rctx
->dummy_pixel_shader
->pm4
)
420 si_pipe_shader_ps(ctx
, rctx
->dummy_pixel_shader
);
422 si_pm4_bind_state(rctx
, vs
, rctx
->dummy_pixel_shader
->pm4
);
428 si_pm4_bind_state(rctx
, ps
, rctx
->ps_shader
->current
->pm4
);
431 if (si_pm4_state_changed(rctx
, ps
) || si_pm4_state_changed(rctx
, vs
)) {
432 /* XXX: Emitting the PS state even when only the VS changed
433 * fixes random failures with piglit glsl-max-varyings.
436 rctx
->emitted
.named
.ps
= NULL
;
437 si_update_spi_map(rctx
);
441 static void si_constant_buffer_update(struct r600_context
*rctx
)
443 struct pipe_context
*ctx
= &rctx
->context
;
444 struct si_pm4_state
*pm4
;
448 if (!rctx
->constbuf_state
[PIPE_SHADER_VERTEX
].dirty_mask
&&
449 !rctx
->constbuf_state
[PIPE_SHADER_FRAGMENT
].dirty_mask
)
452 for (shader
= PIPE_SHADER_VERTEX
; shader
<= PIPE_SHADER_FRAGMENT
; shader
++) {
453 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
455 pm4
= CALLOC_STRUCT(si_pm4_state
);
459 si_pm4_inval_shader_cache(pm4
);
460 si_pm4_sh_data_begin(pm4
);
462 for (i
= 0; i
< 2; i
++) {
463 if (state
->enabled_mask
& (1 << i
)) {
464 struct pipe_constant_buffer
*cb
= &state
->cb
[i
];
465 struct si_resource
*rbuffer
= si_resource(cb
->buffer
);
467 va
= r600_resource_va(ctx
->screen
, (void*)rbuffer
);
468 va
+= cb
->buffer_offset
;
470 si_pm4_add_bo(pm4
, rbuffer
, RADEON_USAGE_READ
);
472 /* Fill in a T# buffer resource description */
473 si_pm4_sh_data_add(pm4
, va
);
474 si_pm4_sh_data_add(pm4
, (S_008F04_BASE_ADDRESS_HI(va
>> 32) |
475 S_008F04_STRIDE(0)));
476 si_pm4_sh_data_add(pm4
, cb
->buffer_size
);
477 si_pm4_sh_data_add(pm4
, S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
478 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
479 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
480 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
481 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
482 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
));
484 /* Fill in an empty T# buffer resource description */
485 si_pm4_sh_data_add(pm4
, 0);
486 si_pm4_sh_data_add(pm4
, 0);
487 si_pm4_sh_data_add(pm4
, 0);
488 si_pm4_sh_data_add(pm4
, 0);
493 case PIPE_SHADER_VERTEX
:
494 si_pm4_sh_data_end(pm4
, R_00B130_SPI_SHADER_USER_DATA_VS_0
, SI_SGPR_CONST
);
495 si_pm4_set_state(rctx
, vs_const
, pm4
);
498 case PIPE_SHADER_FRAGMENT
:
499 si_pm4_sh_data_end(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
, SI_SGPR_CONST
);
500 si_pm4_set_state(rctx
, ps_const
, pm4
);
504 R600_ERR("unsupported %d\n", shader
);
509 state
->dirty_mask
= 0;
513 static void si_vertex_buffer_update(struct r600_context
*rctx
)
515 struct pipe_context
*ctx
= &rctx
->context
;
516 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
517 bool bound
[PIPE_MAX_ATTRIBS
] = {};
521 si_pm4_inval_texture_cache(pm4
);
523 /* bind vertex buffer once */
524 count
= rctx
->vertex_elements
->count
;
525 assert(count
<= 256 / 4);
527 si_pm4_sh_data_begin(pm4
);
528 for (i
= 0 ; i
< count
; i
++) {
529 struct pipe_vertex_element
*ve
= &rctx
->vertex_elements
->elements
[i
];
530 struct pipe_vertex_buffer
*vb
;
531 struct si_resource
*rbuffer
;
534 if (ve
->vertex_buffer_index
>= rctx
->nr_vertex_buffers
)
537 vb
= &rctx
->vertex_buffer
[ve
->vertex_buffer_index
];
538 rbuffer
= (struct si_resource
*)vb
->buffer
;
543 offset
+= vb
->buffer_offset
;
544 offset
+= ve
->src_offset
;
546 va
= r600_resource_va(ctx
->screen
, (void*)rbuffer
);
549 /* Fill in T# buffer resource description */
550 si_pm4_sh_data_add(pm4
, va
& 0xFFFFFFFF);
551 si_pm4_sh_data_add(pm4
, (S_008F04_BASE_ADDRESS_HI(va
>> 32) |
552 S_008F04_STRIDE(vb
->stride
)));
554 /* Round up by rounding down and adding 1 */
555 si_pm4_sh_data_add(pm4
,
556 (vb
->buffer
->width0
- offset
-
557 util_format_get_blocksize(ve
->src_format
)) /
560 si_pm4_sh_data_add(pm4
, vb
->buffer
->width0
- offset
);
561 si_pm4_sh_data_add(pm4
, rctx
->vertex_elements
->rsrc_word3
[i
]);
563 if (!bound
[ve
->vertex_buffer_index
]) {
564 si_pm4_add_bo(pm4
, rbuffer
, RADEON_USAGE_READ
);
565 bound
[ve
->vertex_buffer_index
] = true;
568 si_pm4_sh_data_end(pm4
, R_00B130_SPI_SHADER_USER_DATA_VS_0
, SI_SGPR_VERTEX_BUFFER
);
569 si_pm4_set_state(rctx
, vertex_buffers
, pm4
);
572 static void si_state_draw(struct r600_context
*rctx
,
573 const struct pipe_draw_info
*info
,
574 const struct pipe_index_buffer
*ib
)
576 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
578 /* queries need some special values
579 * (this is non-zero if any query is active) */
580 if (rctx
->num_cs_dw_queries_suspend
) {
581 struct si_state_dsa
*dsa
= rctx
->queued
.named
.dsa
;
583 si_pm4_set_reg(pm4
, R_028004_DB_COUNT_CONTROL
,
584 S_028004_PERFECT_ZPASS_COUNTS(1));
585 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
,
586 dsa
->db_render_override
|
587 S_02800C_NOOP_CULL_DISABLE(1));
591 si_pm4_cmd_begin(pm4
, PKT3_INDEX_TYPE
);
592 if (ib
->index_size
== 4) {
593 si_pm4_cmd_add(pm4
, V_028A7C_VGT_INDEX_32
| (R600_BIG_ENDIAN
?
594 V_028A7C_VGT_DMA_SWAP_32_BIT
: 0));
596 si_pm4_cmd_add(pm4
, V_028A7C_VGT_INDEX_16
| (R600_BIG_ENDIAN
?
597 V_028A7C_VGT_DMA_SWAP_16_BIT
: 0));
599 si_pm4_cmd_end(pm4
, rctx
->predicate_drawing
);
601 si_pm4_cmd_begin(pm4
, PKT3_NUM_INSTANCES
);
602 si_pm4_cmd_add(pm4
, info
->instance_count
);
603 si_pm4_cmd_end(pm4
, rctx
->predicate_drawing
);
606 uint32_t max_size
= (ib
->buffer
->width0
- ib
->offset
) /
607 rctx
->index_buffer
.index_size
;
609 va
= r600_resource_va(&rctx
->screen
->screen
, ib
->buffer
);
612 si_pm4_add_bo(pm4
, (struct si_resource
*)ib
->buffer
, RADEON_USAGE_READ
);
613 si_cmd_draw_index_2(pm4
, max_size
, va
, info
->count
,
614 V_0287F0_DI_SRC_SEL_DMA
,
615 rctx
->predicate_drawing
);
617 uint32_t initiator
= V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
618 initiator
|= S_0287F0_USE_OPAQUE(!!info
->count_from_stream_output
);
619 si_cmd_draw_index_auto(pm4
, info
->count
, initiator
, rctx
->predicate_drawing
);
621 si_pm4_set_state(rctx
, draw
, pm4
);
624 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
626 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
627 struct pipe_index_buffer ib
= {};
628 uint32_t cp_coher_cntl
;
630 if (!info
->count
&& (info
->indexed
|| !info
->count_from_stream_output
))
633 if (!rctx
->ps_shader
|| !rctx
->vs_shader
)
636 si_update_derived_state(rctx
);
637 si_constant_buffer_update(rctx
);
638 si_vertex_buffer_update(rctx
);
641 /* Initialize the index buffer struct. */
642 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
643 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
644 ib
.index_size
= rctx
->index_buffer
.index_size
;
645 ib
.offset
= rctx
->index_buffer
.offset
+ info
->start
* ib
.index_size
;
647 /* Translate or upload, if needed. */
648 r600_translate_index_buffer(rctx
, &ib
, info
->count
);
650 if (ib
.user_buffer
&& !ib
.buffer
) {
651 r600_upload_index_buffer(rctx
, &ib
, info
->count
);
654 } else if (info
->count_from_stream_output
) {
655 r600_context_draw_opaque_count(rctx
, (struct r600_so_target
*)info
->count_from_stream_output
);
658 rctx
->vs_shader_so_strides
= rctx
->vs_shader
->current
->so_strides
;
660 if (!si_update_draw_info_state(rctx
, info
))
663 si_state_draw(rctx
, info
, &ib
);
665 cp_coher_cntl
= si_pm4_sync_flags(rctx
);
667 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
668 si_cmd_surface_sync(pm4
, cp_coher_cntl
);
669 si_pm4_set_state(rctx
, sync
, pm4
);
673 rctx
->pm4_dirty_cdwords
+= si_pm4_dirty_dw(rctx
);
675 si_need_cs_space(rctx
, 0, TRUE
);
677 si_pm4_emit_dirty(rctx
);
678 rctx
->pm4_dirty_cdwords
= 0;
681 if (rctx
->screen
->trace_bo
) {
682 r600_trace_emit(rctx
);
687 /* Enable stream out if needed. */
688 if (rctx
->streamout_start
) {
689 r600_context_streamout_begin(rctx
);
690 rctx
->streamout_start
= FALSE
;
694 rctx
->flags
|= R600_CONTEXT_DST_CACHES_DIRTY
;
696 /* Set the depth buffer as dirty. */
697 if (rctx
->framebuffer
.zsbuf
) {
698 struct pipe_surface
*surf
= rctx
->framebuffer
.zsbuf
;
699 struct r600_resource_texture
*rtex
= (struct r600_resource_texture
*)surf
->texture
;
701 rtex
->dirty_db_mask
|= 1 << surf
->u
.tex
.level
;
704 pipe_resource_reference(&ib
.buffer
, NULL
);