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radeonsi: emit shader pointers before cache flushes & waits
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32
33 #include "ac_debug.h"
34
35 /* special primitive types */
36 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
37
38 static unsigned si_conv_pipe_prim(unsigned mode)
39 {
40 static const unsigned prim_conv[] = {
41 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
42 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
43 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
44 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
45 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
46 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
47 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
48 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
49 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
50 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
51 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
55 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
56 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
57 };
58 assert(mode < ARRAY_SIZE(prim_conv));
59 return prim_conv[mode];
60 }
61
62 static unsigned si_conv_prim_to_gs_out(unsigned mode)
63 {
64 static const int prim_conv[] = {
65 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
66 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
67 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
68 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
69 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
73 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
74 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
75 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
76 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
77 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
78 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
79 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
80 [SI_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
81 };
82 assert(mode < ARRAY_SIZE(prim_conv));
83
84 return prim_conv[mode];
85 }
86
87 /**
88 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
89 * LS.LDS_SIZE is shared by all 3 shader stages.
90 *
91 * The information about LDS and other non-compile-time parameters is then
92 * written to userdata SGPRs.
93 */
94 static void si_emit_derived_tess_state(struct si_context *sctx,
95 const struct pipe_draw_info *info,
96 unsigned *num_patches)
97 {
98 struct radeon_winsys_cs *cs = sctx->gfx_cs;
99 struct si_shader *ls_current;
100 struct si_shader_selector *ls;
101 /* The TES pointer will only be used for sctx->last_tcs.
102 * It would be wrong to think that TCS = TES. */
103 struct si_shader_selector *tcs =
104 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
105 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
106 bool has_primid_instancing_bug = sctx->chip_class == SI &&
107 sctx->screen->info.max_se == 1;
108 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
109 unsigned num_tcs_input_cp = info->vertices_per_patch;
110 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
111 unsigned num_tcs_patch_outputs;
112 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
113 unsigned input_patch_size, output_patch_size, output_patch0_offset;
114 unsigned perpatch_output_offset, lds_size;
115 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
116 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
117
118 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
119 if (sctx->chip_class >= GFX9) {
120 if (sctx->tcs_shader.cso)
121 ls_current = sctx->tcs_shader.current;
122 else
123 ls_current = sctx->fixed_func_tcs_shader.current;
124
125 ls = ls_current->key.part.tcs.ls;
126 } else {
127 ls_current = sctx->vs_shader.current;
128 ls = sctx->vs_shader.cso;
129 }
130
131 if (sctx->last_ls == ls_current &&
132 sctx->last_tcs == tcs &&
133 sctx->last_tes_sh_base == tes_sh_base &&
134 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
135 (!has_primid_instancing_bug ||
136 (sctx->last_tess_uses_primid == tess_uses_primid))) {
137 *num_patches = sctx->last_num_patches;
138 return;
139 }
140
141 sctx->last_ls = ls_current;
142 sctx->last_tcs = tcs;
143 sctx->last_tes_sh_base = tes_sh_base;
144 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
145 sctx->last_tess_uses_primid = tess_uses_primid;
146
147 /* This calculates how shader inputs and outputs among VS, TCS, and TES
148 * are laid out in LDS. */
149 num_tcs_inputs = util_last_bit64(ls->outputs_written);
150
151 if (sctx->tcs_shader.cso) {
152 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
153 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
154 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
155 } else {
156 /* No TCS. Route varyings from LS to TES. */
157 num_tcs_outputs = num_tcs_inputs;
158 num_tcs_output_cp = num_tcs_input_cp;
159 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
160 }
161
162 input_vertex_size = num_tcs_inputs * 16;
163 output_vertex_size = num_tcs_outputs * 16;
164
165 input_patch_size = num_tcs_input_cp * input_vertex_size;
166
167 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
168 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
169
170 /* Ensure that we only need one wave per SIMD so we don't need to check
171 * resource usage. Also ensures that the number of tcs in and out
172 * vertices per threadgroup are at most 256.
173 */
174 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
175
176 /* Make sure that the data fits in LDS. This assumes the shaders only
177 * use LDS for the inputs and outputs.
178 *
179 * While CIK can use 64K per threadgroup, there is a hang on Stoney
180 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
181 * uses 32K at most on all GCN chips.
182 */
183 hardware_lds_size = 32768;
184 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
185 output_patch_size));
186
187 /* Make sure the output data fits in the offchip buffer */
188 *num_patches = MIN2(*num_patches,
189 (sctx->screen->tess_offchip_block_dw_size * 4) /
190 output_patch_size);
191
192 /* Not necessary for correctness, but improves performance. The
193 * specific value is taken from the proprietary driver.
194 */
195 *num_patches = MIN2(*num_patches, 40);
196
197 if (sctx->chip_class == SI) {
198 /* SI bug workaround, related to power management. Limit LS-HS
199 * threadgroups to only one wave.
200 */
201 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
202 *num_patches = MIN2(*num_patches, one_wave);
203 }
204
205 /* The VGT HS block increments the patch ID unconditionally
206 * within a single threadgroup. This results in incorrect
207 * patch IDs when instanced draws are used.
208 *
209 * The intended solution is to restrict threadgroups to
210 * a single instance by setting SWITCH_ON_EOI, which
211 * should cause IA to split instances up. However, this
212 * doesn't work correctly on SI when there is no other
213 * SE to switch to.
214 */
215 if (has_primid_instancing_bug && tess_uses_primid)
216 *num_patches = 1;
217
218 sctx->last_num_patches = *num_patches;
219
220 output_patch0_offset = input_patch_size * *num_patches;
221 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
222
223 /* Compute userdata SGPRs. */
224 assert(((input_vertex_size / 4) & ~0xff) == 0);
225 assert(((output_vertex_size / 4) & ~0xff) == 0);
226 assert(((input_patch_size / 4) & ~0x1fff) == 0);
227 assert(((output_patch_size / 4) & ~0x1fff) == 0);
228 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
229 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
230 assert(num_tcs_input_cp <= 32);
231 assert(num_tcs_output_cp <= 32);
232
233 uint64_t ring_va = r600_resource(sctx->tess_rings)->gpu_address;
234 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
235
236 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
237 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
238 tcs_out_layout = (output_patch_size / 4) |
239 (num_tcs_input_cp << 13) |
240 ring_va;
241 tcs_out_offsets = (output_patch0_offset / 16) |
242 ((perpatch_output_offset / 16) << 16);
243 offchip_layout = *num_patches |
244 (num_tcs_output_cp << 6) |
245 (pervertex_output_patch_size * *num_patches << 12);
246
247 /* Compute the LDS size. */
248 lds_size = output_patch0_offset + output_patch_size * *num_patches;
249
250 if (sctx->chip_class >= CIK) {
251 assert(lds_size <= 65536);
252 lds_size = align(lds_size, 512) / 512;
253 } else {
254 assert(lds_size <= 32768);
255 lds_size = align(lds_size, 256) / 256;
256 }
257
258 /* Set SI_SGPR_VS_STATE_BITS. */
259 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
260 C_VS_STATE_LS_OUT_VERTEX_SIZE;
261 sctx->current_vs_state |= tcs_in_layout;
262
263 if (sctx->chip_class >= GFX9) {
264 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
265 S_00B42C_LDS_SIZE(lds_size);
266
267 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
268
269 /* Set userdata SGPRs for merged LS-HS. */
270 radeon_set_sh_reg_seq(cs,
271 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
272 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
273 radeon_emit(cs, offchip_layout);
274 radeon_emit(cs, tcs_out_offsets);
275 radeon_emit(cs, tcs_out_layout);
276 } else {
277 unsigned ls_rsrc2 = ls_current->config.rsrc2;
278
279 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
280 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
281
282 /* Due to a hw bug, RSRC2_LS must be written twice with another
283 * LS register written in between. */
284 if (sctx->chip_class == CIK && sctx->family != CHIP_HAWAII)
285 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
286 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
287 radeon_emit(cs, ls_current->config.rsrc1);
288 radeon_emit(cs, ls_rsrc2);
289
290 /* Set userdata SGPRs for TCS. */
291 radeon_set_sh_reg_seq(cs,
292 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
293 radeon_emit(cs, offchip_layout);
294 radeon_emit(cs, tcs_out_offsets);
295 radeon_emit(cs, tcs_out_layout);
296 radeon_emit(cs, tcs_in_layout);
297 }
298
299 /* Set userdata SGPRs for TES. */
300 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
301 radeon_emit(cs, offchip_layout);
302 radeon_emit(cs, ring_va);
303
304 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
305 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
306 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
307
308 if (sctx->chip_class >= CIK)
309 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
310 ls_hs_config);
311 else
312 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
313 ls_hs_config);
314 }
315
316 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
317 {
318 switch (info->mode) {
319 case PIPE_PRIM_PATCHES:
320 return info->count / info->vertices_per_patch;
321 case SI_PRIM_RECTANGLE_LIST:
322 return info->count / 3;
323 default:
324 return u_prims_for_vertices(info->mode, info->count);
325 }
326 }
327
328 static unsigned
329 si_get_init_multi_vgt_param(struct si_screen *sscreen,
330 union si_vgt_param_key *key)
331 {
332 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
333 unsigned max_primgroup_in_wave = 2;
334
335 /* SWITCH_ON_EOP(0) is always preferable. */
336 bool wd_switch_on_eop = false;
337 bool ia_switch_on_eop = false;
338 bool ia_switch_on_eoi = false;
339 bool partial_vs_wave = false;
340 bool partial_es_wave = false;
341
342 if (key->u.uses_tess) {
343 /* SWITCH_ON_EOI must be set if PrimID is used. */
344 if (key->u.tess_uses_prim_id)
345 ia_switch_on_eoi = true;
346
347 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
348 if ((sscreen->info.family == CHIP_TAHITI ||
349 sscreen->info.family == CHIP_PITCAIRN ||
350 sscreen->info.family == CHIP_BONAIRE) &&
351 key->u.uses_gs)
352 partial_vs_wave = true;
353
354 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
355 if (sscreen->has_distributed_tess) {
356 if (key->u.uses_gs) {
357 if (sscreen->info.chip_class <= VI)
358 partial_es_wave = true;
359
360 /* GPU hang workaround. */
361 if (sscreen->info.family == CHIP_TONGA ||
362 sscreen->info.family == CHIP_FIJI ||
363 sscreen->info.family == CHIP_POLARIS10 ||
364 sscreen->info.family == CHIP_POLARIS11 ||
365 sscreen->info.family == CHIP_POLARIS12)
366 partial_vs_wave = true;
367 } else {
368 partial_vs_wave = true;
369 }
370 }
371 }
372
373 /* This is a hardware requirement. */
374 if (key->u.line_stipple_enabled ||
375 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
376 ia_switch_on_eop = true;
377 wd_switch_on_eop = true;
378 }
379
380 if (sscreen->info.chip_class >= CIK) {
381 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
382 * 4 shader engines. Set 1 to pass the assertion below.
383 * The other cases are hardware requirements.
384 *
385 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
386 * for points, line strips, and tri strips.
387 */
388 if (sscreen->info.max_se < 4 ||
389 key->u.prim == PIPE_PRIM_POLYGON ||
390 key->u.prim == PIPE_PRIM_LINE_LOOP ||
391 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
392 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
393 (key->u.primitive_restart &&
394 (sscreen->info.family < CHIP_POLARIS10 ||
395 (key->u.prim != PIPE_PRIM_POINTS &&
396 key->u.prim != PIPE_PRIM_LINE_STRIP &&
397 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
398 key->u.count_from_stream_output)
399 wd_switch_on_eop = true;
400
401 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
402 * We don't know that for indirect drawing, so treat it as
403 * always problematic. */
404 if (sscreen->info.family == CHIP_HAWAII &&
405 key->u.uses_instancing)
406 wd_switch_on_eop = true;
407
408 /* Performance recommendation for 4 SE Gfx7-8 parts if
409 * instances are smaller than a primgroup.
410 * Assume indirect draws always use small instances.
411 * This is needed for good VS wave utilization.
412 */
413 if (sscreen->info.chip_class <= VI &&
414 sscreen->info.max_se == 4 &&
415 key->u.multi_instances_smaller_than_primgroup)
416 wd_switch_on_eop = true;
417
418 /* Required on CIK and later. */
419 if (sscreen->info.max_se > 2 && !wd_switch_on_eop)
420 ia_switch_on_eoi = true;
421
422 /* Required by Hawaii and, for some special cases, by VI. */
423 if (ia_switch_on_eoi &&
424 (sscreen->info.family == CHIP_HAWAII ||
425 (sscreen->info.chip_class == VI &&
426 (key->u.uses_gs || max_primgroup_in_wave != 2))))
427 partial_vs_wave = true;
428
429 /* Instancing bug on Bonaire. */
430 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
431 key->u.uses_instancing)
432 partial_vs_wave = true;
433
434 /* If the WD switch is false, the IA switch must be false too. */
435 assert(wd_switch_on_eop || !ia_switch_on_eop);
436 }
437
438 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
439 if (sscreen->info.chip_class <= VI && ia_switch_on_eoi)
440 partial_es_wave = true;
441
442 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
443 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
444 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
445 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
446 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= CIK ? wd_switch_on_eop : 0) |
447 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
448 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == VI ?
449 max_primgroup_in_wave : 0) |
450 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
451 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
452 }
453
454 void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
455 {
456 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
457 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
458 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
459 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
460 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
461 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
462 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
463 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
464 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
465 union si_vgt_param_key key;
466
467 key.index = 0;
468 key.u.prim = prim;
469 key.u.uses_instancing = uses_instancing;
470 key.u.multi_instances_smaller_than_primgroup = multi_instances;
471 key.u.primitive_restart = primitive_restart;
472 key.u.count_from_stream_output = count_from_so;
473 key.u.line_stipple_enabled = line_stipple;
474 key.u.uses_tess = uses_tess;
475 key.u.tess_uses_prim_id = tess_uses_primid;
476 key.u.uses_gs = uses_gs;
477
478 sctx->ia_multi_vgt_param[key.index] =
479 si_get_init_multi_vgt_param(sctx->screen, &key);
480 }
481 }
482
483 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
484 const struct pipe_draw_info *info,
485 unsigned num_patches)
486 {
487 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
488 unsigned primgroup_size;
489 unsigned ia_multi_vgt_param;
490
491 if (sctx->tes_shader.cso) {
492 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
493 } else if (sctx->gs_shader.cso) {
494 primgroup_size = 64; /* recommended with a GS */
495 } else {
496 primgroup_size = 128; /* recommended without a GS and tess */
497 }
498
499 key.u.prim = info->mode;
500 key.u.uses_instancing = info->indirect || info->instance_count > 1;
501 key.u.multi_instances_smaller_than_primgroup =
502 info->indirect ||
503 (info->instance_count > 1 &&
504 (info->count_from_stream_output ||
505 si_num_prims_for_vertices(info) < primgroup_size));
506 key.u.primitive_restart = info->primitive_restart;
507 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
508
509 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
510 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
511
512 if (sctx->gs_shader.cso) {
513 /* GS requirement. */
514 if (sctx->chip_class <= VI &&
515 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
516 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
517
518 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
519 * The hw doc says all multi-SE chips are affected, but Vulkan
520 * only applies it to Hawaii. Do what Vulkan does.
521 */
522 if (sctx->family == CHIP_HAWAII &&
523 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
524 (info->indirect ||
525 (info->instance_count > 1 &&
526 (info->count_from_stream_output ||
527 si_num_prims_for_vertices(info) <= 1))))
528 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
529 }
530
531 return ia_multi_vgt_param;
532 }
533
534 /* rast_prim is the primitive type after GS. */
535 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
536 {
537 struct radeon_winsys_cs *cs = sctx->gfx_cs;
538 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
539 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
540
541 /* Skip this if not rendering lines. */
542 if (rast_prim != PIPE_PRIM_LINES &&
543 rast_prim != PIPE_PRIM_LINE_LOOP &&
544 rast_prim != PIPE_PRIM_LINE_STRIP &&
545 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
546 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
547 return;
548
549 if (rast_prim == sctx->last_rast_prim &&
550 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
551 return;
552
553 /* For lines, reset the stipple pattern at each primitive. Otherwise,
554 * reset the stipple pattern at each packet (line strips, line loops).
555 */
556 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
557 rs->pa_sc_line_stipple |
558 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
559
560 sctx->last_rast_prim = rast_prim;
561 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
562 }
563
564 static void si_emit_vs_state(struct si_context *sctx,
565 const struct pipe_draw_info *info)
566 {
567 sctx->current_vs_state &= C_VS_STATE_INDEXED;
568 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
569
570 if (sctx->num_vs_blit_sgprs) {
571 /* Re-emit the state after we leave u_blitter. */
572 sctx->last_vs_state = ~0;
573 return;
574 }
575
576 if (sctx->current_vs_state != sctx->last_vs_state) {
577 struct radeon_winsys_cs *cs = sctx->gfx_cs;
578
579 radeon_set_sh_reg(cs,
580 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
581 SI_SGPR_VS_STATE_BITS * 4,
582 sctx->current_vs_state);
583
584 sctx->last_vs_state = sctx->current_vs_state;
585 }
586 }
587
588 static void si_emit_draw_registers(struct si_context *sctx,
589 const struct pipe_draw_info *info,
590 unsigned num_patches)
591 {
592 struct radeon_winsys_cs *cs = sctx->gfx_cs;
593 unsigned prim = si_conv_pipe_prim(info->mode);
594 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
595 unsigned ia_multi_vgt_param;
596
597 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
598
599 /* Draw state. */
600 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
601 if (sctx->chip_class >= GFX9)
602 radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
603 else if (sctx->chip_class >= CIK)
604 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
605 else
606 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
607
608 sctx->last_multi_vgt_param = ia_multi_vgt_param;
609 }
610 if (prim != sctx->last_prim) {
611 if (sctx->chip_class >= CIK)
612 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
613 else
614 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
615
616 sctx->last_prim = prim;
617 }
618
619 if (gs_out_prim != sctx->last_gs_out_prim) {
620 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
621 sctx->last_gs_out_prim = gs_out_prim;
622 }
623
624 /* Primitive restart. */
625 if (info->primitive_restart != sctx->last_primitive_restart_en) {
626 if (sctx->chip_class >= GFX9)
627 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
628 info->primitive_restart);
629 else
630 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
631 info->primitive_restart);
632
633 sctx->last_primitive_restart_en = info->primitive_restart;
634
635 }
636 if (info->primitive_restart &&
637 (info->restart_index != sctx->last_restart_index ||
638 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
639 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
640 info->restart_index);
641 sctx->last_restart_index = info->restart_index;
642 }
643 }
644
645 static void si_emit_draw_packets(struct si_context *sctx,
646 const struct pipe_draw_info *info,
647 struct pipe_resource *indexbuf,
648 unsigned index_size,
649 unsigned index_offset)
650 {
651 struct pipe_draw_indirect_info *indirect = info->indirect;
652 struct radeon_winsys_cs *cs = sctx->gfx_cs;
653 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
654 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
655 uint32_t index_max_size = 0;
656 uint64_t index_va = 0;
657
658 if (info->count_from_stream_output) {
659 struct si_streamout_target *t =
660 (struct si_streamout_target*)info->count_from_stream_output;
661 uint64_t va = t->buf_filled_size->gpu_address +
662 t->buf_filled_size_offset;
663
664 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
665 t->stride_in_dw);
666
667 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
668 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
669 COPY_DATA_DST_SEL(COPY_DATA_REG) |
670 COPY_DATA_WR_CONFIRM);
671 radeon_emit(cs, va); /* src address lo */
672 radeon_emit(cs, va >> 32); /* src address hi */
673 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
674 radeon_emit(cs, 0); /* unused */
675
676 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
677 t->buf_filled_size, RADEON_USAGE_READ,
678 RADEON_PRIO_SO_FILLED_SIZE);
679 }
680
681 /* draw packet */
682 if (index_size) {
683 if (index_size != sctx->last_index_size) {
684 unsigned index_type;
685
686 /* index type */
687 switch (index_size) {
688 case 1:
689 index_type = V_028A7C_VGT_INDEX_8;
690 break;
691 case 2:
692 index_type = V_028A7C_VGT_INDEX_16 |
693 (SI_BIG_ENDIAN && sctx->chip_class <= CIK ?
694 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
695 break;
696 case 4:
697 index_type = V_028A7C_VGT_INDEX_32 |
698 (SI_BIG_ENDIAN && sctx->chip_class <= CIK ?
699 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
700 break;
701 default:
702 assert(!"unreachable");
703 return;
704 }
705
706 if (sctx->chip_class >= GFX9) {
707 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
708 2, index_type);
709 } else {
710 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
711 radeon_emit(cs, index_type);
712 }
713
714 sctx->last_index_size = index_size;
715 }
716
717 index_max_size = (indexbuf->width0 - index_offset) /
718 index_size;
719 index_va = r600_resource(indexbuf)->gpu_address + index_offset;
720
721 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
722 (struct r600_resource *)indexbuf,
723 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
724 } else {
725 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
726 * so the state must be re-emitted before the next indexed draw.
727 */
728 if (sctx->chip_class >= CIK)
729 sctx->last_index_size = -1;
730 }
731
732 if (indirect) {
733 uint64_t indirect_va = r600_resource(indirect->buffer)->gpu_address;
734
735 assert(indirect_va % 8 == 0);
736
737 si_invalidate_draw_sh_constants(sctx);
738
739 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
740 radeon_emit(cs, 1);
741 radeon_emit(cs, indirect_va);
742 radeon_emit(cs, indirect_va >> 32);
743
744 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
745 (struct r600_resource *)indirect->buffer,
746 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
747
748 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
749 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
750
751 assert(indirect->offset % 4 == 0);
752
753 if (index_size) {
754 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
755 radeon_emit(cs, index_va);
756 radeon_emit(cs, index_va >> 32);
757
758 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
759 radeon_emit(cs, index_max_size);
760 }
761
762 if (!sctx->screen->has_draw_indirect_multi) {
763 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
764 : PKT3_DRAW_INDIRECT,
765 3, render_cond_bit));
766 radeon_emit(cs, indirect->offset);
767 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
768 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
769 radeon_emit(cs, di_src_sel);
770 } else {
771 uint64_t count_va = 0;
772
773 if (indirect->indirect_draw_count) {
774 struct r600_resource *params_buf =
775 (struct r600_resource *)indirect->indirect_draw_count;
776
777 radeon_add_to_buffer_list(
778 sctx, sctx->gfx_cs, params_buf,
779 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
780
781 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
782 }
783
784 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
785 PKT3_DRAW_INDIRECT_MULTI,
786 8, render_cond_bit));
787 radeon_emit(cs, indirect->offset);
788 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
789 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
790 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
791 S_2C3_DRAW_INDEX_ENABLE(1) |
792 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
793 radeon_emit(cs, indirect->draw_count);
794 radeon_emit(cs, count_va);
795 radeon_emit(cs, count_va >> 32);
796 radeon_emit(cs, indirect->stride);
797 radeon_emit(cs, di_src_sel);
798 }
799 } else {
800 int base_vertex;
801
802 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
803 radeon_emit(cs, info->instance_count);
804
805 /* Base vertex and start instance. */
806 base_vertex = index_size ? info->index_bias : info->start;
807
808 if (sctx->num_vs_blit_sgprs) {
809 /* Re-emit draw constants after we leave u_blitter. */
810 si_invalidate_draw_sh_constants(sctx);
811
812 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
813 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
814 sctx->num_vs_blit_sgprs);
815 radeon_emit_array(cs, sctx->vs_blit_sh_data,
816 sctx->num_vs_blit_sgprs);
817 } else if (base_vertex != sctx->last_base_vertex ||
818 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
819 info->start_instance != sctx->last_start_instance ||
820 info->drawid != sctx->last_drawid ||
821 sh_base_reg != sctx->last_sh_base_reg) {
822 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
823 radeon_emit(cs, base_vertex);
824 radeon_emit(cs, info->start_instance);
825 radeon_emit(cs, info->drawid);
826
827 sctx->last_base_vertex = base_vertex;
828 sctx->last_start_instance = info->start_instance;
829 sctx->last_drawid = info->drawid;
830 sctx->last_sh_base_reg = sh_base_reg;
831 }
832
833 if (index_size) {
834 index_va += info->start * index_size;
835
836 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
837 radeon_emit(cs, index_max_size);
838 radeon_emit(cs, index_va);
839 radeon_emit(cs, index_va >> 32);
840 radeon_emit(cs, info->count);
841 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
842 } else {
843 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
844 radeon_emit(cs, info->count);
845 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
846 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
847 }
848 }
849 }
850
851 static void si_emit_surface_sync(struct si_context *sctx,
852 unsigned cp_coher_cntl)
853 {
854 struct radeon_winsys_cs *cs = sctx->gfx_cs;
855
856 if (sctx->chip_class >= GFX9) {
857 /* Flush caches and wait for the caches to assert idle. */
858 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
859 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
860 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
861 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
862 radeon_emit(cs, 0); /* CP_COHER_BASE */
863 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
864 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
865 } else {
866 /* ACQUIRE_MEM is only required on a compute ring. */
867 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
868 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
869 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
870 radeon_emit(cs, 0); /* CP_COHER_BASE */
871 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
872 }
873 }
874
875 void si_emit_cache_flush(struct si_context *sctx)
876 {
877 struct radeon_winsys_cs *cs = sctx->gfx_cs;
878 uint32_t flags = sctx->flags;
879 uint32_t cp_coher_cntl = 0;
880 uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
881 SI_CONTEXT_FLUSH_AND_INV_DB);
882
883 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
884 sctx->num_cb_cache_flushes++;
885 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
886 sctx->num_db_cache_flushes++;
887
888 /* SI has a bug that it always flushes ICACHE and KCACHE if either
889 * bit is set. An alternative way is to write SQC_CACHES, but that
890 * doesn't seem to work reliably. Since the bug doesn't affect
891 * correctness (it only does more work than necessary) and
892 * the performance impact is likely negligible, there is no plan
893 * to add a workaround for it.
894 */
895
896 if (flags & SI_CONTEXT_INV_ICACHE)
897 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
898 if (flags & SI_CONTEXT_INV_SMEM_L1)
899 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
900
901 if (sctx->chip_class <= VI) {
902 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
903 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
904 S_0085F0_CB0_DEST_BASE_ENA(1) |
905 S_0085F0_CB1_DEST_BASE_ENA(1) |
906 S_0085F0_CB2_DEST_BASE_ENA(1) |
907 S_0085F0_CB3_DEST_BASE_ENA(1) |
908 S_0085F0_CB4_DEST_BASE_ENA(1) |
909 S_0085F0_CB5_DEST_BASE_ENA(1) |
910 S_0085F0_CB6_DEST_BASE_ENA(1) |
911 S_0085F0_CB7_DEST_BASE_ENA(1);
912
913 /* Necessary for DCC */
914 if (sctx->chip_class == VI)
915 si_gfx_write_event_eop(sctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
916 0, EOP_DATA_SEL_DISCARD, NULL,
917 0, 0, SI_NOT_QUERY);
918 }
919 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
920 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
921 S_0085F0_DB_DEST_BASE_ENA(1);
922 }
923
924 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
925 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
926 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
927 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
928 }
929 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
930 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
931 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
932 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
933 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
934 }
935
936 /* Wait for shader engines to go idle.
937 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
938 * for everything including CB/DB cache flushes.
939 */
940 if (!flush_cb_db) {
941 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
942 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
943 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
944 /* Only count explicit shader flushes, not implicit ones
945 * done by SURFACE_SYNC.
946 */
947 sctx->num_vs_flushes++;
948 sctx->num_ps_flushes++;
949 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
950 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
951 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
952 sctx->num_vs_flushes++;
953 }
954 }
955
956 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
957 sctx->compute_is_busy) {
958 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
959 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
960 sctx->num_cs_flushes++;
961 sctx->compute_is_busy = false;
962 }
963
964 /* VGT state synchronization. */
965 if (flags & SI_CONTEXT_VGT_FLUSH) {
966 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
967 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
968 }
969 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
970 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
971 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
972 }
973
974 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
975 * wait for idle on GFX9. We have to use a TS event.
976 */
977 if (sctx->chip_class >= GFX9 && flush_cb_db) {
978 uint64_t va;
979 unsigned tc_flags, cb_db_event;
980
981 /* Set the CB/DB flush event. */
982 switch (flush_cb_db) {
983 case SI_CONTEXT_FLUSH_AND_INV_CB:
984 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
985 break;
986 case SI_CONTEXT_FLUSH_AND_INV_DB:
987 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
988 break;
989 default:
990 /* both CB & DB */
991 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
992 }
993
994 /* These are the only allowed combinations. If you need to
995 * do multiple operations at once, do them separately.
996 * All operations that invalidate L2 also seem to invalidate
997 * metadata. Volatile (VOL) and WC flushes are not listed here.
998 *
999 * TC | TC_WB = writeback & invalidate L2 & L1
1000 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1001 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1002 * TC | TC_NC = invalidate L2 for MTYPE == NC
1003 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1004 * TCL1 = invalidate L1
1005 */
1006 tc_flags = 0;
1007
1008 if (flags & SI_CONTEXT_INV_L2_METADATA) {
1009 tc_flags = EVENT_TC_ACTION_ENA |
1010 EVENT_TC_MD_ACTION_ENA;
1011 }
1012
1013 /* Ideally flush TC together with CB/DB. */
1014 if (flags & SI_CONTEXT_INV_GLOBAL_L2) {
1015 /* Writeback and invalidate everything in L2 & L1. */
1016 tc_flags = EVENT_TC_ACTION_ENA |
1017 EVENT_TC_WB_ACTION_ENA;
1018
1019 /* Clear the flags. */
1020 flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
1021 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
1022 SI_CONTEXT_INV_VMEM_L1);
1023 sctx->num_L2_invalidates++;
1024 }
1025
1026 /* Do the flush (enqueue the event and wait for it). */
1027 va = sctx->wait_mem_scratch->gpu_address;
1028 sctx->wait_mem_number++;
1029
1030 si_gfx_write_event_eop(sctx, cb_db_event, tc_flags,
1031 EOP_DATA_SEL_VALUE_32BIT,
1032 sctx->wait_mem_scratch, va,
1033 sctx->wait_mem_number, SI_NOT_QUERY);
1034 si_gfx_wait_fence(sctx, va, sctx->wait_mem_number, 0xffffffff);
1035 }
1036
1037 /* Make sure ME is idle (it executes most packets) before continuing.
1038 * This prevents read-after-write hazards between PFP and ME.
1039 */
1040 if (cp_coher_cntl ||
1041 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1042 SI_CONTEXT_INV_VMEM_L1 |
1043 SI_CONTEXT_INV_GLOBAL_L2 |
1044 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1045 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1046 radeon_emit(cs, 0);
1047 }
1048
1049 /* SI-CI-VI only:
1050 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1051 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1052 *
1053 * cp_coher_cntl should contain all necessary flags except TC flags
1054 * at this point.
1055 *
1056 * SI-CIK don't support L2 write-back.
1057 */
1058 if (flags & SI_CONTEXT_INV_GLOBAL_L2 ||
1059 (sctx->chip_class <= CIK &&
1060 (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1061 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
1062 * WB must be set on VI+ when TC_ACTION is set.
1063 */
1064 si_emit_surface_sync(sctx, cp_coher_cntl |
1065 S_0085F0_TC_ACTION_ENA(1) |
1066 S_0085F0_TCL1_ACTION_ENA(1) |
1067 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= VI));
1068 cp_coher_cntl = 0;
1069 sctx->num_L2_invalidates++;
1070 } else {
1071 /* L1 invalidation and L2 writeback must be done separately,
1072 * because both operations can't be done together.
1073 */
1074 if (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
1075 /* WB = write-back
1076 * NC = apply to non-coherent MTYPEs
1077 * (i.e. MTYPE <= 1, which is what we use everywhere)
1078 *
1079 * WB doesn't work without NC.
1080 */
1081 si_emit_surface_sync(sctx, cp_coher_cntl |
1082 S_0301F0_TC_WB_ACTION_ENA(1) |
1083 S_0301F0_TC_NC_ACTION_ENA(1));
1084 cp_coher_cntl = 0;
1085 sctx->num_L2_writebacks++;
1086 }
1087 if (flags & SI_CONTEXT_INV_VMEM_L1) {
1088 /* Invalidate per-CU VMEM L1. */
1089 si_emit_surface_sync(sctx, cp_coher_cntl |
1090 S_0085F0_TCL1_ACTION_ENA(1));
1091 cp_coher_cntl = 0;
1092 }
1093 }
1094
1095 /* If TC flushes haven't cleared this... */
1096 if (cp_coher_cntl)
1097 si_emit_surface_sync(sctx, cp_coher_cntl);
1098
1099 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1100 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1101 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1102 EVENT_INDEX(0));
1103 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1104 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1105 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1106 EVENT_INDEX(0));
1107 }
1108
1109 sctx->flags = 0;
1110 }
1111
1112 static void si_get_draw_start_count(struct si_context *sctx,
1113 const struct pipe_draw_info *info,
1114 unsigned *start, unsigned *count)
1115 {
1116 struct pipe_draw_indirect_info *indirect = info->indirect;
1117
1118 if (indirect) {
1119 unsigned indirect_count;
1120 struct pipe_transfer *transfer;
1121 unsigned begin, end;
1122 unsigned map_size;
1123 unsigned *data;
1124
1125 if (indirect->indirect_draw_count) {
1126 data = pipe_buffer_map_range(&sctx->b,
1127 indirect->indirect_draw_count,
1128 indirect->indirect_draw_count_offset,
1129 sizeof(unsigned),
1130 PIPE_TRANSFER_READ, &transfer);
1131
1132 indirect_count = *data;
1133
1134 pipe_buffer_unmap(&sctx->b, transfer);
1135 } else {
1136 indirect_count = indirect->draw_count;
1137 }
1138
1139 if (!indirect_count) {
1140 *start = *count = 0;
1141 return;
1142 }
1143
1144 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1145 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1146 indirect->offset, map_size,
1147 PIPE_TRANSFER_READ, &transfer);
1148
1149 begin = UINT_MAX;
1150 end = 0;
1151
1152 for (unsigned i = 0; i < indirect_count; ++i) {
1153 unsigned count = data[0];
1154 unsigned start = data[2];
1155
1156 if (count > 0) {
1157 begin = MIN2(begin, start);
1158 end = MAX2(end, start + count);
1159 }
1160
1161 data += indirect->stride / sizeof(unsigned);
1162 }
1163
1164 pipe_buffer_unmap(&sctx->b, transfer);
1165
1166 if (begin < end) {
1167 *start = begin;
1168 *count = end - begin;
1169 } else {
1170 *start = *count = 0;
1171 }
1172 } else {
1173 *start = info->start;
1174 *count = info->count;
1175 }
1176 }
1177
1178 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1179 unsigned skip_atom_mask)
1180 {
1181 /* Emit state atoms. */
1182 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1183 while (mask) {
1184 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
1185
1186 atom->emit(sctx, atom);
1187 }
1188 sctx->dirty_atoms &= skip_atom_mask;
1189
1190 /* Emit states. */
1191 mask = sctx->dirty_states;
1192 while (mask) {
1193 unsigned i = u_bit_scan(&mask);
1194 struct si_pm4_state *state = sctx->queued.array[i];
1195
1196 if (!state || sctx->emitted.array[i] == state)
1197 continue;
1198
1199 si_pm4_emit(sctx, state);
1200 sctx->emitted.array[i] = state;
1201 }
1202 sctx->dirty_states = 0;
1203
1204 /* Emit draw states. */
1205 unsigned num_patches = 0;
1206
1207 si_emit_rasterizer_prim_state(sctx);
1208 if (sctx->tes_shader.cso)
1209 si_emit_derived_tess_state(sctx, info, &num_patches);
1210 si_emit_vs_state(sctx, info);
1211 si_emit_draw_registers(sctx, info, num_patches);
1212 }
1213
1214 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1215 {
1216 struct si_context *sctx = (struct si_context *)ctx;
1217 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1218 struct pipe_resource *indexbuf = info->index.resource;
1219 unsigned dirty_tex_counter;
1220 enum pipe_prim_type rast_prim;
1221 unsigned index_size = info->index_size;
1222 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1223
1224 if (likely(!info->indirect)) {
1225 /* SI-CI treat instance_count==0 as instance_count==1. There is
1226 * no workaround for indirect draws, but we can at least skip
1227 * direct draws.
1228 */
1229 if (unlikely(!info->instance_count))
1230 return;
1231
1232 /* Handle count == 0. */
1233 if (unlikely(!info->count &&
1234 (index_size || !info->count_from_stream_output)))
1235 return;
1236 }
1237
1238 if (unlikely(!sctx->vs_shader.cso)) {
1239 assert(0);
1240 return;
1241 }
1242 if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
1243 assert(0);
1244 return;
1245 }
1246 if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
1247 assert(0);
1248 return;
1249 }
1250
1251 /* Recompute and re-emit the texture resource states if needed. */
1252 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1253 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1254 sctx->last_dirty_tex_counter = dirty_tex_counter;
1255 sctx->framebuffer.dirty_cbufs |=
1256 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1257 sctx->framebuffer.dirty_zsbuf = true;
1258 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
1259 si_update_all_texture_descriptors(sctx);
1260 }
1261
1262 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1263
1264 /* Set the rasterization primitive type.
1265 *
1266 * This must be done after si_decompress_textures, which can call
1267 * draw_vbo recursively, and before si_update_shaders, which uses
1268 * current_rast_prim for this draw_vbo call. */
1269 if (sctx->gs_shader.cso)
1270 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1271 else if (sctx->tes_shader.cso) {
1272 if (sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1273 rast_prim = PIPE_PRIM_POINTS;
1274 else
1275 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1276 } else
1277 rast_prim = info->mode;
1278
1279 if (rast_prim != sctx->current_rast_prim) {
1280 bool old_is_poly = sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES;
1281 bool new_is_poly = rast_prim >= PIPE_PRIM_TRIANGLES;
1282 if (old_is_poly != new_is_poly) {
1283 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1284 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
1285 }
1286
1287 sctx->current_rast_prim = rast_prim;
1288 sctx->do_update_shaders = true;
1289 }
1290
1291 if (sctx->tes_shader.cso &&
1292 sctx->screen->has_ls_vgpr_init_bug) {
1293 /* Determine whether the LS VGPR fix should be applied.
1294 *
1295 * It is only required when num input CPs > num output CPs,
1296 * which cannot happen with the fixed function TCS. We should
1297 * also update this bit when switching from TCS to fixed
1298 * function TCS.
1299 */
1300 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1301 bool ls_vgpr_fix =
1302 tcs &&
1303 info->vertices_per_patch >
1304 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1305
1306 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1307 sctx->ls_vgpr_fix = ls_vgpr_fix;
1308 sctx->do_update_shaders = true;
1309 }
1310 }
1311
1312 if (sctx->gs_shader.cso) {
1313 /* Determine whether the GS triangle strip adjacency fix should
1314 * be applied. Rotate every other triangle if
1315 * - triangle strips with adjacency are fed to the GS and
1316 * - primitive restart is disabled (the rotation doesn't help
1317 * when the restart occurs after an odd number of triangles).
1318 */
1319 bool gs_tri_strip_adj_fix =
1320 !sctx->tes_shader.cso &&
1321 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1322 !info->primitive_restart;
1323
1324 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1325 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1326 sctx->do_update_shaders = true;
1327 }
1328 }
1329
1330 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1331 return;
1332
1333 if (index_size) {
1334 /* Translate or upload, if needed. */
1335 /* 8-bit indices are supported on VI. */
1336 if (sctx->chip_class <= CIK && index_size == 1) {
1337 unsigned start, count, start_offset, size, offset;
1338 void *ptr;
1339
1340 si_get_draw_start_count(sctx, info, &start, &count);
1341 start_offset = start * 2;
1342 size = count * 2;
1343
1344 indexbuf = NULL;
1345 u_upload_alloc(ctx->stream_uploader, start_offset,
1346 size,
1347 si_optimal_tcc_alignment(sctx, size),
1348 &offset, &indexbuf, &ptr);
1349 if (!indexbuf)
1350 return;
1351
1352 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1353 index_offset + start,
1354 count, ptr);
1355
1356 /* info->start will be added by the drawing code */
1357 index_offset = offset - start_offset;
1358 index_size = 2;
1359 } else if (info->has_user_indices) {
1360 unsigned start_offset;
1361
1362 assert(!info->indirect);
1363 start_offset = info->start * index_size;
1364
1365 indexbuf = NULL;
1366 u_upload_data(ctx->stream_uploader, start_offset,
1367 info->count * index_size,
1368 sctx->screen->info.tcc_cache_line_size,
1369 (char*)info->index.user + start_offset,
1370 &index_offset, &indexbuf);
1371 if (!indexbuf)
1372 return;
1373
1374 /* info->start will be added by the drawing code */
1375 index_offset -= start_offset;
1376 } else if (sctx->chip_class <= CIK &&
1377 r600_resource(indexbuf)->TC_L2_dirty) {
1378 /* VI reads index buffers through TC L2, so it doesn't
1379 * need this. */
1380 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1381 r600_resource(indexbuf)->TC_L2_dirty = false;
1382 }
1383 }
1384
1385 if (info->indirect) {
1386 struct pipe_draw_indirect_info *indirect = info->indirect;
1387
1388 /* Add the buffer size for memory checking in need_cs_space. */
1389 si_context_add_resource_size(sctx, indirect->buffer);
1390
1391 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1392 if (sctx->chip_class <= VI) {
1393 if (r600_resource(indirect->buffer)->TC_L2_dirty) {
1394 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1395 r600_resource(indirect->buffer)->TC_L2_dirty = false;
1396 }
1397
1398 if (indirect->indirect_draw_count &&
1399 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1400 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1401 r600_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1402 }
1403 }
1404 }
1405
1406 si_need_gfx_cs_space(sctx);
1407
1408 /* Since we've called si_context_add_resource_size for vertex buffers,
1409 * this must be called after si_need_cs_space, because we must let
1410 * need_cs_space flush before we add buffers to the buffer list.
1411 */
1412 if (!si_upload_vertex_buffer_descriptors(sctx))
1413 return;
1414
1415 /* Vega10/Raven scissor bug workaround. This must be done before VPORT
1416 * scissor registers are changed. There is also a more efficient but
1417 * more involved alternative workaround.
1418 */
1419 if ((sctx->family == CHIP_VEGA10 || sctx->family == CHIP_RAVEN) &&
1420 si_is_atom_dirty(sctx, &sctx->scissors.atom)) {
1421 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
1422 si_emit_cache_flush(sctx);
1423 }
1424
1425 /* Use optimal packet order based on whether we need to sync the pipeline. */
1426 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1427 SI_CONTEXT_FLUSH_AND_INV_DB |
1428 SI_CONTEXT_PS_PARTIAL_FLUSH |
1429 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1430 /* If we have to wait for idle, set all states first, so that all
1431 * SET packets are processed in parallel with previous draw calls.
1432 * Then draw and prefetch at the end. This ensures that the time
1433 * the CUs are idle is very short.
1434 */
1435 unsigned masked_atoms = 0;
1436
1437 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
1438 masked_atoms |= 1u << sctx->render_cond_atom.id;
1439
1440 if (!si_upload_graphics_shader_descriptors(sctx))
1441 return;
1442
1443 /* Emit all states except possibly render condition. */
1444 si_emit_all_states(sctx, info, masked_atoms);
1445 si_emit_cache_flush(sctx);
1446 /* <-- CUs are idle here. */
1447
1448 if (si_is_atom_dirty(sctx, &sctx->render_cond_atom))
1449 sctx->render_cond_atom.emit(sctx, NULL);
1450 sctx->dirty_atoms = 0;
1451
1452 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1453 /* <-- CUs are busy here. */
1454
1455 /* Start prefetches after the draw has been started. Both will run
1456 * in parallel, but starting the draw first is more important.
1457 */
1458 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1459 cik_emit_prefetch_L2(sctx);
1460 } else {
1461 /* If we don't wait for idle, start prefetches first, then set
1462 * states, and draw at the end.
1463 */
1464 if (sctx->flags)
1465 si_emit_cache_flush(sctx);
1466
1467 if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
1468 cik_emit_prefetch_L2(sctx);
1469
1470 if (!si_upload_graphics_shader_descriptors(sctx))
1471 return;
1472
1473 si_emit_all_states(sctx, info, 0);
1474 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
1475 }
1476
1477 if (unlikely(sctx->current_saved_cs)) {
1478 si_trace_emit(sctx);
1479 si_log_draw_state(sctx, sctx->log);
1480 }
1481
1482 /* Workaround for a VGT hang when streamout is enabled.
1483 * It must be done after drawing. */
1484 if ((sctx->family == CHIP_HAWAII ||
1485 sctx->family == CHIP_TONGA ||
1486 sctx->family == CHIP_FIJI) &&
1487 si_get_strmout_en(sctx)) {
1488 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1489 }
1490
1491 if (unlikely(sctx->decompression_enabled)) {
1492 sctx->num_decompress_calls++;
1493 } else {
1494 sctx->num_draw_calls++;
1495 if (sctx->framebuffer.state.nr_cbufs > 1)
1496 sctx->num_mrt_draw_calls++;
1497 if (info->primitive_restart)
1498 sctx->num_prim_restart_calls++;
1499 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1500 sctx->num_spill_draw_calls++;
1501 }
1502 if (index_size && indexbuf != info->index.resource)
1503 pipe_resource_reference(&indexbuf, NULL);
1504 }
1505
1506 void si_draw_rectangle(struct blitter_context *blitter,
1507 void *vertex_elements_cso,
1508 blitter_get_vs_func get_vs,
1509 int x1, int y1, int x2, int y2,
1510 float depth, unsigned num_instances,
1511 enum blitter_attrib_type type,
1512 const union blitter_attrib *attrib)
1513 {
1514 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
1515 struct si_context *sctx = (struct si_context*)pipe;
1516
1517 /* Pack position coordinates as signed int16. */
1518 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
1519 ((uint32_t)(y1 & 0xffff) << 16);
1520 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
1521 ((uint32_t)(y2 & 0xffff) << 16);
1522 sctx->vs_blit_sh_data[2] = fui(depth);
1523
1524 switch (type) {
1525 case UTIL_BLITTER_ATTRIB_COLOR:
1526 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
1527 sizeof(float)*4);
1528 break;
1529 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
1530 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
1531 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
1532 sizeof(attrib->texcoord));
1533 break;
1534 case UTIL_BLITTER_ATTRIB_NONE:;
1535 }
1536
1537 pipe->bind_vs_state(pipe, si_get_blit_vs(sctx, type, num_instances));
1538
1539 struct pipe_draw_info info = {};
1540 info.mode = SI_PRIM_RECTANGLE_LIST;
1541 info.count = 3;
1542 info.instance_count = num_instances;
1543
1544 /* Don't set per-stage shader pointers for VS. */
1545 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
1546 sctx->vertex_buffer_pointer_dirty = false;
1547
1548 si_draw_vbo(pipe, &info);
1549 }
1550
1551 void si_trace_emit(struct si_context *sctx)
1552 {
1553 struct radeon_winsys_cs *cs = sctx->gfx_cs;
1554 uint64_t va = sctx->current_saved_cs->trace_buf->gpu_address;
1555 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
1556
1557 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1558 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1559 S_370_WR_CONFIRM(1) |
1560 S_370_ENGINE_SEL(V_370_ME));
1561 radeon_emit(cs, va);
1562 radeon_emit(cs, va >> 32);
1563 radeon_emit(cs, trace_id);
1564 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1565 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
1566
1567 if (sctx->log)
1568 u_log_flush(sctx->log);
1569 }