2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
35 /* special primitive types */
36 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
38 static unsigned si_conv_pipe_prim(unsigned mode
)
40 static const unsigned prim_conv
[] = {
41 [PIPE_PRIM_POINTS
] = V_008958_DI_PT_POINTLIST
,
42 [PIPE_PRIM_LINES
] = V_008958_DI_PT_LINELIST
,
43 [PIPE_PRIM_LINE_LOOP
] = V_008958_DI_PT_LINELOOP
,
44 [PIPE_PRIM_LINE_STRIP
] = V_008958_DI_PT_LINESTRIP
,
45 [PIPE_PRIM_TRIANGLES
] = V_008958_DI_PT_TRILIST
,
46 [PIPE_PRIM_TRIANGLE_STRIP
] = V_008958_DI_PT_TRISTRIP
,
47 [PIPE_PRIM_TRIANGLE_FAN
] = V_008958_DI_PT_TRIFAN
,
48 [PIPE_PRIM_QUADS
] = V_008958_DI_PT_QUADLIST
,
49 [PIPE_PRIM_QUAD_STRIP
] = V_008958_DI_PT_QUADSTRIP
,
50 [PIPE_PRIM_POLYGON
] = V_008958_DI_PT_POLYGON
,
51 [PIPE_PRIM_LINES_ADJACENCY
] = V_008958_DI_PT_LINELIST_ADJ
,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_008958_DI_PT_LINESTRIP_ADJ
,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_008958_DI_PT_TRILIST_ADJ
,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_008958_DI_PT_TRISTRIP_ADJ
,
55 [PIPE_PRIM_PATCHES
] = V_008958_DI_PT_PATCH
,
56 [SI_PRIM_RECTANGLE_LIST
] = V_008958_DI_PT_RECTLIST
58 assert(mode
< ARRAY_SIZE(prim_conv
));
59 return prim_conv
[mode
];
63 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
64 * LS.LDS_SIZE is shared by all 3 shader stages.
66 * The information about LDS and other non-compile-time parameters is then
67 * written to userdata SGPRs.
69 static bool si_emit_derived_tess_state(struct si_context
*sctx
,
70 const struct pipe_draw_info
*info
,
71 unsigned *num_patches
)
73 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
74 struct si_shader
*ls_current
;
75 struct si_shader_selector
*ls
;
76 /* The TES pointer will only be used for sctx->last_tcs.
77 * It would be wrong to think that TCS = TES. */
78 struct si_shader_selector
*tcs
=
79 sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.cso
: sctx
->tes_shader
.cso
;
80 unsigned tess_uses_primid
= sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
;
81 bool has_primid_instancing_bug
= sctx
->chip_class
== SI
&&
82 sctx
->screen
->info
.max_se
== 1;
83 unsigned tes_sh_base
= sctx
->shader_pointers
.sh_base
[PIPE_SHADER_TESS_EVAL
];
84 unsigned num_tcs_input_cp
= info
->vertices_per_patch
;
85 unsigned num_tcs_output_cp
, num_tcs_inputs
, num_tcs_outputs
;
86 unsigned num_tcs_patch_outputs
;
87 unsigned input_vertex_size
, output_vertex_size
, pervertex_output_patch_size
;
88 unsigned input_patch_size
, output_patch_size
, output_patch0_offset
;
89 unsigned perpatch_output_offset
, lds_size
;
90 unsigned tcs_in_layout
, tcs_out_layout
, tcs_out_offsets
;
91 unsigned offchip_layout
, hardware_lds_size
, ls_hs_config
;
93 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
94 if (sctx
->chip_class
>= GFX9
) {
95 if (sctx
->tcs_shader
.cso
)
96 ls_current
= sctx
->tcs_shader
.current
;
98 ls_current
= sctx
->fixed_func_tcs_shader
.current
;
100 ls
= ls_current
->key
.part
.tcs
.ls
;
102 ls_current
= sctx
->vs_shader
.current
;
103 ls
= sctx
->vs_shader
.cso
;
106 if (sctx
->last_ls
== ls_current
&&
107 sctx
->last_tcs
== tcs
&&
108 sctx
->last_tes_sh_base
== tes_sh_base
&&
109 sctx
->last_num_tcs_input_cp
== num_tcs_input_cp
&&
110 (!has_primid_instancing_bug
||
111 (sctx
->last_tess_uses_primid
== tess_uses_primid
))) {
112 *num_patches
= sctx
->last_num_patches
;
116 sctx
->last_ls
= ls_current
;
117 sctx
->last_tcs
= tcs
;
118 sctx
->last_tes_sh_base
= tes_sh_base
;
119 sctx
->last_num_tcs_input_cp
= num_tcs_input_cp
;
120 sctx
->last_tess_uses_primid
= tess_uses_primid
;
122 /* This calculates how shader inputs and outputs among VS, TCS, and TES
123 * are laid out in LDS. */
124 num_tcs_inputs
= util_last_bit64(ls
->outputs_written
);
126 if (sctx
->tcs_shader
.cso
) {
127 num_tcs_outputs
= util_last_bit64(tcs
->outputs_written
);
128 num_tcs_output_cp
= tcs
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
129 num_tcs_patch_outputs
= util_last_bit64(tcs
->patch_outputs_written
);
131 /* No TCS. Route varyings from LS to TES. */
132 num_tcs_outputs
= num_tcs_inputs
;
133 num_tcs_output_cp
= num_tcs_input_cp
;
134 num_tcs_patch_outputs
= 2; /* TESSINNER + TESSOUTER */
137 input_vertex_size
= num_tcs_inputs
* 16;
138 output_vertex_size
= num_tcs_outputs
* 16;
140 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
142 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
143 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
145 /* Ensure that we only need one wave per SIMD so we don't need to check
146 * resource usage. Also ensures that the number of tcs in and out
147 * vertices per threadgroup are at most 256.
149 *num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
151 /* Make sure that the data fits in LDS. This assumes the shaders only
152 * use LDS for the inputs and outputs.
154 * While CIK can use 64K per threadgroup, there is a hang on Stoney
155 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
156 * uses 32K at most on all GCN chips.
158 hardware_lds_size
= 32768;
159 *num_patches
= MIN2(*num_patches
, hardware_lds_size
/ (input_patch_size
+
162 /* Make sure the output data fits in the offchip buffer */
163 *num_patches
= MIN2(*num_patches
,
164 (sctx
->screen
->tess_offchip_block_dw_size
* 4) /
167 /* Not necessary for correctness, but improves performance. The
168 * specific value is taken from the proprietary driver.
170 *num_patches
= MIN2(*num_patches
, 40);
172 if (sctx
->chip_class
== SI
) {
173 /* SI bug workaround, related to power management. Limit LS-HS
174 * threadgroups to only one wave.
176 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
177 *num_patches
= MIN2(*num_patches
, one_wave
);
180 /* The VGT HS block increments the patch ID unconditionally
181 * within a single threadgroup. This results in incorrect
182 * patch IDs when instanced draws are used.
184 * The intended solution is to restrict threadgroups to
185 * a single instance by setting SWITCH_ON_EOI, which
186 * should cause IA to split instances up. However, this
187 * doesn't work correctly on SI when there is no other
190 if (has_primid_instancing_bug
&& tess_uses_primid
)
193 sctx
->last_num_patches
= *num_patches
;
195 output_patch0_offset
= input_patch_size
* *num_patches
;
196 perpatch_output_offset
= output_patch0_offset
+ pervertex_output_patch_size
;
198 /* Compute userdata SGPRs. */
199 assert(((input_vertex_size
/ 4) & ~0xff) == 0);
200 assert(((output_vertex_size
/ 4) & ~0xff) == 0);
201 assert(((input_patch_size
/ 4) & ~0x1fff) == 0);
202 assert(((output_patch_size
/ 4) & ~0x1fff) == 0);
203 assert(((output_patch0_offset
/ 16) & ~0xffff) == 0);
204 assert(((perpatch_output_offset
/ 16) & ~0xffff) == 0);
205 assert(num_tcs_input_cp
<= 32);
206 assert(num_tcs_output_cp
<= 32);
208 uint64_t ring_va
= r600_resource(sctx
->tess_rings
)->gpu_address
;
209 assert((ring_va
& u_bit_consecutive(0, 19)) == 0);
211 tcs_in_layout
= S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size
/ 4) |
212 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size
/ 4);
213 tcs_out_layout
= (output_patch_size
/ 4) |
214 (num_tcs_input_cp
<< 13) |
216 tcs_out_offsets
= (output_patch0_offset
/ 16) |
217 ((perpatch_output_offset
/ 16) << 16);
218 offchip_layout
= *num_patches
|
219 (num_tcs_output_cp
<< 6) |
220 (pervertex_output_patch_size
* *num_patches
<< 12);
222 /* Compute the LDS size. */
223 lds_size
= output_patch0_offset
+ output_patch_size
* *num_patches
;
225 if (sctx
->chip_class
>= CIK
) {
226 assert(lds_size
<= 65536);
227 lds_size
= align(lds_size
, 512) / 512;
229 assert(lds_size
<= 32768);
230 lds_size
= align(lds_size
, 256) / 256;
233 /* Set SI_SGPR_VS_STATE_BITS. */
234 sctx
->current_vs_state
&= C_VS_STATE_LS_OUT_PATCH_SIZE
&
235 C_VS_STATE_LS_OUT_VERTEX_SIZE
;
236 sctx
->current_vs_state
|= tcs_in_layout
;
238 if (sctx
->chip_class
>= GFX9
) {
239 unsigned hs_rsrc2
= ls_current
->config
.rsrc2
|
240 S_00B42C_LDS_SIZE(lds_size
);
242 radeon_set_sh_reg(cs
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
, hs_rsrc2
);
244 /* Set userdata SGPRs for merged LS-HS. */
245 radeon_set_sh_reg_seq(cs
,
246 R_00B430_SPI_SHADER_USER_DATA_LS_0
+
247 GFX9_SGPR_TCS_OFFCHIP_LAYOUT
* 4, 3);
248 radeon_emit(cs
, offchip_layout
);
249 radeon_emit(cs
, tcs_out_offsets
);
250 radeon_emit(cs
, tcs_out_layout
);
252 unsigned ls_rsrc2
= ls_current
->config
.rsrc2
;
254 si_multiwave_lds_size_workaround(sctx
->screen
, &lds_size
);
255 ls_rsrc2
|= S_00B52C_LDS_SIZE(lds_size
);
257 /* Due to a hw bug, RSRC2_LS must be written twice with another
258 * LS register written in between. */
259 if (sctx
->chip_class
== CIK
&& sctx
->family
!= CHIP_HAWAII
)
260 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, ls_rsrc2
);
261 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
262 radeon_emit(cs
, ls_current
->config
.rsrc1
);
263 radeon_emit(cs
, ls_rsrc2
);
265 /* Set userdata SGPRs for TCS. */
266 radeon_set_sh_reg_seq(cs
,
267 R_00B430_SPI_SHADER_USER_DATA_HS_0
+ GFX6_SGPR_TCS_OFFCHIP_LAYOUT
* 4, 4);
268 radeon_emit(cs
, offchip_layout
);
269 radeon_emit(cs
, tcs_out_offsets
);
270 radeon_emit(cs
, tcs_out_layout
);
271 radeon_emit(cs
, tcs_in_layout
);
274 /* Set userdata SGPRs for TES. */
275 radeon_set_sh_reg_seq(cs
, tes_sh_base
+ SI_SGPR_TES_OFFCHIP_LAYOUT
* 4, 2);
276 radeon_emit(cs
, offchip_layout
);
277 radeon_emit(cs
, ring_va
);
279 ls_hs_config
= S_028B58_NUM_PATCHES(*num_patches
) |
280 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
281 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
283 if (sctx
->last_ls_hs_config
!= ls_hs_config
) {
284 if (sctx
->chip_class
>= CIK
) {
285 radeon_set_context_reg_idx(cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
288 radeon_set_context_reg(cs
, R_028B58_VGT_LS_HS_CONFIG
,
291 sctx
->last_ls_hs_config
= ls_hs_config
;
292 return true; /* true if the context rolls */
297 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info
*info
)
299 switch (info
->mode
) {
300 case PIPE_PRIM_PATCHES
:
301 return info
->count
/ info
->vertices_per_patch
;
302 case SI_PRIM_RECTANGLE_LIST
:
303 return info
->count
/ 3;
305 return u_prims_for_vertices(info
->mode
, info
->count
);
310 si_get_init_multi_vgt_param(struct si_screen
*sscreen
,
311 union si_vgt_param_key
*key
)
313 STATIC_ASSERT(sizeof(union si_vgt_param_key
) == 4);
314 unsigned max_primgroup_in_wave
= 2;
316 /* SWITCH_ON_EOP(0) is always preferable. */
317 bool wd_switch_on_eop
= false;
318 bool ia_switch_on_eop
= false;
319 bool ia_switch_on_eoi
= false;
320 bool partial_vs_wave
= false;
321 bool partial_es_wave
= false;
323 if (key
->u
.uses_tess
) {
324 /* SWITCH_ON_EOI must be set if PrimID is used. */
325 if (key
->u
.tess_uses_prim_id
)
326 ia_switch_on_eoi
= true;
328 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
329 if ((sscreen
->info
.family
== CHIP_TAHITI
||
330 sscreen
->info
.family
== CHIP_PITCAIRN
||
331 sscreen
->info
.family
== CHIP_BONAIRE
) &&
333 partial_vs_wave
= true;
335 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
336 if (sscreen
->has_distributed_tess
) {
337 if (key
->u
.uses_gs
) {
338 if (sscreen
->info
.chip_class
<= VI
)
339 partial_es_wave
= true;
341 /* GPU hang workaround. */
342 if (sscreen
->info
.family
== CHIP_TONGA
||
343 sscreen
->info
.family
== CHIP_FIJI
||
344 sscreen
->info
.family
== CHIP_POLARIS10
||
345 sscreen
->info
.family
== CHIP_POLARIS11
||
346 sscreen
->info
.family
== CHIP_POLARIS12
||
347 sscreen
->info
.family
== CHIP_VEGAM
)
348 partial_vs_wave
= true;
350 partial_vs_wave
= true;
355 /* This is a hardware requirement. */
356 if (key
->u
.line_stipple_enabled
||
357 (sscreen
->debug_flags
& DBG(SWITCH_ON_EOP
))) {
358 ia_switch_on_eop
= true;
359 wd_switch_on_eop
= true;
362 if (sscreen
->info
.chip_class
>= CIK
) {
363 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
364 * 4 shader engines. Set 1 to pass the assertion below.
365 * The other cases are hardware requirements.
367 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
368 * for points, line strips, and tri strips.
370 if (sscreen
->info
.max_se
< 4 ||
371 key
->u
.prim
== PIPE_PRIM_POLYGON
||
372 key
->u
.prim
== PIPE_PRIM_LINE_LOOP
||
373 key
->u
.prim
== PIPE_PRIM_TRIANGLE_FAN
||
374 key
->u
.prim
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
||
375 (key
->u
.primitive_restart
&&
376 (sscreen
->info
.family
< CHIP_POLARIS10
||
377 (key
->u
.prim
!= PIPE_PRIM_POINTS
&&
378 key
->u
.prim
!= PIPE_PRIM_LINE_STRIP
&&
379 key
->u
.prim
!= PIPE_PRIM_TRIANGLE_STRIP
))) ||
380 key
->u
.count_from_stream_output
)
381 wd_switch_on_eop
= true;
383 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
384 * We don't know that for indirect drawing, so treat it as
385 * always problematic. */
386 if (sscreen
->info
.family
== CHIP_HAWAII
&&
387 key
->u
.uses_instancing
)
388 wd_switch_on_eop
= true;
390 /* Performance recommendation for 4 SE Gfx7-8 parts if
391 * instances are smaller than a primgroup.
392 * Assume indirect draws always use small instances.
393 * This is needed for good VS wave utilization.
395 if (sscreen
->info
.chip_class
<= VI
&&
396 sscreen
->info
.max_se
== 4 &&
397 key
->u
.multi_instances_smaller_than_primgroup
)
398 wd_switch_on_eop
= true;
400 /* Required on CIK and later. */
401 if (sscreen
->info
.max_se
> 2 && !wd_switch_on_eop
)
402 ia_switch_on_eoi
= true;
404 /* Required by Hawaii and, for some special cases, by VI. */
405 if (ia_switch_on_eoi
&&
406 (sscreen
->info
.family
== CHIP_HAWAII
||
407 (sscreen
->info
.chip_class
== VI
&&
408 (key
->u
.uses_gs
|| max_primgroup_in_wave
!= 2))))
409 partial_vs_wave
= true;
411 /* Instancing bug on Bonaire. */
412 if (sscreen
->info
.family
== CHIP_BONAIRE
&& ia_switch_on_eoi
&&
413 key
->u
.uses_instancing
)
414 partial_vs_wave
= true;
416 /* If the WD switch is false, the IA switch must be false too. */
417 assert(wd_switch_on_eop
|| !ia_switch_on_eop
);
420 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
421 if (sscreen
->info
.chip_class
<= VI
&& ia_switch_on_eoi
)
422 partial_es_wave
= true;
424 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
425 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi
) |
426 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
427 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave
) |
428 S_028AA8_WD_SWITCH_ON_EOP(sscreen
->info
.chip_class
>= CIK
? wd_switch_on_eop
: 0) |
429 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
430 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen
->info
.chip_class
== VI
?
431 max_primgroup_in_wave
: 0) |
432 S_030960_EN_INST_OPT_BASIC(sscreen
->info
.chip_class
>= GFX9
) |
433 S_030960_EN_INST_OPT_ADV(sscreen
->info
.chip_class
>= GFX9
);
436 void si_init_ia_multi_vgt_param_table(struct si_context
*sctx
)
438 for (int prim
= 0; prim
<= SI_PRIM_RECTANGLE_LIST
; prim
++)
439 for (int uses_instancing
= 0; uses_instancing
< 2; uses_instancing
++)
440 for (int multi_instances
= 0; multi_instances
< 2; multi_instances
++)
441 for (int primitive_restart
= 0; primitive_restart
< 2; primitive_restart
++)
442 for (int count_from_so
= 0; count_from_so
< 2; count_from_so
++)
443 for (int line_stipple
= 0; line_stipple
< 2; line_stipple
++)
444 for (int uses_tess
= 0; uses_tess
< 2; uses_tess
++)
445 for (int tess_uses_primid
= 0; tess_uses_primid
< 2; tess_uses_primid
++)
446 for (int uses_gs
= 0; uses_gs
< 2; uses_gs
++) {
447 union si_vgt_param_key key
;
451 key
.u
.uses_instancing
= uses_instancing
;
452 key
.u
.multi_instances_smaller_than_primgroup
= multi_instances
;
453 key
.u
.primitive_restart
= primitive_restart
;
454 key
.u
.count_from_stream_output
= count_from_so
;
455 key
.u
.line_stipple_enabled
= line_stipple
;
456 key
.u
.uses_tess
= uses_tess
;
457 key
.u
.tess_uses_prim_id
= tess_uses_primid
;
458 key
.u
.uses_gs
= uses_gs
;
460 sctx
->ia_multi_vgt_param
[key
.index
] =
461 si_get_init_multi_vgt_param(sctx
->screen
, &key
);
465 static unsigned si_get_ia_multi_vgt_param(struct si_context
*sctx
,
466 const struct pipe_draw_info
*info
,
467 unsigned num_patches
)
469 union si_vgt_param_key key
= sctx
->ia_multi_vgt_param_key
;
470 unsigned primgroup_size
;
471 unsigned ia_multi_vgt_param
;
473 if (sctx
->tes_shader
.cso
) {
474 primgroup_size
= num_patches
; /* must be a multiple of NUM_PATCHES */
475 } else if (sctx
->gs_shader
.cso
) {
476 primgroup_size
= 64; /* recommended with a GS */
478 primgroup_size
= 128; /* recommended without a GS and tess */
481 key
.u
.prim
= info
->mode
;
482 key
.u
.uses_instancing
= info
->indirect
|| info
->instance_count
> 1;
483 key
.u
.multi_instances_smaller_than_primgroup
=
485 (info
->instance_count
> 1 &&
486 (info
->count_from_stream_output
||
487 si_num_prims_for_vertices(info
) < primgroup_size
));
488 key
.u
.primitive_restart
= info
->primitive_restart
;
489 key
.u
.count_from_stream_output
= info
->count_from_stream_output
!= NULL
;
491 ia_multi_vgt_param
= sctx
->ia_multi_vgt_param
[key
.index
] |
492 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1);
494 if (sctx
->gs_shader
.cso
) {
495 /* GS requirement. */
496 if (sctx
->chip_class
<= VI
&&
497 SI_GS_PER_ES
/ primgroup_size
>= sctx
->screen
->gs_table_depth
- 3)
498 ia_multi_vgt_param
|= S_028AA8_PARTIAL_ES_WAVE_ON(1);
500 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
501 * The hw doc says all multi-SE chips are affected, but Vulkan
502 * only applies it to Hawaii. Do what Vulkan does.
504 if (sctx
->family
== CHIP_HAWAII
&&
505 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param
) &&
507 (info
->instance_count
> 1 &&
508 (info
->count_from_stream_output
||
509 si_num_prims_for_vertices(info
) <= 1))))
510 sctx
->flags
|= SI_CONTEXT_VGT_FLUSH
;
513 return ia_multi_vgt_param
;
516 /* rast_prim is the primitive type after GS. */
517 static bool si_emit_rasterizer_prim_state(struct si_context
*sctx
)
519 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
520 enum pipe_prim_type rast_prim
= sctx
->current_rast_prim
;
521 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
523 /* Skip this if not rendering lines. */
524 if (!util_prim_is_lines(rast_prim
))
527 if (rast_prim
== sctx
->last_rast_prim
&&
528 rs
->pa_sc_line_stipple
== sctx
->last_sc_line_stipple
)
531 /* For lines, reset the stipple pattern at each primitive. Otherwise,
532 * reset the stipple pattern at each packet (line strips, line loops).
534 radeon_set_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
535 rs
->pa_sc_line_stipple
|
536 S_028A0C_AUTO_RESET_CNTL(rast_prim
== PIPE_PRIM_LINES
? 1 : 2));
538 sctx
->last_rast_prim
= rast_prim
;
539 sctx
->last_sc_line_stipple
= rs
->pa_sc_line_stipple
;
540 return true; /* true if the context rolls */
543 static void si_emit_vs_state(struct si_context
*sctx
,
544 const struct pipe_draw_info
*info
)
546 sctx
->current_vs_state
&= C_VS_STATE_INDEXED
;
547 sctx
->current_vs_state
|= S_VS_STATE_INDEXED(!!info
->index_size
);
549 if (sctx
->num_vs_blit_sgprs
) {
550 /* Re-emit the state after we leave u_blitter. */
551 sctx
->last_vs_state
= ~0;
555 if (sctx
->current_vs_state
!= sctx
->last_vs_state
) {
556 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
558 radeon_set_sh_reg(cs
,
559 sctx
->shader_pointers
.sh_base
[PIPE_SHADER_VERTEX
] +
560 SI_SGPR_VS_STATE_BITS
* 4,
561 sctx
->current_vs_state
);
563 sctx
->last_vs_state
= sctx
->current_vs_state
;
567 static inline bool si_prim_restart_index_changed(struct si_context
*sctx
,
568 const struct pipe_draw_info
*info
)
570 return info
->primitive_restart
&&
571 (info
->restart_index
!= sctx
->last_restart_index
||
572 sctx
->last_restart_index
== SI_RESTART_INDEX_UNKNOWN
);
575 static void si_emit_draw_registers(struct si_context
*sctx
,
576 const struct pipe_draw_info
*info
,
577 unsigned num_patches
)
579 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
580 unsigned prim
= si_conv_pipe_prim(info
->mode
);
581 unsigned ia_multi_vgt_param
;
583 ia_multi_vgt_param
= si_get_ia_multi_vgt_param(sctx
, info
, num_patches
);
586 if (ia_multi_vgt_param
!= sctx
->last_multi_vgt_param
) {
587 if (sctx
->chip_class
>= GFX9
)
588 radeon_set_uconfig_reg_idx(cs
, R_030960_IA_MULTI_VGT_PARAM
, 4, ia_multi_vgt_param
);
589 else if (sctx
->chip_class
>= CIK
)
590 radeon_set_context_reg_idx(cs
, R_028AA8_IA_MULTI_VGT_PARAM
, 1, ia_multi_vgt_param
);
592 radeon_set_context_reg(cs
, R_028AA8_IA_MULTI_VGT_PARAM
, ia_multi_vgt_param
);
594 sctx
->last_multi_vgt_param
= ia_multi_vgt_param
;
596 if (prim
!= sctx
->last_prim
) {
597 if (sctx
->chip_class
>= CIK
)
598 radeon_set_uconfig_reg_idx(cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
600 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
602 sctx
->last_prim
= prim
;
605 /* Primitive restart. */
606 if (info
->primitive_restart
!= sctx
->last_primitive_restart_en
) {
607 if (sctx
->chip_class
>= GFX9
)
608 radeon_set_uconfig_reg(cs
, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN
,
609 info
->primitive_restart
);
611 radeon_set_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
,
612 info
->primitive_restart
);
614 sctx
->last_primitive_restart_en
= info
->primitive_restart
;
617 if (si_prim_restart_index_changed(sctx
, info
)) {
618 radeon_set_context_reg(cs
, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX
,
619 info
->restart_index
);
620 sctx
->last_restart_index
= info
->restart_index
;
624 static void si_emit_draw_packets(struct si_context
*sctx
,
625 const struct pipe_draw_info
*info
,
626 struct pipe_resource
*indexbuf
,
628 unsigned index_offset
)
630 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
631 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
632 unsigned sh_base_reg
= sctx
->shader_pointers
.sh_base
[PIPE_SHADER_VERTEX
];
633 bool render_cond_bit
= sctx
->render_cond
&& !sctx
->render_cond_force_off
;
634 uint32_t index_max_size
= 0;
635 uint64_t index_va
= 0;
637 if (info
->count_from_stream_output
) {
638 struct si_streamout_target
*t
=
639 (struct si_streamout_target
*)info
->count_from_stream_output
;
640 uint64_t va
= t
->buf_filled_size
->gpu_address
+
641 t
->buf_filled_size_offset
;
643 radeon_set_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
,
646 radeon_emit(cs
, PKT3(PKT3_COPY_DATA
, 4, 0));
647 radeon_emit(cs
, COPY_DATA_SRC_SEL(COPY_DATA_MEM
) |
648 COPY_DATA_DST_SEL(COPY_DATA_REG
) |
649 COPY_DATA_WR_CONFIRM
);
650 radeon_emit(cs
, va
); /* src address lo */
651 radeon_emit(cs
, va
>> 32); /* src address hi */
652 radeon_emit(cs
, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2);
653 radeon_emit(cs
, 0); /* unused */
655 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
656 t
->buf_filled_size
, RADEON_USAGE_READ
,
657 RADEON_PRIO_SO_FILLED_SIZE
);
662 if (index_size
!= sctx
->last_index_size
) {
666 switch (index_size
) {
668 index_type
= V_028A7C_VGT_INDEX_8
;
671 index_type
= V_028A7C_VGT_INDEX_16
|
672 (SI_BIG_ENDIAN
&& sctx
->chip_class
<= CIK
?
673 V_028A7C_VGT_DMA_SWAP_16_BIT
: 0);
676 index_type
= V_028A7C_VGT_INDEX_32
|
677 (SI_BIG_ENDIAN
&& sctx
->chip_class
<= CIK
?
678 V_028A7C_VGT_DMA_SWAP_32_BIT
: 0);
681 assert(!"unreachable");
685 if (sctx
->chip_class
>= GFX9
) {
686 radeon_set_uconfig_reg_idx(cs
, R_03090C_VGT_INDEX_TYPE
,
689 radeon_emit(cs
, PKT3(PKT3_INDEX_TYPE
, 0, 0));
690 radeon_emit(cs
, index_type
);
693 sctx
->last_index_size
= index_size
;
696 index_max_size
= (indexbuf
->width0
- index_offset
) /
698 index_va
= r600_resource(indexbuf
)->gpu_address
+ index_offset
;
700 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
701 r600_resource(indexbuf
),
702 RADEON_USAGE_READ
, RADEON_PRIO_INDEX_BUFFER
);
704 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
705 * so the state must be re-emitted before the next indexed draw.
707 if (sctx
->chip_class
>= CIK
)
708 sctx
->last_index_size
= -1;
712 uint64_t indirect_va
= r600_resource(indirect
->buffer
)->gpu_address
;
714 assert(indirect_va
% 8 == 0);
716 si_invalidate_draw_sh_constants(sctx
);
718 radeon_emit(cs
, PKT3(PKT3_SET_BASE
, 2, 0));
720 radeon_emit(cs
, indirect_va
);
721 radeon_emit(cs
, indirect_va
>> 32);
723 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
724 r600_resource(indirect
->buffer
),
725 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
727 unsigned di_src_sel
= index_size
? V_0287F0_DI_SRC_SEL_DMA
728 : V_0287F0_DI_SRC_SEL_AUTO_INDEX
;
730 assert(indirect
->offset
% 4 == 0);
733 radeon_emit(cs
, PKT3(PKT3_INDEX_BASE
, 1, 0));
734 radeon_emit(cs
, index_va
);
735 radeon_emit(cs
, index_va
>> 32);
737 radeon_emit(cs
, PKT3(PKT3_INDEX_BUFFER_SIZE
, 0, 0));
738 radeon_emit(cs
, index_max_size
);
741 if (!sctx
->screen
->has_draw_indirect_multi
) {
742 radeon_emit(cs
, PKT3(index_size
? PKT3_DRAW_INDEX_INDIRECT
743 : PKT3_DRAW_INDIRECT
,
744 3, render_cond_bit
));
745 radeon_emit(cs
, indirect
->offset
);
746 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
747 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
748 radeon_emit(cs
, di_src_sel
);
750 uint64_t count_va
= 0;
752 if (indirect
->indirect_draw_count
) {
753 struct r600_resource
*params_buf
=
754 r600_resource(indirect
->indirect_draw_count
);
756 radeon_add_to_buffer_list(
757 sctx
, sctx
->gfx_cs
, params_buf
,
758 RADEON_USAGE_READ
, RADEON_PRIO_DRAW_INDIRECT
);
760 count_va
= params_buf
->gpu_address
+ indirect
->indirect_draw_count_offset
;
763 radeon_emit(cs
, PKT3(index_size
? PKT3_DRAW_INDEX_INDIRECT_MULTI
:
764 PKT3_DRAW_INDIRECT_MULTI
,
765 8, render_cond_bit
));
766 radeon_emit(cs
, indirect
->offset
);
767 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4 - SI_SH_REG_OFFSET
) >> 2);
768 radeon_emit(cs
, (sh_base_reg
+ SI_SGPR_START_INSTANCE
* 4 - SI_SH_REG_OFFSET
) >> 2);
769 radeon_emit(cs
, ((sh_base_reg
+ SI_SGPR_DRAWID
* 4 - SI_SH_REG_OFFSET
) >> 2) |
770 S_2C3_DRAW_INDEX_ENABLE(1) |
771 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect
->indirect_draw_count
));
772 radeon_emit(cs
, indirect
->draw_count
);
773 radeon_emit(cs
, count_va
);
774 radeon_emit(cs
, count_va
>> 32);
775 radeon_emit(cs
, indirect
->stride
);
776 radeon_emit(cs
, di_src_sel
);
781 radeon_emit(cs
, PKT3(PKT3_NUM_INSTANCES
, 0, 0));
782 radeon_emit(cs
, info
->instance_count
);
784 /* Base vertex and start instance. */
785 base_vertex
= index_size
? info
->index_bias
: info
->start
;
787 if (sctx
->num_vs_blit_sgprs
) {
788 /* Re-emit draw constants after we leave u_blitter. */
789 si_invalidate_draw_sh_constants(sctx
);
791 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
792 radeon_set_sh_reg_seq(cs
, sh_base_reg
+ SI_SGPR_VS_BLIT_DATA
* 4,
793 sctx
->num_vs_blit_sgprs
);
794 radeon_emit_array(cs
, sctx
->vs_blit_sh_data
,
795 sctx
->num_vs_blit_sgprs
);
796 } else if (base_vertex
!= sctx
->last_base_vertex
||
797 sctx
->last_base_vertex
== SI_BASE_VERTEX_UNKNOWN
||
798 info
->start_instance
!= sctx
->last_start_instance
||
799 info
->drawid
!= sctx
->last_drawid
||
800 sh_base_reg
!= sctx
->last_sh_base_reg
) {
801 radeon_set_sh_reg_seq(cs
, sh_base_reg
+ SI_SGPR_BASE_VERTEX
* 4, 3);
802 radeon_emit(cs
, base_vertex
);
803 radeon_emit(cs
, info
->start_instance
);
804 radeon_emit(cs
, info
->drawid
);
806 sctx
->last_base_vertex
= base_vertex
;
807 sctx
->last_start_instance
= info
->start_instance
;
808 sctx
->last_drawid
= info
->drawid
;
809 sctx
->last_sh_base_reg
= sh_base_reg
;
813 index_va
+= info
->start
* index_size
;
815 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_2
, 4, render_cond_bit
));
816 radeon_emit(cs
, index_max_size
);
817 radeon_emit(cs
, index_va
);
818 radeon_emit(cs
, index_va
>> 32);
819 radeon_emit(cs
, info
->count
);
820 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_DMA
);
822 radeon_emit(cs
, PKT3(PKT3_DRAW_INDEX_AUTO
, 1, render_cond_bit
));
823 radeon_emit(cs
, info
->count
);
824 radeon_emit(cs
, V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
825 S_0287F0_USE_OPAQUE(!!info
->count_from_stream_output
));
830 static void si_emit_surface_sync(struct si_context
*sctx
,
831 unsigned cp_coher_cntl
)
833 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
835 if (sctx
->chip_class
>= GFX9
) {
836 /* Flush caches and wait for the caches to assert idle. */
837 radeon_emit(cs
, PKT3(PKT3_ACQUIRE_MEM
, 5, 0));
838 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
839 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
840 radeon_emit(cs
, 0xffffff); /* CP_COHER_SIZE_HI */
841 radeon_emit(cs
, 0); /* CP_COHER_BASE */
842 radeon_emit(cs
, 0); /* CP_COHER_BASE_HI */
843 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
845 /* ACQUIRE_MEM is only required on a compute ring. */
846 radeon_emit(cs
, PKT3(PKT3_SURFACE_SYNC
, 3, 0));
847 radeon_emit(cs
, cp_coher_cntl
); /* CP_COHER_CNTL */
848 radeon_emit(cs
, 0xffffffff); /* CP_COHER_SIZE */
849 radeon_emit(cs
, 0); /* CP_COHER_BASE */
850 radeon_emit(cs
, 0x0000000A); /* POLL_INTERVAL */
854 void si_emit_cache_flush(struct si_context
*sctx
)
856 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
857 uint32_t flags
= sctx
->flags
;
858 uint32_t cp_coher_cntl
= 0;
859 uint32_t flush_cb_db
= flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
|
860 SI_CONTEXT_FLUSH_AND_INV_DB
);
862 if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
)
863 sctx
->num_cb_cache_flushes
++;
864 if (flags
& SI_CONTEXT_FLUSH_AND_INV_DB
)
865 sctx
->num_db_cache_flushes
++;
867 /* SI has a bug that it always flushes ICACHE and KCACHE if either
868 * bit is set. An alternative way is to write SQC_CACHES, but that
869 * doesn't seem to work reliably. Since the bug doesn't affect
870 * correctness (it only does more work than necessary) and
871 * the performance impact is likely negligible, there is no plan
872 * to add a workaround for it.
875 if (flags
& SI_CONTEXT_INV_ICACHE
)
876 cp_coher_cntl
|= S_0085F0_SH_ICACHE_ACTION_ENA(1);
877 if (flags
& SI_CONTEXT_INV_SMEM_L1
)
878 cp_coher_cntl
|= S_0085F0_SH_KCACHE_ACTION_ENA(1);
880 if (sctx
->chip_class
<= VI
) {
881 if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
882 cp_coher_cntl
|= S_0085F0_CB_ACTION_ENA(1) |
883 S_0085F0_CB0_DEST_BASE_ENA(1) |
884 S_0085F0_CB1_DEST_BASE_ENA(1) |
885 S_0085F0_CB2_DEST_BASE_ENA(1) |
886 S_0085F0_CB3_DEST_BASE_ENA(1) |
887 S_0085F0_CB4_DEST_BASE_ENA(1) |
888 S_0085F0_CB5_DEST_BASE_ENA(1) |
889 S_0085F0_CB6_DEST_BASE_ENA(1) |
890 S_0085F0_CB7_DEST_BASE_ENA(1);
892 /* Necessary for DCC */
893 if (sctx
->chip_class
== VI
)
894 si_gfx_write_event_eop(sctx
, V_028A90_FLUSH_AND_INV_CB_DATA_TS
,
895 0, EOP_DATA_SEL_DISCARD
, NULL
,
898 if (flags
& SI_CONTEXT_FLUSH_AND_INV_DB
)
899 cp_coher_cntl
|= S_0085F0_DB_ACTION_ENA(1) |
900 S_0085F0_DB_DEST_BASE_ENA(1);
903 if (flags
& SI_CONTEXT_FLUSH_AND_INV_CB
) {
904 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
905 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
906 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META
) | EVENT_INDEX(0));
908 if (flags
& (SI_CONTEXT_FLUSH_AND_INV_DB
|
909 SI_CONTEXT_FLUSH_AND_INV_DB_META
)) {
910 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
911 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
912 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META
) | EVENT_INDEX(0));
915 /* Wait for shader engines to go idle.
916 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
917 * for everything including CB/DB cache flushes.
920 if (flags
& SI_CONTEXT_PS_PARTIAL_FLUSH
) {
921 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
922 radeon_emit(cs
, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
923 /* Only count explicit shader flushes, not implicit ones
924 * done by SURFACE_SYNC.
926 sctx
->num_vs_flushes
++;
927 sctx
->num_ps_flushes
++;
928 } else if (flags
& SI_CONTEXT_VS_PARTIAL_FLUSH
) {
929 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
930 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
931 sctx
->num_vs_flushes
++;
935 if (flags
& SI_CONTEXT_CS_PARTIAL_FLUSH
&&
936 sctx
->compute_is_busy
) {
937 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
938 radeon_emit(cs
, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH
| EVENT_INDEX(4)));
939 sctx
->num_cs_flushes
++;
940 sctx
->compute_is_busy
= false;
943 /* VGT state synchronization. */
944 if (flags
& SI_CONTEXT_VGT_FLUSH
) {
945 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
946 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
948 if (flags
& SI_CONTEXT_VGT_STREAMOUT_SYNC
) {
949 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
950 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC
) | EVENT_INDEX(0));
953 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
954 * wait for idle on GFX9. We have to use a TS event.
956 if (sctx
->chip_class
>= GFX9
&& flush_cb_db
) {
958 unsigned tc_flags
, cb_db_event
;
960 /* Set the CB/DB flush event. */
961 switch (flush_cb_db
) {
962 case SI_CONTEXT_FLUSH_AND_INV_CB
:
963 cb_db_event
= V_028A90_FLUSH_AND_INV_CB_DATA_TS
;
965 case SI_CONTEXT_FLUSH_AND_INV_DB
:
966 cb_db_event
= V_028A90_FLUSH_AND_INV_DB_DATA_TS
;
970 cb_db_event
= V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
;
973 /* These are the only allowed combinations. If you need to
974 * do multiple operations at once, do them separately.
975 * All operations that invalidate L2 also seem to invalidate
976 * metadata. Volatile (VOL) and WC flushes are not listed here.
978 * TC | TC_WB = writeback & invalidate L2 & L1
979 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
980 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
981 * TC | TC_NC = invalidate L2 for MTYPE == NC
982 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
983 * TCL1 = invalidate L1
987 if (flags
& SI_CONTEXT_INV_L2_METADATA
) {
988 tc_flags
= EVENT_TC_ACTION_ENA
|
989 EVENT_TC_MD_ACTION_ENA
;
992 /* Ideally flush TC together with CB/DB. */
993 if (flags
& SI_CONTEXT_INV_GLOBAL_L2
) {
994 /* Writeback and invalidate everything in L2 & L1. */
995 tc_flags
= EVENT_TC_ACTION_ENA
|
996 EVENT_TC_WB_ACTION_ENA
;
998 /* Clear the flags. */
999 flags
&= ~(SI_CONTEXT_INV_GLOBAL_L2
|
1000 SI_CONTEXT_WRITEBACK_GLOBAL_L2
|
1001 SI_CONTEXT_INV_VMEM_L1
);
1002 sctx
->num_L2_invalidates
++;
1005 /* Do the flush (enqueue the event and wait for it). */
1006 va
= sctx
->wait_mem_scratch
->gpu_address
;
1007 sctx
->wait_mem_number
++;
1009 si_gfx_write_event_eop(sctx
, cb_db_event
, tc_flags
,
1010 EOP_DATA_SEL_VALUE_32BIT
,
1011 sctx
->wait_mem_scratch
, va
,
1012 sctx
->wait_mem_number
, SI_NOT_QUERY
);
1013 si_gfx_wait_fence(sctx
, va
, sctx
->wait_mem_number
, 0xffffffff);
1016 /* Make sure ME is idle (it executes most packets) before continuing.
1017 * This prevents read-after-write hazards between PFP and ME.
1019 if (cp_coher_cntl
||
1020 (flags
& (SI_CONTEXT_CS_PARTIAL_FLUSH
|
1021 SI_CONTEXT_INV_VMEM_L1
|
1022 SI_CONTEXT_INV_GLOBAL_L2
|
1023 SI_CONTEXT_WRITEBACK_GLOBAL_L2
))) {
1024 radeon_emit(cs
, PKT3(PKT3_PFP_SYNC_ME
, 0, 0));
1029 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1030 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1032 * cp_coher_cntl should contain all necessary flags except TC flags
1035 * SI-CIK don't support L2 write-back.
1037 if (flags
& SI_CONTEXT_INV_GLOBAL_L2
||
1038 (sctx
->chip_class
<= CIK
&&
1039 (flags
& SI_CONTEXT_WRITEBACK_GLOBAL_L2
))) {
1040 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
1041 * WB must be set on VI+ when TC_ACTION is set.
1043 si_emit_surface_sync(sctx
, cp_coher_cntl
|
1044 S_0085F0_TC_ACTION_ENA(1) |
1045 S_0085F0_TCL1_ACTION_ENA(1) |
1046 S_0301F0_TC_WB_ACTION_ENA(sctx
->chip_class
>= VI
));
1048 sctx
->num_L2_invalidates
++;
1050 /* L1 invalidation and L2 writeback must be done separately,
1051 * because both operations can't be done together.
1053 if (flags
& SI_CONTEXT_WRITEBACK_GLOBAL_L2
) {
1055 * NC = apply to non-coherent MTYPEs
1056 * (i.e. MTYPE <= 1, which is what we use everywhere)
1058 * WB doesn't work without NC.
1060 si_emit_surface_sync(sctx
, cp_coher_cntl
|
1061 S_0301F0_TC_WB_ACTION_ENA(1) |
1062 S_0301F0_TC_NC_ACTION_ENA(1));
1064 sctx
->num_L2_writebacks
++;
1066 if (flags
& SI_CONTEXT_INV_VMEM_L1
) {
1067 /* Invalidate per-CU VMEM L1. */
1068 si_emit_surface_sync(sctx
, cp_coher_cntl
|
1069 S_0085F0_TCL1_ACTION_ENA(1));
1074 /* If TC flushes haven't cleared this... */
1076 si_emit_surface_sync(sctx
, cp_coher_cntl
);
1078 if (flags
& SI_CONTEXT_START_PIPELINE_STATS
) {
1079 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1080 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
1082 } else if (flags
& SI_CONTEXT_STOP_PIPELINE_STATS
) {
1083 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1084 radeon_emit(cs
, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP
) |
1091 static void si_get_draw_start_count(struct si_context
*sctx
,
1092 const struct pipe_draw_info
*info
,
1093 unsigned *start
, unsigned *count
)
1095 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
1098 unsigned indirect_count
;
1099 struct pipe_transfer
*transfer
;
1100 unsigned begin
, end
;
1104 if (indirect
->indirect_draw_count
) {
1105 data
= pipe_buffer_map_range(&sctx
->b
,
1106 indirect
->indirect_draw_count
,
1107 indirect
->indirect_draw_count_offset
,
1109 PIPE_TRANSFER_READ
, &transfer
);
1111 indirect_count
= *data
;
1113 pipe_buffer_unmap(&sctx
->b
, transfer
);
1115 indirect_count
= indirect
->draw_count
;
1118 if (!indirect_count
) {
1119 *start
= *count
= 0;
1123 map_size
= (indirect_count
- 1) * indirect
->stride
+ 3 * sizeof(unsigned);
1124 data
= pipe_buffer_map_range(&sctx
->b
, indirect
->buffer
,
1125 indirect
->offset
, map_size
,
1126 PIPE_TRANSFER_READ
, &transfer
);
1131 for (unsigned i
= 0; i
< indirect_count
; ++i
) {
1132 unsigned count
= data
[0];
1133 unsigned start
= data
[2];
1136 begin
= MIN2(begin
, start
);
1137 end
= MAX2(end
, start
+ count
);
1140 data
+= indirect
->stride
/ sizeof(unsigned);
1143 pipe_buffer_unmap(&sctx
->b
, transfer
);
1147 *count
= end
- begin
;
1149 *start
= *count
= 0;
1152 *start
= info
->start
;
1153 *count
= info
->count
;
1157 static void si_emit_all_states(struct si_context
*sctx
, const struct pipe_draw_info
*info
,
1158 unsigned skip_atom_mask
)
1160 unsigned num_patches
= 0;
1161 bool context_roll
= false; /* set correctly for GFX9 only */
1163 context_roll
|= si_emit_rasterizer_prim_state(sctx
);
1164 if (sctx
->tes_shader
.cso
)
1165 context_roll
|= si_emit_derived_tess_state(sctx
, info
, &num_patches
);
1166 if (info
->count_from_stream_output
)
1167 context_roll
= true;
1169 /* Vega10/Raven scissor bug workaround. When any context register is
1170 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
1171 * registers must be written too.
1173 if ((sctx
->family
== CHIP_VEGA10
|| sctx
->family
== CHIP_RAVEN
) &&
1175 sctx
->dirty_atoms
& si_atoms_that_roll_context() ||
1176 sctx
->dirty_states
& si_states_that_roll_context() ||
1177 si_prim_restart_index_changed(sctx
, info
))) {
1178 sctx
->scissors
.dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1179 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
);
1182 /* Emit state atoms. */
1183 unsigned mask
= sctx
->dirty_atoms
& ~skip_atom_mask
;
1185 sctx
->atoms
.array
[u_bit_scan(&mask
)].emit(sctx
);
1187 sctx
->dirty_atoms
&= skip_atom_mask
;
1190 mask
= sctx
->dirty_states
;
1192 unsigned i
= u_bit_scan(&mask
);
1193 struct si_pm4_state
*state
= sctx
->queued
.array
[i
];
1195 if (!state
|| sctx
->emitted
.array
[i
] == state
)
1198 si_pm4_emit(sctx
, state
);
1199 sctx
->emitted
.array
[i
] = state
;
1201 sctx
->dirty_states
= 0;
1203 /* Emit draw states. */
1204 si_emit_vs_state(sctx
, info
);
1205 si_emit_draw_registers(sctx
, info
, num_patches
);
1208 void si_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
)
1210 struct si_context
*sctx
= (struct si_context
*)ctx
;
1211 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1212 struct pipe_resource
*indexbuf
= info
->index
.resource
;
1213 unsigned dirty_tex_counter
;
1214 enum pipe_prim_type rast_prim
;
1215 unsigned index_size
= info
->index_size
;
1216 unsigned index_offset
= info
->indirect
? info
->start
* index_size
: 0;
1218 if (likely(!info
->indirect
)) {
1219 /* SI-CI treat instance_count==0 as instance_count==1. There is
1220 * no workaround for indirect draws, but we can at least skip
1223 if (unlikely(!info
->instance_count
))
1226 /* Handle count == 0. */
1227 if (unlikely(!info
->count
&&
1228 (index_size
|| !info
->count_from_stream_output
)))
1232 if (unlikely(!sctx
->vs_shader
.cso
)) {
1236 if (unlikely(!sctx
->ps_shader
.cso
&& (!rs
|| !rs
->rasterizer_discard
))) {
1240 if (unlikely(!!sctx
->tes_shader
.cso
!= (info
->mode
== PIPE_PRIM_PATCHES
))) {
1245 /* Recompute and re-emit the texture resource states if needed. */
1246 dirty_tex_counter
= p_atomic_read(&sctx
->screen
->dirty_tex_counter
);
1247 if (unlikely(dirty_tex_counter
!= sctx
->last_dirty_tex_counter
)) {
1248 sctx
->last_dirty_tex_counter
= dirty_tex_counter
;
1249 sctx
->framebuffer
.dirty_cbufs
|=
1250 ((1 << sctx
->framebuffer
.state
.nr_cbufs
) - 1);
1251 sctx
->framebuffer
.dirty_zsbuf
= true;
1252 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
1253 si_update_all_texture_descriptors(sctx
);
1256 si_decompress_textures(sctx
, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS
));
1258 /* Set the rasterization primitive type.
1260 * This must be done after si_decompress_textures, which can call
1261 * draw_vbo recursively, and before si_update_shaders, which uses
1262 * current_rast_prim for this draw_vbo call. */
1263 if (sctx
->gs_shader
.cso
)
1264 rast_prim
= sctx
->gs_shader
.cso
->gs_output_prim
;
1265 else if (sctx
->tes_shader
.cso
) {
1266 if (sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
1267 rast_prim
= PIPE_PRIM_POINTS
;
1269 rast_prim
= sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1271 rast_prim
= info
->mode
;
1273 if (rast_prim
!= sctx
->current_rast_prim
) {
1274 if (util_prim_is_points_or_lines(sctx
->current_rast_prim
) !=
1275 util_prim_is_points_or_lines(rast_prim
))
1276 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.guardband
);
1278 sctx
->current_rast_prim
= rast_prim
;
1279 sctx
->do_update_shaders
= true;
1282 if (sctx
->tes_shader
.cso
&&
1283 sctx
->screen
->has_ls_vgpr_init_bug
) {
1284 /* Determine whether the LS VGPR fix should be applied.
1286 * It is only required when num input CPs > num output CPs,
1287 * which cannot happen with the fixed function TCS. We should
1288 * also update this bit when switching from TCS to fixed
1291 struct si_shader_selector
*tcs
= sctx
->tcs_shader
.cso
;
1294 info
->vertices_per_patch
>
1295 tcs
->info
.properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
];
1297 if (ls_vgpr_fix
!= sctx
->ls_vgpr_fix
) {
1298 sctx
->ls_vgpr_fix
= ls_vgpr_fix
;
1299 sctx
->do_update_shaders
= true;
1303 if (sctx
->gs_shader
.cso
) {
1304 /* Determine whether the GS triangle strip adjacency fix should
1305 * be applied. Rotate every other triangle if
1306 * - triangle strips with adjacency are fed to the GS and
1307 * - primitive restart is disabled (the rotation doesn't help
1308 * when the restart occurs after an odd number of triangles).
1310 bool gs_tri_strip_adj_fix
=
1311 !sctx
->tes_shader
.cso
&&
1312 info
->mode
== PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
&&
1313 !info
->primitive_restart
;
1315 if (gs_tri_strip_adj_fix
!= sctx
->gs_tri_strip_adj_fix
) {
1316 sctx
->gs_tri_strip_adj_fix
= gs_tri_strip_adj_fix
;
1317 sctx
->do_update_shaders
= true;
1321 if (sctx
->do_update_shaders
&& !si_update_shaders(sctx
))
1325 /* Translate or upload, if needed. */
1326 /* 8-bit indices are supported on VI. */
1327 if (sctx
->chip_class
<= CIK
&& index_size
== 1) {
1328 unsigned start
, count
, start_offset
, size
, offset
;
1331 si_get_draw_start_count(sctx
, info
, &start
, &count
);
1332 start_offset
= start
* 2;
1336 u_upload_alloc(ctx
->stream_uploader
, start_offset
,
1338 si_optimal_tcc_alignment(sctx
, size
),
1339 &offset
, &indexbuf
, &ptr
);
1343 util_shorten_ubyte_elts_to_userptr(&sctx
->b
, info
, 0, 0,
1344 index_offset
+ start
,
1347 /* info->start will be added by the drawing code */
1348 index_offset
= offset
- start_offset
;
1350 } else if (info
->has_user_indices
) {
1351 unsigned start_offset
;
1353 assert(!info
->indirect
);
1354 start_offset
= info
->start
* index_size
;
1357 u_upload_data(ctx
->stream_uploader
, start_offset
,
1358 info
->count
* index_size
,
1359 sctx
->screen
->info
.tcc_cache_line_size
,
1360 (char*)info
->index
.user
+ start_offset
,
1361 &index_offset
, &indexbuf
);
1365 /* info->start will be added by the drawing code */
1366 index_offset
-= start_offset
;
1367 } else if (sctx
->chip_class
<= CIK
&&
1368 r600_resource(indexbuf
)->TC_L2_dirty
) {
1369 /* VI reads index buffers through TC L2, so it doesn't
1371 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1372 r600_resource(indexbuf
)->TC_L2_dirty
= false;
1376 if (info
->indirect
) {
1377 struct pipe_draw_indirect_info
*indirect
= info
->indirect
;
1379 /* Add the buffer size for memory checking in need_cs_space. */
1380 si_context_add_resource_size(sctx
, indirect
->buffer
);
1382 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1383 if (sctx
->chip_class
<= VI
) {
1384 if (r600_resource(indirect
->buffer
)->TC_L2_dirty
) {
1385 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1386 r600_resource(indirect
->buffer
)->TC_L2_dirty
= false;
1389 if (indirect
->indirect_draw_count
&&
1390 r600_resource(indirect
->indirect_draw_count
)->TC_L2_dirty
) {
1391 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
1392 r600_resource(indirect
->indirect_draw_count
)->TC_L2_dirty
= false;
1397 si_need_gfx_cs_space(sctx
);
1399 /* Since we've called si_context_add_resource_size for vertex buffers,
1400 * this must be called after si_need_cs_space, because we must let
1401 * need_cs_space flush before we add buffers to the buffer list.
1403 if (!si_upload_vertex_buffer_descriptors(sctx
))
1406 /* Use optimal packet order based on whether we need to sync the pipeline. */
1407 if (unlikely(sctx
->flags
& (SI_CONTEXT_FLUSH_AND_INV_CB
|
1408 SI_CONTEXT_FLUSH_AND_INV_DB
|
1409 SI_CONTEXT_PS_PARTIAL_FLUSH
|
1410 SI_CONTEXT_CS_PARTIAL_FLUSH
))) {
1411 /* If we have to wait for idle, set all states first, so that all
1412 * SET packets are processed in parallel with previous draw calls.
1413 * Then draw and prefetch at the end. This ensures that the time
1414 * the CUs are idle is very short.
1416 unsigned masked_atoms
= 0;
1418 if (unlikely(sctx
->flags
& SI_CONTEXT_FLUSH_FOR_RENDER_COND
))
1419 masked_atoms
|= si_get_atom_bit(sctx
, &sctx
->atoms
.s
.render_cond
);
1421 if (!si_upload_graphics_shader_descriptors(sctx
))
1424 /* Emit all states except possibly render condition. */
1425 si_emit_all_states(sctx
, info
, masked_atoms
);
1426 si_emit_cache_flush(sctx
);
1427 /* <-- CUs are idle here. */
1429 if (si_is_atom_dirty(sctx
, &sctx
->atoms
.s
.render_cond
))
1430 sctx
->atoms
.s
.render_cond
.emit(sctx
);
1431 sctx
->dirty_atoms
= 0;
1433 si_emit_draw_packets(sctx
, info
, indexbuf
, index_size
, index_offset
);
1434 /* <-- CUs are busy here. */
1436 /* Start prefetches after the draw has been started. Both will run
1437 * in parallel, but starting the draw first is more important.
1439 if (sctx
->chip_class
>= CIK
&& sctx
->prefetch_L2_mask
)
1440 cik_emit_prefetch_L2(sctx
, false);
1442 /* If we don't wait for idle, start prefetches first, then set
1443 * states, and draw at the end.
1446 si_emit_cache_flush(sctx
);
1448 /* Only prefetch the API VS and VBO descriptors. */
1449 if (sctx
->chip_class
>= CIK
&& sctx
->prefetch_L2_mask
)
1450 cik_emit_prefetch_L2(sctx
, true);
1452 if (!si_upload_graphics_shader_descriptors(sctx
))
1455 si_emit_all_states(sctx
, info
, 0);
1456 si_emit_draw_packets(sctx
, info
, indexbuf
, index_size
, index_offset
);
1458 /* Prefetch the remaining shaders after the draw has been
1460 if (sctx
->chip_class
>= CIK
&& sctx
->prefetch_L2_mask
)
1461 cik_emit_prefetch_L2(sctx
, false);
1464 if (unlikely(sctx
->current_saved_cs
)) {
1465 si_trace_emit(sctx
);
1466 si_log_draw_state(sctx
, sctx
->log
);
1469 /* Workaround for a VGT hang when streamout is enabled.
1470 * It must be done after drawing. */
1471 if ((sctx
->family
== CHIP_HAWAII
||
1472 sctx
->family
== CHIP_TONGA
||
1473 sctx
->family
== CHIP_FIJI
) &&
1474 si_get_strmout_en(sctx
)) {
1475 sctx
->flags
|= SI_CONTEXT_VGT_STREAMOUT_SYNC
;
1478 if (unlikely(sctx
->decompression_enabled
)) {
1479 sctx
->num_decompress_calls
++;
1481 sctx
->num_draw_calls
++;
1482 if (sctx
->framebuffer
.state
.nr_cbufs
> 1)
1483 sctx
->num_mrt_draw_calls
++;
1484 if (info
->primitive_restart
)
1485 sctx
->num_prim_restart_calls
++;
1486 if (G_0286E8_WAVESIZE(sctx
->spi_tmpring_size
))
1487 sctx
->num_spill_draw_calls
++;
1489 if (index_size
&& indexbuf
!= info
->index
.resource
)
1490 pipe_resource_reference(&indexbuf
, NULL
);
1493 void si_draw_rectangle(struct blitter_context
*blitter
,
1494 void *vertex_elements_cso
,
1495 blitter_get_vs_func get_vs
,
1496 int x1
, int y1
, int x2
, int y2
,
1497 float depth
, unsigned num_instances
,
1498 enum blitter_attrib_type type
,
1499 const union blitter_attrib
*attrib
)
1501 struct pipe_context
*pipe
= util_blitter_get_pipe(blitter
);
1502 struct si_context
*sctx
= (struct si_context
*)pipe
;
1504 /* Pack position coordinates as signed int16. */
1505 sctx
->vs_blit_sh_data
[0] = (uint32_t)(x1
& 0xffff) |
1506 ((uint32_t)(y1
& 0xffff) << 16);
1507 sctx
->vs_blit_sh_data
[1] = (uint32_t)(x2
& 0xffff) |
1508 ((uint32_t)(y2
& 0xffff) << 16);
1509 sctx
->vs_blit_sh_data
[2] = fui(depth
);
1512 case UTIL_BLITTER_ATTRIB_COLOR
:
1513 memcpy(&sctx
->vs_blit_sh_data
[3], attrib
->color
,
1516 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY
:
1517 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW
:
1518 memcpy(&sctx
->vs_blit_sh_data
[3], &attrib
->texcoord
,
1519 sizeof(attrib
->texcoord
));
1521 case UTIL_BLITTER_ATTRIB_NONE
:;
1524 pipe
->bind_vs_state(pipe
, si_get_blit_vs(sctx
, type
, num_instances
));
1526 struct pipe_draw_info info
= {};
1527 info
.mode
= SI_PRIM_RECTANGLE_LIST
;
1529 info
.instance_count
= num_instances
;
1531 /* Don't set per-stage shader pointers for VS. */
1532 sctx
->shader_pointers_dirty
&= ~SI_DESCS_SHADER_MASK(VERTEX
);
1533 sctx
->vertex_buffer_pointer_dirty
= false;
1535 si_draw_vbo(pipe
, &info
);
1538 void si_trace_emit(struct si_context
*sctx
)
1540 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
1541 uint64_t va
= sctx
->current_saved_cs
->trace_buf
->gpu_address
;
1542 uint32_t trace_id
= ++sctx
->current_saved_cs
->trace_id
;
1544 radeon_emit(cs
, PKT3(PKT3_WRITE_DATA
, 3, 0));
1545 radeon_emit(cs
, S_370_DST_SEL(V_370_MEMORY_SYNC
) |
1546 S_370_WR_CONFIRM(1) |
1547 S_370_ENGINE_SEL(V_370_ME
));
1548 radeon_emit(cs
, va
);
1549 radeon_emit(cs
, va
>> 32);
1550 radeon_emit(cs
, trace_id
);
1551 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1552 radeon_emit(cs
, AC_ENCODE_TRACE_POINT(trace_id
));
1555 u_log_flush(sctx
->log
);