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radeonsi: use optimal WD settings for primitive restart on Polaris
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "radeon/r600_cs.h"
30 #include "sid.h"
31
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
35 #include "util/u_memory.h"
36
37 static unsigned si_conv_pipe_prim(unsigned mode)
38 {
39 static const unsigned prim_conv[] = {
40 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
41 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
42 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
43 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
44 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
45 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
46 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
47 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
48 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
49 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
50 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
51 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
52 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
53 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
54 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
55 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
56 };
57 assert(mode < ARRAY_SIZE(prim_conv));
58 return prim_conv[mode];
59 }
60
61 static unsigned si_conv_prim_to_gs_out(unsigned mode)
62 {
63 static const int prim_conv[] = {
64 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
65 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
66 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
67 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
68 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
69 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
73 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
74 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
75 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
76 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
77 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
78 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
79 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
80 };
81 assert(mode < ARRAY_SIZE(prim_conv));
82
83 return prim_conv[mode];
84 }
85
86 /**
87 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
88 * LS.LDS_SIZE is shared by all 3 shader stages.
89 *
90 * The information about LDS and other non-compile-time parameters is then
91 * written to userdata SGPRs.
92 */
93 static void si_emit_derived_tess_state(struct si_context *sctx,
94 const struct pipe_draw_info *info,
95 unsigned *num_patches)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_shader_ctx_state *ls = &sctx->vs_shader;
99 /* The TES pointer will only be used for sctx->last_tcs.
100 * It would be wrong to think that TCS = TES. */
101 struct si_shader_selector *tcs =
102 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
103 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
104 unsigned num_tcs_input_cp = info->vertices_per_patch;
105 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
106 unsigned num_tcs_patch_outputs;
107 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
108 unsigned input_patch_size, output_patch_size, output_patch0_offset;
109 unsigned perpatch_output_offset, lds_size, ls_rsrc2;
110 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
111 unsigned offchip_layout, hardware_lds_size;
112
113 /* This calculates how shader inputs and outputs among VS, TCS, and TES
114 * are laid out in LDS. */
115 num_tcs_inputs = util_last_bit64(ls->cso->outputs_written);
116
117 if (sctx->tcs_shader.cso) {
118 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
119 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
120 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
121 } else {
122 /* No TCS. Route varyings from LS to TES. */
123 num_tcs_outputs = num_tcs_inputs;
124 num_tcs_output_cp = num_tcs_input_cp;
125 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
126 }
127
128 input_vertex_size = num_tcs_inputs * 16;
129 output_vertex_size = num_tcs_outputs * 16;
130
131 input_patch_size = num_tcs_input_cp * input_vertex_size;
132
133 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
134 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
135
136 /* Ensure that we only need one wave per SIMD so we don't need to check
137 * resource usage. Also ensures that the number of tcs in and out
138 * vertices per threadgroup are at most 256.
139 */
140 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
141
142 /* Make sure that the data fits in LDS. This assumes the shaders only
143 * use LDS for the inputs and outputs.
144 */
145 hardware_lds_size = sctx->b.chip_class >= CIK ? 65536 : 32768;
146 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
147 output_patch_size));
148
149 /* Make sure the output data fits in the offchip buffer */
150 *num_patches = MIN2(*num_patches, SI_TESS_OFFCHIP_BLOCK_SIZE /
151 output_patch_size);
152
153 /* Not necessary for correctness, but improves performance. The
154 * specific value is taken from the proprietary driver.
155 */
156 *num_patches = MIN2(*num_patches, 40);
157
158 output_patch0_offset = input_patch_size * *num_patches;
159 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
160
161 lds_size = output_patch0_offset + output_patch_size * *num_patches;
162 ls_rsrc2 = ls->current->config.rsrc2;
163
164 if (sctx->b.chip_class >= CIK) {
165 assert(lds_size <= 65536);
166 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 512) / 512);
167 } else {
168 assert(lds_size <= 32768);
169 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 256) / 256);
170 }
171
172 if (sctx->last_ls == ls->current &&
173 sctx->last_tcs == tcs &&
174 sctx->last_tes_sh_base == tes_sh_base &&
175 sctx->last_num_tcs_input_cp == num_tcs_input_cp)
176 return;
177
178 sctx->last_ls = ls->current;
179 sctx->last_tcs = tcs;
180 sctx->last_tes_sh_base = tes_sh_base;
181 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
182
183 /* Due to a hw bug, RSRC2_LS must be written twice with another
184 * LS register written in between. */
185 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
186 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
187 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
188 radeon_emit(cs, ls->current->config.rsrc1);
189 radeon_emit(cs, ls_rsrc2);
190
191 /* Compute userdata SGPRs. */
192 assert(((input_vertex_size / 4) & ~0xff) == 0);
193 assert(((output_vertex_size / 4) & ~0xff) == 0);
194 assert(((input_patch_size / 4) & ~0x1fff) == 0);
195 assert(((output_patch_size / 4) & ~0x1fff) == 0);
196 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
197 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
198 assert(num_tcs_input_cp <= 32);
199 assert(num_tcs_output_cp <= 32);
200
201 tcs_in_layout = (input_patch_size / 4) |
202 ((input_vertex_size / 4) << 13);
203 tcs_out_layout = (output_patch_size / 4) |
204 ((output_vertex_size / 4) << 13);
205 tcs_out_offsets = (output_patch0_offset / 16) |
206 ((perpatch_output_offset / 16) << 16);
207 offchip_layout = (pervertex_output_patch_size * *num_patches << 16) |
208 (num_tcs_output_cp << 9) | *num_patches;
209
210 /* Set them for LS. */
211 radeon_set_sh_reg(cs,
212 R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4,
213 tcs_in_layout);
214
215 /* Set them for TCS. */
216 radeon_set_sh_reg_seq(cs,
217 R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
218 radeon_emit(cs, offchip_layout);
219 radeon_emit(cs, tcs_out_offsets);
220 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
221 radeon_emit(cs, tcs_in_layout);
222
223 /* Set them for TES. */
224 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 1);
225 radeon_emit(cs, offchip_layout);
226 }
227
228 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
229 {
230 switch (info->mode) {
231 case PIPE_PRIM_PATCHES:
232 return info->count / info->vertices_per_patch;
233 case R600_PRIM_RECTANGLE_LIST:
234 return info->count / 3;
235 default:
236 return u_prims_for_vertices(info->mode, info->count);
237 }
238 }
239
240 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
241 const struct pipe_draw_info *info,
242 unsigned num_patches)
243 {
244 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
245 unsigned prim = info->mode;
246 unsigned primgroup_size = 128; /* recommended without a GS */
247 unsigned max_primgroup_in_wave = 2;
248
249 /* SWITCH_ON_EOP(0) is always preferable. */
250 bool wd_switch_on_eop = false;
251 bool ia_switch_on_eop = false;
252 bool ia_switch_on_eoi = false;
253 bool partial_vs_wave = false;
254 bool partial_es_wave = false;
255
256 if (sctx->gs_shader.cso)
257 primgroup_size = 64; /* recommended with a GS */
258
259 if (sctx->tes_shader.cso) {
260 /* primgroup_size must be set to a multiple of NUM_PATCHES */
261 primgroup_size = num_patches;
262
263 /* SWITCH_ON_EOI must be set if PrimID is used. */
264 if ((sctx->tcs_shader.cso && sctx->tcs_shader.cso->info.uses_primid) ||
265 sctx->tes_shader.cso->info.uses_primid)
266 ia_switch_on_eoi = true;
267
268 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
269 if ((sctx->b.family == CHIP_TAHITI ||
270 sctx->b.family == CHIP_PITCAIRN ||
271 sctx->b.family == CHIP_BONAIRE) &&
272 sctx->gs_shader.cso)
273 partial_vs_wave = true;
274
275 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
276 if (sctx->b.chip_class >= VI) {
277 if (sctx->gs_shader.cso)
278 partial_es_wave = true;
279 else
280 partial_vs_wave = true;
281 }
282 }
283
284 /* This is a hardware requirement. */
285 if ((rs && rs->line_stipple_enable) ||
286 (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
287 ia_switch_on_eop = true;
288 wd_switch_on_eop = true;
289 }
290
291 if (sctx->b.chip_class >= CIK) {
292 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
293 * 4 shader engines. Set 1 to pass the assertion below.
294 * The other cases are hardware requirements.
295 *
296 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
297 * for points, line strips, and tri strips.
298 */
299 if (sctx->b.screen->info.max_se < 4 ||
300 prim == PIPE_PRIM_POLYGON ||
301 prim == PIPE_PRIM_LINE_LOOP ||
302 prim == PIPE_PRIM_TRIANGLE_FAN ||
303 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
304 (info->primitive_restart &&
305 (sctx->b.family < CHIP_POLARIS10 ||
306 (prim != PIPE_PRIM_POINTS &&
307 prim != PIPE_PRIM_LINE_STRIP &&
308 prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
309 info->count_from_stream_output)
310 wd_switch_on_eop = true;
311
312 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
313 * We don't know that for indirect drawing, so treat it as
314 * always problematic. */
315 if (sctx->b.family == CHIP_HAWAII &&
316 (info->indirect || info->instance_count > 1))
317 wd_switch_on_eop = true;
318
319 /* Performance recommendation for 4 SE Gfx7-8 parts if
320 * instances are smaller than a primgroup. Ignore the fact
321 * primgroup_size is a primitive count, not vertex count.
322 * Don't do anything for indirect draws.
323 */
324 if (sctx->b.chip_class <= VI &&
325 sctx->b.screen->info.max_se >= 4 &&
326 !info->indirect &&
327 info->instance_count > 1 && info->count < primgroup_size)
328 wd_switch_on_eop = true;
329
330 /* Required on CIK and later. */
331 if (sctx->b.screen->info.max_se > 2 && !wd_switch_on_eop)
332 ia_switch_on_eoi = true;
333
334 /* Required by Hawaii and, for some special cases, by VI. */
335 if (ia_switch_on_eoi &&
336 (sctx->b.family == CHIP_HAWAII ||
337 (sctx->b.chip_class == VI &&
338 (sctx->gs_shader.cso || max_primgroup_in_wave != 2))))
339 partial_vs_wave = true;
340
341 /* Instancing bug on Bonaire. */
342 if (sctx->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
343 (info->indirect || info->instance_count > 1))
344 partial_vs_wave = true;
345
346 /* If the WD switch is false, the IA switch must be false too. */
347 assert(wd_switch_on_eop || !ia_switch_on_eop);
348 }
349
350 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
351 if (ia_switch_on_eoi)
352 partial_es_wave = true;
353
354 /* GS requirement. */
355 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
356 partial_es_wave = true;
357
358 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
359 * on multi-SE chips. */
360 if (sctx->b.screen->info.max_se >= 2 && ia_switch_on_eoi &&
361 (info->indirect ||
362 (info->instance_count > 1 &&
363 si_num_prims_for_vertices(info) <= 1)))
364 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
365
366 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
367 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
368 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
369 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
370 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
371 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
372 S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx->b.chip_class >= VI ?
373 max_primgroup_in_wave : 0);
374 }
375
376 static unsigned si_get_ls_hs_config(struct si_context *sctx,
377 const struct pipe_draw_info *info,
378 unsigned num_patches)
379 {
380 unsigned num_output_cp;
381
382 if (!sctx->tes_shader.cso)
383 return 0;
384
385 num_output_cp = sctx->tcs_shader.cso ?
386 sctx->tcs_shader.cso->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
387 info->vertices_per_patch;
388
389 return S_028B58_NUM_PATCHES(num_patches) |
390 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
391 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
392 }
393
394 static void si_emit_scratch_reloc(struct si_context *sctx)
395 {
396 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
397
398 if (!sctx->emit_scratch_reloc)
399 return;
400
401 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
402 sctx->spi_tmpring_size);
403
404 if (sctx->scratch_buffer) {
405 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
406 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
407 RADEON_PRIO_SCRATCH_BUFFER);
408
409 }
410 sctx->emit_scratch_reloc = false;
411 }
412
413 /* rast_prim is the primitive type after GS. */
414 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
415 {
416 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
417 unsigned rast_prim = sctx->current_rast_prim;
418 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
419
420 /* Skip this if not rendering lines. */
421 if (rast_prim != PIPE_PRIM_LINES &&
422 rast_prim != PIPE_PRIM_LINE_LOOP &&
423 rast_prim != PIPE_PRIM_LINE_STRIP &&
424 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
425 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
426 return;
427
428 if (rast_prim == sctx->last_rast_prim &&
429 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
430 return;
431
432 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
433 rs->pa_sc_line_stipple |
434 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 :
435 rast_prim == PIPE_PRIM_LINE_STRIP ? 2 : 0));
436
437 sctx->last_rast_prim = rast_prim;
438 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
439 }
440
441 static void si_emit_draw_registers(struct si_context *sctx,
442 const struct pipe_draw_info *info)
443 {
444 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
445 unsigned prim = si_conv_pipe_prim(info->mode);
446 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
447 unsigned ia_multi_vgt_param, ls_hs_config, num_patches = 0;
448
449 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
450 * whether the "fractional odd" tessellation spacing is used.
451 */
452 if (sctx->b.family >= CHIP_POLARIS10) {
453 struct si_shader_selector *tes = sctx->tes_shader.cso;
454 unsigned vtx_reuse_depth = 30;
455
456 if (tes &&
457 tes->info.properties[TGSI_PROPERTY_TES_SPACING] ==
458 PIPE_TESS_SPACING_FRACTIONAL_ODD)
459 vtx_reuse_depth = 14;
460
461 if (vtx_reuse_depth != sctx->last_vtx_reuse_depth) {
462 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
463 vtx_reuse_depth);
464 sctx->last_vtx_reuse_depth = vtx_reuse_depth;
465 }
466 }
467
468 if (sctx->tes_shader.cso)
469 si_emit_derived_tess_state(sctx, info, &num_patches);
470
471 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
472 ls_hs_config = si_get_ls_hs_config(sctx, info, num_patches);
473
474 /* Draw state. */
475 if (prim != sctx->last_prim ||
476 ia_multi_vgt_param != sctx->last_multi_vgt_param ||
477 ls_hs_config != sctx->last_ls_hs_config) {
478 if (sctx->b.family >= CHIP_POLARIS10) {
479 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
480 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
481 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
482 } else if (sctx->b.chip_class >= CIK) {
483 radeon_emit(cs, PKT3(PKT3_DRAW_PREAMBLE, 2, 0));
484 radeon_emit(cs, prim); /* VGT_PRIMITIVE_TYPE */
485 radeon_emit(cs, ia_multi_vgt_param); /* IA_MULTI_VGT_PARAM */
486 radeon_emit(cs, ls_hs_config); /* VGT_LS_HS_CONFIG */
487 } else {
488 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
489 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
490 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
491 }
492
493 sctx->last_prim = prim;
494 sctx->last_multi_vgt_param = ia_multi_vgt_param;
495 sctx->last_ls_hs_config = ls_hs_config;
496 }
497
498 if (gs_out_prim != sctx->last_gs_out_prim) {
499 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
500 sctx->last_gs_out_prim = gs_out_prim;
501 }
502
503 /* Primitive restart. */
504 if (info->primitive_restart != sctx->last_primitive_restart_en) {
505 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
506 sctx->last_primitive_restart_en = info->primitive_restart;
507
508 if (info->primitive_restart &&
509 (info->restart_index != sctx->last_restart_index ||
510 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
511 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
512 info->restart_index);
513 sctx->last_restart_index = info->restart_index;
514 }
515 }
516 }
517
518 static void si_emit_draw_packets(struct si_context *sctx,
519 const struct pipe_draw_info *info,
520 const struct pipe_index_buffer *ib)
521 {
522 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
523 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
524 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
525
526 if (info->count_from_stream_output) {
527 struct r600_so_target *t =
528 (struct r600_so_target*)info->count_from_stream_output;
529 uint64_t va = t->buf_filled_size->gpu_address +
530 t->buf_filled_size_offset;
531
532 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
533 t->stride_in_dw);
534
535 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
536 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
537 COPY_DATA_DST_SEL(COPY_DATA_REG) |
538 COPY_DATA_WR_CONFIRM);
539 radeon_emit(cs, va); /* src address lo */
540 radeon_emit(cs, va >> 32); /* src address hi */
541 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
542 radeon_emit(cs, 0); /* unused */
543
544 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
545 t->buf_filled_size, RADEON_USAGE_READ,
546 RADEON_PRIO_SO_FILLED_SIZE);
547 }
548
549 /* draw packet */
550 if (info->indexed) {
551 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
552
553 /* index type */
554 switch (ib->index_size) {
555 case 1:
556 radeon_emit(cs, V_028A7C_VGT_INDEX_8);
557 break;
558 case 2:
559 radeon_emit(cs, V_028A7C_VGT_INDEX_16 |
560 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
561 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
562 break;
563 case 4:
564 radeon_emit(cs, V_028A7C_VGT_INDEX_32 |
565 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
566 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
567 break;
568 default:
569 assert(!"unreachable");
570 return;
571 }
572 }
573
574 if (!info->indirect) {
575 int base_vertex;
576
577 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
578 radeon_emit(cs, info->instance_count);
579
580 /* Base vertex and start instance. */
581 base_vertex = info->indexed ? info->index_bias : info->start;
582
583 if (base_vertex != sctx->last_base_vertex ||
584 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
585 info->start_instance != sctx->last_start_instance ||
586 sh_base_reg != sctx->last_sh_base_reg) {
587 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
588 radeon_emit(cs, base_vertex);
589 radeon_emit(cs, info->start_instance);
590
591 sctx->last_base_vertex = base_vertex;
592 sctx->last_start_instance = info->start_instance;
593 sctx->last_sh_base_reg = sh_base_reg;
594 }
595 } else {
596 si_invalidate_draw_sh_constants(sctx);
597
598 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
599 (struct r600_resource *)info->indirect,
600 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
601 }
602
603 if (info->indexed) {
604 uint32_t index_max_size = (ib->buffer->width0 - ib->offset) /
605 ib->index_size;
606 uint64_t index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
607
608 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
609 (struct r600_resource *)ib->buffer,
610 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
611
612 if (info->indirect) {
613 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
614
615 assert(indirect_va % 8 == 0);
616 assert(index_va % 2 == 0);
617 assert(info->indirect_offset % 4 == 0);
618
619 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
620 radeon_emit(cs, 1);
621 radeon_emit(cs, indirect_va);
622 radeon_emit(cs, indirect_va >> 32);
623
624 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
625 radeon_emit(cs, index_va);
626 radeon_emit(cs, index_va >> 32);
627
628 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
629 radeon_emit(cs, index_max_size);
630
631 if (sctx->b.family < CHIP_POLARIS10) {
632 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT, 3, render_cond_bit));
633 radeon_emit(cs, info->indirect_offset);
634 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
635 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
636 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
637 } else {
638 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT_MULTI, 8, render_cond_bit));
639 radeon_emit(cs, info->indirect_offset);
640 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
641 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
642 radeon_emit(cs, 0); /* draw_index */
643 radeon_emit(cs, 1); /* count */
644 radeon_emit(cs, 0); /* count_addr -- disabled */
645 radeon_emit(cs, 0);
646 radeon_emit(cs, 16); /* stride */
647 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
648 }
649 } else {
650 index_va += info->start * ib->index_size;
651
652 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
653 radeon_emit(cs, index_max_size);
654 radeon_emit(cs, index_va);
655 radeon_emit(cs, (index_va >> 32UL) & 0xFF);
656 radeon_emit(cs, info->count);
657 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
658 }
659 } else {
660 if (info->indirect) {
661 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
662
663 assert(indirect_va % 8 == 0);
664 assert(info->indirect_offset % 4 == 0);
665
666 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
667 radeon_emit(cs, 1);
668 radeon_emit(cs, indirect_va);
669 radeon_emit(cs, indirect_va >> 32);
670
671 if (sctx->b.family < CHIP_POLARIS10) {
672 radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, render_cond_bit));
673 radeon_emit(cs, info->indirect_offset);
674 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
675 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
676 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
677 } else {
678 radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT_MULTI, 8, render_cond_bit));
679 radeon_emit(cs, info->indirect_offset);
680 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
681 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
682 radeon_emit(cs, 0); /* draw_index */
683 radeon_emit(cs, 1); /* count */
684 radeon_emit(cs, 0); /* count_addr -- disabled */
685 radeon_emit(cs, 0);
686 radeon_emit(cs, 16); /* stride */
687 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
688 }
689 } else {
690 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
691 radeon_emit(cs, info->count);
692 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
693 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
694 }
695 }
696 }
697
698 void si_emit_cache_flush(struct si_context *si_ctx, struct r600_atom *atom)
699 {
700 struct r600_common_context *sctx = &si_ctx->b;
701 struct radeon_winsys_cs *cs = sctx->gfx.cs;
702 uint32_t cp_coher_cntl = 0;
703
704 /* SI has a bug that it always flushes ICACHE and KCACHE if either
705 * bit is set. An alternative way is to write SQC_CACHES, but that
706 * doesn't seem to work reliably. Since the bug doesn't affect
707 * correctness (it only does more work than necessary) and
708 * the performance impact is likely negligible, there is no plan
709 * to add a workaround for it.
710 */
711
712 if (sctx->flags & SI_CONTEXT_INV_ICACHE)
713 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
714 if (sctx->flags & SI_CONTEXT_INV_SMEM_L1)
715 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
716
717 if (sctx->flags & SI_CONTEXT_INV_VMEM_L1)
718 cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
719 if (sctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
720 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
721
722 if (sctx->chip_class >= VI)
723 cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1);
724 }
725
726 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
727 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
728 S_0085F0_CB0_DEST_BASE_ENA(1) |
729 S_0085F0_CB1_DEST_BASE_ENA(1) |
730 S_0085F0_CB2_DEST_BASE_ENA(1) |
731 S_0085F0_CB3_DEST_BASE_ENA(1) |
732 S_0085F0_CB4_DEST_BASE_ENA(1) |
733 S_0085F0_CB5_DEST_BASE_ENA(1) |
734 S_0085F0_CB6_DEST_BASE_ENA(1) |
735 S_0085F0_CB7_DEST_BASE_ENA(1);
736
737 /* Necessary for DCC */
738 if (sctx->chip_class >= VI) {
739 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
740 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) |
741 EVENT_INDEX(5));
742 radeon_emit(cs, 0);
743 radeon_emit(cs, 0);
744 radeon_emit(cs, 0);
745 radeon_emit(cs, 0);
746 }
747 }
748 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
749 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
750 S_0085F0_DB_DEST_BASE_ENA(1);
751 }
752
753 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) {
754 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
755 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
756 /* needed for wait for idle in SURFACE_SYNC */
757 assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB);
758 }
759 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) {
760 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
761 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
762 /* needed for wait for idle in SURFACE_SYNC */
763 assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB);
764 }
765
766 /* Wait for shader engines to go idle.
767 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
768 * for everything including CB/DB cache flushes.
769 */
770 if (!(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
771 SI_CONTEXT_FLUSH_AND_INV_DB))) {
772 if (sctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
773 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
774 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
775 } else if (sctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
776 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
777 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
778 }
779 }
780 if (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH) {
781 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
782 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
783 }
784
785 /* VGT state synchronization. */
786 if (sctx->flags & SI_CONTEXT_VGT_FLUSH) {
787 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
788 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
789 }
790 if (sctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
791 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
792 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
793 }
794
795 /* Make sure ME is idle (it executes most packets) before continuing.
796 * This prevents read-after-write hazards between PFP and ME.
797 */
798 if (cp_coher_cntl || (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH)) {
799 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
800 radeon_emit(cs, 0);
801 }
802
803 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
804 * Therefore, it should be last. Done in PFP.
805 */
806 if (cp_coher_cntl) {
807 /* ACQUIRE_MEM is only required on a compute ring. */
808 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
809 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
810 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
811 radeon_emit(cs, 0); /* CP_COHER_BASE */
812 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
813 }
814
815 if (sctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
816 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
817 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
818 EVENT_INDEX(0));
819 } else if (sctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
820 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
821 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
822 EVENT_INDEX(0));
823 }
824
825 sctx->flags = 0;
826 }
827
828 static void si_get_draw_start_count(struct si_context *sctx,
829 const struct pipe_draw_info *info,
830 unsigned *start, unsigned *count)
831 {
832 if (info->indirect) {
833 struct r600_resource *indirect =
834 (struct r600_resource*)info->indirect;
835 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
836 indirect, PIPE_TRANSFER_READ);
837 data += info->indirect_offset/sizeof(int);
838 *start = data[2];
839 *count = data[0];
840 } else {
841 *start = info->start;
842 *count = info->count;
843 }
844 }
845
846 void si_ce_pre_draw_synchronization(struct si_context *sctx)
847 {
848 if (sctx->ce_need_synchronization) {
849 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
850 radeon_emit(sctx->ce_ib, 1);
851
852 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
853 radeon_emit(sctx->b.gfx.cs, 1);
854 }
855 }
856
857 void si_ce_post_draw_synchronization(struct si_context *sctx)
858 {
859 if (sctx->ce_need_synchronization) {
860 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
861 radeon_emit(sctx->b.gfx.cs, 0);
862
863 sctx->ce_need_synchronization = false;
864 }
865 }
866
867 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
868 {
869 struct si_context *sctx = (struct si_context *)ctx;
870 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
871 struct pipe_index_buffer ib = {};
872 unsigned mask, dirty_fb_counter, dirty_tex_counter;
873
874 if (!info->count && !info->indirect &&
875 (info->indexed || !info->count_from_stream_output))
876 return;
877
878 if (!sctx->vs_shader.cso) {
879 assert(0);
880 return;
881 }
882 if (!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard)) {
883 assert(0);
884 return;
885 }
886 if (!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES)) {
887 assert(0);
888 return;
889 }
890
891 /* Re-emit the framebuffer state if needed. */
892 dirty_fb_counter = p_atomic_read(&sctx->b.screen->dirty_fb_counter);
893 if (dirty_fb_counter != sctx->b.last_dirty_fb_counter) {
894 sctx->b.last_dirty_fb_counter = dirty_fb_counter;
895 sctx->framebuffer.dirty_cbufs |=
896 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
897 sctx->framebuffer.dirty_zsbuf = true;
898 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
899 }
900
901 /* Invalidate & recompute texture descriptors if needed. */
902 dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_descriptor_counter);
903 if (dirty_tex_counter != sctx->b.last_dirty_tex_descriptor_counter) {
904 sctx->b.last_dirty_tex_descriptor_counter = dirty_tex_counter;
905 si_update_all_texture_descriptors(sctx);
906 }
907
908 si_decompress_graphics_textures(sctx);
909
910 /* Set the rasterization primitive type.
911 *
912 * This must be done after si_decompress_textures, which can call
913 * draw_vbo recursively, and before si_update_shaders, which uses
914 * current_rast_prim for this draw_vbo call. */
915 if (sctx->gs_shader.cso)
916 sctx->current_rast_prim = sctx->gs_shader.cso->gs_output_prim;
917 else if (sctx->tes_shader.cso)
918 sctx->current_rast_prim =
919 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
920 else
921 sctx->current_rast_prim = info->mode;
922
923 if (!si_update_shaders(sctx) ||
924 !si_upload_graphics_shader_descriptors(sctx))
925 return;
926
927 if (info->indexed) {
928 /* Initialize the index buffer struct. */
929 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
930 ib.user_buffer = sctx->index_buffer.user_buffer;
931 ib.index_size = sctx->index_buffer.index_size;
932 ib.offset = sctx->index_buffer.offset;
933
934 /* Translate or upload, if needed. */
935 /* 8-bit indices are supported on VI. */
936 if (sctx->b.chip_class <= CIK && ib.index_size == 1) {
937 struct pipe_resource *out_buffer = NULL;
938 unsigned out_offset, start, count, start_offset;
939 void *ptr;
940
941 si_get_draw_start_count(sctx, info, &start, &count);
942 start_offset = start * ib.index_size;
943
944 u_upload_alloc(sctx->b.uploader, start_offset, count * 2, 256,
945 &out_offset, &out_buffer, &ptr);
946 if (!out_buffer) {
947 pipe_resource_reference(&ib.buffer, NULL);
948 return;
949 }
950
951 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
952 ib.offset + start_offset,
953 count, ptr);
954
955 pipe_resource_reference(&ib.buffer, NULL);
956 ib.user_buffer = NULL;
957 ib.buffer = out_buffer;
958 /* info->start will be added by the drawing code */
959 ib.offset = out_offset - start_offset;
960 ib.index_size = 2;
961 } else if (ib.user_buffer && !ib.buffer) {
962 unsigned start, count, start_offset;
963
964 si_get_draw_start_count(sctx, info, &start, &count);
965 start_offset = start * ib.index_size;
966
967 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
968 256, (char*)ib.user_buffer + start_offset,
969 &ib.offset, &ib.buffer);
970 if (!ib.buffer)
971 return;
972 /* info->start will be added by the drawing code */
973 ib.offset -= start_offset;
974 }
975 }
976
977 /* VI reads index buffers through TC L2. */
978 if (info->indexed && sctx->b.chip_class <= CIK &&
979 r600_resource(ib.buffer)->TC_L2_dirty) {
980 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
981 r600_resource(ib.buffer)->TC_L2_dirty = false;
982 }
983
984 /* Check flush flags. */
985 if (sctx->b.flags)
986 si_mark_atom_dirty(sctx, sctx->atoms.s.cache_flush);
987
988 si_need_cs_space(sctx);
989
990 /* Emit states. */
991 mask = sctx->dirty_atoms;
992 while (mask) {
993 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
994
995 atom->emit(&sctx->b, atom);
996 }
997 sctx->dirty_atoms = 0;
998
999 si_pm4_emit_dirty(sctx);
1000 si_emit_scratch_reloc(sctx);
1001 si_emit_rasterizer_prim_state(sctx);
1002 si_emit_draw_registers(sctx, info);
1003
1004 si_ce_pre_draw_synchronization(sctx);
1005
1006 si_emit_draw_packets(sctx, info, &ib);
1007
1008 si_ce_post_draw_synchronization(sctx);
1009
1010 if (sctx->trace_buf)
1011 si_trace_emit(sctx);
1012
1013 /* Workaround for a VGT hang when streamout is enabled.
1014 * It must be done after drawing. */
1015 if ((sctx->b.family == CHIP_HAWAII ||
1016 sctx->b.family == CHIP_TONGA ||
1017 sctx->b.family == CHIP_FIJI) &&
1018 r600_get_strmout_en(&sctx->b)) {
1019 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1020 }
1021
1022 /* Set the depth buffer as dirty. */
1023 if (sctx->framebuffer.state.zsbuf) {
1024 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1025 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1026
1027 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1028
1029 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1030 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
1031 }
1032 if (sctx->framebuffer.compressed_cb_mask) {
1033 struct pipe_surface *surf;
1034 struct r600_texture *rtex;
1035 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1036
1037 do {
1038 unsigned i = u_bit_scan(&mask);
1039 surf = sctx->framebuffer.state.cbufs[i];
1040 rtex = (struct r600_texture*)surf->texture;
1041
1042 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1043 } while (mask);
1044 }
1045
1046 pipe_resource_reference(&ib.buffer, NULL);
1047 sctx->b.num_draw_calls++;
1048 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1049 sctx->b.num_spill_draw_calls++;
1050 }
1051
1052 void si_trace_emit(struct si_context *sctx)
1053 {
1054 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1055
1056 sctx->trace_id++;
1057 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
1058 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
1059 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1060 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1061 S_370_WR_CONFIRM(1) |
1062 S_370_ENGINE_SEL(V_370_ME));
1063 radeon_emit(cs, sctx->trace_buf->gpu_address);
1064 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
1065 radeon_emit(cs, sctx->trace_id);
1066 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1067 radeon_emit(cs, SI_ENCODE_TRACE_POINT(sctx->trace_id));
1068 }