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radeonsi: emit VS_STATE register explicitly from si_draw_vbo
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "radeon/r600_cs.h"
29 #include "sid.h"
30 #include "gfx9d.h"
31
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
35
36 #include "ac_debug.h"
37
38 static unsigned si_conv_pipe_prim(unsigned mode)
39 {
40 static const unsigned prim_conv[] = {
41 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
42 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
43 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
44 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
45 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
46 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
47 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
48 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
49 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
50 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
51 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
52 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
53 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
54 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
55 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
56 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
57 };
58 assert(mode < ARRAY_SIZE(prim_conv));
59 return prim_conv[mode];
60 }
61
62 static unsigned si_conv_prim_to_gs_out(unsigned mode)
63 {
64 static const int prim_conv[] = {
65 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
66 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
67 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
68 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
69 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
73 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
74 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
75 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
76 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
77 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
78 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
79 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
80 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
81 };
82 assert(mode < ARRAY_SIZE(prim_conv));
83
84 return prim_conv[mode];
85 }
86
87 /**
88 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
89 * LS.LDS_SIZE is shared by all 3 shader stages.
90 *
91 * The information about LDS and other non-compile-time parameters is then
92 * written to userdata SGPRs.
93 */
94 static void si_emit_derived_tess_state(struct si_context *sctx,
95 const struct pipe_draw_info *info,
96 unsigned *num_patches)
97 {
98 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
99 struct si_shader_ctx_state *ls = &sctx->vs_shader;
100 /* The TES pointer will only be used for sctx->last_tcs.
101 * It would be wrong to think that TCS = TES. */
102 struct si_shader_selector *tcs =
103 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
104 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
105 unsigned num_tcs_input_cp = info->vertices_per_patch;
106 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
107 unsigned num_tcs_patch_outputs;
108 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
109 unsigned input_patch_size, output_patch_size, output_patch0_offset;
110 unsigned perpatch_output_offset, lds_size, ls_rsrc2;
111 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
112 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
113
114 if (sctx->last_ls == ls->current &&
115 sctx->last_tcs == tcs &&
116 sctx->last_tes_sh_base == tes_sh_base &&
117 sctx->last_num_tcs_input_cp == num_tcs_input_cp) {
118 *num_patches = sctx->last_num_patches;
119 return;
120 }
121
122 sctx->last_ls = ls->current;
123 sctx->last_tcs = tcs;
124 sctx->last_tes_sh_base = tes_sh_base;
125 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
126
127 /* This calculates how shader inputs and outputs among VS, TCS, and TES
128 * are laid out in LDS. */
129 num_tcs_inputs = util_last_bit64(ls->cso->outputs_written);
130
131 if (sctx->tcs_shader.cso) {
132 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
133 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
134 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
135 } else {
136 /* No TCS. Route varyings from LS to TES. */
137 num_tcs_outputs = num_tcs_inputs;
138 num_tcs_output_cp = num_tcs_input_cp;
139 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
140 }
141
142 input_vertex_size = num_tcs_inputs * 16;
143 output_vertex_size = num_tcs_outputs * 16;
144
145 input_patch_size = num_tcs_input_cp * input_vertex_size;
146
147 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
148 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
149
150 /* Ensure that we only need one wave per SIMD so we don't need to check
151 * resource usage. Also ensures that the number of tcs in and out
152 * vertices per threadgroup are at most 256.
153 */
154 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
155
156 /* Make sure that the data fits in LDS. This assumes the shaders only
157 * use LDS for the inputs and outputs.
158 */
159 hardware_lds_size = sctx->b.chip_class >= CIK ? 65536 : 32768;
160 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
161 output_patch_size));
162
163 /* Make sure the output data fits in the offchip buffer */
164 *num_patches = MIN2(*num_patches,
165 (sctx->screen->tess_offchip_block_dw_size * 4) /
166 output_patch_size);
167
168 /* Not necessary for correctness, but improves performance. The
169 * specific value is taken from the proprietary driver.
170 */
171 *num_patches = MIN2(*num_patches, 40);
172
173 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
174 if (sctx->b.chip_class == SI) {
175 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
176 *num_patches = MIN2(*num_patches, one_wave);
177 }
178
179 sctx->last_num_patches = *num_patches;
180
181 output_patch0_offset = input_patch_size * *num_patches;
182 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
183
184 lds_size = output_patch0_offset + output_patch_size * *num_patches;
185 ls_rsrc2 = ls->current->config.rsrc2;
186
187 if (sctx->b.chip_class >= CIK) {
188 assert(lds_size <= 65536);
189 lds_size = align(lds_size, 512) / 512;
190 } else {
191 assert(lds_size <= 32768);
192 lds_size = align(lds_size, 256) / 256;
193 }
194 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
195 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
196
197 /* Due to a hw bug, RSRC2_LS must be written twice with another
198 * LS register written in between. */
199 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
200 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
201 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
202 radeon_emit(cs, ls->current->config.rsrc1);
203 radeon_emit(cs, ls_rsrc2);
204
205 /* Compute userdata SGPRs. */
206 assert(((input_vertex_size / 4) & ~0xff) == 0);
207 assert(((output_vertex_size / 4) & ~0xff) == 0);
208 assert(((input_patch_size / 4) & ~0x1fff) == 0);
209 assert(((output_patch_size / 4) & ~0x1fff) == 0);
210 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
211 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
212 assert(num_tcs_input_cp <= 32);
213 assert(num_tcs_output_cp <= 32);
214
215 tcs_in_layout = (input_patch_size / 4) |
216 ((input_vertex_size / 4) << 13);
217 tcs_out_layout = (output_patch_size / 4) |
218 ((output_vertex_size / 4) << 13);
219 tcs_out_offsets = (output_patch0_offset / 16) |
220 ((perpatch_output_offset / 16) << 16);
221 offchip_layout = (pervertex_output_patch_size * *num_patches << 16) |
222 (num_tcs_output_cp << 9) | *num_patches;
223
224 /* Set them for LS. */
225 radeon_set_sh_reg(cs,
226 R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4,
227 tcs_in_layout);
228
229 /* Set them for TCS. */
230 radeon_set_sh_reg_seq(cs,
231 R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
232 radeon_emit(cs, offchip_layout);
233 radeon_emit(cs, tcs_out_offsets);
234 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
235 radeon_emit(cs, tcs_in_layout);
236
237 /* Set them for TES. */
238 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 1);
239 radeon_emit(cs, offchip_layout);
240
241 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
242 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
243 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
244
245 if (sctx->b.chip_class >= CIK)
246 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
247 ls_hs_config);
248 else
249 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
250 ls_hs_config);
251 }
252
253 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
254 {
255 switch (info->mode) {
256 case PIPE_PRIM_PATCHES:
257 return info->count / info->vertices_per_patch;
258 case R600_PRIM_RECTANGLE_LIST:
259 return info->count / 3;
260 default:
261 return u_prims_for_vertices(info->mode, info->count);
262 }
263 }
264
265 static unsigned
266 si_get_init_multi_vgt_param(struct si_screen *sscreen,
267 union si_vgt_param_key *key)
268 {
269 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
270 unsigned max_primgroup_in_wave = 2;
271
272 /* SWITCH_ON_EOP(0) is always preferable. */
273 bool wd_switch_on_eop = false;
274 bool ia_switch_on_eop = false;
275 bool ia_switch_on_eoi = false;
276 bool partial_vs_wave = false;
277 bool partial_es_wave = false;
278
279 if (key->u.uses_tess) {
280 /* SWITCH_ON_EOI must be set if PrimID is used. */
281 if (key->u.tcs_tes_uses_prim_id)
282 ia_switch_on_eoi = true;
283
284 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
285 if ((sscreen->b.family == CHIP_TAHITI ||
286 sscreen->b.family == CHIP_PITCAIRN ||
287 sscreen->b.family == CHIP_BONAIRE) &&
288 key->u.uses_gs)
289 partial_vs_wave = true;
290
291 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
292 if (sscreen->has_distributed_tess) {
293 if (key->u.uses_gs) {
294 partial_es_wave = true;
295
296 /* GPU hang workaround. */
297 if (sscreen->b.family == CHIP_TONGA ||
298 sscreen->b.family == CHIP_FIJI ||
299 sscreen->b.family == CHIP_POLARIS10 ||
300 sscreen->b.family == CHIP_POLARIS11)
301 partial_vs_wave = true;
302 } else {
303 partial_vs_wave = true;
304 }
305 }
306 }
307
308 /* This is a hardware requirement. */
309 if (key->u.line_stipple_enabled ||
310 (sscreen->b.debug_flags & DBG_SWITCH_ON_EOP)) {
311 ia_switch_on_eop = true;
312 wd_switch_on_eop = true;
313 }
314
315 if (sscreen->b.chip_class >= CIK) {
316 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
317 * 4 shader engines. Set 1 to pass the assertion below.
318 * The other cases are hardware requirements.
319 *
320 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
321 * for points, line strips, and tri strips.
322 */
323 if (sscreen->b.info.max_se < 4 ||
324 key->u.prim == PIPE_PRIM_POLYGON ||
325 key->u.prim == PIPE_PRIM_LINE_LOOP ||
326 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
327 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
328 (key->u.primitive_restart &&
329 (sscreen->b.family < CHIP_POLARIS10 ||
330 (key->u.prim != PIPE_PRIM_POINTS &&
331 key->u.prim != PIPE_PRIM_LINE_STRIP &&
332 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
333 key->u.count_from_stream_output)
334 wd_switch_on_eop = true;
335
336 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
337 * We don't know that for indirect drawing, so treat it as
338 * always problematic. */
339 if (sscreen->b.family == CHIP_HAWAII &&
340 key->u.uses_instancing)
341 wd_switch_on_eop = true;
342
343 /* Performance recommendation for 4 SE Gfx7-8 parts if
344 * instances are smaller than a primgroup.
345 * Assume indirect draws always use small instances.
346 * This is needed for good VS wave utilization.
347 */
348 if (sscreen->b.chip_class <= VI &&
349 sscreen->b.info.max_se == 4 &&
350 key->u.multi_instances_smaller_than_primgroup)
351 wd_switch_on_eop = true;
352
353 /* Required on CIK and later. */
354 if (sscreen->b.info.max_se > 2 && !wd_switch_on_eop)
355 ia_switch_on_eoi = true;
356
357 /* Required by Hawaii and, for some special cases, by VI. */
358 if (ia_switch_on_eoi &&
359 (sscreen->b.family == CHIP_HAWAII ||
360 (sscreen->b.chip_class == VI &&
361 (key->u.uses_gs || max_primgroup_in_wave != 2))))
362 partial_vs_wave = true;
363
364 /* Instancing bug on Bonaire. */
365 if (sscreen->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
366 key->u.uses_instancing)
367 partial_vs_wave = true;
368
369 /* If the WD switch is false, the IA switch must be false too. */
370 assert(wd_switch_on_eop || !ia_switch_on_eop);
371 }
372
373 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
374 if (ia_switch_on_eoi)
375 partial_es_wave = true;
376
377 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
378 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
379 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
380 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
381 S_028AA8_WD_SWITCH_ON_EOP(sscreen->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
382 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->b.chip_class >= VI ?
383 max_primgroup_in_wave : 0) |
384 S_030960_EN_INST_OPT_BASIC(sscreen->b.chip_class >= GFX9) |
385 S_030960_EN_INST_OPT_ADV(sscreen->b.chip_class >= GFX9);
386 }
387
388 void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
389 {
390 for (int prim = 0; prim <= R600_PRIM_RECTANGLE_LIST; prim++)
391 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
392 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
393 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
394 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
395 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
396 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
397 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
398 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
399 union si_vgt_param_key key;
400
401 key.index = 0;
402 key.u.prim = prim;
403 key.u.uses_instancing = uses_instancing;
404 key.u.multi_instances_smaller_than_primgroup = multi_instances;
405 key.u.primitive_restart = primitive_restart;
406 key.u.count_from_stream_output = count_from_so;
407 key.u.line_stipple_enabled = line_stipple;
408 key.u.uses_tess = uses_tess;
409 key.u.tcs_tes_uses_prim_id = tess_uses_primid;
410 key.u.uses_gs = uses_gs;
411
412 sctx->ia_multi_vgt_param[key.index] =
413 si_get_init_multi_vgt_param(sctx->screen, &key);
414 }
415 }
416
417 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
418 const struct pipe_draw_info *info,
419 unsigned num_patches)
420 {
421 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
422 unsigned primgroup_size;
423 unsigned ia_multi_vgt_param;
424
425 if (sctx->tes_shader.cso) {
426 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
427 } else if (sctx->gs_shader.cso) {
428 primgroup_size = 64; /* recommended with a GS */
429 } else {
430 primgroup_size = 128; /* recommended without a GS and tess */
431 }
432
433 key.u.prim = info->mode;
434 key.u.uses_instancing = info->indirect || info->instance_count > 1;
435 key.u.multi_instances_smaller_than_primgroup =
436 info->indirect ||
437 (info->instance_count > 1 &&
438 (info->count_from_stream_output ||
439 si_num_prims_for_vertices(info) < primgroup_size));
440 key.u.primitive_restart = info->primitive_restart;
441 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
442
443 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
444 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
445
446 if (sctx->gs_shader.cso) {
447 /* GS requirement. */
448 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
449 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
450
451 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
452 * The hw doc says all multi-SE chips are affected, but Vulkan
453 * only applies it to Hawaii. Do what Vulkan does.
454 */
455 if (sctx->b.family == CHIP_HAWAII &&
456 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
457 (info->indirect ||
458 (info->instance_count > 1 &&
459 (info->count_from_stream_output ||
460 si_num_prims_for_vertices(info) <= 1))))
461 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
462 }
463
464 return ia_multi_vgt_param;
465 }
466
467 /* rast_prim is the primitive type after GS. */
468 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
469 {
470 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
471 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
472 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
473
474 /* Skip this if not rendering lines. */
475 if (rast_prim != PIPE_PRIM_LINES &&
476 rast_prim != PIPE_PRIM_LINE_LOOP &&
477 rast_prim != PIPE_PRIM_LINE_STRIP &&
478 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
479 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
480 return;
481
482 if (rast_prim == sctx->last_rast_prim &&
483 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
484 return;
485
486 /* For lines, reset the stipple pattern at each primitive. Otherwise,
487 * reset the stipple pattern at each packet (line strips, line loops).
488 */
489 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
490 rs->pa_sc_line_stipple |
491 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
492
493 sctx->last_rast_prim = rast_prim;
494 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
495 }
496
497 static void si_emit_vs_state(struct si_context *sctx)
498 {
499 if (sctx->current_vs_state != sctx->last_vs_state) {
500 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
501
502 radeon_set_sh_reg(cs,
503 R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_VS_STATE_BITS * 4,
504 sctx->current_vs_state);
505
506 sctx->last_vs_state = sctx->current_vs_state;
507 }
508 }
509
510 static void si_emit_draw_registers(struct si_context *sctx,
511 const struct pipe_draw_info *info,
512 unsigned num_patches)
513 {
514 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
515 unsigned prim = si_conv_pipe_prim(info->mode);
516 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
517 unsigned ia_multi_vgt_param;
518
519 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
520
521 /* Draw state. */
522 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
523 if (sctx->b.chip_class >= GFX9)
524 radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
525 else if (sctx->b.chip_class >= CIK)
526 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
527 else
528 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
529
530 sctx->last_multi_vgt_param = ia_multi_vgt_param;
531 }
532 if (prim != sctx->last_prim) {
533 if (sctx->b.chip_class >= CIK)
534 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
535 else
536 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
537
538 sctx->last_prim = prim;
539 }
540
541 if (gs_out_prim != sctx->last_gs_out_prim) {
542 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
543 sctx->last_gs_out_prim = gs_out_prim;
544 }
545
546 /* Primitive restart. */
547 if (info->primitive_restart != sctx->last_primitive_restart_en) {
548 if (sctx->b.chip_class >= GFX9)
549 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
550 info->primitive_restart);
551 else
552 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
553 info->primitive_restart);
554
555 sctx->last_primitive_restart_en = info->primitive_restart;
556
557 }
558 if (info->primitive_restart &&
559 (info->restart_index != sctx->last_restart_index ||
560 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
561 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
562 info->restart_index);
563 sctx->last_restart_index = info->restart_index;
564 }
565 }
566
567 static void si_emit_draw_packets(struct si_context *sctx,
568 const struct pipe_draw_info *info,
569 const struct pipe_index_buffer *ib)
570 {
571 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
572 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
573 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
574 uint32_t index_max_size = 0;
575 uint64_t index_va = 0;
576
577 if (info->count_from_stream_output) {
578 struct r600_so_target *t =
579 (struct r600_so_target*)info->count_from_stream_output;
580 uint64_t va = t->buf_filled_size->gpu_address +
581 t->buf_filled_size_offset;
582
583 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
584 t->stride_in_dw);
585
586 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
587 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
588 COPY_DATA_DST_SEL(COPY_DATA_REG) |
589 COPY_DATA_WR_CONFIRM);
590 radeon_emit(cs, va); /* src address lo */
591 radeon_emit(cs, va >> 32); /* src address hi */
592 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
593 radeon_emit(cs, 0); /* unused */
594
595 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
596 t->buf_filled_size, RADEON_USAGE_READ,
597 RADEON_PRIO_SO_FILLED_SIZE);
598 }
599
600 /* draw packet */
601 if (info->indexed) {
602 if (ib->index_size != sctx->last_index_size) {
603 unsigned index_type;
604
605 /* index type */
606 switch (ib->index_size) {
607 case 1:
608 index_type = V_028A7C_VGT_INDEX_8;
609 break;
610 case 2:
611 index_type = V_028A7C_VGT_INDEX_16 |
612 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
613 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
614 break;
615 case 4:
616 index_type = V_028A7C_VGT_INDEX_32 |
617 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
618 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
619 break;
620 default:
621 assert(!"unreachable");
622 return;
623 }
624
625 if (sctx->b.chip_class >= GFX9) {
626 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
627 2, index_type);
628 } else {
629 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
630 radeon_emit(cs, index_type);
631 }
632
633 sctx->last_index_size = ib->index_size;
634 }
635
636 index_max_size = (ib->buffer->width0 - ib->offset) /
637 ib->index_size;
638 index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
639
640 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
641 (struct r600_resource *)ib->buffer,
642 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
643 } else {
644 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
645 * so the state must be re-emitted before the next indexed draw.
646 */
647 if (sctx->b.chip_class >= CIK)
648 sctx->last_index_size = -1;
649 }
650
651 if (!info->indirect) {
652 int base_vertex;
653
654 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
655 radeon_emit(cs, info->instance_count);
656
657 /* Base vertex and start instance. */
658 base_vertex = info->indexed ? info->index_bias : info->start;
659
660 if (base_vertex != sctx->last_base_vertex ||
661 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
662 info->start_instance != sctx->last_start_instance ||
663 info->drawid != sctx->last_drawid ||
664 sh_base_reg != sctx->last_sh_base_reg) {
665 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
666 radeon_emit(cs, base_vertex);
667 radeon_emit(cs, info->start_instance);
668 radeon_emit(cs, info->drawid);
669
670 sctx->last_base_vertex = base_vertex;
671 sctx->last_start_instance = info->start_instance;
672 sctx->last_drawid = info->drawid;
673 sctx->last_sh_base_reg = sh_base_reg;
674 }
675 } else {
676 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
677
678 assert(indirect_va % 8 == 0);
679
680 si_invalidate_draw_sh_constants(sctx);
681
682 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
683 radeon_emit(cs, 1);
684 radeon_emit(cs, indirect_va);
685 radeon_emit(cs, indirect_va >> 32);
686
687 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
688 (struct r600_resource *)info->indirect,
689 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
690 }
691
692 if (info->indirect) {
693 unsigned di_src_sel = info->indexed ? V_0287F0_DI_SRC_SEL_DMA
694 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
695
696 assert(info->indirect_offset % 4 == 0);
697
698 if (info->indexed) {
699 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
700 radeon_emit(cs, index_va);
701 radeon_emit(cs, index_va >> 32);
702
703 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
704 radeon_emit(cs, index_max_size);
705 }
706
707 if (!sctx->screen->has_draw_indirect_multi) {
708 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT
709 : PKT3_DRAW_INDIRECT,
710 3, render_cond_bit));
711 radeon_emit(cs, info->indirect_offset);
712 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
713 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
714 radeon_emit(cs, di_src_sel);
715 } else {
716 uint64_t count_va = 0;
717
718 if (info->indirect_params) {
719 struct r600_resource *params_buf =
720 (struct r600_resource *)info->indirect_params;
721
722 radeon_add_to_buffer_list(
723 &sctx->b, &sctx->b.gfx, params_buf,
724 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
725
726 count_va = params_buf->gpu_address + info->indirect_params_offset;
727 }
728
729 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
730 PKT3_DRAW_INDIRECT_MULTI,
731 8, render_cond_bit));
732 radeon_emit(cs, info->indirect_offset);
733 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
734 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
735 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
736 S_2C3_DRAW_INDEX_ENABLE(1) |
737 S_2C3_COUNT_INDIRECT_ENABLE(!!info->indirect_params));
738 radeon_emit(cs, info->indirect_count);
739 radeon_emit(cs, count_va);
740 radeon_emit(cs, count_va >> 32);
741 radeon_emit(cs, info->indirect_stride);
742 radeon_emit(cs, di_src_sel);
743 }
744 } else {
745 if (info->indexed) {
746 index_va += info->start * ib->index_size;
747
748 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
749 radeon_emit(cs, index_max_size);
750 radeon_emit(cs, index_va);
751 radeon_emit(cs, index_va >> 32);
752 radeon_emit(cs, info->count);
753 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
754 } else {
755 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
756 radeon_emit(cs, info->count);
757 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
758 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
759 }
760 }
761 }
762
763 static void si_emit_surface_sync(struct r600_common_context *rctx,
764 unsigned cp_coher_cntl)
765 {
766 struct radeon_winsys_cs *cs = rctx->gfx.cs;
767
768 if (rctx->chip_class >= GFX9) {
769 /* Flush caches and wait for the caches to assert idle. */
770 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
771 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
772 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
773 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
774 radeon_emit(cs, 0); /* CP_COHER_BASE */
775 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
776 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
777 } else {
778 /* ACQUIRE_MEM is only required on a compute ring. */
779 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
780 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
781 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
782 radeon_emit(cs, 0); /* CP_COHER_BASE */
783 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
784 }
785 }
786
787 void si_emit_cache_flush(struct si_context *sctx)
788 {
789 struct r600_common_context *rctx = &sctx->b;
790 struct radeon_winsys_cs *cs = rctx->gfx.cs;
791 uint32_t cp_coher_cntl = 0;
792 uint32_t flush_cb_db = rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
793 SI_CONTEXT_FLUSH_AND_INV_DB);
794
795 if (rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
796 SI_CONTEXT_FLUSH_AND_INV_DB))
797 sctx->b.num_fb_cache_flushes++;
798
799 /* SI has a bug that it always flushes ICACHE and KCACHE if either
800 * bit is set. An alternative way is to write SQC_CACHES, but that
801 * doesn't seem to work reliably. Since the bug doesn't affect
802 * correctness (it only does more work than necessary) and
803 * the performance impact is likely negligible, there is no plan
804 * to add a workaround for it.
805 */
806
807 if (rctx->flags & SI_CONTEXT_INV_ICACHE)
808 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
809 if (rctx->flags & SI_CONTEXT_INV_SMEM_L1)
810 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
811
812 if (rctx->chip_class <= VI) {
813 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
814 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
815 S_0085F0_CB0_DEST_BASE_ENA(1) |
816 S_0085F0_CB1_DEST_BASE_ENA(1) |
817 S_0085F0_CB2_DEST_BASE_ENA(1) |
818 S_0085F0_CB3_DEST_BASE_ENA(1) |
819 S_0085F0_CB4_DEST_BASE_ENA(1) |
820 S_0085F0_CB5_DEST_BASE_ENA(1) |
821 S_0085F0_CB6_DEST_BASE_ENA(1) |
822 S_0085F0_CB7_DEST_BASE_ENA(1);
823
824 /* Necessary for DCC */
825 if (rctx->chip_class == VI)
826 r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
827 0, 0, NULL, 0, 0, 0);
828 }
829 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB)
830 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
831 S_0085F0_DB_DEST_BASE_ENA(1);
832 }
833
834 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
835 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
836 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
837 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
838 }
839 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
840 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
841 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
842 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
843 }
844
845 /* Wait for shader engines to go idle.
846 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
847 * for everything including CB/DB cache flushes.
848 */
849 if (!flush_cb_db) {
850 if (rctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
851 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
852 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
853 /* Only count explicit shader flushes, not implicit ones
854 * done by SURFACE_SYNC.
855 */
856 rctx->num_vs_flushes++;
857 rctx->num_ps_flushes++;
858 } else if (rctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
859 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
860 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
861 rctx->num_vs_flushes++;
862 }
863 }
864
865 if (rctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
866 sctx->compute_is_busy) {
867 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
868 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
869 rctx->num_cs_flushes++;
870 sctx->compute_is_busy = false;
871 }
872
873 /* VGT state synchronization. */
874 if (rctx->flags & SI_CONTEXT_VGT_FLUSH) {
875 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
876 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
877 }
878 if (rctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
879 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
880 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
881 }
882
883 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
884 * wait for idle on GFX9. We have to use a TS event.
885 */
886 if (sctx->b.chip_class >= GFX9 && flush_cb_db) {
887 struct r600_resource *rbuf = NULL;
888 uint64_t va;
889 unsigned offset = 0, tc_flags, cb_db_event;
890
891 /* Set the CB/DB flush event. */
892 switch (flush_cb_db) {
893 case SI_CONTEXT_FLUSH_AND_INV_CB:
894 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
895 break;
896 case SI_CONTEXT_FLUSH_AND_INV_DB:
897 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
898 break;
899 default:
900 /* both CB & DB */
901 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
902 }
903
904 /* TC | TC_WB = invalidate L2 data
905 * TC_MD | TC_WB = invalidate L2 metadata
906 * TC | TC_WB | TC_MD = invalidate L2 data & metadata
907 *
908 * The metadata cache must always be invalidated for coherency
909 * between CB/DB and shaders. (metadata = HTILE, CMASK, DCC)
910 *
911 * TC must be invalidated on GFX9 only if the CB/DB surface is
912 * not pipe-aligned. If the surface is RB-aligned, it might not
913 * strictly be pipe-aligned since RB alignment takes precendence.
914 */
915 tc_flags = EVENT_TC_WB_ACTION_ENA |
916 EVENT_TC_MD_ACTION_ENA;
917
918 /* Ideally flush TC together with CB/DB. */
919 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
920 tc_flags |= EVENT_TC_ACTION_ENA |
921 EVENT_TCL1_ACTION_ENA;
922
923 /* Clear the flags. */
924 rctx->flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
925 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
926 SI_CONTEXT_INV_VMEM_L1);
927 }
928
929 /* Allocate memory for the fence. */
930 u_suballocator_alloc(rctx->allocator_zeroed_memory, 4, 4,
931 &offset, (struct pipe_resource**)&rbuf);
932 va = rbuf->gpu_address + offset;
933
934 r600_gfx_write_event_eop(rctx, cb_db_event, tc_flags, 1,
935 rbuf, va, 0, 1);
936 r600_gfx_wait_fence(rctx, va, 1, 0xffffffff);
937 }
938
939 /* Make sure ME is idle (it executes most packets) before continuing.
940 * This prevents read-after-write hazards between PFP and ME.
941 */
942 if (cp_coher_cntl ||
943 (rctx->flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
944 SI_CONTEXT_INV_VMEM_L1 |
945 SI_CONTEXT_INV_GLOBAL_L2 |
946 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
947 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
948 radeon_emit(cs, 0);
949 }
950
951 /* SI-CI-VI only:
952 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
953 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
954 *
955 * cp_coher_cntl should contain all necessary flags except TC flags
956 * at this point.
957 *
958 * SI-CIK don't support L2 write-back.
959 */
960 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2 ||
961 (rctx->chip_class <= CIK &&
962 (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
963 /* Invalidate L1 & L2. (L1 is always invalidated on SI)
964 * WB must be set on VI+ when TC_ACTION is set.
965 */
966 si_emit_surface_sync(rctx, cp_coher_cntl |
967 S_0085F0_TC_ACTION_ENA(1) |
968 S_0085F0_TCL1_ACTION_ENA(1) |
969 S_0301F0_TC_WB_ACTION_ENA(rctx->chip_class >= VI));
970 cp_coher_cntl = 0;
971 sctx->b.num_L2_invalidates++;
972 } else {
973 /* L1 invalidation and L2 writeback must be done separately,
974 * because both operations can't be done together.
975 */
976 if (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
977 /* WB = write-back
978 * NC = apply to non-coherent MTYPEs
979 * (i.e. MTYPE <= 1, which is what we use everywhere)
980 *
981 * WB doesn't work without NC.
982 */
983 si_emit_surface_sync(rctx, cp_coher_cntl |
984 S_0301F0_TC_WB_ACTION_ENA(1) |
985 S_0301F0_TC_NC_ACTION_ENA(1));
986 cp_coher_cntl = 0;
987 sctx->b.num_L2_writebacks++;
988 }
989 if (rctx->flags & SI_CONTEXT_INV_VMEM_L1) {
990 /* Invalidate per-CU VMEM L1. */
991 si_emit_surface_sync(rctx, cp_coher_cntl |
992 S_0085F0_TCL1_ACTION_ENA(1));
993 cp_coher_cntl = 0;
994 }
995 }
996
997 /* If TC flushes haven't cleared this... */
998 if (cp_coher_cntl)
999 si_emit_surface_sync(rctx, cp_coher_cntl);
1000
1001 if (rctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
1002 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1003 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1004 EVENT_INDEX(0));
1005 } else if (rctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
1006 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1007 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1008 EVENT_INDEX(0));
1009 }
1010
1011 rctx->flags = 0;
1012 }
1013
1014 static void si_get_draw_start_count(struct si_context *sctx,
1015 const struct pipe_draw_info *info,
1016 unsigned *start, unsigned *count)
1017 {
1018 if (info->indirect) {
1019 unsigned indirect_count;
1020 struct pipe_transfer *transfer;
1021 unsigned begin, end;
1022 unsigned map_size;
1023 unsigned *data;
1024
1025 if (info->indirect_params) {
1026 data = pipe_buffer_map_range(&sctx->b.b,
1027 info->indirect_params,
1028 info->indirect_params_offset,
1029 sizeof(unsigned),
1030 PIPE_TRANSFER_READ, &transfer);
1031
1032 indirect_count = *data;
1033
1034 pipe_buffer_unmap(&sctx->b.b, transfer);
1035 } else {
1036 indirect_count = info->indirect_count;
1037 }
1038
1039 if (!indirect_count) {
1040 *start = *count = 0;
1041 return;
1042 }
1043
1044 map_size = (indirect_count - 1) * info->indirect_stride + 3 * sizeof(unsigned);
1045 data = pipe_buffer_map_range(&sctx->b.b, info->indirect,
1046 info->indirect_offset, map_size,
1047 PIPE_TRANSFER_READ, &transfer);
1048
1049 begin = UINT_MAX;
1050 end = 0;
1051
1052 for (unsigned i = 0; i < indirect_count; ++i) {
1053 unsigned count = data[0];
1054 unsigned start = data[2];
1055
1056 if (count > 0) {
1057 begin = MIN2(begin, start);
1058 end = MAX2(end, start + count);
1059 }
1060
1061 data += info->indirect_stride / sizeof(unsigned);
1062 }
1063
1064 pipe_buffer_unmap(&sctx->b.b, transfer);
1065
1066 if (begin < end) {
1067 *start = begin;
1068 *count = end - begin;
1069 } else {
1070 *start = *count = 0;
1071 }
1072 } else {
1073 *start = info->start;
1074 *count = info->count;
1075 }
1076 }
1077
1078 void si_ce_pre_draw_synchronization(struct si_context *sctx)
1079 {
1080 if (sctx->ce_need_synchronization) {
1081 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
1082 radeon_emit(sctx->ce_ib, 1);
1083
1084 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
1085 radeon_emit(sctx->b.gfx.cs, 1);
1086 }
1087 }
1088
1089 void si_ce_post_draw_synchronization(struct si_context *sctx)
1090 {
1091 if (sctx->ce_need_synchronization) {
1092 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
1093 radeon_emit(sctx->b.gfx.cs, 0);
1094
1095 sctx->ce_need_synchronization = false;
1096 }
1097 }
1098
1099 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1100 {
1101 struct si_context *sctx = (struct si_context *)ctx;
1102 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1103 const struct pipe_index_buffer *ib = &sctx->index_buffer;
1104 struct pipe_index_buffer ib_tmp; /* for index buffer uploads only */
1105 unsigned mask, dirty_tex_counter;
1106 enum pipe_prim_type rast_prim;
1107 unsigned num_patches = 0;
1108
1109 if (likely(!info->indirect)) {
1110 /* SI-CI treat instance_count==0 as instance_count==1. There is
1111 * no workaround for indirect draws, but we can at least skip
1112 * direct draws.
1113 */
1114 if (unlikely(!info->instance_count))
1115 return;
1116
1117 /* Handle count == 0. */
1118 if (unlikely(!info->count &&
1119 (info->indexed || !info->count_from_stream_output)))
1120 return;
1121 }
1122
1123 if (unlikely(!sctx->vs_shader.cso)) {
1124 assert(0);
1125 return;
1126 }
1127 if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
1128 assert(0);
1129 return;
1130 }
1131 if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
1132 assert(0);
1133 return;
1134 }
1135
1136 /* Recompute and re-emit the texture resource states if needed. */
1137 dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_counter);
1138 if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_counter)) {
1139 sctx->b.last_dirty_tex_counter = dirty_tex_counter;
1140 sctx->framebuffer.dirty_cbufs |=
1141 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1142 sctx->framebuffer.dirty_zsbuf = true;
1143 sctx->framebuffer.do_update_surf_dirtiness = true;
1144 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
1145 si_update_all_texture_descriptors(sctx);
1146 }
1147
1148 si_decompress_graphics_textures(sctx);
1149
1150 /* Set the rasterization primitive type.
1151 *
1152 * This must be done after si_decompress_textures, which can call
1153 * draw_vbo recursively, and before si_update_shaders, which uses
1154 * current_rast_prim for this draw_vbo call. */
1155 if (sctx->gs_shader.cso)
1156 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1157 else if (sctx->tes_shader.cso)
1158 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1159 else
1160 rast_prim = info->mode;
1161
1162 if (rast_prim != sctx->current_rast_prim) {
1163 sctx->current_rast_prim = rast_prim;
1164 sctx->do_update_shaders = true;
1165 }
1166
1167 if (sctx->gs_shader.cso) {
1168 /* Determine whether the GS triangle strip adjacency fix should
1169 * be applied. Rotate every other triangle if
1170 * - triangle strips with adjacency are fed to the GS and
1171 * - primitive restart is disabled (the rotation doesn't help
1172 * when the restart occurs after an odd number of triangles).
1173 */
1174 bool gs_tri_strip_adj_fix =
1175 !sctx->tes_shader.cso &&
1176 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1177 !info->primitive_restart;
1178
1179 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1180 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1181 sctx->do_update_shaders = true;
1182 }
1183 }
1184
1185 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1186 return;
1187
1188 if (!si_upload_graphics_shader_descriptors(sctx))
1189 return;
1190
1191 ib_tmp.buffer = NULL;
1192
1193 if (info->indexed) {
1194 /* Translate or upload, if needed. */
1195 /* 8-bit indices are supported on VI. */
1196 if (sctx->b.chip_class <= CIK && ib->index_size == 1) {
1197 unsigned start, count, start_offset, size;
1198 void *ptr;
1199
1200 si_get_draw_start_count(sctx, info, &start, &count);
1201 start_offset = start * 2;
1202 size = count * 2;
1203
1204 u_upload_alloc(ctx->stream_uploader, start_offset,
1205 size,
1206 si_optimal_tcc_alignment(sctx, size),
1207 &ib_tmp.offset, &ib_tmp.buffer, &ptr);
1208 if (!ib_tmp.buffer)
1209 return;
1210
1211 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, ib, 0, 0,
1212 ib->offset + start,
1213 count, ptr);
1214
1215 /* info->start will be added by the drawing code */
1216 ib_tmp.offset -= start_offset;
1217 ib_tmp.index_size = 2;
1218 ib = &ib_tmp;
1219 } else if (ib->user_buffer && !ib->buffer) {
1220 unsigned start, count, start_offset;
1221
1222 si_get_draw_start_count(sctx, info, &start, &count);
1223 start_offset = start * ib->index_size;
1224
1225 u_upload_data(ctx->stream_uploader, start_offset,
1226 count * ib->index_size,
1227 sctx->screen->b.info.tcc_cache_line_size,
1228 (char*)ib->user_buffer + start_offset,
1229 &ib_tmp.offset, &ib_tmp.buffer);
1230 if (!ib_tmp.buffer)
1231 return;
1232
1233 /* info->start will be added by the drawing code */
1234 ib_tmp.offset -= start_offset;
1235 ib_tmp.index_size = ib->index_size;
1236 ib = &ib_tmp;
1237 } else if (sctx->b.chip_class <= CIK &&
1238 r600_resource(ib->buffer)->TC_L2_dirty) {
1239 /* VI reads index buffers through TC L2, so it doesn't
1240 * need this. */
1241 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1242 r600_resource(ib->buffer)->TC_L2_dirty = false;
1243 }
1244 }
1245
1246 if (info->indirect) {
1247 /* Add the buffer size for memory checking in need_cs_space. */
1248 r600_context_add_resource_size(ctx, info->indirect);
1249
1250 if (r600_resource(info->indirect)->TC_L2_dirty) {
1251 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1252 r600_resource(info->indirect)->TC_L2_dirty = false;
1253 }
1254
1255 if (info->indirect_params &&
1256 r600_resource(info->indirect_params)->TC_L2_dirty) {
1257 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1258 r600_resource(info->indirect_params)->TC_L2_dirty = false;
1259 }
1260 }
1261
1262 si_need_cs_space(sctx);
1263
1264 /* Since we've called r600_context_add_resource_size for vertex buffers,
1265 * this must be called after si_need_cs_space, because we must let
1266 * need_cs_space flush before we add buffers to the buffer list.
1267 */
1268 if (!si_upload_vertex_buffer_descriptors(sctx))
1269 return;
1270
1271 /* GFX9 scissor bug workaround. There is also a more efficient but
1272 * more involved alternative workaround. */
1273 if (sctx->b.chip_class == GFX9 &&
1274 si_is_atom_dirty(sctx, &sctx->b.scissors.atom))
1275 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
1276
1277 /* Flush caches before the first state atom, which does L2 prefetches. */
1278 if (sctx->b.flags)
1279 si_emit_cache_flush(sctx);
1280
1281 /* Emit state atoms. */
1282 mask = sctx->dirty_atoms;
1283 while (mask) {
1284 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
1285
1286 atom->emit(&sctx->b, atom);
1287 }
1288 sctx->dirty_atoms = 0;
1289
1290 /* Emit states. */
1291 mask = sctx->dirty_states;
1292 while (mask) {
1293 unsigned i = u_bit_scan(&mask);
1294 struct si_pm4_state *state = sctx->queued.array[i];
1295
1296 if (!state || sctx->emitted.array[i] == state)
1297 continue;
1298
1299 si_pm4_emit(sctx, state);
1300 sctx->emitted.array[i] = state;
1301 }
1302 sctx->dirty_states = 0;
1303
1304 si_emit_rasterizer_prim_state(sctx);
1305 if (sctx->tes_shader.cso)
1306 si_emit_derived_tess_state(sctx, info, &num_patches);
1307 si_emit_vs_state(sctx);
1308 si_emit_draw_registers(sctx, info, num_patches);
1309
1310 si_ce_pre_draw_synchronization(sctx);
1311 si_emit_draw_packets(sctx, info, ib);
1312 si_ce_post_draw_synchronization(sctx);
1313
1314 if (sctx->trace_buf)
1315 si_trace_emit(sctx);
1316
1317 /* Workaround for a VGT hang when streamout is enabled.
1318 * It must be done after drawing. */
1319 if ((sctx->b.family == CHIP_HAWAII ||
1320 sctx->b.family == CHIP_TONGA ||
1321 sctx->b.family == CHIP_FIJI) &&
1322 r600_get_strmout_en(&sctx->b)) {
1323 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1324 }
1325
1326 if (sctx->framebuffer.do_update_surf_dirtiness) {
1327 /* Set the depth buffer as dirty. */
1328 if (sctx->framebuffer.state.zsbuf) {
1329 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1330 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1331
1332 if (!rtex->tc_compatible_htile)
1333 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1334
1335 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1336 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
1337 }
1338 if (sctx->framebuffer.compressed_cb_mask) {
1339 struct pipe_surface *surf;
1340 struct r600_texture *rtex;
1341 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1342
1343 do {
1344 unsigned i = u_bit_scan(&mask);
1345 surf = sctx->framebuffer.state.cbufs[i];
1346 rtex = (struct r600_texture*)surf->texture;
1347
1348 if (rtex->fmask.size)
1349 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1350 if (rtex->dcc_gather_statistics)
1351 rtex->separate_dcc_dirty = true;
1352 } while (mask);
1353 }
1354 sctx->framebuffer.do_update_surf_dirtiness = false;
1355 }
1356
1357 pipe_resource_reference(&ib_tmp.buffer, NULL);
1358 sctx->b.num_draw_calls++;
1359 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1360 sctx->b.num_spill_draw_calls++;
1361 }
1362
1363 void si_trace_emit(struct si_context *sctx)
1364 {
1365 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1366
1367 sctx->trace_id++;
1368 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
1369 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
1370 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1371 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1372 S_370_WR_CONFIRM(1) |
1373 S_370_ENGINE_SEL(V_370_ME));
1374 radeon_emit(cs, sctx->trace_buf->gpu_address);
1375 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
1376 radeon_emit(cs, sctx->trace_id);
1377 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1378 radeon_emit(cs, AC_ENCODE_TRACE_POINT(sctx->trace_id));
1379 }