2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
29 #include "radeon/r600_cs.h"
31 /* For MSAA sample positions. */
32 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
33 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
34 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
35 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
36 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
39 * There are two locations (4, 4), (-4, -4). */
40 static const uint32_t sample_locs_2x
[4] = {
41 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
42 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
43 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
44 FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
47 * There are 4 locations: (-2, -6), (6, -2), (-6, 2), (2, 6). */
48 static const uint32_t sample_locs_4x
[4] = {
49 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
50 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
51 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
52 FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
56 static const uint32_t sample_locs_8x
[] = {
57 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
58 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
59 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
60 FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
61 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
62 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
63 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
64 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
67 static const uint32_t sample_locs_16x
[] = {
68 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
69 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
70 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
71 FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
72 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
73 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
74 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
75 FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
76 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
77 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
78 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
79 FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
80 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
81 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
82 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
83 FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
86 static void si_get_sample_position(struct pipe_context
*ctx
, unsigned sample_count
,
87 unsigned sample_index
, float *out_value
)
94 switch (sample_count
) {
97 out_value
[0] = out_value
[1] = 0.5;
100 offset
= 4 * (sample_index
* 2);
101 val
.idx
= (sample_locs_2x
[0] >> offset
) & 0xf;
102 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
103 val
.idx
= (sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
104 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
107 offset
= 4 * (sample_index
* 2);
108 val
.idx
= (sample_locs_4x
[0] >> offset
) & 0xf;
109 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
110 val
.idx
= (sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
111 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
114 offset
= 4 * (sample_index
% 4 * 2);
115 index
= (sample_index
/ 4) * 4;
116 val
.idx
= (sample_locs_8x
[index
] >> offset
) & 0xf;
117 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
118 val
.idx
= (sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
119 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
122 offset
= 4 * (sample_index
% 4 * 2);
123 index
= (sample_index
/ 4) * 4;
124 val
.idx
= (sample_locs_16x
[index
] >> offset
) & 0xf;
125 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
126 val
.idx
= (sample_locs_16x
[index
] >> (offset
+ 4)) & 0xf;
127 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
132 void si_emit_sample_locations(struct radeon_winsys_cs
*cs
, int nr_samples
)
134 switch (nr_samples
) {
137 radeon_set_context_reg(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 0);
138 radeon_set_context_reg(cs
, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, 0);
139 radeon_set_context_reg(cs
, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, 0);
140 radeon_set_context_reg(cs
, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, 0);
143 radeon_set_context_reg(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_2x
[0]);
144 radeon_set_context_reg(cs
, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_2x
[1]);
145 radeon_set_context_reg(cs
, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_2x
[2]);
146 radeon_set_context_reg(cs
, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_2x
[3]);
149 radeon_set_context_reg(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_4x
[0]);
150 radeon_set_context_reg(cs
, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_4x
[1]);
151 radeon_set_context_reg(cs
, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_4x
[2]);
152 radeon_set_context_reg(cs
, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_4x
[3]);
155 radeon_set_context_reg_seq(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 14);
156 radeon_emit(cs
, sample_locs_8x
[0]);
157 radeon_emit(cs
, sample_locs_8x
[4]);
160 radeon_emit(cs
, sample_locs_8x
[1]);
161 radeon_emit(cs
, sample_locs_8x
[5]);
164 radeon_emit(cs
, sample_locs_8x
[2]);
165 radeon_emit(cs
, sample_locs_8x
[6]);
168 radeon_emit(cs
, sample_locs_8x
[3]);
169 radeon_emit(cs
, sample_locs_8x
[7]);
172 radeon_set_context_reg_seq(cs
, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, 16);
173 radeon_emit(cs
, sample_locs_16x
[0]);
174 radeon_emit(cs
, sample_locs_16x
[4]);
175 radeon_emit(cs
, sample_locs_16x
[8]);
176 radeon_emit(cs
, sample_locs_16x
[12]);
177 radeon_emit(cs
, sample_locs_16x
[1]);
178 radeon_emit(cs
, sample_locs_16x
[5]);
179 radeon_emit(cs
, sample_locs_16x
[9]);
180 radeon_emit(cs
, sample_locs_16x
[13]);
181 radeon_emit(cs
, sample_locs_16x
[2]);
182 radeon_emit(cs
, sample_locs_16x
[6]);
183 radeon_emit(cs
, sample_locs_16x
[10]);
184 radeon_emit(cs
, sample_locs_16x
[14]);
185 radeon_emit(cs
, sample_locs_16x
[3]);
186 radeon_emit(cs
, sample_locs_16x
[7]);
187 radeon_emit(cs
, sample_locs_16x
[11]);
188 radeon_emit(cs
, sample_locs_16x
[15]);
193 void si_init_msaa_functions(struct si_context
*sctx
)
197 sctx
->b
.b
.get_sample_position
= si_get_sample_position
;
199 si_get_sample_position(&sctx
->b
.b
, 1, 0, sctx
->sample_locations_1x
[0]);
201 for (i
= 0; i
< 2; i
++)
202 si_get_sample_position(&sctx
->b
.b
, 2, i
, sctx
->sample_locations_2x
[i
]);
203 for (i
= 0; i
< 4; i
++)
204 si_get_sample_position(&sctx
->b
.b
, 4, i
, sctx
->sample_locations_4x
[i
]);
205 for (i
= 0; i
< 8; i
++)
206 si_get_sample_position(&sctx
->b
.b
, 8, i
, sctx
->sample_locations_8x
[i
]);
207 for (i
= 0; i
< 16; i
++)
208 si_get_sample_position(&sctx
->b
.b
, 16, i
, sctx
->sample_locations_16x
[i
]);