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radeonsi: calculate optimal GS ring sizes to fix GS hangs on Tonga
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/u_memory.h"
36 #include "util/u_prim.h"
37 #include "util/u_simple_shaders.h"
38
39 static void si_set_tesseval_regs(struct si_shader *shader,
40 struct si_pm4_state *pm4)
41 {
42 struct tgsi_shader_info *info = &shader->selector->info;
43 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
44 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
45 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
46 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
47 unsigned type, partitioning, topology;
48
49 switch (tes_prim_mode) {
50 case PIPE_PRIM_LINES:
51 type = V_028B6C_TESS_ISOLINE;
52 break;
53 case PIPE_PRIM_TRIANGLES:
54 type = V_028B6C_TESS_TRIANGLE;
55 break;
56 case PIPE_PRIM_QUADS:
57 type = V_028B6C_TESS_QUAD;
58 break;
59 default:
60 assert(0);
61 return;
62 }
63
64 switch (tes_spacing) {
65 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
66 partitioning = V_028B6C_PART_FRAC_ODD;
67 break;
68 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
69 partitioning = V_028B6C_PART_FRAC_EVEN;
70 break;
71 case PIPE_TESS_SPACING_EQUAL:
72 partitioning = V_028B6C_PART_INTEGER;
73 break;
74 default:
75 assert(0);
76 return;
77 }
78
79 if (tes_point_mode)
80 topology = V_028B6C_OUTPUT_POINT;
81 else if (tes_prim_mode == PIPE_PRIM_LINES)
82 topology = V_028B6C_OUTPUT_LINE;
83 else if (tes_vertex_order_cw)
84 /* for some reason, this must be the other way around */
85 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
86 else
87 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
88
89 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
90 S_028B6C_TYPE(type) |
91 S_028B6C_PARTITIONING(partitioning) |
92 S_028B6C_TOPOLOGY(topology));
93 }
94
95 static void si_shader_ls(struct si_shader *shader)
96 {
97 struct si_pm4_state *pm4;
98 unsigned num_sgprs, num_user_sgprs;
99 unsigned vgpr_comp_cnt;
100 uint64_t va;
101
102 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
103 if (pm4 == NULL)
104 return;
105
106 va = shader->bo->gpu_address;
107 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
108
109 /* We need at least 2 components for LS.
110 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
111 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 1;
112
113 num_user_sgprs = SI_LS_NUM_USER_SGPR;
114 num_sgprs = shader->num_sgprs;
115 if (num_user_sgprs > num_sgprs) {
116 /* Last 2 reserved SGPRs are used for VCC */
117 num_sgprs = num_user_sgprs + 2;
118 }
119 assert(num_sgprs <= 104);
120
121 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
122 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
123
124 shader->ls_rsrc1 = S_00B528_VGPRS((shader->num_vgprs - 1) / 4) |
125 S_00B528_SGPRS((num_sgprs - 1) / 8) |
126 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
127 S_00B528_DX10_CLAMP(shader->dx10_clamp_mode);
128 shader->ls_rsrc2 = S_00B52C_USER_SGPR(num_user_sgprs) |
129 S_00B52C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0);
130 }
131
132 static void si_shader_hs(struct si_shader *shader)
133 {
134 struct si_pm4_state *pm4;
135 unsigned num_sgprs, num_user_sgprs;
136 uint64_t va;
137
138 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
139 if (pm4 == NULL)
140 return;
141
142 va = shader->bo->gpu_address;
143 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
144
145 num_user_sgprs = SI_TCS_NUM_USER_SGPR;
146 num_sgprs = shader->num_sgprs;
147 /* One SGPR after user SGPRs is pre-loaded with tessellation factor
148 * buffer offset. */
149 if ((num_user_sgprs + 1) > num_sgprs) {
150 /* Last 2 reserved SGPRs are used for VCC */
151 num_sgprs = num_user_sgprs + 1 + 2;
152 }
153 assert(num_sgprs <= 104);
154
155 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
156 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
157 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
158 S_00B428_VGPRS((shader->num_vgprs - 1) / 4) |
159 S_00B428_SGPRS((num_sgprs - 1) / 8) |
160 S_00B428_DX10_CLAMP(shader->dx10_clamp_mode));
161 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
162 S_00B42C_USER_SGPR(num_user_sgprs) |
163 S_00B42C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
164 }
165
166 static void si_shader_es(struct si_shader *shader)
167 {
168 struct si_pm4_state *pm4;
169 unsigned num_sgprs, num_user_sgprs;
170 unsigned vgpr_comp_cnt;
171 uint64_t va;
172
173 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
174
175 if (pm4 == NULL)
176 return;
177
178 va = shader->bo->gpu_address;
179 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
180
181 if (shader->selector->type == PIPE_SHADER_VERTEX) {
182 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
183 num_user_sgprs = SI_ES_NUM_USER_SGPR;
184 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
185 vgpr_comp_cnt = 3; /* all components are needed for TES */
186 num_user_sgprs = SI_TES_NUM_USER_SGPR;
187 } else
188 unreachable("invalid shader selector type");
189
190 num_sgprs = shader->num_sgprs;
191 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
192 if ((num_user_sgprs + 1) > num_sgprs) {
193 /* Last 2 reserved SGPRs are used for VCC */
194 num_sgprs = num_user_sgprs + 1 + 2;
195 }
196 assert(num_sgprs <= 104);
197
198 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
199 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
200 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
201 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
202 S_00B328_SGPRS((num_sgprs - 1) / 8) |
203 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
204 S_00B328_DX10_CLAMP(shader->dx10_clamp_mode));
205 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
206 S_00B32C_USER_SGPR(num_user_sgprs) |
207 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
208
209 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
210 si_set_tesseval_regs(shader, pm4);
211 }
212
213 static void si_shader_gs(struct si_shader *shader)
214 {
215 unsigned gs_vert_itemsize = shader->selector->gsvs_vertex_size;
216 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
217 unsigned gsvs_itemsize = shader->selector->max_gsvs_emit_size >> 2;
218 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
219 unsigned cut_mode;
220 struct si_pm4_state *pm4;
221 unsigned num_sgprs, num_user_sgprs;
222 uint64_t va;
223 unsigned max_stream = shader->selector->max_gs_stream;
224
225 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
226 assert(gsvs_itemsize < (1 << 15));
227
228 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
229
230 if (pm4 == NULL)
231 return;
232
233 if (gs_max_vert_out <= 128) {
234 cut_mode = V_028A40_GS_CUT_128;
235 } else if (gs_max_vert_out <= 256) {
236 cut_mode = V_028A40_GS_CUT_256;
237 } else if (gs_max_vert_out <= 512) {
238 cut_mode = V_028A40_GS_CUT_512;
239 } else {
240 assert(gs_max_vert_out <= 1024);
241 cut_mode = V_028A40_GS_CUT_1024;
242 }
243
244 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
245 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
246 S_028A40_CUT_MODE(cut_mode)|
247 S_028A40_ES_WRITE_OPTIMIZE(1) |
248 S_028A40_GS_WRITE_OPTIMIZE(1));
249
250 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
251 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
252 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
253
254 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
255 shader->selector->esgs_itemsize / 4);
256 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
257
258 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
259
260 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
261 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
262 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
263 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
264
265 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
266 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
267 S_028B90_ENABLE(gs_num_invocations > 0));
268
269 va = shader->bo->gpu_address;
270 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
271 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
272 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
273
274 num_user_sgprs = SI_GS_NUM_USER_SGPR;
275 num_sgprs = shader->num_sgprs;
276 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
277 if ((num_user_sgprs + 2) > num_sgprs) {
278 /* Last 2 reserved SGPRs are used for VCC */
279 num_sgprs = num_user_sgprs + 2 + 2;
280 }
281 assert(num_sgprs <= 104);
282
283 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
284 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
285 S_00B228_SGPRS((num_sgprs - 1) / 8) |
286 S_00B228_DX10_CLAMP(shader->dx10_clamp_mode));
287 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
288 S_00B22C_USER_SGPR(num_user_sgprs) |
289 S_00B22C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
290 }
291
292 static void si_shader_vs(struct si_shader *shader)
293 {
294 struct si_pm4_state *pm4;
295 unsigned num_sgprs, num_user_sgprs;
296 unsigned nparams, vgpr_comp_cnt;
297 uint64_t va;
298 unsigned window_space =
299 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
300 bool enable_prim_id = si_vs_exports_prim_id(shader);
301
302 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
303
304 if (pm4 == NULL)
305 return;
306
307 /* If this is the GS copy shader, the GS state writes this register.
308 * Otherwise, the VS state writes it.
309 */
310 if (!shader->is_gs_copy_shader) {
311 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
312 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
313 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
314 } else
315 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
316
317 va = shader->bo->gpu_address;
318 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
319
320 if (shader->is_gs_copy_shader) {
321 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
322 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
323 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
324 vgpr_comp_cnt = shader->uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
325 num_user_sgprs = SI_VS_NUM_USER_SGPR;
326 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
327 vgpr_comp_cnt = 3; /* all components are needed for TES */
328 num_user_sgprs = SI_TES_NUM_USER_SGPR;
329 } else
330 unreachable("invalid shader selector type");
331
332 num_sgprs = shader->num_sgprs;
333 if (num_user_sgprs > num_sgprs) {
334 /* Last 2 reserved SGPRs are used for VCC */
335 num_sgprs = num_user_sgprs + 2;
336 }
337 assert(num_sgprs <= 104);
338
339 /* VS is required to export at least one param. */
340 nparams = MAX2(shader->nr_param_exports, 1);
341 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
342 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
343
344 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
345 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
346 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
347 V_02870C_SPI_SHADER_4COMP :
348 V_02870C_SPI_SHADER_NONE) |
349 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
350 V_02870C_SPI_SHADER_4COMP :
351 V_02870C_SPI_SHADER_NONE) |
352 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
353 V_02870C_SPI_SHADER_4COMP :
354 V_02870C_SPI_SHADER_NONE));
355
356 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
357 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
358 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
359 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
360 S_00B128_SGPRS((num_sgprs - 1) / 8) |
361 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
362 S_00B128_DX10_CLAMP(shader->dx10_clamp_mode));
363 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
364 S_00B12C_USER_SGPR(num_user_sgprs) |
365 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
366 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
367 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
368 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
369 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
370 S_00B12C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
371 if (window_space)
372 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
373 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
374 else
375 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
376 S_028818_VTX_W0_FMT(1) |
377 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
378 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
379 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
380
381 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
382 si_set_tesseval_regs(shader, pm4);
383 }
384
385 static void si_shader_ps(struct si_shader *shader)
386 {
387 struct tgsi_shader_info *info = &shader->selector->info;
388 struct si_pm4_state *pm4;
389 unsigned i, spi_ps_in_control;
390 unsigned num_sgprs, num_user_sgprs;
391 unsigned spi_baryc_cntl = 0;
392 uint64_t va;
393 bool has_centroid;
394
395 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
396
397 if (pm4 == NULL)
398 return;
399
400 for (i = 0; i < info->num_inputs; i++) {
401 switch (info->input_semantic_name[i]) {
402 case TGSI_SEMANTIC_POSITION:
403 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
404 * Possible vaules:
405 * 0 -> Position = pixel center (default)
406 * 1 -> Position = pixel centroid
407 * 2 -> Position = at sample position
408 */
409 switch (info->input_interpolate_loc[i]) {
410 case TGSI_INTERPOLATE_LOC_CENTROID:
411 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
412 break;
413 case TGSI_INTERPOLATE_LOC_SAMPLE:
414 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
415 break;
416 }
417
418 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
419 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
420 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
421 break;
422 }
423 }
424
425 has_centroid = G_0286CC_PERSP_CENTROID_ENA(shader->spi_ps_input_ena) ||
426 G_0286CC_LINEAR_CENTROID_ENA(shader->spi_ps_input_ena);
427
428 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
429 S_0286D8_BC_OPTIMIZE_DISABLE(has_centroid);
430
431 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
432 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
433
434 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
435 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
436 shader->spi_shader_col_format);
437 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
438
439 va = shader->bo->gpu_address;
440 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
441 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
442 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
443
444 num_user_sgprs = SI_PS_NUM_USER_SGPR;
445 num_sgprs = shader->num_sgprs;
446 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
447 if ((num_user_sgprs + 1) > num_sgprs) {
448 /* Last 2 reserved SGPRs are used for VCC */
449 num_sgprs = num_user_sgprs + 1 + 2;
450 }
451 assert(num_sgprs <= 104);
452
453 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
454 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
455 S_00B028_SGPRS((num_sgprs - 1) / 8) |
456 S_00B028_DX10_CLAMP(shader->dx10_clamp_mode));
457 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
458 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
459 S_00B02C_USER_SGPR(num_user_sgprs) |
460 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
461 }
462
463 static void si_shader_init_pm4_state(struct si_shader *shader)
464 {
465
466 if (shader->pm4)
467 si_pm4_free_state_simple(shader->pm4);
468
469 switch (shader->selector->type) {
470 case PIPE_SHADER_VERTEX:
471 if (shader->key.vs.as_ls)
472 si_shader_ls(shader);
473 else if (shader->key.vs.as_es)
474 si_shader_es(shader);
475 else
476 si_shader_vs(shader);
477 break;
478 case PIPE_SHADER_TESS_CTRL:
479 si_shader_hs(shader);
480 break;
481 case PIPE_SHADER_TESS_EVAL:
482 if (shader->key.tes.as_es)
483 si_shader_es(shader);
484 else
485 si_shader_vs(shader);
486 break;
487 case PIPE_SHADER_GEOMETRY:
488 si_shader_gs(shader);
489 si_shader_vs(shader->gs_copy_shader);
490 break;
491 case PIPE_SHADER_FRAGMENT:
492 si_shader_ps(shader);
493 break;
494 default:
495 assert(0);
496 }
497 }
498
499 /* Compute the key for the hw shader variant */
500 static inline void si_shader_selector_key(struct pipe_context *ctx,
501 struct si_shader_selector *sel,
502 union si_shader_key *key)
503 {
504 struct si_context *sctx = (struct si_context *)ctx;
505 unsigned i;
506
507 memset(key, 0, sizeof(*key));
508
509 switch (sel->type) {
510 case PIPE_SHADER_VERTEX:
511 if (sctx->vertex_elements)
512 for (i = 0; i < sctx->vertex_elements->count; ++i)
513 key->vs.instance_divisors[i] =
514 sctx->vertex_elements->elements[i].instance_divisor;
515
516 if (sctx->tes_shader.cso)
517 key->vs.as_ls = 1;
518 else if (sctx->gs_shader.cso) {
519 key->vs.as_es = 1;
520 key->vs.es_enabled_outputs = sctx->gs_shader.cso->inputs_read;
521 }
522
523 if (!sctx->gs_shader.cso && sctx->ps_shader.cso &&
524 sctx->ps_shader.cso->info.uses_primid)
525 key->vs.export_prim_id = 1;
526 break;
527 case PIPE_SHADER_TESS_CTRL:
528 key->tcs.prim_mode =
529 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
530 break;
531 case PIPE_SHADER_TESS_EVAL:
532 if (sctx->gs_shader.cso) {
533 key->tes.as_es = 1;
534 key->tes.es_enabled_outputs = sctx->gs_shader.cso->inputs_read;
535 } else if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
536 key->tes.export_prim_id = 1;
537 break;
538 case PIPE_SHADER_GEOMETRY:
539 break;
540 case PIPE_SHADER_FRAGMENT: {
541 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
542
543 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
544 key->ps.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
545 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
546
547 if (rs) {
548 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
549 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
550 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
551 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
552
553 key->ps.color_two_side = rs->two_side;
554
555 if (sctx->queued.named.blend) {
556 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
557 rs->multisample_enable &&
558 !sctx->framebuffer.cb0_is_integer;
559 }
560
561 key->ps.poly_stipple = rs->poly_stipple_enable && is_poly;
562 key->ps.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
563 (is_line && rs->line_smooth)) &&
564 sctx->framebuffer.nr_samples <= 1;
565 key->ps.clamp_color = rs->clamp_fragment_color;
566 }
567
568 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
569 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
570 if (sctx->queued.named.dsa &&
571 !sctx->framebuffer.cb0_is_integer)
572 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
573 break;
574 }
575 default:
576 assert(0);
577 }
578 }
579
580 /* Select the hw shader variant depending on the current state. */
581 static int si_shader_select(struct pipe_context *ctx,
582 struct si_shader_ctx_state *state)
583 {
584 struct si_context *sctx = (struct si_context *)ctx;
585 struct si_shader_selector *sel = state->cso;
586 struct si_shader *current = state->current;
587 union si_shader_key key;
588 struct si_shader *iter, *shader = NULL;
589 int r;
590
591 si_shader_selector_key(ctx, sel, &key);
592
593 /* Check if we don't need to change anything.
594 * This path is also used for most shaders that don't need multiple
595 * variants, it will cost just a computation of the key and this
596 * test. */
597 if (likely(current && memcmp(&current->key, &key, sizeof(key)) == 0))
598 return 0;
599
600 pipe_mutex_lock(sel->mutex);
601
602 /* Find the shader variant. */
603 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
604 /* Don't check the "current" shader. We checked it above. */
605 if (current != iter &&
606 memcmp(&iter->key, &key, sizeof(key)) == 0) {
607 state->current = iter;
608 pipe_mutex_unlock(sel->mutex);
609 return 0;
610 }
611 }
612
613 /* Build a new shader. */
614 shader = CALLOC_STRUCT(si_shader);
615 if (!shader) {
616 pipe_mutex_unlock(sel->mutex);
617 return -ENOMEM;
618 }
619 shader->selector = sel;
620 shader->key = key;
621
622 r = si_shader_create(sctx->screen, sctx->tm, shader);
623 if (unlikely(r)) {
624 R600_ERR("Failed to build shader variant (type=%u) %d\n",
625 sel->type, r);
626 FREE(shader);
627 pipe_mutex_unlock(sel->mutex);
628 return r;
629 }
630 si_shader_init_pm4_state(shader);
631
632 if (!sel->last_variant) {
633 sel->first_variant = shader;
634 sel->last_variant = shader;
635 } else {
636 sel->last_variant->next_variant = shader;
637 sel->last_variant = shader;
638 }
639 state->current = shader;
640 p_atomic_inc(&sctx->screen->b.num_compilations);
641 pipe_mutex_unlock(sel->mutex);
642 return 0;
643 }
644
645 static void *si_create_shader_selector(struct pipe_context *ctx,
646 const struct pipe_shader_state *state)
647 {
648 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
649 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
650 int i;
651
652 if (!sel)
653 return NULL;
654
655 sel->tokens = tgsi_dup_tokens(state->tokens);
656 if (!sel->tokens) {
657 FREE(sel);
658 return NULL;
659 }
660
661 sel->so = state->stream_output;
662 tgsi_scan_shader(state->tokens, &sel->info);
663 sel->type = util_pipe_shader_from_tgsi_processor(sel->info.processor);
664 p_atomic_inc(&sscreen->b.num_shaders_created);
665
666 /* First set which opcode uses which (i,j) pair. */
667 if (sel->info.uses_persp_opcode_interp_centroid)
668 sel->info.uses_persp_centroid = true;
669
670 if (sel->info.uses_linear_opcode_interp_centroid)
671 sel->info.uses_linear_centroid = true;
672
673 if (sel->info.uses_persp_opcode_interp_offset ||
674 sel->info.uses_persp_opcode_interp_sample)
675 sel->info.uses_persp_center = true;
676
677 if (sel->info.uses_linear_opcode_interp_offset ||
678 sel->info.uses_linear_opcode_interp_sample)
679 sel->info.uses_linear_center = true;
680
681 /* Determine if the shader has to use a conditional assignment when
682 * emulating force_persample_interp.
683 */
684 sel->forces_persample_interp_for_persp =
685 sel->info.uses_persp_center +
686 sel->info.uses_persp_centroid +
687 sel->info.uses_persp_sample >= 2;
688
689 sel->forces_persample_interp_for_linear =
690 sel->info.uses_linear_center +
691 sel->info.uses_linear_centroid +
692 sel->info.uses_linear_sample >= 2;
693
694 switch (sel->type) {
695 case PIPE_SHADER_GEOMETRY:
696 sel->gs_output_prim =
697 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
698 sel->gs_max_out_vertices =
699 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
700 sel->gs_num_invocations =
701 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
702 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
703 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
704 sel->gs_max_out_vertices;
705
706 sel->max_gs_stream = 0;
707 for (i = 0; i < sel->so.num_outputs; i++)
708 sel->max_gs_stream = MAX2(sel->max_gs_stream,
709 sel->so.output[i].stream);
710
711 sel->gs_input_verts_per_prim =
712 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
713
714 for (i = 0; i < sel->info.num_inputs; i++) {
715 unsigned name = sel->info.input_semantic_name[i];
716 unsigned index = sel->info.input_semantic_index[i];
717
718 switch (name) {
719 case TGSI_SEMANTIC_PRIMID:
720 break;
721 default:
722 sel->inputs_read |=
723 1llu << si_shader_io_get_unique_index(name, index);
724 }
725 }
726 break;
727
728 case PIPE_SHADER_VERTEX:
729 case PIPE_SHADER_TESS_CTRL:
730 case PIPE_SHADER_TESS_EVAL:
731 for (i = 0; i < sel->info.num_outputs; i++) {
732 unsigned name = sel->info.output_semantic_name[i];
733 unsigned index = sel->info.output_semantic_index[i];
734
735 switch (name) {
736 case TGSI_SEMANTIC_TESSINNER:
737 case TGSI_SEMANTIC_TESSOUTER:
738 case TGSI_SEMANTIC_PATCH:
739 sel->patch_outputs_written |=
740 1llu << si_shader_io_get_unique_index(name, index);
741 break;
742 default:
743 sel->outputs_written |=
744 1llu << si_shader_io_get_unique_index(name, index);
745 }
746 }
747 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
748 break;
749 case PIPE_SHADER_FRAGMENT:
750 for (i = 0; i < sel->info.num_outputs; i++) {
751 unsigned name = sel->info.output_semantic_name[i];
752 unsigned index = sel->info.output_semantic_index[i];
753
754 if (name == TGSI_SEMANTIC_COLOR)
755 sel->ps_colors_written |= 1 << index;
756 }
757 break;
758 }
759
760 if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
761 struct si_shader_ctx_state state = {sel};
762
763 if (si_shader_select(ctx, &state)) {
764 fprintf(stderr, "radeonsi: can't create a shader\n");
765 tgsi_free_tokens(sel->tokens);
766 FREE(sel);
767 return NULL;
768 }
769 }
770
771 pipe_mutex_init(sel->mutex);
772 return sel;
773 }
774
775 /**
776 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
777 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
778 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
779 * called to emit the rest.
780 */
781 static void si_update_viewports_and_scissors(struct si_context *sctx)
782 {
783 struct tgsi_shader_info *info = si_get_vs_info(sctx);
784
785 if (!info || !info->writes_viewport_index)
786 return;
787
788 if (sctx->scissors.dirty_mask)
789 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
790 if (sctx->viewports.dirty_mask)
791 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
792 }
793
794 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
795 {
796 struct si_context *sctx = (struct si_context *)ctx;
797 struct si_shader_selector *sel = state;
798
799 if (sctx->vs_shader.cso == sel)
800 return;
801
802 sctx->vs_shader.cso = sel;
803 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
804 si_mark_atom_dirty(sctx, &sctx->clip_regs);
805 si_update_viewports_and_scissors(sctx);
806 }
807
808 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
809 {
810 struct si_context *sctx = (struct si_context *)ctx;
811 struct si_shader_selector *sel = state;
812 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
813
814 if (sctx->gs_shader.cso == sel)
815 return;
816
817 sctx->gs_shader.cso = sel;
818 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
819 si_mark_atom_dirty(sctx, &sctx->clip_regs);
820 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
821
822 if (enable_changed)
823 si_shader_change_notify(sctx);
824 si_update_viewports_and_scissors(sctx);
825 }
826
827 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
828 {
829 struct si_context *sctx = (struct si_context *)ctx;
830 struct si_shader_selector *sel = state;
831 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
832
833 if (sctx->tcs_shader.cso == sel)
834 return;
835
836 sctx->tcs_shader.cso = sel;
837 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
838
839 if (enable_changed)
840 sctx->last_tcs = NULL; /* invalidate derived tess state */
841 }
842
843 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
844 {
845 struct si_context *sctx = (struct si_context *)ctx;
846 struct si_shader_selector *sel = state;
847 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
848
849 if (sctx->tes_shader.cso == sel)
850 return;
851
852 sctx->tes_shader.cso = sel;
853 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
854 si_mark_atom_dirty(sctx, &sctx->clip_regs);
855 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
856
857 if (enable_changed) {
858 si_shader_change_notify(sctx);
859 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
860 }
861 si_update_viewports_and_scissors(sctx);
862 }
863
864 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
865 {
866 struct si_context *sctx = (struct si_context *)ctx;
867 struct si_shader_selector *sel = state;
868
869 /* skip if supplied shader is one already in use */
870 if (sctx->ps_shader.cso == sel)
871 return;
872
873 sctx->ps_shader.cso = sel;
874 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
875 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
876 }
877
878 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
879 {
880 struct si_context *sctx = (struct si_context *)ctx;
881 struct si_shader_selector *sel = (struct si_shader_selector *)state;
882 struct si_shader *p = sel->first_variant, *c;
883 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
884 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
885 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
886 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
887 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
888 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
889 };
890
891 if (current_shader[sel->type]->cso == sel) {
892 current_shader[sel->type]->cso = NULL;
893 current_shader[sel->type]->current = NULL;
894 }
895
896 while (p) {
897 c = p->next_variant;
898 switch (sel->type) {
899 case PIPE_SHADER_VERTEX:
900 if (p->key.vs.as_ls)
901 si_pm4_delete_state(sctx, ls, p->pm4);
902 else if (p->key.vs.as_es)
903 si_pm4_delete_state(sctx, es, p->pm4);
904 else
905 si_pm4_delete_state(sctx, vs, p->pm4);
906 break;
907 case PIPE_SHADER_TESS_CTRL:
908 si_pm4_delete_state(sctx, hs, p->pm4);
909 break;
910 case PIPE_SHADER_TESS_EVAL:
911 if (p->key.tes.as_es)
912 si_pm4_delete_state(sctx, es, p->pm4);
913 else
914 si_pm4_delete_state(sctx, vs, p->pm4);
915 break;
916 case PIPE_SHADER_GEOMETRY:
917 si_pm4_delete_state(sctx, gs, p->pm4);
918 si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
919 break;
920 case PIPE_SHADER_FRAGMENT:
921 si_pm4_delete_state(sctx, ps, p->pm4);
922 break;
923 }
924
925 si_shader_destroy(p);
926 free(p);
927 p = c;
928 }
929
930 pipe_mutex_destroy(sel->mutex);
931 free(sel->tokens);
932 free(sel);
933 }
934
935 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
936 {
937 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
938 struct si_shader *ps = sctx->ps_shader.current;
939 struct si_shader *vs = si_get_vs_state(sctx);
940 struct tgsi_shader_info *psinfo;
941 struct tgsi_shader_info *vsinfo = &vs->selector->info;
942 unsigned i, j, tmp, num_written = 0;
943
944 if (!ps || !ps->nparam)
945 return;
946
947 psinfo = &ps->selector->info;
948
949 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps->nparam);
950
951 for (i = 0; i < psinfo->num_inputs; i++) {
952 unsigned name = psinfo->input_semantic_name[i];
953 unsigned index = psinfo->input_semantic_index[i];
954 unsigned interpolate = psinfo->input_interpolate[i];
955 unsigned param_offset = ps->ps_input_param_offset[i];
956
957 if (name == TGSI_SEMANTIC_POSITION ||
958 name == TGSI_SEMANTIC_FACE)
959 /* Read from preloaded VGPRs, not parameters */
960 continue;
961
962 bcolor:
963 tmp = 0;
964
965 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
966 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
967 tmp |= S_028644_FLAT_SHADE(1);
968
969 if (name == TGSI_SEMANTIC_PCOORD ||
970 (name == TGSI_SEMANTIC_TEXCOORD &&
971 sctx->sprite_coord_enable & (1 << index))) {
972 tmp |= S_028644_PT_SPRITE_TEX(1);
973 }
974
975 for (j = 0; j < vsinfo->num_outputs; j++) {
976 if (name == vsinfo->output_semantic_name[j] &&
977 index == vsinfo->output_semantic_index[j]) {
978 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
979 break;
980 }
981 }
982
983 if (name == TGSI_SEMANTIC_PRIMID)
984 /* PrimID is written after the last output. */
985 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[vsinfo->num_outputs]);
986 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(tmp)) {
987 /* No corresponding output found, load defaults into input.
988 * Don't set any other bits.
989 * (FLAT_SHADE=1 completely changes behavior) */
990 tmp = S_028644_OFFSET(0x20);
991 }
992
993 assert(param_offset == num_written);
994 radeon_emit(cs, tmp);
995 num_written++;
996
997 if (name == TGSI_SEMANTIC_COLOR &&
998 ps->key.ps.color_two_side) {
999 name = TGSI_SEMANTIC_BCOLOR;
1000 param_offset++;
1001 goto bcolor;
1002 }
1003 }
1004 assert(ps->nparam == num_written);
1005 }
1006
1007 static void si_emit_spi_ps_input(struct si_context *sctx, struct r600_atom *atom)
1008 {
1009 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1010 struct si_shader *ps = sctx->ps_shader.current;
1011 unsigned input_ena;
1012
1013 if (!ps)
1014 return;
1015
1016 input_ena = ps->spi_ps_input_ena;
1017
1018 /* we need to enable at least one of them, otherwise we hang the GPU */
1019 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1020 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1021 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1022 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1023 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1024 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1025 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1026 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1027
1028 if (sctx->force_persample_interp) {
1029 unsigned num_persp = G_0286CC_PERSP_SAMPLE_ENA(input_ena) +
1030 G_0286CC_PERSP_CENTER_ENA(input_ena) +
1031 G_0286CC_PERSP_CENTROID_ENA(input_ena);
1032 unsigned num_linear = G_0286CC_LINEAR_SAMPLE_ENA(input_ena) +
1033 G_0286CC_LINEAR_CENTER_ENA(input_ena) +
1034 G_0286CC_LINEAR_CENTROID_ENA(input_ena);
1035
1036 /* If only one set of (i,j) coordinates is used, we can disable
1037 * CENTER/CENTROID, enable SAMPLE and it will load SAMPLE coordinates
1038 * where CENTER/CENTROID are expected, effectively forcing per-sample
1039 * interpolation.
1040 */
1041 if (num_persp == 1) {
1042 input_ena &= C_0286CC_PERSP_CENTER_ENA;
1043 input_ena &= C_0286CC_PERSP_CENTROID_ENA;
1044 input_ena |= G_0286CC_PERSP_SAMPLE_ENA(1);
1045 }
1046 if (num_linear == 1) {
1047 input_ena &= C_0286CC_LINEAR_CENTER_ENA;
1048 input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
1049 input_ena |= G_0286CC_LINEAR_SAMPLE_ENA(1);
1050 }
1051
1052 /* If at least 2 sets of coordinates are used, we can't use this
1053 * trick and have to select SAMPLE using a conditional assignment
1054 * in the shader with "force_persample_interp" being a shader constant.
1055 */
1056 }
1057
1058 radeon_set_context_reg_seq(cs, R_0286CC_SPI_PS_INPUT_ENA, 2);
1059 radeon_emit(cs, input_ena);
1060 radeon_emit(cs, input_ena);
1061
1062 if (ps->selector->forces_persample_interp_for_persp ||
1063 ps->selector->forces_persample_interp_for_linear)
1064 radeon_set_sh_reg(cs, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1065 SI_SGPR_PS_STATE_BITS * 4,
1066 sctx->force_persample_interp);
1067 }
1068
1069 /**
1070 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1071 */
1072 static void si_init_config_add_vgt_flush(struct si_context *sctx)
1073 {
1074 if (sctx->init_config_has_vgt_flush)
1075 return;
1076
1077 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1078 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1079 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1080 si_pm4_cmd_end(sctx->init_config, false);
1081 sctx->init_config_has_vgt_flush = true;
1082 }
1083
1084 /* Initialize state related to ESGS / GSVS ring buffers */
1085 static bool si_update_gs_ring_buffers(struct si_context *sctx)
1086 {
1087 struct si_shader_selector *es =
1088 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
1089 struct si_shader_selector *gs = sctx->gs_shader.cso;
1090 struct si_pm4_state *pm4;
1091
1092 /* Chip constants. */
1093 unsigned num_se = sctx->screen->b.info.max_se;
1094 unsigned wave_size = 64;
1095 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1096 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1097 unsigned alignment = 256 * num_se;
1098 /* The maximum size is 63.999 MB per SE. */
1099 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1100
1101 /* Calculate the minimum size. */
1102 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
1103 wave_size, alignment);
1104
1105 /* These are recommended sizes, not minimum sizes. */
1106 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1107 es->esgs_itemsize * gs->gs_input_verts_per_prim;
1108 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1109 gs->max_gsvs_emit_size * (gs->max_gs_stream + 1);
1110
1111 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1112 esgs_ring_size = align(esgs_ring_size, alignment);
1113 gsvs_ring_size = align(gsvs_ring_size, alignment);
1114
1115 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1116 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1117
1118 /* Some rings don't have to be allocated if shaders don't use them.
1119 * (e.g. no varyings between ES and GS or GS and VS)
1120 */
1121 bool update_esgs = esgs_ring_size &&
1122 (!sctx->esgs_ring ||
1123 sctx->esgs_ring->width0 < esgs_ring_size);
1124 bool update_gsvs = gsvs_ring_size &&
1125 (!sctx->gsvs_ring ||
1126 sctx->gsvs_ring->width0 < gsvs_ring_size);
1127
1128 if (!update_esgs && !update_gsvs)
1129 return true;
1130
1131 if (update_esgs) {
1132 pipe_resource_reference(&sctx->esgs_ring, NULL);
1133 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1134 PIPE_USAGE_DEFAULT,
1135 esgs_ring_size);
1136 if (!sctx->esgs_ring)
1137 return false;
1138 }
1139
1140 if (update_gsvs) {
1141 pipe_resource_reference(&sctx->gsvs_ring, NULL);
1142 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1143 PIPE_USAGE_DEFAULT,
1144 gsvs_ring_size);
1145 if (!sctx->gsvs_ring)
1146 return false;
1147 }
1148
1149 /* Create the "init_config_gs_rings" state. */
1150 pm4 = CALLOC_STRUCT(si_pm4_state);
1151 if (!pm4)
1152 return false;
1153
1154 if (sctx->b.chip_class >= CIK) {
1155 if (sctx->esgs_ring)
1156 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
1157 sctx->esgs_ring->width0 / 256);
1158 if (sctx->gsvs_ring)
1159 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
1160 sctx->gsvs_ring->width0 / 256);
1161 } else {
1162 if (sctx->esgs_ring)
1163 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
1164 sctx->esgs_ring->width0 / 256);
1165 if (sctx->gsvs_ring)
1166 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
1167 sctx->gsvs_ring->width0 / 256);
1168 }
1169
1170 /* Set the state. */
1171 if (sctx->init_config_gs_rings)
1172 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
1173 sctx->init_config_gs_rings = pm4;
1174
1175 if (!sctx->init_config_has_vgt_flush) {
1176 si_init_config_add_vgt_flush(sctx);
1177 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1178 }
1179
1180 /* Flush the context to re-emit both init_config states. */
1181 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1182 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1183
1184 /* Set ring bindings. */
1185 if (sctx->esgs_ring) {
1186 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
1187 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1188 true, true, 4, 64, 0);
1189 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
1190 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1191 false, false, 0, 0, 0);
1192 }
1193 if (sctx->gsvs_ring)
1194 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
1195 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
1196 false, false, 0, 0, 0);
1197 return true;
1198 }
1199
1200 static void si_update_gsvs_ring_bindings(struct si_context *sctx)
1201 {
1202 unsigned gsvs_itemsize = sctx->gs_shader.cso->max_gsvs_emit_size;
1203 uint64_t offset;
1204
1205 if (!sctx->gsvs_ring || gsvs_itemsize == sctx->last_gsvs_itemsize)
1206 return;
1207
1208 sctx->last_gsvs_itemsize = gsvs_itemsize;
1209
1210 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
1211 sctx->gsvs_ring, gsvs_itemsize,
1212 64, true, true, 4, 16, 0);
1213
1214 offset = gsvs_itemsize * 64;
1215 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_1,
1216 sctx->gsvs_ring, gsvs_itemsize,
1217 64, true, true, 4, 16, offset);
1218
1219 offset = (gsvs_itemsize * 2) * 64;
1220 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_2,
1221 sctx->gsvs_ring, gsvs_itemsize,
1222 64, true, true, 4, 16, offset);
1223
1224 offset = (gsvs_itemsize * 3) * 64;
1225 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_3,
1226 sctx->gsvs_ring, gsvs_itemsize,
1227 64, true, true, 4, 16, offset);
1228 }
1229
1230 /**
1231 * @returns 1 if \p sel has been updated to use a new scratch buffer
1232 * 0 if not
1233 * < 0 if there was a failure
1234 */
1235 static int si_update_scratch_buffer(struct si_context *sctx,
1236 struct si_shader *shader)
1237 {
1238 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1239 int r;
1240
1241 if (!shader)
1242 return 0;
1243
1244 /* This shader doesn't need a scratch buffer */
1245 if (shader->scratch_bytes_per_wave == 0)
1246 return 0;
1247
1248 /* This shader is already configured to use the current
1249 * scratch buffer. */
1250 if (shader->scratch_bo == sctx->scratch_buffer)
1251 return 0;
1252
1253 assert(sctx->scratch_buffer);
1254
1255 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
1256
1257 /* Replace the shader bo with a new bo that has the relocs applied. */
1258 r = si_shader_binary_upload(sctx->screen, shader);
1259 if (r)
1260 return r;
1261
1262 /* Update the shader state to use the new shader bo. */
1263 si_shader_init_pm4_state(shader);
1264
1265 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1266
1267 return 1;
1268 }
1269
1270 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1271 {
1272 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
1273 }
1274
1275 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
1276 {
1277 return shader ? shader->scratch_bytes_per_wave : 0;
1278 }
1279
1280 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1281 {
1282 unsigned bytes = 0;
1283
1284 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
1285 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
1286 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
1287 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
1288 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
1289 return bytes;
1290 }
1291
1292 static bool si_update_spi_tmpring_size(struct si_context *sctx)
1293 {
1294 unsigned current_scratch_buffer_size =
1295 si_get_current_scratch_buffer_size(sctx);
1296 unsigned scratch_bytes_per_wave =
1297 si_get_max_scratch_bytes_per_wave(sctx);
1298 unsigned scratch_needed_size = scratch_bytes_per_wave *
1299 sctx->scratch_waves;
1300 int r;
1301
1302 if (scratch_needed_size > 0) {
1303 if (scratch_needed_size > current_scratch_buffer_size) {
1304 /* Create a bigger scratch buffer */
1305 pipe_resource_reference(
1306 (struct pipe_resource**)&sctx->scratch_buffer,
1307 NULL);
1308
1309 sctx->scratch_buffer =
1310 si_resource_create_custom(&sctx->screen->b.b,
1311 PIPE_USAGE_DEFAULT, scratch_needed_size);
1312 if (!sctx->scratch_buffer)
1313 return false;
1314 sctx->emit_scratch_reloc = true;
1315 }
1316
1317 /* Update the shaders, so they are using the latest scratch. The
1318 * scratch buffer may have been changed since these shaders were
1319 * last used, so we still need to try to update them, even if
1320 * they require scratch buffers smaller than the current size.
1321 */
1322 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
1323 if (r < 0)
1324 return false;
1325 if (r == 1)
1326 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1327
1328 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
1329 if (r < 0)
1330 return false;
1331 if (r == 1)
1332 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1333
1334 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
1335 if (r < 0)
1336 return false;
1337 if (r == 1)
1338 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1339
1340 /* VS can be bound as LS, ES, or VS. */
1341 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
1342 if (r < 0)
1343 return false;
1344 if (r == 1) {
1345 if (sctx->tes_shader.current)
1346 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1347 else if (sctx->gs_shader.current)
1348 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1349 else
1350 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1351 }
1352
1353 /* TES can be bound as ES or VS. */
1354 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
1355 if (r < 0)
1356 return false;
1357 if (r == 1) {
1358 if (sctx->gs_shader.current)
1359 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1360 else
1361 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1362 }
1363 }
1364
1365 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1366 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1367 "scratch size should already be aligned correctly.");
1368
1369 sctx->spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1370 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1371 return true;
1372 }
1373
1374 static void si_init_tess_factor_ring(struct si_context *sctx)
1375 {
1376 assert(!sctx->tf_ring);
1377
1378 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1379 PIPE_USAGE_DEFAULT,
1380 32768 * sctx->screen->b.info.max_se);
1381 if (!sctx->tf_ring)
1382 return;
1383
1384 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1385
1386 si_init_config_add_vgt_flush(sctx);
1387
1388 /* Append these registers to the init config state. */
1389 if (sctx->b.chip_class >= CIK) {
1390 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
1391 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1392 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
1393 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1394 } else {
1395 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
1396 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1397 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
1398 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1399 }
1400
1401 /* Flush the context to re-emit the init_config state.
1402 * This is done only once in a lifetime of a context.
1403 */
1404 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1405 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1406 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1407
1408 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
1409 SI_RING_TESS_FACTOR, sctx->tf_ring, 0,
1410 sctx->tf_ring->width0, false, false, 0, 0, 0);
1411 }
1412
1413 /**
1414 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1415 * VS passes its outputs to TES directly, so the fixed-function shader only
1416 * has to write TESSOUTER and TESSINNER.
1417 */
1418 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1419 {
1420 struct ureg_src const0, const1;
1421 struct ureg_dst tessouter, tessinner;
1422 struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
1423
1424 if (!ureg)
1425 return; /* if we get here, we're screwed */
1426
1427 assert(!sctx->fixed_func_tcs_shader.cso);
1428
1429 ureg_DECL_constant2D(ureg, 0, 1, SI_DRIVER_STATE_CONST_BUF);
1430 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1431 SI_DRIVER_STATE_CONST_BUF);
1432 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1433 SI_DRIVER_STATE_CONST_BUF);
1434
1435 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1436 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1437
1438 ureg_MOV(ureg, tessouter, const0);
1439 ureg_MOV(ureg, tessinner, const1);
1440 ureg_END(ureg);
1441
1442 sctx->fixed_func_tcs_shader.cso =
1443 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1444 }
1445
1446 static void si_update_vgt_shader_config(struct si_context *sctx)
1447 {
1448 /* Calculate the index of the config.
1449 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1450 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
1451 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1452
1453 if (!*pm4) {
1454 uint32_t stages = 0;
1455
1456 *pm4 = CALLOC_STRUCT(si_pm4_state);
1457
1458 if (sctx->tes_shader.cso) {
1459 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1460 S_028B54_HS_EN(1);
1461
1462 if (sctx->gs_shader.cso)
1463 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1464 S_028B54_GS_EN(1) |
1465 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1466 else
1467 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1468 } else if (sctx->gs_shader.cso) {
1469 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1470 S_028B54_GS_EN(1) |
1471 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1472 }
1473
1474 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1475 }
1476 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1477 }
1478
1479 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
1480 {
1481 struct pipe_stream_output_info *so = &shader->so;
1482 uint32_t enabled_stream_buffers_mask = 0;
1483 int i;
1484
1485 for (i = 0; i < so->num_outputs; i++)
1486 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
1487 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
1488 sctx->b.streamout.stride_in_dw = shader->so.stride;
1489 }
1490
1491 bool si_update_shaders(struct si_context *sctx)
1492 {
1493 struct pipe_context *ctx = (struct pipe_context*)sctx;
1494 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1495 int r;
1496
1497 /* Update stages before GS. */
1498 if (sctx->tes_shader.cso) {
1499 if (!sctx->tf_ring) {
1500 si_init_tess_factor_ring(sctx);
1501 if (!sctx->tf_ring)
1502 return false;
1503 }
1504
1505 /* VS as LS */
1506 r = si_shader_select(ctx, &sctx->vs_shader);
1507 if (r)
1508 return false;
1509 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1510
1511 if (sctx->tcs_shader.cso) {
1512 r = si_shader_select(ctx, &sctx->tcs_shader);
1513 if (r)
1514 return false;
1515 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1516 } else {
1517 if (!sctx->fixed_func_tcs_shader.cso) {
1518 si_generate_fixed_func_tcs(sctx);
1519 if (!sctx->fixed_func_tcs_shader.cso)
1520 return false;
1521 }
1522
1523 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader);
1524 if (r)
1525 return false;
1526 si_pm4_bind_state(sctx, hs,
1527 sctx->fixed_func_tcs_shader.current->pm4);
1528 }
1529
1530 r = si_shader_select(ctx, &sctx->tes_shader);
1531 if (r)
1532 return false;
1533
1534 if (sctx->gs_shader.cso) {
1535 /* TES as ES */
1536 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1537 } else {
1538 /* TES as VS */
1539 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1540 si_update_so(sctx, sctx->tes_shader.cso);
1541 }
1542 } else if (sctx->gs_shader.cso) {
1543 /* VS as ES */
1544 r = si_shader_select(ctx, &sctx->vs_shader);
1545 if (r)
1546 return false;
1547 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1548 } else {
1549 /* VS as VS */
1550 r = si_shader_select(ctx, &sctx->vs_shader);
1551 if (r)
1552 return false;
1553 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1554 si_update_so(sctx, sctx->vs_shader.cso);
1555 }
1556
1557 /* Update GS. */
1558 if (sctx->gs_shader.cso) {
1559 r = si_shader_select(ctx, &sctx->gs_shader);
1560 if (r)
1561 return false;
1562 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1563 si_pm4_bind_state(sctx, vs, sctx->gs_shader.current->gs_copy_shader->pm4);
1564 si_update_so(sctx, sctx->gs_shader.cso);
1565
1566 if (!si_update_gs_ring_buffers(sctx))
1567 return false;
1568
1569 si_update_gsvs_ring_bindings(sctx);
1570 } else {
1571 si_pm4_bind_state(sctx, gs, NULL);
1572 si_pm4_bind_state(sctx, es, NULL);
1573 }
1574
1575 si_update_vgt_shader_config(sctx);
1576
1577 if (sctx->ps_shader.cso) {
1578 r = si_shader_select(ctx, &sctx->ps_shader);
1579 if (r)
1580 return false;
1581 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1582
1583 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1584 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
1585 sctx->flatshade != rs->flatshade) {
1586 sctx->sprite_coord_enable = rs->sprite_coord_enable;
1587 sctx->flatshade = rs->flatshade;
1588 si_mark_atom_dirty(sctx, &sctx->spi_map);
1589 }
1590
1591 if (si_pm4_state_changed(sctx, ps) ||
1592 sctx->force_persample_interp != rs->force_persample_interp) {
1593 sctx->force_persample_interp = rs->force_persample_interp;
1594 si_mark_atom_dirty(sctx, &sctx->spi_ps_input);
1595 }
1596
1597 if (sctx->ps_db_shader_control != sctx->ps_shader.current->db_shader_control) {
1598 sctx->ps_db_shader_control = sctx->ps_shader.current->db_shader_control;
1599 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1600 }
1601
1602 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.ps.poly_line_smoothing) {
1603 sctx->smoothing_enabled = sctx->ps_shader.current->key.ps.poly_line_smoothing;
1604 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1605
1606 if (sctx->b.chip_class == SI)
1607 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1608 }
1609 }
1610
1611 if (si_pm4_state_changed(sctx, ls) ||
1612 si_pm4_state_changed(sctx, hs) ||
1613 si_pm4_state_changed(sctx, es) ||
1614 si_pm4_state_changed(sctx, gs) ||
1615 si_pm4_state_changed(sctx, vs) ||
1616 si_pm4_state_changed(sctx, ps)) {
1617 if (!si_update_spi_tmpring_size(sctx))
1618 return false;
1619 }
1620 return true;
1621 }
1622
1623 void si_init_shader_functions(struct si_context *sctx)
1624 {
1625 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
1626 si_init_atom(sctx, &sctx->spi_ps_input, &sctx->atoms.s.spi_ps_input, si_emit_spi_ps_input);
1627
1628 sctx->b.b.create_vs_state = si_create_shader_selector;
1629 sctx->b.b.create_tcs_state = si_create_shader_selector;
1630 sctx->b.b.create_tes_state = si_create_shader_selector;
1631 sctx->b.b.create_gs_state = si_create_shader_selector;
1632 sctx->b.b.create_fs_state = si_create_shader_selector;
1633
1634 sctx->b.b.bind_vs_state = si_bind_vs_shader;
1635 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
1636 sctx->b.b.bind_tes_state = si_bind_tes_shader;
1637 sctx->b.b.bind_gs_state = si_bind_gs_shader;
1638 sctx->b.b.bind_fs_state = si_bind_ps_shader;
1639
1640 sctx->b.b.delete_vs_state = si_delete_shader_selector;
1641 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
1642 sctx->b.b.delete_tes_state = si_delete_shader_selector;
1643 sctx->b.b.delete_gs_state = si_delete_shader_selector;
1644 sctx->b.b.delete_fs_state = si_delete_shader_selector;
1645 }