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radeonsi: add support for gl_PrimitiveID in the fragment shader
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_ureg.h"
34 #include "util/u_memory.h"
35 #include "util/u_simple_shaders.h"
36
37 static void si_set_tesseval_regs(struct si_shader *shader,
38 struct si_pm4_state *pm4)
39 {
40 struct tgsi_shader_info *info = &shader->selector->info;
41 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
42 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
43 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
44 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
45 unsigned type, partitioning, topology;
46
47 switch (tes_prim_mode) {
48 case PIPE_PRIM_LINES:
49 type = V_028B6C_TESS_ISOLINE;
50 break;
51 case PIPE_PRIM_TRIANGLES:
52 type = V_028B6C_TESS_TRIANGLE;
53 break;
54 case PIPE_PRIM_QUADS:
55 type = V_028B6C_TESS_QUAD;
56 break;
57 default:
58 assert(0);
59 return;
60 }
61
62 switch (tes_spacing) {
63 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
64 partitioning = V_028B6C_PART_FRAC_ODD;
65 break;
66 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
67 partitioning = V_028B6C_PART_FRAC_EVEN;
68 break;
69 case PIPE_TESS_SPACING_EQUAL:
70 partitioning = V_028B6C_PART_INTEGER;
71 break;
72 default:
73 assert(0);
74 return;
75 }
76
77 if (tes_point_mode)
78 topology = V_028B6C_OUTPUT_POINT;
79 else if (tes_prim_mode == PIPE_PRIM_LINES)
80 topology = V_028B6C_OUTPUT_LINE;
81 else if (tes_vertex_order_cw)
82 /* for some reason, this must be the other way around */
83 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
84 else
85 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
86
87 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
88 S_028B6C_TYPE(type) |
89 S_028B6C_PARTITIONING(partitioning) |
90 S_028B6C_TOPOLOGY(topology));
91 }
92
93 static void si_shader_ls(struct si_shader *shader)
94 {
95 struct si_pm4_state *pm4;
96 unsigned num_sgprs, num_user_sgprs;
97 unsigned vgpr_comp_cnt;
98 uint64_t va;
99
100 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
101 if (pm4 == NULL)
102 return;
103
104 va = shader->bo->gpu_address;
105 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
106
107 /* We need at least 2 components for LS.
108 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
109 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 1;
110
111 num_user_sgprs = SI_LS_NUM_USER_SGPR;
112 num_sgprs = shader->num_sgprs;
113 if (num_user_sgprs > num_sgprs) {
114 /* Last 2 reserved SGPRs are used for VCC */
115 num_sgprs = num_user_sgprs + 2;
116 }
117 assert(num_sgprs <= 104);
118
119 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
120 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
121
122 shader->ls_rsrc1 = S_00B528_VGPRS((shader->num_vgprs - 1) / 4) |
123 S_00B528_SGPRS((num_sgprs - 1) / 8) |
124 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt);
125 shader->ls_rsrc2 = S_00B52C_USER_SGPR(num_user_sgprs) |
126 S_00B52C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0);
127 }
128
129 static void si_shader_hs(struct si_shader *shader)
130 {
131 struct si_pm4_state *pm4;
132 unsigned num_sgprs, num_user_sgprs;
133 uint64_t va;
134
135 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
136 if (pm4 == NULL)
137 return;
138
139 va = shader->bo->gpu_address;
140 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
141
142 num_user_sgprs = SI_TCS_NUM_USER_SGPR;
143 num_sgprs = shader->num_sgprs;
144 /* One SGPR after user SGPRs is pre-loaded with tessellation factor
145 * buffer offset. */
146 if ((num_user_sgprs + 1) > num_sgprs) {
147 /* Last 2 reserved SGPRs are used for VCC */
148 num_sgprs = num_user_sgprs + 1 + 2;
149 }
150 assert(num_sgprs <= 104);
151
152 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
153 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
154 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
155 S_00B428_VGPRS((shader->num_vgprs - 1) / 4) |
156 S_00B428_SGPRS((num_sgprs - 1) / 8));
157 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
158 S_00B42C_USER_SGPR(num_user_sgprs) |
159 S_00B42C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
160 }
161
162 static void si_shader_es(struct si_shader *shader)
163 {
164 struct si_pm4_state *pm4;
165 unsigned num_sgprs, num_user_sgprs;
166 unsigned vgpr_comp_cnt;
167 uint64_t va;
168
169 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
170
171 if (pm4 == NULL)
172 return;
173
174 va = shader->bo->gpu_address;
175 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
176
177 if (shader->selector->type == PIPE_SHADER_VERTEX) {
178 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
179 num_user_sgprs = SI_VS_NUM_USER_SGPR;
180 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
181 vgpr_comp_cnt = 3; /* all components are needed for TES */
182 num_user_sgprs = SI_TES_NUM_USER_SGPR;
183 } else
184 assert(0);
185
186 num_sgprs = shader->num_sgprs;
187 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
188 if ((num_user_sgprs + 1) > num_sgprs) {
189 /* Last 2 reserved SGPRs are used for VCC */
190 num_sgprs = num_user_sgprs + 1 + 2;
191 }
192 assert(num_sgprs <= 104);
193
194 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
195 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
196 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
197 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
198 S_00B328_SGPRS((num_sgprs - 1) / 8) |
199 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
200 S_00B328_DX10_CLAMP(shader->dx10_clamp_mode));
201 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
202 S_00B32C_USER_SGPR(num_user_sgprs) |
203 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
204
205 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
206 si_set_tesseval_regs(shader, pm4);
207 }
208
209 static unsigned si_gs_get_max_stream(struct si_shader *shader)
210 {
211 struct pipe_stream_output_info *so = &shader->selector->so;
212 unsigned max_stream = 0, i;
213
214 if (so->num_outputs == 0)
215 return 0;
216
217 for (i = 0; i < so->num_outputs; i++) {
218 if (so->output[i].stream > max_stream)
219 max_stream = so->output[i].stream;
220 }
221 return max_stream;
222 }
223
224 static void si_shader_gs(struct si_shader *shader)
225 {
226 unsigned gs_vert_itemsize = shader->selector->info.num_outputs * 16;
227 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
228 unsigned gsvs_itemsize = (gs_vert_itemsize * gs_max_vert_out) >> 2;
229 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
230 unsigned cut_mode;
231 struct si_pm4_state *pm4;
232 unsigned num_sgprs, num_user_sgprs;
233 uint64_t va;
234 unsigned max_stream = si_gs_get_max_stream(shader);
235
236 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
237 assert(gsvs_itemsize < (1 << 15));
238
239 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
240
241 if (pm4 == NULL)
242 return;
243
244 if (gs_max_vert_out <= 128) {
245 cut_mode = V_028A40_GS_CUT_128;
246 } else if (gs_max_vert_out <= 256) {
247 cut_mode = V_028A40_GS_CUT_256;
248 } else if (gs_max_vert_out <= 512) {
249 cut_mode = V_028A40_GS_CUT_512;
250 } else {
251 assert(gs_max_vert_out <= 1024);
252 cut_mode = V_028A40_GS_CUT_1024;
253 }
254
255 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
256 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
257 S_028A40_CUT_MODE(cut_mode)|
258 S_028A40_ES_WRITE_OPTIMIZE(1) |
259 S_028A40_GS_WRITE_OPTIMIZE(1));
260
261 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
262 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
263 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
264
265 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
266 util_bitcount64(shader->selector->inputs_read) * (16 >> 2));
267 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
268
269 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
270
271 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
272 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
273 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
274 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
275
276 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
277 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
278 S_028B90_ENABLE(gs_num_invocations > 0));
279
280 va = shader->bo->gpu_address;
281 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
282 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
283 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
284
285 num_user_sgprs = SI_GS_NUM_USER_SGPR;
286 num_sgprs = shader->num_sgprs;
287 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
288 if ((num_user_sgprs + 2) > num_sgprs) {
289 /* Last 2 reserved SGPRs are used for VCC */
290 num_sgprs = num_user_sgprs + 2 + 2;
291 }
292 assert(num_sgprs <= 104);
293
294 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
295 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
296 S_00B228_SGPRS((num_sgprs - 1) / 8) |
297 S_00B228_DX10_CLAMP(shader->dx10_clamp_mode));
298 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
299 S_00B22C_USER_SGPR(num_user_sgprs) |
300 S_00B22C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
301 }
302
303 static void si_shader_vs(struct si_shader *shader)
304 {
305 struct si_pm4_state *pm4;
306 unsigned num_sgprs, num_user_sgprs;
307 unsigned nparams, vgpr_comp_cnt;
308 uint64_t va;
309 unsigned window_space =
310 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
311 bool enable_prim_id = si_vs_exports_prim_id(shader);
312
313 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
314
315 if (pm4 == NULL)
316 return;
317
318 /* If this is the GS copy shader, the GS state writes this register.
319 * Otherwise, the VS state writes it.
320 */
321 if (!shader->is_gs_copy_shader) {
322 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
323 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
324 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
325 } else
326 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
327
328 va = shader->bo->gpu_address;
329 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
330
331 if (shader->is_gs_copy_shader) {
332 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
333 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
334 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
335 vgpr_comp_cnt = shader->uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
336 num_user_sgprs = SI_VS_NUM_USER_SGPR;
337 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
338 vgpr_comp_cnt = 3; /* all components are needed for TES */
339 num_user_sgprs = SI_TES_NUM_USER_SGPR;
340 } else
341 assert(0);
342
343 num_sgprs = shader->num_sgprs;
344 if (num_user_sgprs > num_sgprs) {
345 /* Last 2 reserved SGPRs are used for VCC */
346 num_sgprs = num_user_sgprs + 2;
347 }
348 assert(num_sgprs <= 104);
349
350 /* VS is required to export at least one param. */
351 nparams = MAX2(shader->nr_param_exports, 1);
352 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
353 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
354
355 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
356 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
357 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
358 V_02870C_SPI_SHADER_4COMP :
359 V_02870C_SPI_SHADER_NONE) |
360 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
361 V_02870C_SPI_SHADER_4COMP :
362 V_02870C_SPI_SHADER_NONE) |
363 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
364 V_02870C_SPI_SHADER_4COMP :
365 V_02870C_SPI_SHADER_NONE));
366
367 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
368 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
369 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
370 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
371 S_00B128_SGPRS((num_sgprs - 1) / 8) |
372 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
373 S_00B128_DX10_CLAMP(shader->dx10_clamp_mode));
374 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
375 S_00B12C_USER_SGPR(num_user_sgprs) |
376 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
377 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
378 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
379 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
380 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
381 S_00B12C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
382 if (window_space)
383 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
384 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
385 else
386 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
387 S_028818_VTX_W0_FMT(1) |
388 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
389 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
390 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
391
392 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
393 si_set_tesseval_regs(shader, pm4);
394 }
395
396 static void si_shader_ps(struct si_shader *shader)
397 {
398 struct tgsi_shader_info *info = &shader->selector->info;
399 struct si_pm4_state *pm4;
400 unsigned i, spi_ps_in_control;
401 unsigned num_sgprs, num_user_sgprs;
402 unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
403 uint64_t va;
404
405 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
406
407 if (pm4 == NULL)
408 return;
409
410 for (i = 0; i < info->num_inputs; i++) {
411 switch (info->input_semantic_name[i]) {
412 case TGSI_SEMANTIC_POSITION:
413 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
414 * Possible vaules:
415 * 0 -> Position = pixel center (default)
416 * 1 -> Position = pixel centroid
417 * 2 -> Position = at sample position
418 */
419 switch (info->input_interpolate_loc[i]) {
420 case TGSI_INTERPOLATE_LOC_CENTROID:
421 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
422 break;
423 case TGSI_INTERPOLATE_LOC_SAMPLE:
424 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
425 break;
426 }
427
428 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
429 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
430 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
431 break;
432 }
433 }
434
435 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
436 S_0286D8_BC_OPTIMIZE_DISABLE(1);
437
438 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
439 spi_ps_input_ena = shader->spi_ps_input_ena;
440 /* we need to enable at least one of them, otherwise we hang the GPU */
441 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
442 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
443 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
444 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
445 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
446 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
447 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
448 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
449
450 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
451 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
452 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
453
454 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
455 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
456 shader->spi_shader_col_format);
457 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
458
459 va = shader->bo->gpu_address;
460 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
461 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
462 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
463
464 num_user_sgprs = SI_PS_NUM_USER_SGPR;
465 num_sgprs = shader->num_sgprs;
466 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
467 if ((num_user_sgprs + 1) > num_sgprs) {
468 /* Last 2 reserved SGPRs are used for VCC */
469 num_sgprs = num_user_sgprs + 1 + 2;
470 }
471 assert(num_sgprs <= 104);
472
473 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
474 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
475 S_00B028_SGPRS((num_sgprs - 1) / 8) |
476 S_00B028_DX10_CLAMP(shader->dx10_clamp_mode));
477 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
478 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
479 S_00B02C_USER_SGPR(num_user_sgprs) |
480 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
481 }
482
483 static void si_shader_init_pm4_state(struct si_shader *shader)
484 {
485
486 if (shader->pm4)
487 si_pm4_free_state_simple(shader->pm4);
488
489 switch (shader->selector->type) {
490 case PIPE_SHADER_VERTEX:
491 if (shader->key.vs.as_ls)
492 si_shader_ls(shader);
493 else if (shader->key.vs.as_es)
494 si_shader_es(shader);
495 else
496 si_shader_vs(shader);
497 break;
498 case PIPE_SHADER_TESS_CTRL:
499 si_shader_hs(shader);
500 break;
501 case PIPE_SHADER_TESS_EVAL:
502 if (shader->key.tes.as_es)
503 si_shader_es(shader);
504 else
505 si_shader_vs(shader);
506 break;
507 case PIPE_SHADER_GEOMETRY:
508 si_shader_gs(shader);
509 si_shader_vs(shader->gs_copy_shader);
510 break;
511 case PIPE_SHADER_FRAGMENT:
512 si_shader_ps(shader);
513 break;
514 default:
515 assert(0);
516 }
517 }
518
519 /* Compute the key for the hw shader variant */
520 static inline void si_shader_selector_key(struct pipe_context *ctx,
521 struct si_shader_selector *sel,
522 union si_shader_key *key)
523 {
524 struct si_context *sctx = (struct si_context *)ctx;
525 unsigned i;
526
527 memset(key, 0, sizeof(*key));
528
529 switch (sel->type) {
530 case PIPE_SHADER_VERTEX:
531 if (sctx->vertex_elements)
532 for (i = 0; i < sctx->vertex_elements->count; ++i)
533 key->vs.instance_divisors[i] =
534 sctx->vertex_elements->elements[i].instance_divisor;
535
536 if (sctx->tes_shader)
537 key->vs.as_ls = 1;
538 else if (sctx->gs_shader) {
539 key->vs.as_es = 1;
540 key->vs.es_enabled_outputs = sctx->gs_shader->inputs_read;
541 }
542
543 if (!sctx->gs_shader && sctx->ps_shader &&
544 sctx->ps_shader->info.uses_primid)
545 key->vs.export_prim_id = 1;
546 break;
547 case PIPE_SHADER_TESS_CTRL:
548 key->tcs.prim_mode =
549 sctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
550 break;
551 case PIPE_SHADER_TESS_EVAL:
552 if (sctx->gs_shader) {
553 key->tes.as_es = 1;
554 key->tes.es_enabled_outputs = sctx->gs_shader->inputs_read;
555 } else if (sctx->ps_shader && sctx->ps_shader->info.uses_primid)
556 key->tes.export_prim_id = 1;
557 break;
558 case PIPE_SHADER_GEOMETRY:
559 break;
560 case PIPE_SHADER_FRAGMENT: {
561 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
562
563 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
564 key->ps.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
565 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
566
567 if (rs) {
568 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
569 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
570 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
571 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
572
573 key->ps.color_two_side = rs->two_side;
574
575 if (sctx->queued.named.blend) {
576 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
577 rs->multisample_enable &&
578 !sctx->framebuffer.cb0_is_integer;
579 }
580
581 key->ps.poly_stipple = rs->poly_stipple_enable && is_poly;
582 key->ps.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
583 (is_line && rs->line_smooth)) &&
584 sctx->framebuffer.nr_samples <= 1;
585 }
586
587 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
588 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
589 if (sctx->queued.named.dsa &&
590 !sctx->framebuffer.cb0_is_integer)
591 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
592 break;
593 }
594 default:
595 assert(0);
596 }
597 }
598
599 /* Select the hw shader variant depending on the current state. */
600 static int si_shader_select(struct pipe_context *ctx,
601 struct si_shader_selector *sel)
602 {
603 struct si_context *sctx = (struct si_context *)ctx;
604 union si_shader_key key;
605 struct si_shader * shader = NULL;
606 int r;
607
608 si_shader_selector_key(ctx, sel, &key);
609
610 /* Check if we don't need to change anything.
611 * This path is also used for most shaders that don't need multiple
612 * variants, it will cost just a computation of the key and this
613 * test. */
614 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
615 return 0;
616 }
617
618 /* lookup if we have other variants in the list */
619 if (sel->num_shaders > 1) {
620 struct si_shader *p = sel->current, *c = p->next_variant;
621
622 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
623 p = c;
624 c = c->next_variant;
625 }
626
627 if (c) {
628 p->next_variant = c->next_variant;
629 shader = c;
630 }
631 }
632
633 if (shader) {
634 shader->next_variant = sel->current;
635 sel->current = shader;
636 } else {
637 shader = CALLOC(1, sizeof(struct si_shader));
638 shader->selector = sel;
639 shader->key = key;
640
641 shader->next_variant = sel->current;
642 sel->current = shader;
643 r = si_shader_create((struct si_screen*)ctx->screen, sctx->tm,
644 shader);
645 if (unlikely(r)) {
646 R600_ERR("Failed to build shader variant (type=%u) %d\n",
647 sel->type, r);
648 sel->current = NULL;
649 FREE(shader);
650 return r;
651 }
652 si_shader_init_pm4_state(shader);
653 sel->num_shaders++;
654 p_atomic_inc(&sctx->screen->b.num_compilations);
655 }
656
657 return 0;
658 }
659
660 static void *si_create_shader_state(struct pipe_context *ctx,
661 const struct pipe_shader_state *state,
662 unsigned pipe_shader_type)
663 {
664 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
665 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
666 int i;
667
668 sel->type = pipe_shader_type;
669 sel->tokens = tgsi_dup_tokens(state->tokens);
670 sel->so = state->stream_output;
671 tgsi_scan_shader(state->tokens, &sel->info);
672 p_atomic_inc(&sscreen->b.num_shaders_created);
673
674 switch (pipe_shader_type) {
675 case PIPE_SHADER_GEOMETRY:
676 sel->gs_output_prim =
677 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
678 sel->gs_max_out_vertices =
679 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
680 sel->gs_num_invocations =
681 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
682
683 for (i = 0; i < sel->info.num_inputs; i++) {
684 unsigned name = sel->info.input_semantic_name[i];
685 unsigned index = sel->info.input_semantic_index[i];
686
687 switch (name) {
688 case TGSI_SEMANTIC_PRIMID:
689 break;
690 default:
691 sel->inputs_read |=
692 1llu << si_shader_io_get_unique_index(name, index);
693 }
694 }
695 break;
696
697 case PIPE_SHADER_VERTEX:
698 case PIPE_SHADER_TESS_CTRL:
699 for (i = 0; i < sel->info.num_outputs; i++) {
700 unsigned name = sel->info.output_semantic_name[i];
701 unsigned index = sel->info.output_semantic_index[i];
702
703 switch (name) {
704 case TGSI_SEMANTIC_TESSINNER:
705 case TGSI_SEMANTIC_TESSOUTER:
706 case TGSI_SEMANTIC_PATCH:
707 sel->patch_outputs_written |=
708 1llu << si_shader_io_get_unique_index(name, index);
709 break;
710 default:
711 sel->outputs_written |=
712 1llu << si_shader_io_get_unique_index(name, index);
713 }
714 }
715 break;
716 }
717
718 if (sscreen->b.debug_flags & DBG_PRECOMPILE)
719 si_shader_select(ctx, sel);
720
721 return sel;
722 }
723
724 static void *si_create_fs_state(struct pipe_context *ctx,
725 const struct pipe_shader_state *state)
726 {
727 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
728 }
729
730 static void *si_create_gs_state(struct pipe_context *ctx,
731 const struct pipe_shader_state *state)
732 {
733 return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
734 }
735
736 static void *si_create_vs_state(struct pipe_context *ctx,
737 const struct pipe_shader_state *state)
738 {
739 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
740 }
741
742 static void *si_create_tcs_state(struct pipe_context *ctx,
743 const struct pipe_shader_state *state)
744 {
745 return si_create_shader_state(ctx, state, PIPE_SHADER_TESS_CTRL);
746 }
747
748 static void *si_create_tes_state(struct pipe_context *ctx,
749 const struct pipe_shader_state *state)
750 {
751 return si_create_shader_state(ctx, state, PIPE_SHADER_TESS_EVAL);
752 }
753
754 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
755 {
756 struct si_context *sctx = (struct si_context *)ctx;
757 struct si_shader_selector *sel = state;
758
759 if (sctx->vs_shader == sel || !sel)
760 return;
761
762 sctx->vs_shader = sel;
763 si_mark_atom_dirty(sctx, &sctx->clip_regs);
764 }
765
766 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
767 {
768 struct si_context *sctx = (struct si_context *)ctx;
769 struct si_shader_selector *sel = state;
770 bool enable_changed = !!sctx->gs_shader != !!sel;
771
772 if (sctx->gs_shader == sel)
773 return;
774
775 sctx->gs_shader = sel;
776 si_mark_atom_dirty(sctx, &sctx->clip_regs);
777 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
778
779 if (enable_changed)
780 si_shader_change_notify(sctx);
781 }
782
783 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
784 {
785 struct si_context *sctx = (struct si_context *)ctx;
786 struct si_shader_selector *sel = state;
787 bool enable_changed = !!sctx->tcs_shader != !!sel;
788
789 if (sctx->tcs_shader == sel)
790 return;
791
792 sctx->tcs_shader = sel;
793
794 if (enable_changed)
795 sctx->last_tcs = NULL; /* invalidate derived tess state */
796 }
797
798 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
799 {
800 struct si_context *sctx = (struct si_context *)ctx;
801 struct si_shader_selector *sel = state;
802 bool enable_changed = !!sctx->tes_shader != !!sel;
803
804 if (sctx->tes_shader == sel)
805 return;
806
807 sctx->tes_shader = sel;
808 si_mark_atom_dirty(sctx, &sctx->clip_regs);
809 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
810
811 if (enable_changed) {
812 si_shader_change_notify(sctx);
813 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
814 }
815 }
816
817 static void si_make_dummy_ps(struct si_context *sctx)
818 {
819 if (!sctx->dummy_pixel_shader) {
820 sctx->dummy_pixel_shader =
821 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
822 TGSI_SEMANTIC_GENERIC,
823 TGSI_INTERPOLATE_CONSTANT);
824 }
825 }
826
827 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
828 {
829 struct si_context *sctx = (struct si_context *)ctx;
830 struct si_shader_selector *sel = state;
831
832 /* skip if supplied shader is one already in use */
833 if (sctx->ps_shader == sel)
834 return;
835
836 /* use a dummy shader if binding a NULL shader */
837 if (!sel) {
838 si_make_dummy_ps(sctx);
839 sel = sctx->dummy_pixel_shader;
840 }
841
842 sctx->ps_shader = sel;
843 }
844
845 static void si_delete_shader_selector(struct pipe_context *ctx,
846 struct si_shader_selector *sel)
847 {
848 struct si_context *sctx = (struct si_context *)ctx;
849 struct si_shader *p = sel->current, *c;
850
851 while (p) {
852 c = p->next_variant;
853 switch (sel->type) {
854 case PIPE_SHADER_VERTEX:
855 if (p->key.vs.as_ls)
856 si_pm4_delete_state(sctx, ls, p->pm4);
857 else if (p->key.vs.as_es)
858 si_pm4_delete_state(sctx, es, p->pm4);
859 else
860 si_pm4_delete_state(sctx, vs, p->pm4);
861 break;
862 case PIPE_SHADER_TESS_CTRL:
863 si_pm4_delete_state(sctx, hs, p->pm4);
864 break;
865 case PIPE_SHADER_TESS_EVAL:
866 if (p->key.tes.as_es)
867 si_pm4_delete_state(sctx, es, p->pm4);
868 else
869 si_pm4_delete_state(sctx, vs, p->pm4);
870 break;
871 case PIPE_SHADER_GEOMETRY:
872 si_pm4_delete_state(sctx, gs, p->pm4);
873 si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
874 break;
875 case PIPE_SHADER_FRAGMENT:
876 si_pm4_delete_state(sctx, ps, p->pm4);
877 break;
878 }
879
880 si_shader_destroy(ctx, p);
881 free(p);
882 p = c;
883 }
884
885 free(sel->tokens);
886 free(sel);
887 }
888
889 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
890 {
891 struct si_context *sctx = (struct si_context *)ctx;
892 struct si_shader_selector *sel = (struct si_shader_selector *)state;
893
894 if (sctx->vs_shader == sel) {
895 sctx->vs_shader = NULL;
896 }
897
898 si_delete_shader_selector(ctx, sel);
899 }
900
901 static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
902 {
903 struct si_context *sctx = (struct si_context *)ctx;
904 struct si_shader_selector *sel = (struct si_shader_selector *)state;
905
906 if (sctx->gs_shader == sel) {
907 sctx->gs_shader = NULL;
908 }
909
910 si_delete_shader_selector(ctx, sel);
911 }
912
913 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
914 {
915 struct si_context *sctx = (struct si_context *)ctx;
916 struct si_shader_selector *sel = (struct si_shader_selector *)state;
917
918 if (sctx->ps_shader == sel) {
919 sctx->ps_shader = NULL;
920 }
921
922 si_delete_shader_selector(ctx, sel);
923 }
924
925 static void si_delete_tcs_shader(struct pipe_context *ctx, void *state)
926 {
927 struct si_context *sctx = (struct si_context *)ctx;
928 struct si_shader_selector *sel = (struct si_shader_selector *)state;
929
930 if (sctx->tcs_shader == sel) {
931 sctx->tcs_shader = NULL;
932 }
933
934 si_delete_shader_selector(ctx, sel);
935 }
936
937 static void si_delete_tes_shader(struct pipe_context *ctx, void *state)
938 {
939 struct si_context *sctx = (struct si_context *)ctx;
940 struct si_shader_selector *sel = (struct si_shader_selector *)state;
941
942 if (sctx->tes_shader == sel) {
943 sctx->tes_shader = NULL;
944 }
945
946 si_delete_shader_selector(ctx, sel);
947 }
948
949 static void si_update_spi_map(struct si_context *sctx)
950 {
951 struct si_shader *ps = sctx->ps_shader->current;
952 struct si_shader *vs = si_get_vs_state(sctx);
953 struct tgsi_shader_info *psinfo = &ps->selector->info;
954 struct tgsi_shader_info *vsinfo = &vs->selector->info;
955 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
956 unsigned i, j, tmp;
957
958 for (i = 0; i < psinfo->num_inputs; i++) {
959 unsigned name = psinfo->input_semantic_name[i];
960 unsigned index = psinfo->input_semantic_index[i];
961 unsigned interpolate = psinfo->input_interpolate[i];
962 unsigned param_offset = ps->ps_input_param_offset[i];
963
964 if (name == TGSI_SEMANTIC_POSITION ||
965 name == TGSI_SEMANTIC_FACE)
966 /* Read from preloaded VGPRs, not parameters */
967 continue;
968
969 bcolor:
970 tmp = 0;
971
972 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
973 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
974 tmp |= S_028644_FLAT_SHADE(1);
975
976 if (name == TGSI_SEMANTIC_PCOORD ||
977 (name == TGSI_SEMANTIC_TEXCOORD &&
978 sctx->sprite_coord_enable & (1 << index))) {
979 tmp |= S_028644_PT_SPRITE_TEX(1);
980 }
981
982 for (j = 0; j < vsinfo->num_outputs; j++) {
983 if (name == vsinfo->output_semantic_name[j] &&
984 index == vsinfo->output_semantic_index[j]) {
985 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
986 break;
987 }
988 }
989
990 if (name == TGSI_SEMANTIC_PRIMID)
991 /* PrimID is written after the last output. */
992 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[vsinfo->num_outputs]);
993 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(tmp)) {
994 /* No corresponding output found, load defaults into input.
995 * Don't set any other bits.
996 * (FLAT_SHADE=1 completely changes behavior) */
997 tmp = S_028644_OFFSET(0x20);
998 }
999
1000 si_pm4_set_reg(pm4,
1001 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
1002 tmp);
1003
1004 if (name == TGSI_SEMANTIC_COLOR &&
1005 ps->key.ps.color_two_side) {
1006 name = TGSI_SEMANTIC_BCOLOR;
1007 param_offset++;
1008 goto bcolor;
1009 }
1010 }
1011
1012 si_pm4_set_state(sctx, spi, pm4);
1013 }
1014
1015 /* Initialize state related to ESGS / GSVS ring buffers */
1016 static void si_init_gs_rings(struct si_context *sctx)
1017 {
1018 unsigned esgs_ring_size = 128 * 1024;
1019 unsigned gsvs_ring_size = 64 * 1024 * 1024;
1020
1021 assert(!sctx->gs_rings);
1022 sctx->gs_rings = CALLOC_STRUCT(si_pm4_state);
1023
1024 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1025 PIPE_USAGE_DEFAULT, esgs_ring_size);
1026
1027 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1028 PIPE_USAGE_DEFAULT, gsvs_ring_size);
1029
1030 if (sctx->b.chip_class >= CIK) {
1031 si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
1032 esgs_ring_size / 256);
1033 si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
1034 gsvs_ring_size / 256);
1035 } else {
1036 si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
1037 esgs_ring_size / 256);
1038 si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
1039 gsvs_ring_size / 256);
1040 }
1041
1042 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
1043 sctx->esgs_ring, 0, esgs_ring_size,
1044 true, true, 4, 64, 0);
1045 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
1046 sctx->esgs_ring, 0, esgs_ring_size,
1047 false, false, 0, 0, 0);
1048 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
1049 sctx->gsvs_ring, 0, gsvs_ring_size,
1050 false, false, 0, 0, 0);
1051 }
1052
1053 static void si_update_gs_rings(struct si_context *sctx)
1054 {
1055 unsigned gs_vert_itemsize = sctx->gs_shader->info.num_outputs * 16;
1056 unsigned gs_max_vert_out = sctx->gs_shader->gs_max_out_vertices;
1057 unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
1058 uint64_t offset;
1059
1060 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
1061 sctx->gsvs_ring, gsvs_itemsize,
1062 64, true, true, 4, 16, 0);
1063
1064 offset = gsvs_itemsize * 64;
1065 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_1,
1066 sctx->gsvs_ring, gsvs_itemsize,
1067 64, true, true, 4, 16, offset);
1068
1069 offset = (gsvs_itemsize * 2) * 64;
1070 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_2,
1071 sctx->gsvs_ring, gsvs_itemsize,
1072 64, true, true, 4, 16, offset);
1073
1074 offset = (gsvs_itemsize * 3) * 64;
1075 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_3,
1076 sctx->gsvs_ring, gsvs_itemsize,
1077 64, true, true, 4, 16, offset);
1078
1079 }
1080 /**
1081 * @returns 1 if \p sel has been updated to use a new scratch buffer and 0
1082 * otherwise.
1083 */
1084 static unsigned si_update_scratch_buffer(struct si_context *sctx,
1085 struct si_shader_selector *sel)
1086 {
1087 struct si_shader *shader;
1088 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1089
1090 if (!sel)
1091 return 0;
1092
1093 shader = sel->current;
1094
1095 /* This shader doesn't need a scratch buffer */
1096 if (shader->scratch_bytes_per_wave == 0)
1097 return 0;
1098
1099 /* This shader is already configured to use the current
1100 * scratch buffer. */
1101 if (shader->scratch_bo == sctx->scratch_buffer)
1102 return 0;
1103
1104 assert(sctx->scratch_buffer);
1105
1106 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
1107
1108 /* Replace the shader bo with a new bo that has the relocs applied. */
1109 si_shader_binary_upload(sctx->screen, shader);
1110
1111 /* Update the shader state to use the new shader bo. */
1112 si_shader_init_pm4_state(shader);
1113
1114 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1115
1116 return 1;
1117 }
1118
1119 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1120 {
1121 if (!sctx->scratch_buffer)
1122 return 0;
1123
1124 return sctx->scratch_buffer->b.b.width0;
1125 }
1126
1127 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_context *sctx,
1128 struct si_shader_selector *sel)
1129 {
1130 if (!sel)
1131 return 0;
1132
1133 return sel->current->scratch_bytes_per_wave;
1134 }
1135
1136 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1137 {
1138 unsigned bytes = 0;
1139
1140 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->ps_shader));
1141 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->gs_shader));
1142 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->vs_shader));
1143 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->tcs_shader));
1144 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->tes_shader));
1145 return bytes;
1146 }
1147
1148 static void si_update_spi_tmpring_size(struct si_context *sctx)
1149 {
1150 unsigned current_scratch_buffer_size =
1151 si_get_current_scratch_buffer_size(sctx);
1152 unsigned scratch_bytes_per_wave =
1153 si_get_max_scratch_bytes_per_wave(sctx);
1154 unsigned scratch_needed_size = scratch_bytes_per_wave *
1155 sctx->scratch_waves;
1156
1157 if (scratch_needed_size > 0) {
1158
1159 if (scratch_needed_size > current_scratch_buffer_size) {
1160 /* Create a bigger scratch buffer */
1161 pipe_resource_reference(
1162 (struct pipe_resource**)&sctx->scratch_buffer,
1163 NULL);
1164
1165 sctx->scratch_buffer =
1166 si_resource_create_custom(&sctx->screen->b.b,
1167 PIPE_USAGE_DEFAULT, scratch_needed_size);
1168 }
1169
1170 /* Update the shaders, so they are using the latest scratch. The
1171 * scratch buffer may have been changed since these shaders were
1172 * last used, so we still need to try to update them, even if
1173 * they require scratch buffers smaller than the current size.
1174 */
1175 if (si_update_scratch_buffer(sctx, sctx->ps_shader))
1176 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
1177 if (si_update_scratch_buffer(sctx, sctx->gs_shader))
1178 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
1179 if (si_update_scratch_buffer(sctx, sctx->tcs_shader))
1180 si_pm4_bind_state(sctx, hs, sctx->tcs_shader->current->pm4);
1181
1182 /* VS can be bound as LS, ES, or VS. */
1183 if (sctx->tes_shader) {
1184 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
1185 si_pm4_bind_state(sctx, ls, sctx->vs_shader->current->pm4);
1186 } else if (sctx->gs_shader) {
1187 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
1188 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
1189 } else {
1190 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
1191 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
1192 }
1193
1194 /* TES can be bound as ES or VS. */
1195 if (sctx->gs_shader) {
1196 if (si_update_scratch_buffer(sctx, sctx->tes_shader))
1197 si_pm4_bind_state(sctx, es, sctx->tes_shader->current->pm4);
1198 } else {
1199 if (si_update_scratch_buffer(sctx, sctx->tes_shader))
1200 si_pm4_bind_state(sctx, vs, sctx->tes_shader->current->pm4);
1201 }
1202 }
1203
1204 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1205 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1206 "scratch size should already be aligned correctly.");
1207
1208 sctx->spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1209 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1210 }
1211
1212 static void si_init_tess_factor_ring(struct si_context *sctx)
1213 {
1214 assert(!sctx->tf_state);
1215 sctx->tf_state = CALLOC_STRUCT(si_pm4_state);
1216
1217 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1218 PIPE_USAGE_DEFAULT,
1219 32768 * sctx->screen->b.info.max_se);
1220 sctx->b.clear_buffer(&sctx->b.b, sctx->tf_ring, 0,
1221 sctx->tf_ring->width0, fui(0), false);
1222 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1223
1224 if (sctx->b.chip_class >= CIK) {
1225 si_pm4_set_reg(sctx->tf_state, R_030938_VGT_TF_RING_SIZE,
1226 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1227 si_pm4_set_reg(sctx->tf_state, R_030940_VGT_TF_MEMORY_BASE,
1228 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1229 } else {
1230 si_pm4_set_reg(sctx->tf_state, R_008988_VGT_TF_RING_SIZE,
1231 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1232 si_pm4_set_reg(sctx->tf_state, R_0089B8_VGT_TF_MEMORY_BASE,
1233 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1234 }
1235 si_pm4_add_bo(sctx->tf_state, r600_resource(sctx->tf_ring),
1236 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
1237 si_pm4_bind_state(sctx, tf_ring, sctx->tf_state);
1238
1239 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
1240 SI_RING_TESS_FACTOR, sctx->tf_ring, 0,
1241 sctx->tf_ring->width0, false, false, 0, 0, 0);
1242
1243 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
1244 }
1245
1246 /**
1247 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1248 * VS passes its outputs to TES directly, so the fixed-function shader only
1249 * has to write TESSOUTER and TESSINNER.
1250 */
1251 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1252 {
1253 struct ureg_src const0, const1;
1254 struct ureg_dst tessouter, tessinner;
1255 struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
1256
1257 if (!ureg)
1258 return; /* if we get here, we're screwed */
1259
1260 assert(!sctx->fixed_func_tcs_shader);
1261
1262 ureg_DECL_constant2D(ureg, 0, 1, SI_DRIVER_STATE_CONST_BUF);
1263 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1264 SI_DRIVER_STATE_CONST_BUF);
1265 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1266 SI_DRIVER_STATE_CONST_BUF);
1267
1268 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1269 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1270
1271 ureg_MOV(ureg, tessouter, const0);
1272 ureg_MOV(ureg, tessinner, const1);
1273 ureg_END(ureg);
1274
1275 sctx->fixed_func_tcs_shader =
1276 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1277 assert(sctx->fixed_func_tcs_shader);
1278 }
1279
1280 static void si_update_vgt_shader_config(struct si_context *sctx)
1281 {
1282 /* Calculate the index of the config.
1283 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1284 unsigned index = 2*!!sctx->tes_shader + !!sctx->gs_shader;
1285 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1286
1287 if (!*pm4) {
1288 uint32_t stages = 0;
1289
1290 *pm4 = CALLOC_STRUCT(si_pm4_state);
1291
1292 if (sctx->tes_shader) {
1293 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1294 S_028B54_HS_EN(1);
1295
1296 if (sctx->gs_shader)
1297 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1298 S_028B54_GS_EN(1) |
1299 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1300 else
1301 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1302 } else if (sctx->gs_shader) {
1303 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1304 S_028B54_GS_EN(1) |
1305 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1306 }
1307
1308 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1309 }
1310 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1311 }
1312
1313 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
1314 {
1315 struct pipe_stream_output_info *so = &shader->so;
1316 uint32_t enabled_stream_buffers_mask = 0;
1317 int i;
1318
1319 for (i = 0; i < so->num_outputs; i++)
1320 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
1321 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
1322 sctx->b.streamout.stride_in_dw = shader->so.stride;
1323 }
1324
1325 void si_update_shaders(struct si_context *sctx)
1326 {
1327 struct pipe_context *ctx = (struct pipe_context*)sctx;
1328 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1329
1330 /* Update stages before GS. */
1331 if (sctx->tes_shader) {
1332 if (!sctx->tf_state)
1333 si_init_tess_factor_ring(sctx);
1334
1335 /* VS as LS */
1336 si_shader_select(ctx, sctx->vs_shader);
1337 si_pm4_bind_state(sctx, ls, sctx->vs_shader->current->pm4);
1338
1339 if (sctx->tcs_shader) {
1340 si_shader_select(ctx, sctx->tcs_shader);
1341 si_pm4_bind_state(sctx, hs, sctx->tcs_shader->current->pm4);
1342 } else {
1343 if (!sctx->fixed_func_tcs_shader)
1344 si_generate_fixed_func_tcs(sctx);
1345 si_shader_select(ctx, sctx->fixed_func_tcs_shader);
1346 si_pm4_bind_state(sctx, hs,
1347 sctx->fixed_func_tcs_shader->current->pm4);
1348 }
1349
1350 si_shader_select(ctx, sctx->tes_shader);
1351 if (sctx->gs_shader) {
1352 /* TES as ES */
1353 si_pm4_bind_state(sctx, es, sctx->tes_shader->current->pm4);
1354 } else {
1355 /* TES as VS */
1356 si_pm4_bind_state(sctx, vs, sctx->tes_shader->current->pm4);
1357 si_update_so(sctx, sctx->tes_shader);
1358 }
1359 } else if (sctx->gs_shader) {
1360 /* VS as ES */
1361 si_shader_select(ctx, sctx->vs_shader);
1362 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
1363 } else {
1364 /* VS as VS */
1365 si_shader_select(ctx, sctx->vs_shader);
1366 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
1367 si_update_so(sctx, sctx->vs_shader);
1368 }
1369
1370 /* Update GS. */
1371 if (sctx->gs_shader) {
1372 si_shader_select(ctx, sctx->gs_shader);
1373 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
1374 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
1375 si_update_so(sctx, sctx->gs_shader);
1376
1377 if (!sctx->gs_rings)
1378 si_init_gs_rings(sctx);
1379
1380 if (sctx->emitted.named.gs_rings != sctx->gs_rings)
1381 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
1382 si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
1383
1384 si_update_gs_rings(sctx);
1385 } else {
1386 si_pm4_bind_state(sctx, gs_rings, NULL);
1387 si_pm4_bind_state(sctx, gs, NULL);
1388 si_pm4_bind_state(sctx, es, NULL);
1389 }
1390
1391 si_update_vgt_shader_config(sctx);
1392
1393 si_shader_select(ctx, sctx->ps_shader);
1394
1395 if (!sctx->ps_shader->current) {
1396 struct si_shader_selector *sel;
1397
1398 /* use a dummy shader if compiling the shader (variant) failed */
1399 si_make_dummy_ps(sctx);
1400 sel = sctx->dummy_pixel_shader;
1401 si_shader_select(ctx, sel);
1402 sctx->ps_shader->current = sel->current;
1403 }
1404
1405 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
1406
1407 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1408 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
1409 sctx->flatshade != rs->flatshade) {
1410 sctx->sprite_coord_enable = rs->sprite_coord_enable;
1411 sctx->flatshade = rs->flatshade;
1412 si_update_spi_map(sctx);
1413 }
1414
1415 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1416 si_pm4_state_changed(sctx, gs)) {
1417 si_update_spi_tmpring_size(sctx);
1418 }
1419
1420 if (sctx->ps_db_shader_control != sctx->ps_shader->current->db_shader_control) {
1421 sctx->ps_db_shader_control = sctx->ps_shader->current->db_shader_control;
1422 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1423 }
1424
1425 if (sctx->smoothing_enabled != sctx->ps_shader->current->key.ps.poly_line_smoothing) {
1426 sctx->smoothing_enabled = sctx->ps_shader->current->key.ps.poly_line_smoothing;
1427 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1428
1429 if (sctx->b.chip_class == SI)
1430 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1431 }
1432 }
1433
1434 void si_init_shader_functions(struct si_context *sctx)
1435 {
1436 sctx->b.b.create_vs_state = si_create_vs_state;
1437 sctx->b.b.create_tcs_state = si_create_tcs_state;
1438 sctx->b.b.create_tes_state = si_create_tes_state;
1439 sctx->b.b.create_gs_state = si_create_gs_state;
1440 sctx->b.b.create_fs_state = si_create_fs_state;
1441
1442 sctx->b.b.bind_vs_state = si_bind_vs_shader;
1443 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
1444 sctx->b.b.bind_tes_state = si_bind_tes_shader;
1445 sctx->b.b.bind_gs_state = si_bind_gs_shader;
1446 sctx->b.b.bind_fs_state = si_bind_ps_shader;
1447
1448 sctx->b.b.delete_vs_state = si_delete_vs_shader;
1449 sctx->b.b.delete_tcs_state = si_delete_tcs_shader;
1450 sctx->b.b.delete_tes_state = si_delete_tes_shader;
1451 sctx->b.b.delete_gs_state = si_delete_gs_shader;
1452 sctx->b.b.delete_fs_state = si_delete_ps_shader;
1453 }