2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
47 void *si_get_ir_binary(struct si_shader_selector
*sel
)
54 ir_binary
= sel
->tokens
;
55 ir_size
= tgsi_num_tokens(sel
->tokens
) *
56 sizeof(struct tgsi_token
);
61 nir_serialize(&blob
, sel
->nir
);
62 ir_binary
= blob
.data
;
66 unsigned size
= 4 + ir_size
+ sizeof(sel
->so
);
67 char *result
= (char*)MALLOC(size
);
71 *((uint32_t*)result
) = size
;
72 memcpy(result
+ 4, ir_binary
, ir_size
);
73 memcpy(result
+ 4 + ir_size
, &sel
->so
, sizeof(sel
->so
));
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
84 /* data may be NULL if size == 0 */
86 memcpy(ptr
, data
, size
);
87 ptr
+= DIV_ROUND_UP(size
, 4);
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
94 memcpy(data
, ptr
, size
);
95 ptr
+= DIV_ROUND_UP(size
, 4);
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
103 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
106 return write_data(ptr
, data
, size
);
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
113 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
116 assert(*data
== NULL
);
119 *data
= malloc(*size
);
120 return read_data(ptr
, *data
, *size
);
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
127 static void *si_get_shader_binary(struct si_shader
*shader
)
129 /* There is always a size of data followed by the data itself. */
130 unsigned relocs_size
= shader
->binary
.reloc_count
*
131 sizeof(shader
->binary
.relocs
[0]);
132 unsigned disasm_size
= shader
->binary
.disasm_string
?
133 strlen(shader
->binary
.disasm_string
) + 1 : 0;
134 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
135 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
138 4 + /* CRC32 of the data below */
139 align(sizeof(shader
->config
), 4) +
140 align(sizeof(shader
->info
), 4) +
141 4 + align(shader
->binary
.code_size
, 4) +
142 4 + align(shader
->binary
.rodata_size
, 4) +
143 4 + align(relocs_size
, 4) +
144 4 + align(disasm_size
, 4) +
145 4 + align(llvm_ir_size
, 4);
146 void *buffer
= CALLOC(1, size
);
147 uint32_t *ptr
= (uint32_t*)buffer
;
153 ptr
++; /* CRC32 is calculated at the end. */
155 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
156 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
157 ptr
= write_chunk(ptr
, shader
->binary
.code
, shader
->binary
.code_size
);
158 ptr
= write_chunk(ptr
, shader
->binary
.rodata
, shader
->binary
.rodata_size
);
159 ptr
= write_chunk(ptr
, shader
->binary
.relocs
, relocs_size
);
160 ptr
= write_chunk(ptr
, shader
->binary
.disasm_string
, disasm_size
);
161 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
162 assert((char *)ptr
- (char *)buffer
== size
);
165 ptr
= (uint32_t*)buffer
;
167 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
172 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
174 uint32_t *ptr
= (uint32_t*)binary
;
175 uint32_t size
= *ptr
++;
176 uint32_t crc32
= *ptr
++;
179 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
180 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
184 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
185 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
186 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.code
,
187 &shader
->binary
.code_size
);
188 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.rodata
,
189 &shader
->binary
.rodata_size
);
190 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.relocs
, &chunk_size
);
191 shader
->binary
.reloc_count
= chunk_size
/ sizeof(shader
->binary
.relocs
[0]);
192 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.disasm_string
, &chunk_size
);
193 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
199 * Insert a shader into the cache. It's assumed the shader is not in the cache.
200 * Use si_shader_cache_load_shader before calling this.
202 * Returns false on failure, in which case the ir_binary should be freed.
204 bool si_shader_cache_insert_shader(struct si_screen
*sscreen
, void *ir_binary
,
205 struct si_shader
*shader
,
206 bool insert_into_disk_cache
)
209 struct hash_entry
*entry
;
210 uint8_t key
[CACHE_KEY_SIZE
];
212 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
214 return false; /* already added */
216 hw_binary
= si_get_shader_binary(shader
);
220 if (_mesa_hash_table_insert(sscreen
->shader_cache
, ir_binary
,
221 hw_binary
) == NULL
) {
226 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
227 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_binary
,
228 *((uint32_t *)ir_binary
), key
);
229 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
,
230 *((uint32_t *) hw_binary
), NULL
);
236 bool si_shader_cache_load_shader(struct si_screen
*sscreen
, void *ir_binary
,
237 struct si_shader
*shader
)
239 struct hash_entry
*entry
=
240 _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
242 if (sscreen
->disk_shader_cache
) {
243 unsigned char sha1
[CACHE_KEY_SIZE
];
244 size_t tg_size
= *((uint32_t *) ir_binary
);
246 disk_cache_compute_key(sscreen
->disk_shader_cache
,
247 ir_binary
, tg_size
, sha1
);
251 disk_cache_get(sscreen
->disk_shader_cache
,
256 if (binary_size
< sizeof(uint32_t) ||
257 *((uint32_t*)buffer
) != binary_size
) {
258 /* Something has gone wrong discard the item
259 * from the cache and rebuild/link from
262 assert(!"Invalid radeonsi shader disk cache "
265 disk_cache_remove(sscreen
->disk_shader_cache
,
272 if (!si_load_shader_binary(shader
, buffer
)) {
278 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
,
285 if (si_load_shader_binary(shader
, entry
->data
))
290 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
294 static uint32_t si_shader_cache_key_hash(const void *key
)
296 /* The first dword is the key size. */
297 return util_hash_crc32(key
, *(uint32_t*)key
);
300 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
302 uint32_t *keya
= (uint32_t*)a
;
303 uint32_t *keyb
= (uint32_t*)b
;
305 /* The first dword is the key size. */
309 return memcmp(keya
, keyb
, *keya
) == 0;
312 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
314 FREE((void*)entry
->key
);
318 bool si_init_shader_cache(struct si_screen
*sscreen
)
320 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
321 sscreen
->shader_cache
=
322 _mesa_hash_table_create(NULL
,
323 si_shader_cache_key_hash
,
324 si_shader_cache_key_equals
);
326 return sscreen
->shader_cache
!= NULL
;
329 void si_destroy_shader_cache(struct si_screen
*sscreen
)
331 if (sscreen
->shader_cache
)
332 _mesa_hash_table_destroy(sscreen
->shader_cache
,
333 si_destroy_shader_cache_entry
);
334 mtx_destroy(&sscreen
->shader_cache_mutex
);
339 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
340 struct si_shader_selector
*tes
,
341 struct si_pm4_state
*pm4
)
343 struct tgsi_shader_info
*info
= &tes
->info
;
344 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
345 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
346 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
347 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
348 unsigned type
, partitioning
, topology
, distribution_mode
;
350 switch (tes_prim_mode
) {
351 case PIPE_PRIM_LINES
:
352 type
= V_028B6C_TESS_ISOLINE
;
354 case PIPE_PRIM_TRIANGLES
:
355 type
= V_028B6C_TESS_TRIANGLE
;
357 case PIPE_PRIM_QUADS
:
358 type
= V_028B6C_TESS_QUAD
;
365 switch (tes_spacing
) {
366 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
367 partitioning
= V_028B6C_PART_FRAC_ODD
;
369 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
370 partitioning
= V_028B6C_PART_FRAC_EVEN
;
372 case PIPE_TESS_SPACING_EQUAL
:
373 partitioning
= V_028B6C_PART_INTEGER
;
381 topology
= V_028B6C_OUTPUT_POINT
;
382 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
383 topology
= V_028B6C_OUTPUT_LINE
;
384 else if (tes_vertex_order_cw
)
385 /* for some reason, this must be the other way around */
386 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
388 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
390 if (sscreen
->has_distributed_tess
) {
391 if (sscreen
->info
.family
== CHIP_FIJI
||
392 sscreen
->info
.family
>= CHIP_POLARIS10
)
393 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
395 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
397 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
399 si_pm4_set_reg(pm4
, R_028B6C_VGT_TF_PARAM
,
400 S_028B6C_TYPE(type
) |
401 S_028B6C_PARTITIONING(partitioning
) |
402 S_028B6C_TOPOLOGY(topology
) |
403 S_028B6C_DISTRIBUTION_MODE(distribution_mode
));
406 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
407 * whether the "fractional odd" tessellation spacing is used.
409 * Possible VGT configurations and which state should set the register:
411 * Reg set in | VGT shader configuration | Value
412 * ------------------------------------------------------
414 * VS as ES | ES -> GS -> VS | 30
415 * TES as VS | LS -> HS -> VS | 14 or 30
416 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
418 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
420 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
421 struct si_shader_selector
*sel
,
422 struct si_shader
*shader
,
423 struct si_pm4_state
*pm4
)
425 unsigned type
= sel
->type
;
427 if (sscreen
->info
.family
< CHIP_POLARIS10
)
430 /* VS as VS, or VS as ES: */
431 if ((type
== PIPE_SHADER_VERTEX
&&
433 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
434 /* TES as VS, or TES as ES: */
435 type
== PIPE_SHADER_TESS_EVAL
) {
436 unsigned vtx_reuse_depth
= 30;
438 if (type
== PIPE_SHADER_TESS_EVAL
&&
439 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
440 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
441 vtx_reuse_depth
= 14;
443 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
448 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
451 si_pm4_clear_state(shader
->pm4
);
453 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
458 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs
)
460 /* Add the pointer to VBO descriptors. */
461 if (HAVE_32BIT_POINTERS
) {
462 return num_always_on_user_sgprs
+ 1;
464 assert(num_always_on_user_sgprs
% 2 == 0);
465 return num_always_on_user_sgprs
+ 2;
469 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
471 struct si_pm4_state
*pm4
;
472 unsigned vgpr_comp_cnt
;
475 assert(sscreen
->info
.chip_class
<= VI
);
477 pm4
= si_get_shader_pm4_state(shader
);
481 va
= shader
->bo
->gpu_address
;
482 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
484 /* We need at least 2 components for LS.
485 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
486 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
488 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
490 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
491 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
493 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
494 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
495 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
496 S_00B528_DX10_CLAMP(1) |
497 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
498 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
)) |
499 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
502 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
504 struct si_pm4_state
*pm4
;
506 unsigned ls_vgpr_comp_cnt
= 0;
508 pm4
= si_get_shader_pm4_state(shader
);
512 va
= shader
->bo
->gpu_address
;
513 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
515 if (sscreen
->info
.chip_class
>= GFX9
) {
516 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
517 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
519 /* We need at least 2 components for LS.
520 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
521 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
523 ls_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
525 unsigned num_user_sgprs
=
526 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR
);
528 shader
->config
.rsrc2
=
529 S_00B42C_USER_SGPR(num_user_sgprs
) |
530 S_00B42C_USER_SGPR_MSB(num_user_sgprs
>> 5) |
531 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
533 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
534 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
536 shader
->config
.rsrc2
=
537 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
538 S_00B42C_OC_LDS_EN(1) |
539 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
542 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
543 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
544 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
545 S_00B428_DX10_CLAMP(1) |
546 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
547 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
549 if (sscreen
->info
.chip_class
<= VI
) {
550 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
551 shader
->config
.rsrc2
);
555 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
557 struct si_pm4_state
*pm4
;
558 unsigned num_user_sgprs
;
559 unsigned vgpr_comp_cnt
;
563 assert(sscreen
->info
.chip_class
<= VI
);
565 pm4
= si_get_shader_pm4_state(shader
);
569 va
= shader
->bo
->gpu_address
;
570 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
572 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
573 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
574 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
575 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
576 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
577 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
578 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
580 unreachable("invalid shader selector type");
582 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
584 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
585 shader
->selector
->esgs_itemsize
/ 4);
586 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
587 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
588 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
589 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
590 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
591 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
592 S_00B328_DX10_CLAMP(1) |
593 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
594 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
595 S_00B32C_USER_SGPR(num_user_sgprs
) |
596 S_00B32C_OC_LDS_EN(oc_lds_en
) |
597 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
599 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
600 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
602 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
605 static unsigned si_conv_prim_to_gs_out(unsigned mode
)
607 static const int prim_conv
[] = {
608 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
609 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
610 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
611 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
612 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
613 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
614 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
615 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
616 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
617 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
618 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
619 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
620 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
621 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
622 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
624 assert(mode
< ARRAY_SIZE(prim_conv
));
626 return prim_conv
[mode
];
629 struct gfx9_gs_info
{
630 unsigned es_verts_per_subgroup
;
631 unsigned gs_prims_per_subgroup
;
632 unsigned gs_inst_prims_in_subgroup
;
633 unsigned max_prims_per_subgroup
;
637 static void gfx9_get_gs_info(struct si_shader_selector
*es
,
638 struct si_shader_selector
*gs
,
639 struct gfx9_gs_info
*out
)
641 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
642 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
643 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
644 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
646 /* All these are in dwords: */
647 /* We can't allow using the whole LDS, because GS waves compete with
648 * other shader stages for LDS space. */
649 const unsigned max_lds_size
= 8 * 1024;
650 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
651 unsigned esgs_lds_size
;
653 /* All these are per subgroup: */
654 const unsigned max_out_prims
= 32 * 1024;
655 const unsigned max_es_verts
= 255;
656 const unsigned ideal_gs_prims
= 64;
657 unsigned max_gs_prims
, gs_prims
;
658 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
660 if (uses_adjacency
|| gs_num_invocations
> 1)
661 max_gs_prims
= 127 / gs_num_invocations
;
665 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
666 * Make sure we don't go over the maximum value.
668 if (gs
->gs_max_out_vertices
> 0) {
669 max_gs_prims
= MIN2(max_gs_prims
,
671 (gs
->gs_max_out_vertices
* gs_num_invocations
));
673 assert(max_gs_prims
> 0);
675 /* If the primitive has adjacency, halve the number of vertices
676 * that will be reused in multiple primitives.
678 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
680 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
681 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
683 /* Compute ESGS LDS size based on the worst case number of ES vertices
684 * needed to create the target number of GS prims per subgroup.
686 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
688 /* If total LDS usage is too big, refactor partitions based on ratio
689 * of ESGS item sizes.
691 if (esgs_lds_size
> max_lds_size
) {
692 /* Our target GS Prims Per Subgroup was too large. Calculate
693 * the maximum number of GS Prims Per Subgroup that will fit
694 * into LDS, capped by the maximum that the hardware can support.
696 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
698 assert(gs_prims
> 0);
699 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
702 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
703 assert(esgs_lds_size
<= max_lds_size
);
706 /* Now calculate remaining ESGS information. */
708 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
710 es_verts
= max_es_verts
;
712 /* Vertices for adjacency primitives are not always reused, so restore
713 * it for ES_VERTS_PER_SUBGRP.
715 min_es_verts
= gs
->gs_input_verts_per_prim
;
717 /* For normal primitives, the VGT only checks if they are past the ES
718 * verts per subgroup after allocating a full GS primitive and if they
719 * are, kick off a new subgroup. But if those additional ES verts are
720 * unique (e.g. not reused) we need to make sure there is enough LDS
721 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
723 es_verts
-= min_es_verts
- 1;
725 out
->es_verts_per_subgroup
= es_verts
;
726 out
->gs_prims_per_subgroup
= gs_prims
;
727 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
728 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
729 gs
->gs_max_out_vertices
;
730 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
732 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
735 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
737 struct si_shader_selector
*sel
= shader
->selector
;
738 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
739 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
740 struct si_pm4_state
*pm4
;
742 unsigned max_stream
= sel
->max_gs_stream
;
745 pm4
= si_get_shader_pm4_state(shader
);
749 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
750 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, offset
);
752 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
753 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, offset
);
755 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
756 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, offset
);
757 si_pm4_set_reg(pm4
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
758 si_conv_prim_to_gs_out(sel
->gs_output_prim
));
760 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
761 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
763 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
764 assert(offset
< (1 << 15));
766 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, sel
->gs_max_out_vertices
);
768 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, num_components
[0]);
769 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, (max_stream
>= 1) ? num_components
[1] : 0);
770 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, (max_stream
>= 2) ? num_components
[2] : 0);
771 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, (max_stream
>= 3) ? num_components
[3] : 0);
773 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
,
774 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
775 S_028B90_ENABLE(gs_num_invocations
> 0));
777 va
= shader
->bo
->gpu_address
;
778 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
780 if (sscreen
->info
.chip_class
>= GFX9
) {
781 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
782 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
783 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
784 struct gfx9_gs_info gs_info
;
786 if (es_type
== PIPE_SHADER_VERTEX
)
787 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
788 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
789 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
790 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
792 unreachable("invalid shader selector type");
794 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
795 * VGPR[0:4] are always loaded.
797 if (sel
->info
.uses_invocationid
)
798 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
799 else if (sel
->info
.uses_primid
)
800 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
801 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
802 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
804 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
806 unsigned num_user_sgprs
;
807 if (es_type
== PIPE_SHADER_VERTEX
)
808 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
810 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
812 gfx9_get_gs_info(shader
->key
.part
.gs
.es
, sel
, &gs_info
);
814 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
815 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
817 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
818 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
819 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
820 S_00B228_DX10_CLAMP(1) |
821 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
822 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
823 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
824 S_00B22C_USER_SGPR(num_user_sgprs
) |
825 S_00B22C_USER_SGPR_MSB(num_user_sgprs
>> 5) |
826 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
827 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
828 S_00B22C_LDS_SIZE(gs_info
.lds_size
) |
829 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
831 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
832 S_028A44_ES_VERTS_PER_SUBGRP(gs_info
.es_verts_per_subgroup
) |
833 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info
.gs_prims_per_subgroup
) |
834 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info
.gs_inst_prims_in_subgroup
));
835 si_pm4_set_reg(pm4
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
836 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info
.max_prims_per_subgroup
));
837 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
838 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4);
840 if (es_type
== PIPE_SHADER_TESS_EVAL
)
841 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
843 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
846 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
847 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
849 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
850 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
851 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
852 S_00B228_DX10_CLAMP(1) |
853 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
854 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
855 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
856 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
861 * Compute the state for \p shader, which will run as a vertex shader on the
864 * If \p gs is non-NULL, it points to the geometry shader for which this shader
865 * is the copy shader.
867 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
868 struct si_shader_selector
*gs
)
870 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
871 struct si_pm4_state
*pm4
;
872 unsigned num_user_sgprs
;
873 unsigned nparams
, vgpr_comp_cnt
;
876 unsigned window_space
=
877 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
878 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
880 pm4
= si_get_shader_pm4_state(shader
);
884 /* We always write VGT_GS_MODE in the VS state, because every switch
885 * between different shader pipelines involving a different GS or no
886 * GS at all involves a switch of the VS (different GS use different
887 * copy shaders). On the other hand, when the API switches from a GS to
888 * no GS and then back to the same GS used originally, the GS state is
892 unsigned mode
= V_028A40_GS_OFF
;
894 /* PrimID needs GS scenario A. */
896 mode
= V_028A40_GS_SCENARIO_A
;
898 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, S_028A40_MODE(mode
));
899 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, enable_prim_id
);
901 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
,
902 ac_vgt_gs_mode(gs
->gs_max_out_vertices
,
903 sscreen
->info
.chip_class
));
904 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
907 if (sscreen
->info
.chip_class
<= VI
) {
908 /* Reuse needs to be set off if we write oViewport. */
909 si_pm4_set_reg(pm4
, R_028AB4_VGT_REUSE_OFF
,
910 S_028AB4_REUSE_OFF(info
->writes_viewport_index
));
913 va
= shader
->bo
->gpu_address
;
914 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
917 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
918 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
919 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
920 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
921 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
922 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
924 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
926 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
927 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
928 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
930 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
932 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
933 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
934 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
936 unreachable("invalid shader selector type");
938 /* VS is required to export at least one param. */
939 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
940 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
941 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
943 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
944 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
945 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
946 V_02870C_SPI_SHADER_4COMP
:
947 V_02870C_SPI_SHADER_NONE
) |
948 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
949 V_02870C_SPI_SHADER_4COMP
:
950 V_02870C_SPI_SHADER_NONE
) |
951 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
952 V_02870C_SPI_SHADER_4COMP
:
953 V_02870C_SPI_SHADER_NONE
));
955 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
957 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
958 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
959 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
960 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
961 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
962 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
963 S_00B128_DX10_CLAMP(1) |
964 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
965 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
966 S_00B12C_USER_SGPR(num_user_sgprs
) |
967 S_00B12C_OC_LDS_EN(oc_lds_en
) |
968 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
969 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
970 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
971 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
972 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
973 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
975 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
976 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
978 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
979 S_028818_VTX_W0_FMT(1) |
980 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
981 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
982 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
984 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
985 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
987 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
990 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
992 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
993 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
994 !!(info
->colors_read
& 0xf0);
995 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
996 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
998 assert(num_interp
<= 32);
999 return MIN2(num_interp
, 32);
1002 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
1004 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
1005 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
1007 /* If the i-th target format is set, all previous target formats must
1008 * be non-zero to avoid hangs.
1010 for (i
= 0; i
< num_targets
; i
++)
1011 if (!(value
& (0xf << (i
* 4))))
1012 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
1017 static void si_shader_ps(struct si_shader
*shader
)
1019 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1020 struct si_pm4_state
*pm4
;
1021 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1022 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1024 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1026 /* we need to enable at least one of them, otherwise we hang the GPU */
1027 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1028 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1029 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1030 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1031 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1032 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1033 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1034 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1035 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1036 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1037 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1038 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1039 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1040 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1042 /* Validate interpolation optimization flags (read as implications). */
1043 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1044 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1045 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1046 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1047 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1048 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1049 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1050 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1051 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1052 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1053 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1054 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1055 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1056 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1057 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1058 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1059 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1060 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1062 /* Validate cases when the optimizations are off (read as implications). */
1063 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1064 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1065 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1066 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1067 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1068 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1070 pm4
= si_get_shader_pm4_state(shader
);
1074 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1076 * 0 -> Position = pixel center
1077 * 1 -> Position = pixel centroid
1078 * 2 -> Position = at sample position
1080 * From GLSL 4.5 specification, section 7.1:
1081 * "The variable gl_FragCoord is available as an input variable from
1082 * within fragment shaders and it holds the window relative coordinates
1083 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1084 * value can be for any location within the pixel, or one of the
1085 * fragment samples. The use of centroid does not further restrict
1086 * this value to be inside the current primitive."
1088 * Meaning that centroid has no effect and we can return anything within
1089 * the pixel. Thus, return the value at sample position, because that's
1090 * the most accurate one shaders can get.
1092 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1094 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1095 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1096 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1098 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1099 cb_shader_mask
= ac_get_cb_shader_mask(spi_shader_col_format
);
1101 /* Ensure that some export memory is always allocated, for two reasons:
1103 * 1) Correctness: The hardware ignores the EXEC mask if no export
1104 * memory is allocated, so KILL and alpha test do not work correctly
1106 * 2) Performance: Every shader needs at least a NULL export, even when
1107 * it writes no color/depth output. The NULL export instruction
1108 * stalls without this setting.
1110 * Don't add this to CB_SHADER_MASK.
1112 if (!spi_shader_col_format
&&
1113 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1114 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1116 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, input_ena
);
1117 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
,
1118 shader
->config
.spi_ps_input_addr
);
1120 /* Set interpolation controls. */
1121 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
1123 /* Set registers. */
1124 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
1125 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
1127 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
,
1128 ac_get_spi_shader_z_format(info
->writes_z
,
1129 info
->writes_stencil
,
1130 info
->writes_samplemask
));
1132 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
, spi_shader_col_format
);
1133 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, cb_shader_mask
);
1135 va
= shader
->bo
->gpu_address
;
1136 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1137 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1138 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1140 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
1141 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1142 S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
1143 S_00B028_DX10_CLAMP(1) |
1144 S_00B028_FLOAT_MODE(shader
->config
.float_mode
));
1145 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1146 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1147 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1148 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1151 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1152 struct si_shader
*shader
)
1154 switch (shader
->selector
->type
) {
1155 case PIPE_SHADER_VERTEX
:
1156 if (shader
->key
.as_ls
)
1157 si_shader_ls(sscreen
, shader
);
1158 else if (shader
->key
.as_es
)
1159 si_shader_es(sscreen
, shader
);
1161 si_shader_vs(sscreen
, shader
, NULL
);
1163 case PIPE_SHADER_TESS_CTRL
:
1164 si_shader_hs(sscreen
, shader
);
1166 case PIPE_SHADER_TESS_EVAL
:
1167 if (shader
->key
.as_es
)
1168 si_shader_es(sscreen
, shader
);
1170 si_shader_vs(sscreen
, shader
, NULL
);
1172 case PIPE_SHADER_GEOMETRY
:
1173 si_shader_gs(sscreen
, shader
);
1175 case PIPE_SHADER_FRAGMENT
:
1176 si_shader_ps(shader
);
1183 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1185 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1186 if (sctx
->queued
.named
.dsa
)
1187 return sctx
->queued
.named
.dsa
->alpha_func
;
1189 return PIPE_FUNC_ALWAYS
;
1192 static void si_shader_selector_key_vs(struct si_context
*sctx
,
1193 struct si_shader_selector
*vs
,
1194 struct si_shader_key
*key
,
1195 struct si_vs_prolog_bits
*prolog_key
)
1197 if (!sctx
->vertex_elements
||
1198 vs
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
])
1201 prolog_key
->instance_divisor_is_one
=
1202 sctx
->vertex_elements
->instance_divisor_is_one
;
1203 prolog_key
->instance_divisor_is_fetched
=
1204 sctx
->vertex_elements
->instance_divisor_is_fetched
;
1206 /* Prefer a monolithic shader to allow scheduling divisions around
1208 if (prolog_key
->instance_divisor_is_fetched
)
1209 key
->opt
.prefer_mono
= 1;
1211 unsigned count
= MIN2(vs
->info
.num_inputs
,
1212 sctx
->vertex_elements
->count
);
1213 memcpy(key
->mono
.vs_fix_fetch
, sctx
->vertex_elements
->fix_fetch
, count
);
1216 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1217 struct si_shader_selector
*vs
,
1218 struct si_shader_key
*key
)
1220 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1222 key
->opt
.clip_disable
=
1223 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1224 (vs
->info
.clipdist_writemask
||
1225 vs
->info
.writes_clipvertex
) &&
1226 !vs
->info
.culldist_writemask
;
1228 /* Find out if PS is disabled. */
1229 bool ps_disabled
= true;
1231 const struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1232 bool alpha_to_coverage
= blend
&& blend
->alpha_to_coverage
;
1233 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1234 ps
->info
.writes_z
||
1235 ps
->info
.writes_stencil
||
1236 ps
->info
.writes_samplemask
||
1237 alpha_to_coverage
||
1238 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1239 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1241 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1244 !ps
->info
.writes_memory
);
1247 /* Find out which VS outputs aren't used by the PS. */
1248 uint64_t outputs_written
= vs
->outputs_written_before_ps
;
1249 uint64_t inputs_read
= 0;
1251 /* Ignore outputs that are not passed from VS to PS. */
1252 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0, true)) |
1253 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0, true)) |
1254 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX
, 0, true)));
1257 inputs_read
= ps
->inputs_read
;
1260 uint64_t linked
= outputs_written
& inputs_read
;
1262 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1265 /* Compute the key for the hw shader variant */
1266 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1267 struct si_shader_selector
*sel
,
1268 struct si_shader_key
*key
)
1270 struct si_context
*sctx
= (struct si_context
*)ctx
;
1272 memset(key
, 0, sizeof(*key
));
1274 switch (sel
->type
) {
1275 case PIPE_SHADER_VERTEX
:
1276 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1278 if (sctx
->tes_shader
.cso
)
1280 else if (sctx
->gs_shader
.cso
)
1283 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1285 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1286 key
->mono
.u
.vs_export_prim_id
= 1;
1289 case PIPE_SHADER_TESS_CTRL
:
1290 if (sctx
->chip_class
>= GFX9
) {
1291 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1292 key
, &key
->part
.tcs
.ls_prolog
);
1293 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1295 /* When the LS VGPR fix is needed, monolithic shaders
1297 * - avoid initializing EXEC in both the LS prolog
1298 * and the LS main part when !vs_needs_prolog
1299 * - remove the fixup for unused input VGPRs
1301 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1303 /* The LS output / HS input layout can be communicated
1304 * directly instead of via user SGPRs for merged LS-HS.
1305 * The LS VGPR fix prefers this too.
1307 key
->opt
.prefer_mono
= 1;
1310 key
->part
.tcs
.epilog
.prim_mode
=
1311 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1312 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1313 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1314 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1315 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1317 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1318 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1320 case PIPE_SHADER_TESS_EVAL
:
1321 if (sctx
->gs_shader
.cso
)
1324 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1326 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1327 key
->mono
.u
.vs_export_prim_id
= 1;
1330 case PIPE_SHADER_GEOMETRY
:
1331 if (sctx
->chip_class
>= GFX9
) {
1332 if (sctx
->tes_shader
.cso
) {
1333 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1335 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1336 key
, &key
->part
.gs
.vs_prolog
);
1337 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1338 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
1341 /* Merged ES-GS can have unbalanced wave usage.
1343 * ES threads are per-vertex, while GS threads are
1344 * per-primitive. So without any amplification, there
1345 * are fewer GS threads than ES threads, which can result
1346 * in empty (no-op) GS waves. With too much amplification,
1347 * there are more GS threads than ES threads, which
1348 * can result in empty (no-op) ES waves.
1350 * Non-monolithic shaders are implemented by setting EXEC
1351 * at the beginning of shader parts, and don't jump to
1352 * the end if EXEC is 0.
1354 * Monolithic shaders use conditional blocks, so they can
1355 * jump and skip empty waves of ES or GS. So set this to
1356 * always use optimized variants, which are monolithic.
1358 key
->opt
.prefer_mono
= 1;
1360 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1362 case PIPE_SHADER_FRAGMENT
: {
1363 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1364 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1366 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1367 sel
->info
.colors_written
== 0x1)
1368 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1371 /* Select the shader color format based on whether
1372 * blending or alpha are needed.
1374 key
->part
.ps
.epilog
.spi_shader_col_format
=
1375 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1376 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1377 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1378 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1379 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1380 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1381 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1382 sctx
->framebuffer
.spi_shader_col_format
);
1383 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1385 /* The output for dual source blending should have
1386 * the same format as the first output.
1388 if (blend
->dual_src_blend
)
1389 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1390 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1392 key
->part
.ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
1394 /* If alpha-to-coverage is enabled, we have to export alpha
1395 * even if there is no color buffer.
1397 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1398 blend
&& blend
->alpha_to_coverage
)
1399 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1401 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1402 * to the range supported by the type if a channel has less
1403 * than 16 bits and the export format is 16_ABGR.
1405 if (sctx
->chip_class
<= CIK
&& sctx
->family
!= CHIP_HAWAII
) {
1406 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1407 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1410 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1411 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1412 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1413 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1414 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1417 bool is_poly
= !util_prim_is_points_or_lines(sctx
->current_rast_prim
);
1418 bool is_line
= util_prim_is_lines(sctx
->current_rast_prim
);
1420 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1421 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1423 if (sctx
->queued
.named
.blend
) {
1424 key
->part
.ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
1425 rs
->multisample_enable
;
1428 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1429 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1430 (is_line
&& rs
->line_smooth
)) &&
1431 sctx
->framebuffer
.nr_samples
<= 1;
1432 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1434 if (sctx
->ps_iter_samples
> 1 &&
1435 sel
->info
.reads_samplemask
) {
1436 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
1437 util_logbase2(sctx
->ps_iter_samples
);
1440 if (rs
->force_persample_interp
&&
1441 rs
->multisample_enable
&&
1442 sctx
->framebuffer
.nr_samples
> 1 &&
1443 sctx
->ps_iter_samples
> 1) {
1444 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1445 sel
->info
.uses_persp_center
||
1446 sel
->info
.uses_persp_centroid
;
1448 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1449 sel
->info
.uses_linear_center
||
1450 sel
->info
.uses_linear_centroid
;
1451 } else if (rs
->multisample_enable
&&
1452 sctx
->framebuffer
.nr_samples
> 1) {
1453 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1454 sel
->info
.uses_persp_center
&&
1455 sel
->info
.uses_persp_centroid
;
1456 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1457 sel
->info
.uses_linear_center
&&
1458 sel
->info
.uses_linear_centroid
;
1460 /* Make sure SPI doesn't compute more than 1 pair
1461 * of (i,j), which is the optimization here. */
1462 key
->part
.ps
.prolog
.force_persp_center_interp
=
1463 sel
->info
.uses_persp_center
+
1464 sel
->info
.uses_persp_centroid
+
1465 sel
->info
.uses_persp_sample
> 1;
1467 key
->part
.ps
.prolog
.force_linear_center_interp
=
1468 sel
->info
.uses_linear_center
+
1469 sel
->info
.uses_linear_centroid
+
1470 sel
->info
.uses_linear_sample
> 1;
1472 if (sel
->info
.opcode_count
[TGSI_OPCODE_INTERP_SAMPLE
])
1473 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
1476 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1478 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1479 if (sctx
->ps_uses_fbfetch
) {
1480 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
1481 struct pipe_resource
*tex
= cb0
->texture
;
1483 /* 1D textures are allocated and used as 2D on GFX9. */
1484 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
1485 key
->mono
.u
.ps
.fbfetch_is_1D
= sctx
->chip_class
!= GFX9
&&
1486 (tex
->target
== PIPE_TEXTURE_1D
||
1487 tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
1488 key
->mono
.u
.ps
.fbfetch_layered
= tex
->target
== PIPE_TEXTURE_1D_ARRAY
||
1489 tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
1490 tex
->target
== PIPE_TEXTURE_CUBE
||
1491 tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
1492 tex
->target
== PIPE_TEXTURE_3D
;
1500 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
1501 memset(&key
->opt
, 0, sizeof(key
->opt
));
1504 static void si_build_shader_variant(struct si_shader
*shader
,
1508 struct si_shader_selector
*sel
= shader
->selector
;
1509 struct si_screen
*sscreen
= sel
->screen
;
1510 struct ac_llvm_compiler
*compiler
;
1511 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
1514 if (thread_index
>= 0) {
1516 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler_lowp
));
1517 compiler
= &sscreen
->compiler_lowp
[thread_index
];
1519 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
1520 compiler
= &sscreen
->compiler
[thread_index
];
1525 assert(!low_priority
);
1526 compiler
= shader
->compiler_ctx_state
.compiler
;
1529 r
= si_shader_create(sscreen
, compiler
, shader
, debug
);
1531 PRINT_ERR("Failed to build shader variant (type=%u) %d\n",
1533 shader
->compilation_failed
= true;
1537 if (shader
->compiler_ctx_state
.is_debug_context
) {
1538 FILE *f
= open_memstream(&shader
->shader_log
,
1539 &shader
->shader_log_size
);
1541 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
, false);
1546 si_shader_init_pm4_state(sscreen
, shader
);
1549 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
1551 struct si_shader
*shader
= (struct si_shader
*)job
;
1553 assert(thread_index
>= 0);
1555 si_build_shader_variant(shader
, thread_index
, true);
1558 static const struct si_shader_key zeroed
;
1560 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
1561 struct si_shader_selector
*sel
,
1562 struct si_compiler_ctx_state
*compiler_state
,
1563 struct si_shader_key
*key
)
1565 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
1568 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
1573 /* We can leave the fence as permanently signaled because the
1574 * main part becomes visible globally only after it has been
1576 util_queue_fence_init(&main_part
->ready
);
1578 main_part
->selector
= sel
;
1579 main_part
->key
.as_es
= key
->as_es
;
1580 main_part
->key
.as_ls
= key
->as_ls
;
1581 main_part
->is_monolithic
= false;
1583 if (si_compile_tgsi_shader(sscreen
, compiler_state
->compiler
,
1584 main_part
, &compiler_state
->debug
) != 0) {
1593 /* Select the hw shader variant depending on the current state. */
1594 static int si_shader_select_with_key(struct si_screen
*sscreen
,
1595 struct si_shader_ctx_state
*state
,
1596 struct si_compiler_ctx_state
*compiler_state
,
1597 struct si_shader_key
*key
,
1600 struct si_shader_selector
*sel
= state
->cso
;
1601 struct si_shader_selector
*previous_stage_sel
= NULL
;
1602 struct si_shader
*current
= state
->current
;
1603 struct si_shader
*iter
, *shader
= NULL
;
1606 /* Check if we don't need to change anything.
1607 * This path is also used for most shaders that don't need multiple
1608 * variants, it will cost just a computation of the key and this
1610 if (likely(current
&&
1611 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
1612 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
1613 if (current
->is_optimized
) {
1614 memset(&key
->opt
, 0, sizeof(key
->opt
));
1615 goto current_not_ready
;
1618 util_queue_fence_wait(¤t
->ready
);
1621 return current
->compilation_failed
? -1 : 0;
1625 /* This must be done before the mutex is locked, because async GS
1626 * compilation calls this function too, and therefore must enter
1629 * Only wait if we are in a draw call. Don't wait if we are
1630 * in a compiler thread.
1632 if (thread_index
< 0)
1633 util_queue_fence_wait(&sel
->ready
);
1635 mtx_lock(&sel
->mutex
);
1637 /* Find the shader variant. */
1638 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
1639 /* Don't check the "current" shader. We checked it above. */
1640 if (current
!= iter
&&
1641 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
1642 mtx_unlock(&sel
->mutex
);
1644 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
1645 /* If it's an optimized shader and its compilation has
1646 * been started but isn't done, use the unoptimized
1647 * shader so as not to cause a stall due to compilation.
1649 if (iter
->is_optimized
) {
1650 memset(&key
->opt
, 0, sizeof(key
->opt
));
1654 util_queue_fence_wait(&iter
->ready
);
1657 if (iter
->compilation_failed
) {
1658 return -1; /* skip the draw call */
1661 state
->current
= iter
;
1666 /* Build a new shader. */
1667 shader
= CALLOC_STRUCT(si_shader
);
1669 mtx_unlock(&sel
->mutex
);
1673 util_queue_fence_init(&shader
->ready
);
1675 shader
->selector
= sel
;
1677 shader
->compiler_ctx_state
= *compiler_state
;
1679 /* If this is a merged shader, get the first shader's selector. */
1680 if (sscreen
->info
.chip_class
>= GFX9
) {
1681 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1682 previous_stage_sel
= key
->part
.tcs
.ls
;
1683 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1684 previous_stage_sel
= key
->part
.gs
.es
;
1686 /* We need to wait for the previous shader. */
1687 if (previous_stage_sel
&& thread_index
< 0)
1688 util_queue_fence_wait(&previous_stage_sel
->ready
);
1691 /* Compile the main shader part if it doesn't exist. This can happen
1692 * if the initial guess was wrong. */
1693 bool is_pure_monolithic
=
1694 sscreen
->use_monolithic_shaders
||
1695 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
1697 if (!is_pure_monolithic
) {
1700 /* Make sure the main shader part is present. This is needed
1701 * for shaders that can be compiled as VS, LS, or ES, and only
1702 * one of them is compiled at creation.
1704 * For merged shaders, check that the starting shader's main
1707 if (previous_stage_sel
) {
1708 struct si_shader_key shader1_key
= zeroed
;
1710 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1711 shader1_key
.as_ls
= 1;
1712 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1713 shader1_key
.as_es
= 1;
1717 mtx_lock(&previous_stage_sel
->mutex
);
1718 ok
= si_check_missing_main_part(sscreen
,
1720 compiler_state
, &shader1_key
);
1721 mtx_unlock(&previous_stage_sel
->mutex
);
1723 ok
= si_check_missing_main_part(sscreen
, sel
,
1724 compiler_state
, key
);
1728 mtx_unlock(&sel
->mutex
);
1729 return -ENOMEM
; /* skip the draw call */
1733 /* Keep the reference to the 1st shader of merged shaders, so that
1734 * Gallium can't destroy it before we destroy the 2nd shader.
1736 * Set sctx = NULL, because it's unused if we're not releasing
1737 * the shader, and we don't have any sctx here.
1739 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
1740 previous_stage_sel
);
1742 /* Monolithic-only shaders don't make a distinction between optimized
1743 * and unoptimized. */
1744 shader
->is_monolithic
=
1745 is_pure_monolithic
||
1746 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1748 shader
->is_optimized
=
1749 !is_pure_monolithic
&&
1750 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1752 /* If it's an optimized shader, compile it asynchronously. */
1753 if (shader
->is_optimized
&&
1754 !is_pure_monolithic
&&
1756 /* Compile it asynchronously. */
1757 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
1758 shader
, &shader
->ready
,
1759 si_build_shader_variant_low_priority
, NULL
);
1761 /* Add only after the ready fence was reset, to guard against a
1762 * race with si_bind_XX_shader. */
1763 if (!sel
->last_variant
) {
1764 sel
->first_variant
= shader
;
1765 sel
->last_variant
= shader
;
1767 sel
->last_variant
->next_variant
= shader
;
1768 sel
->last_variant
= shader
;
1771 /* Use the default (unoptimized) shader for now. */
1772 memset(&key
->opt
, 0, sizeof(key
->opt
));
1773 mtx_unlock(&sel
->mutex
);
1777 /* Reset the fence before adding to the variant list. */
1778 util_queue_fence_reset(&shader
->ready
);
1780 if (!sel
->last_variant
) {
1781 sel
->first_variant
= shader
;
1782 sel
->last_variant
= shader
;
1784 sel
->last_variant
->next_variant
= shader
;
1785 sel
->last_variant
= shader
;
1788 mtx_unlock(&sel
->mutex
);
1790 assert(!shader
->is_optimized
);
1791 si_build_shader_variant(shader
, thread_index
, false);
1793 util_queue_fence_signal(&shader
->ready
);
1795 if (!shader
->compilation_failed
)
1796 state
->current
= shader
;
1798 return shader
->compilation_failed
? -1 : 0;
1801 static int si_shader_select(struct pipe_context
*ctx
,
1802 struct si_shader_ctx_state
*state
,
1803 struct si_compiler_ctx_state
*compiler_state
)
1805 struct si_context
*sctx
= (struct si_context
*)ctx
;
1806 struct si_shader_key key
;
1808 si_shader_selector_key(ctx
, state
->cso
, &key
);
1809 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
1813 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
1815 struct si_shader_key
*key
)
1817 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
1819 switch (info
->processor
) {
1820 case PIPE_SHADER_VERTEX
:
1821 switch (next_shader
) {
1822 case PIPE_SHADER_GEOMETRY
:
1825 case PIPE_SHADER_TESS_CTRL
:
1826 case PIPE_SHADER_TESS_EVAL
:
1830 /* If POSITION isn't written, it can only be a HW VS
1831 * if streamout is used. If streamout isn't used,
1832 * assume that it's a HW LS. (the next shader is TCS)
1833 * This heuristic is needed for separate shader objects.
1835 if (!info
->writes_position
&& !streamout
)
1840 case PIPE_SHADER_TESS_EVAL
:
1841 if (next_shader
== PIPE_SHADER_GEOMETRY
||
1842 !info
->writes_position
)
1849 * Compile the main shader part or the monolithic shader as part of
1850 * si_shader_selector initialization. Since it can be done asynchronously,
1851 * there is no way to report compile failures to applications.
1853 static void si_init_shader_selector_async(void *job
, int thread_index
)
1855 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
1856 struct si_screen
*sscreen
= sel
->screen
;
1857 struct ac_llvm_compiler
*compiler
;
1858 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
1860 assert(!debug
->debug_message
|| debug
->async
);
1861 assert(thread_index
>= 0);
1862 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
1863 compiler
= &sscreen
->compiler
[thread_index
];
1865 /* Compile the main shader part for use with a prolog and/or epilog.
1866 * If this fails, the driver will try to compile a monolithic shader
1869 if (!sscreen
->use_monolithic_shaders
) {
1870 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
1871 void *ir_binary
= NULL
;
1874 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
1878 /* We can leave the fence signaled because use of the default
1879 * main part is guarded by the selector's ready fence. */
1880 util_queue_fence_init(&shader
->ready
);
1882 shader
->selector
= sel
;
1883 shader
->is_monolithic
= false;
1884 si_parse_next_shader_property(&sel
->info
,
1885 sel
->so
.num_outputs
!= 0,
1888 if (sel
->tokens
|| sel
->nir
)
1889 ir_binary
= si_get_ir_binary(sel
);
1891 /* Try to load the shader from the shader cache. */
1892 mtx_lock(&sscreen
->shader_cache_mutex
);
1895 si_shader_cache_load_shader(sscreen
, ir_binary
, shader
)) {
1896 mtx_unlock(&sscreen
->shader_cache_mutex
);
1897 si_shader_dump_stats_for_shader_db(shader
, debug
);
1899 mtx_unlock(&sscreen
->shader_cache_mutex
);
1901 /* Compile the shader if it hasn't been loaded from the cache. */
1902 if (si_compile_tgsi_shader(sscreen
, compiler
, shader
,
1906 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
1911 mtx_lock(&sscreen
->shader_cache_mutex
);
1912 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
, shader
, true))
1914 mtx_unlock(&sscreen
->shader_cache_mutex
);
1918 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
1920 /* Unset "outputs_written" flags for outputs converted to
1921 * DEFAULT_VAL, so that later inter-shader optimizations don't
1922 * try to eliminate outputs that don't exist in the final
1925 * This is only done if non-monolithic shaders are enabled.
1927 if ((sel
->type
== PIPE_SHADER_VERTEX
||
1928 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
1929 !shader
->key
.as_ls
&&
1930 !shader
->key
.as_es
) {
1933 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
1934 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
1936 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
1939 unsigned name
= sel
->info
.output_semantic_name
[i
];
1940 unsigned index
= sel
->info
.output_semantic_index
[i
];
1944 case TGSI_SEMANTIC_GENERIC
:
1945 /* don't process indices the function can't handle */
1946 if (index
>= SI_MAX_IO_GENERIC
)
1950 id
= si_shader_io_get_unique_index(name
, index
, true);
1951 sel
->outputs_written_before_ps
&= ~(1ull << id
);
1953 case TGSI_SEMANTIC_POSITION
: /* ignore these */
1954 case TGSI_SEMANTIC_PSIZE
:
1955 case TGSI_SEMANTIC_CLIPVERTEX
:
1956 case TGSI_SEMANTIC_EDGEFLAG
:
1963 /* The GS copy shader is always pre-compiled. */
1964 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
1965 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, compiler
, sel
, debug
);
1966 if (!sel
->gs_copy_shader
) {
1967 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
1971 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
1975 void si_schedule_initial_compile(struct si_context
*sctx
, unsigned processor
,
1976 struct util_queue_fence
*ready_fence
,
1977 struct si_compiler_ctx_state
*compiler_ctx_state
,
1978 void *job
, util_queue_execute_func execute
)
1980 util_queue_fence_init(ready_fence
);
1982 struct util_async_debug_callback async_debug
;
1984 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
1986 si_can_dump_shader(sctx
->screen
, processor
);
1989 u_async_debug_init(&async_debug
);
1990 compiler_ctx_state
->debug
= async_debug
.base
;
1993 util_queue_add_job(&sctx
->screen
->shader_compiler_queue
, job
,
1994 ready_fence
, execute
, NULL
);
1997 util_queue_fence_wait(ready_fence
);
1998 u_async_debug_drain(&async_debug
, &sctx
->debug
);
1999 u_async_debug_cleanup(&async_debug
);
2003 /* Return descriptor slot usage masks from the given shader info. */
2004 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
2005 uint32_t *const_and_shader_buffers
,
2006 uint64_t *samplers_and_images
)
2008 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_samplers
;
2010 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
2011 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
2012 /* two 8-byte images share one 16-byte slot */
2013 num_images
= align(util_last_bit(info
->images_declared
), 2);
2014 num_samplers
= util_last_bit(info
->samplers_declared
);
2016 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2017 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
2018 *const_and_shader_buffers
=
2019 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
2021 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2022 start
= si_get_image_slot(num_images
- 1) / 2;
2023 *samplers_and_images
=
2024 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
2027 static void *si_create_shader_selector(struct pipe_context
*ctx
,
2028 const struct pipe_shader_state
*state
)
2030 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2031 struct si_context
*sctx
= (struct si_context
*)ctx
;
2032 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2038 pipe_reference_init(&sel
->reference
, 1);
2039 sel
->screen
= sscreen
;
2040 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
2041 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2043 sel
->so
= state
->stream_output
;
2045 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2046 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2052 tgsi_scan_shader(state
->tokens
, &sel
->info
);
2053 tgsi_scan_tess_ctrl(state
->tokens
, &sel
->info
, &sel
->tcs_info
);
2055 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2057 sel
->nir
= state
->ir
.nir
;
2059 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2060 si_nir_scan_tess_ctrl(sel
->nir
, &sel
->info
, &sel
->tcs_info
);
2065 sel
->type
= sel
->info
.processor
;
2066 p_atomic_inc(&sscreen
->num_shaders_created
);
2067 si_get_active_slot_masks(&sel
->info
,
2068 &sel
->active_const_and_shader_buffers
,
2069 &sel
->active_samplers_and_images
);
2071 /* Record which streamout buffers are enabled. */
2072 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2073 sel
->enabled_streamout_buffer_mask
|=
2074 (1 << sel
->so
.output
[i
].output_buffer
) <<
2075 (sel
->so
.output
[i
].stream
* 4);
2078 /* The prolog is a no-op if there are no inputs. */
2079 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2080 sel
->info
.num_inputs
&&
2081 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
2083 sel
->force_correct_derivs_after_kill
=
2084 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2085 sel
->info
.uses_derivatives
&&
2086 sel
->info
.uses_kill
&&
2087 sctx
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2089 /* Set which opcode uses which (i,j) pair. */
2090 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2091 sel
->info
.uses_persp_centroid
= true;
2093 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2094 sel
->info
.uses_linear_centroid
= true;
2096 if (sel
->info
.uses_persp_opcode_interp_offset
||
2097 sel
->info
.uses_persp_opcode_interp_sample
)
2098 sel
->info
.uses_persp_center
= true;
2100 if (sel
->info
.uses_linear_opcode_interp_offset
||
2101 sel
->info
.uses_linear_opcode_interp_sample
)
2102 sel
->info
.uses_linear_center
= true;
2104 switch (sel
->type
) {
2105 case PIPE_SHADER_GEOMETRY
:
2106 sel
->gs_output_prim
=
2107 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2108 sel
->gs_max_out_vertices
=
2109 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2110 sel
->gs_num_invocations
=
2111 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2112 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2113 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2114 sel
->gs_max_out_vertices
;
2116 sel
->max_gs_stream
= 0;
2117 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2118 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2119 sel
->so
.output
[i
].stream
);
2121 sel
->gs_input_verts_per_prim
=
2122 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2125 case PIPE_SHADER_TESS_CTRL
:
2126 /* Always reserve space for these. */
2127 sel
->patch_outputs_written
|=
2128 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2129 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2131 case PIPE_SHADER_VERTEX
:
2132 case PIPE_SHADER_TESS_EVAL
:
2133 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2134 unsigned name
= sel
->info
.output_semantic_name
[i
];
2135 unsigned index
= sel
->info
.output_semantic_index
[i
];
2138 case TGSI_SEMANTIC_TESSINNER
:
2139 case TGSI_SEMANTIC_TESSOUTER
:
2140 case TGSI_SEMANTIC_PATCH
:
2141 sel
->patch_outputs_written
|=
2142 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2145 case TGSI_SEMANTIC_GENERIC
:
2146 /* don't process indices the function can't handle */
2147 if (index
>= SI_MAX_IO_GENERIC
)
2151 sel
->outputs_written
|=
2152 1ull << si_shader_io_get_unique_index(name
, index
, false);
2153 sel
->outputs_written_before_ps
|=
2154 1ull << si_shader_io_get_unique_index(name
, index
, true);
2156 case TGSI_SEMANTIC_EDGEFLAG
:
2160 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2161 sel
->lshs_vertex_stride
= sel
->esgs_itemsize
;
2163 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2164 * will start on a different bank. (except for the maximum 32*16).
2166 if (sel
->lshs_vertex_stride
< 32*16)
2167 sel
->lshs_vertex_stride
+= 4;
2169 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2170 * conflicts, i.e. each vertex will start at a different bank.
2172 if (sctx
->chip_class
>= GFX9
)
2173 sel
->esgs_itemsize
+= 4;
2175 assert(((sel
->esgs_itemsize
/ 4) & C_028AAC_ITEMSIZE
) == 0);
2178 case PIPE_SHADER_FRAGMENT
:
2179 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2180 unsigned name
= sel
->info
.input_semantic_name
[i
];
2181 unsigned index
= sel
->info
.input_semantic_index
[i
];
2184 case TGSI_SEMANTIC_GENERIC
:
2185 /* don't process indices the function can't handle */
2186 if (index
>= SI_MAX_IO_GENERIC
)
2191 1ull << si_shader_io_get_unique_index(name
, index
, true);
2193 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2198 for (i
= 0; i
< 8; i
++)
2199 if (sel
->info
.colors_written
& (1 << i
))
2200 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2202 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2203 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2204 int index
= sel
->info
.input_semantic_index
[i
];
2205 sel
->color_attr_index
[index
] = i
;
2211 /* PA_CL_VS_OUT_CNTL */
2213 sel
->info
.writes_psize
|| sel
->info
.writes_edgeflag
||
2214 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
2215 sel
->pa_cl_vs_out_cntl
=
2216 S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
2217 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
) |
2218 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
2219 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
2220 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2221 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
2222 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2223 SIX_BITS
: sel
->info
.clipdist_writemask
;
2224 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2225 sel
->info
.num_written_clipdistance
;
2227 /* DB_SHADER_CONTROL */
2228 sel
->db_shader_control
=
2229 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2230 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2231 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2232 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2234 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2235 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2236 sel
->db_shader_control
|=
2237 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2239 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2240 sel
->db_shader_control
|=
2241 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2245 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2247 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2248 * --|-----------|------------|------------|--------------------|-------------------|-------------
2249 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2250 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2251 * 2 | false | true | n/a | LateZ | 1 | 0
2252 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2253 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2255 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2256 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2258 * Don't use ReZ without profiling !!!
2260 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2263 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2265 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2266 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2267 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2268 } else if (sel
->info
.writes_memory
) {
2270 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2271 S_02880C_EXEC_ON_HIER_FAIL(1);
2274 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2277 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2279 si_schedule_initial_compile(sctx
, sel
->info
.processor
, &sel
->ready
,
2280 &sel
->compiler_ctx_state
, sel
,
2281 si_init_shader_selector_async
);
2285 static void si_update_streamout_state(struct si_context
*sctx
)
2287 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2289 if (!shader_with_so
)
2292 sctx
->streamout
.enabled_stream_buffers_mask
=
2293 shader_with_so
->enabled_streamout_buffer_mask
;
2294 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2297 static void si_update_clip_regs(struct si_context
*sctx
,
2298 struct si_shader_selector
*old_hw_vs
,
2299 struct si_shader
*old_hw_vs_variant
,
2300 struct si_shader_selector
*next_hw_vs
,
2301 struct si_shader
*next_hw_vs_variant
)
2305 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2306 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2307 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2308 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2309 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2310 !old_hw_vs_variant
||
2311 !next_hw_vs_variant
||
2312 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2313 next_hw_vs_variant
->key
.opt
.clip_disable
))
2314 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
2317 static void si_update_common_shader_state(struct si_context
*sctx
)
2319 sctx
->uses_bindless_samplers
=
2320 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2321 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2322 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2323 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2324 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2325 sctx
->uses_bindless_images
=
2326 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2327 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2328 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2329 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2330 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2331 sctx
->do_update_shaders
= true;
2334 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2336 struct si_context
*sctx
= (struct si_context
*)ctx
;
2337 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2338 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2339 struct si_shader_selector
*sel
= state
;
2341 if (sctx
->vs_shader
.cso
== sel
)
2344 sctx
->vs_shader
.cso
= sel
;
2345 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2346 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
] : 0;
2348 si_update_common_shader_state(sctx
);
2349 si_update_vs_viewport_state(sctx
);
2350 si_set_active_descriptors_for_shader(sctx
, sel
);
2351 si_update_streamout_state(sctx
);
2352 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2353 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2356 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
2358 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
2359 (sctx
->tes_shader
.cso
&&
2360 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2361 (sctx
->tcs_shader
.cso
&&
2362 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
2363 (sctx
->gs_shader
.cso
&&
2364 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
2365 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
2366 sctx
->ps_shader
.cso
->info
.uses_primid
);
2369 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2371 struct si_context
*sctx
= (struct si_context
*)ctx
;
2372 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2373 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2374 struct si_shader_selector
*sel
= state
;
2375 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
2377 if (sctx
->gs_shader
.cso
== sel
)
2380 sctx
->gs_shader
.cso
= sel
;
2381 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2382 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
2384 si_update_common_shader_state(sctx
);
2385 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2387 if (enable_changed
) {
2388 si_shader_change_notify(sctx
);
2389 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2390 si_update_tess_uses_prim_id(sctx
);
2392 si_update_vs_viewport_state(sctx
);
2393 si_set_active_descriptors_for_shader(sctx
, sel
);
2394 si_update_streamout_state(sctx
);
2395 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2396 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2399 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
2401 struct si_context
*sctx
= (struct si_context
*)ctx
;
2402 struct si_shader_selector
*sel
= state
;
2403 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
2405 if (sctx
->tcs_shader
.cso
== sel
)
2408 sctx
->tcs_shader
.cso
= sel
;
2409 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2410 si_update_tess_uses_prim_id(sctx
);
2412 si_update_common_shader_state(sctx
);
2415 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
2417 si_set_active_descriptors_for_shader(sctx
, sel
);
2420 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
2422 struct si_context
*sctx
= (struct si_context
*)ctx
;
2423 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2424 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2425 struct si_shader_selector
*sel
= state
;
2426 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
2428 if (sctx
->tes_shader
.cso
== sel
)
2431 sctx
->tes_shader
.cso
= sel
;
2432 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
2433 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
2434 si_update_tess_uses_prim_id(sctx
);
2436 si_update_common_shader_state(sctx
);
2437 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2439 if (enable_changed
) {
2440 si_shader_change_notify(sctx
);
2441 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
2443 si_update_vs_viewport_state(sctx
);
2444 si_set_active_descriptors_for_shader(sctx
, sel
);
2445 si_update_streamout_state(sctx
);
2446 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2447 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2450 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
2452 struct si_context
*sctx
= (struct si_context
*)ctx
;
2453 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
2454 struct si_shader_selector
*sel
= state
;
2456 /* skip if supplied shader is one already in use */
2460 sctx
->ps_shader
.cso
= sel
;
2461 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
2463 si_update_common_shader_state(sctx
);
2465 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2466 si_update_tess_uses_prim_id(sctx
);
2469 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
2470 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
2472 if (sctx
->screen
->has_out_of_order_rast
&&
2474 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
2475 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
2476 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
2477 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2479 si_set_active_descriptors_for_shader(sctx
, sel
);
2480 si_update_ps_colorbuf0_slot(sctx
);
2483 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
2485 if (shader
->is_optimized
) {
2486 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
2490 util_queue_fence_destroy(&shader
->ready
);
2493 switch (shader
->selector
->type
) {
2494 case PIPE_SHADER_VERTEX
:
2495 if (shader
->key
.as_ls
) {
2496 assert(sctx
->chip_class
<= VI
);
2497 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
2498 } else if (shader
->key
.as_es
) {
2499 assert(sctx
->chip_class
<= VI
);
2500 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2502 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2505 case PIPE_SHADER_TESS_CTRL
:
2506 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
2508 case PIPE_SHADER_TESS_EVAL
:
2509 if (shader
->key
.as_es
) {
2510 assert(sctx
->chip_class
<= VI
);
2511 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2513 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2516 case PIPE_SHADER_GEOMETRY
:
2517 if (shader
->is_gs_copy_shader
)
2518 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2520 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
2522 case PIPE_SHADER_FRAGMENT
:
2523 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
2528 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
2529 si_shader_destroy(shader
);
2533 void si_destroy_shader_selector(struct si_context
*sctx
,
2534 struct si_shader_selector
*sel
)
2536 struct si_shader
*p
= sel
->first_variant
, *c
;
2537 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
2538 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
2539 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
2540 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
2541 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
2542 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
2545 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
2547 if (current_shader
[sel
->type
]->cso
== sel
) {
2548 current_shader
[sel
->type
]->cso
= NULL
;
2549 current_shader
[sel
->type
]->current
= NULL
;
2553 c
= p
->next_variant
;
2554 si_delete_shader(sctx
, p
);
2558 if (sel
->main_shader_part
)
2559 si_delete_shader(sctx
, sel
->main_shader_part
);
2560 if (sel
->main_shader_part_ls
)
2561 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
2562 if (sel
->main_shader_part_es
)
2563 si_delete_shader(sctx
, sel
->main_shader_part_es
);
2564 if (sel
->gs_copy_shader
)
2565 si_delete_shader(sctx
, sel
->gs_copy_shader
);
2567 util_queue_fence_destroy(&sel
->ready
);
2568 mtx_destroy(&sel
->mutex
);
2570 ralloc_free(sel
->nir
);
2574 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
2576 struct si_context
*sctx
= (struct si_context
*)ctx
;
2577 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
2579 si_shader_selector_reference(sctx
, &sel
, NULL
);
2582 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
2583 struct si_shader
*vs
, unsigned name
,
2584 unsigned index
, unsigned interpolate
)
2586 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
2587 unsigned j
, offset
, ps_input_cntl
= 0;
2589 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2590 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
))
2591 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
2593 if (name
== TGSI_SEMANTIC_PCOORD
||
2594 (name
== TGSI_SEMANTIC_TEXCOORD
&&
2595 sctx
->sprite_coord_enable
& (1 << index
))) {
2596 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
2599 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
2600 if (name
== vsinfo
->output_semantic_name
[j
] &&
2601 index
== vsinfo
->output_semantic_index
[j
]) {
2602 offset
= vs
->info
.vs_output_param_offset
[j
];
2604 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
2605 /* The input is loaded from parameter memory. */
2606 ps_input_cntl
|= S_028644_OFFSET(offset
);
2607 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2608 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
2609 /* This can happen with depth-only rendering. */
2612 /* The input is a DEFAULT_VAL constant. */
2613 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
2614 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
2615 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
2618 ps_input_cntl
= S_028644_OFFSET(0x20) |
2619 S_028644_DEFAULT_VAL(offset
);
2625 if (name
== TGSI_SEMANTIC_PRIMID
)
2626 /* PrimID is written after the last output. */
2627 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
2628 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2629 /* No corresponding output found, load defaults into input.
2630 * Don't set any other bits.
2631 * (FLAT_SHADE=1 completely changes behavior) */
2632 ps_input_cntl
= S_028644_OFFSET(0x20);
2633 /* D3D 9 behaviour. GL is undefined */
2634 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
2635 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
2637 return ps_input_cntl
;
2640 static void si_emit_spi_map(struct si_context
*sctx
)
2642 struct si_shader
*ps
= sctx
->ps_shader
.current
;
2643 struct si_shader
*vs
= si_get_vs_state(sctx
);
2644 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
2645 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
2646 unsigned spi_ps_input_cntl
[32];
2648 if (!ps
|| !ps
->selector
->info
.num_inputs
)
2651 num_interp
= si_get_ps_num_interp(ps
);
2652 assert(num_interp
> 0);
2654 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
2655 unsigned name
= psinfo
->input_semantic_name
[i
];
2656 unsigned index
= psinfo
->input_semantic_index
[i
];
2657 unsigned interpolate
= psinfo
->input_interpolate
[i
];
2659 spi_ps_input_cntl
[num_written
++] = si_get_ps_input_cntl(sctx
, vs
, name
,
2660 index
, interpolate
);
2662 if (name
== TGSI_SEMANTIC_COLOR
) {
2663 assert(index
< ARRAY_SIZE(bcol_interp
));
2664 bcol_interp
[index
] = interpolate
;
2668 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
2669 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
2671 for (i
= 0; i
< 2; i
++) {
2672 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
2675 spi_ps_input_cntl
[num_written
++] =
2676 si_get_ps_input_cntl(sctx
, vs
, bcol
, i
, bcol_interp
[i
]);
2680 assert(num_interp
== num_written
);
2682 /* R_028644_SPI_PS_INPUT_CNTL_0 */
2683 /* Dota 2: Only ~16% of SPI map updates set different values. */
2684 /* Talos: Only ~9% of SPI map updates set different values. */
2685 radeon_opt_set_context_regn(sctx
, R_028644_SPI_PS_INPUT_CNTL_0
,
2687 sctx
->tracked_regs
.spi_ps_input_cntl
, num_interp
);
2691 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2693 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
2695 if (sctx
->init_config_has_vgt_flush
)
2698 /* Done by Vulkan before VGT_FLUSH. */
2699 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2700 si_pm4_cmd_add(sctx
->init_config
,
2701 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2702 si_pm4_cmd_end(sctx
->init_config
, false);
2704 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2705 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2706 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2707 si_pm4_cmd_end(sctx
->init_config
, false);
2708 sctx
->init_config_has_vgt_flush
= true;
2711 /* Initialize state related to ESGS / GSVS ring buffers */
2712 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
2714 struct si_shader_selector
*es
=
2715 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
2716 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
2717 struct si_pm4_state
*pm4
;
2719 /* Chip constants. */
2720 unsigned num_se
= sctx
->screen
->info
.max_se
;
2721 unsigned wave_size
= 64;
2722 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
2723 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2724 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2726 unsigned gs_vertex_reuse
= (sctx
->chip_class
>= VI
? 32 : 16) * num_se
;
2727 unsigned alignment
= 256 * num_se
;
2728 /* The maximum size is 63.999 MB per SE. */
2729 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
2731 /* Calculate the minimum size. */
2732 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
2733 wave_size
, alignment
);
2735 /* These are recommended sizes, not minimum sizes. */
2736 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
2737 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
2738 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
2739 gs
->max_gsvs_emit_size
;
2741 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
2742 esgs_ring_size
= align(esgs_ring_size
, alignment
);
2743 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
2745 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
2746 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
2748 /* Some rings don't have to be allocated if shaders don't use them.
2749 * (e.g. no varyings between ES and GS or GS and VS)
2751 * GFX9 doesn't have the ESGS ring.
2753 bool update_esgs
= sctx
->chip_class
<= VI
&&
2755 (!sctx
->esgs_ring
||
2756 sctx
->esgs_ring
->width0
< esgs_ring_size
);
2757 bool update_gsvs
= gsvs_ring_size
&&
2758 (!sctx
->gsvs_ring
||
2759 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
2761 if (!update_esgs
&& !update_gsvs
)
2765 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
2767 pipe_aligned_buffer_create(sctx
->b
.screen
,
2768 SI_RESOURCE_FLAG_UNMAPPABLE
,
2770 esgs_ring_size
, alignment
);
2771 if (!sctx
->esgs_ring
)
2776 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
2778 pipe_aligned_buffer_create(sctx
->b
.screen
,
2779 SI_RESOURCE_FLAG_UNMAPPABLE
,
2781 gsvs_ring_size
, alignment
);
2782 if (!sctx
->gsvs_ring
)
2786 /* Create the "init_config_gs_rings" state. */
2787 pm4
= CALLOC_STRUCT(si_pm4_state
);
2791 if (sctx
->chip_class
>= CIK
) {
2792 if (sctx
->esgs_ring
) {
2793 assert(sctx
->chip_class
<= VI
);
2794 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
2795 sctx
->esgs_ring
->width0
/ 256);
2797 if (sctx
->gsvs_ring
)
2798 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
2799 sctx
->gsvs_ring
->width0
/ 256);
2801 if (sctx
->esgs_ring
)
2802 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
2803 sctx
->esgs_ring
->width0
/ 256);
2804 if (sctx
->gsvs_ring
)
2805 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
2806 sctx
->gsvs_ring
->width0
/ 256);
2809 /* Set the state. */
2810 if (sctx
->init_config_gs_rings
)
2811 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
2812 sctx
->init_config_gs_rings
= pm4
;
2814 if (!sctx
->init_config_has_vgt_flush
) {
2815 si_init_config_add_vgt_flush(sctx
);
2816 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
2819 /* Flush the context to re-emit both init_config states. */
2820 sctx
->initial_gfx_cs_size
= 0; /* force flush */
2821 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
2823 /* Set ring bindings. */
2824 if (sctx
->esgs_ring
) {
2825 assert(sctx
->chip_class
<= VI
);
2826 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
,
2827 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2828 true, true, 4, 64, 0);
2829 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
,
2830 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2831 false, false, 0, 0, 0);
2833 if (sctx
->gsvs_ring
) {
2834 si_set_ring_buffer(sctx
, SI_RING_GSVS
,
2835 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
2836 false, false, 0, 0, 0);
2842 static void si_shader_lock(struct si_shader
*shader
)
2844 mtx_lock(&shader
->selector
->mutex
);
2845 if (shader
->previous_stage_sel
) {
2846 assert(shader
->previous_stage_sel
!= shader
->selector
);
2847 mtx_lock(&shader
->previous_stage_sel
->mutex
);
2851 static void si_shader_unlock(struct si_shader
*shader
)
2853 if (shader
->previous_stage_sel
)
2854 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
2855 mtx_unlock(&shader
->selector
->mutex
);
2859 * @returns 1 if \p sel has been updated to use a new scratch buffer
2861 * < 0 if there was a failure
2863 static int si_update_scratch_buffer(struct si_context
*sctx
,
2864 struct si_shader
*shader
)
2866 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
2872 /* This shader doesn't need a scratch buffer */
2873 if (shader
->config
.scratch_bytes_per_wave
== 0)
2876 /* Prevent race conditions when updating:
2877 * - si_shader::scratch_bo
2878 * - si_shader::binary::code
2879 * - si_shader::previous_stage::binary::code.
2881 si_shader_lock(shader
);
2883 /* This shader is already configured to use the current
2884 * scratch buffer. */
2885 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
2886 si_shader_unlock(shader
);
2890 assert(sctx
->scratch_buffer
);
2892 if (shader
->previous_stage
)
2893 si_shader_apply_scratch_relocs(shader
->previous_stage
, scratch_va
);
2895 si_shader_apply_scratch_relocs(shader
, scratch_va
);
2897 /* Replace the shader bo with a new bo that has the relocs applied. */
2898 r
= si_shader_binary_upload(sctx
->screen
, shader
);
2900 si_shader_unlock(shader
);
2904 /* Update the shader state to use the new shader bo. */
2905 si_shader_init_pm4_state(sctx
->screen
, shader
);
2907 r600_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
2909 si_shader_unlock(shader
);
2913 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
2915 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
2918 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
2920 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
2923 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
2925 if (!sctx
->tes_shader
.cso
)
2926 return NULL
; /* tessellation disabled */
2928 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
2929 sctx
->fixed_func_tcs_shader
.current
;
2932 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
2936 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
2937 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
2938 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
2939 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
2941 if (sctx
->tes_shader
.cso
) {
2942 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2944 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(tcs
));
2949 static bool si_update_scratch_relocs(struct si_context
*sctx
)
2951 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2954 /* Update the shaders, so that they are using the latest scratch.
2955 * The scratch buffer may have been changed since these shaders were
2956 * last used, so we still need to try to update them, even if they
2957 * require scratch buffers smaller than the current size.
2959 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
2963 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
2965 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
2969 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
2971 r
= si_update_scratch_buffer(sctx
, tcs
);
2975 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
2977 /* VS can be bound as LS, ES, or VS. */
2978 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
2982 if (sctx
->tes_shader
.current
)
2983 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
2984 else if (sctx
->gs_shader
.current
)
2985 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
2987 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
2990 /* TES can be bound as ES or VS. */
2991 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
2995 if (sctx
->gs_shader
.current
)
2996 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
2998 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3004 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
3006 unsigned current_scratch_buffer_size
=
3007 si_get_current_scratch_buffer_size(sctx
);
3008 unsigned scratch_bytes_per_wave
=
3009 si_get_max_scratch_bytes_per_wave(sctx
);
3010 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
3011 sctx
->scratch_waves
;
3012 unsigned spi_tmpring_size
;
3014 if (scratch_needed_size
> 0) {
3015 if (scratch_needed_size
> current_scratch_buffer_size
) {
3016 /* Create a bigger scratch buffer */
3017 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
3019 sctx
->scratch_buffer
=
3020 si_aligned_buffer_create(&sctx
->screen
->b
,
3021 SI_RESOURCE_FLAG_UNMAPPABLE
,
3023 scratch_needed_size
, 256);
3024 if (!sctx
->scratch_buffer
)
3027 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3028 si_context_add_resource_size(sctx
,
3029 &sctx
->scratch_buffer
->b
.b
);
3032 if (!si_update_scratch_relocs(sctx
))
3036 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3037 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
3038 "scratch size should already be aligned correctly.");
3040 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3041 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
3042 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3043 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3044 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3049 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3051 assert(!sctx
->tess_rings
);
3053 /* The address must be aligned to 2^19, because the shader only
3054 * receives the high 13 bits.
3056 sctx
->tess_rings
= pipe_aligned_buffer_create(sctx
->b
.screen
,
3057 SI_RESOURCE_FLAG_32BIT
,
3059 sctx
->screen
->tess_offchip_ring_size
+
3060 sctx
->screen
->tess_factor_ring_size
,
3062 if (!sctx
->tess_rings
)
3065 si_init_config_add_vgt_flush(sctx
);
3067 si_pm4_add_bo(sctx
->init_config
, r600_resource(sctx
->tess_rings
),
3068 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3070 uint64_t factor_va
= r600_resource(sctx
->tess_rings
)->gpu_address
+
3071 sctx
->screen
->tess_offchip_ring_size
;
3073 /* Append these registers to the init config state. */
3074 if (sctx
->chip_class
>= CIK
) {
3075 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3076 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3077 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3079 if (sctx
->chip_class
>= GFX9
)
3080 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3081 S_030944_BASE_HI(factor_va
>> 40));
3082 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3083 sctx
->screen
->vgt_hs_offchip_param
);
3085 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3086 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3087 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3089 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3090 sctx
->screen
->vgt_hs_offchip_param
);
3093 /* Flush the context to re-emit the init_config state.
3094 * This is done only once in a lifetime of a context.
3096 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3097 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3098 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3101 static void si_update_vgt_shader_config(struct si_context
*sctx
)
3103 /* Calculate the index of the config.
3104 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3105 unsigned index
= 2*!!sctx
->tes_shader
.cso
+ !!sctx
->gs_shader
.cso
;
3106 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[index
];
3109 uint32_t stages
= 0;
3111 *pm4
= CALLOC_STRUCT(si_pm4_state
);
3113 if (sctx
->tes_shader
.cso
) {
3114 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3115 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3117 if (sctx
->gs_shader
.cso
)
3118 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3120 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3122 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3123 } else if (sctx
->gs_shader
.cso
) {
3124 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3126 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3129 if (sctx
->chip_class
>= GFX9
)
3130 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3132 si_pm4_set_reg(*pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3134 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3137 bool si_update_shaders(struct si_context
*sctx
)
3139 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3140 struct si_compiler_ctx_state compiler_state
;
3141 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3142 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3143 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3144 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3145 unsigned old_spi_shader_col_format
=
3146 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3149 compiler_state
.compiler
= &sctx
->compiler
;
3150 compiler_state
.debug
= sctx
->debug
;
3151 compiler_state
.is_debug_context
= sctx
->is_debug
;
3153 /* Update stages before GS. */
3154 if (sctx
->tes_shader
.cso
) {
3155 if (!sctx
->tess_rings
) {
3156 si_init_tess_factor_ring(sctx
);
3157 if (!sctx
->tess_rings
)
3162 if (sctx
->chip_class
<= VI
) {
3163 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3167 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3170 if (sctx
->tcs_shader
.cso
) {
3171 r
= si_shader_select(ctx
, &sctx
->tcs_shader
,
3175 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3177 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3178 sctx
->fixed_func_tcs_shader
.cso
=
3179 si_create_fixed_func_tcs(sctx
);
3180 if (!sctx
->fixed_func_tcs_shader
.cso
)
3184 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3188 si_pm4_bind_state(sctx
, hs
,
3189 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3192 if (sctx
->gs_shader
.cso
) {
3194 if (sctx
->chip_class
<= VI
) {
3195 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3199 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3203 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3207 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3209 } else if (sctx
->gs_shader
.cso
) {
3210 if (sctx
->chip_class
<= VI
) {
3212 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3216 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3218 si_pm4_bind_state(sctx
, ls
, NULL
);
3219 si_pm4_bind_state(sctx
, hs
, NULL
);
3223 r
= si_shader_select(ctx
, &sctx
->vs_shader
, &compiler_state
);
3226 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3227 si_pm4_bind_state(sctx
, ls
, NULL
);
3228 si_pm4_bind_state(sctx
, hs
, NULL
);
3232 if (sctx
->gs_shader
.cso
) {
3233 r
= si_shader_select(ctx
, &sctx
->gs_shader
, &compiler_state
);
3236 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3237 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3239 if (!si_update_gs_ring_buffers(sctx
))
3242 si_pm4_bind_state(sctx
, gs
, NULL
);
3243 if (sctx
->chip_class
<= VI
)
3244 si_pm4_bind_state(sctx
, es
, NULL
);
3247 si_update_vgt_shader_config(sctx
);
3249 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3250 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
3252 if (sctx
->ps_shader
.cso
) {
3253 unsigned db_shader_control
;
3255 r
= si_shader_select(ctx
, &sctx
->ps_shader
, &compiler_state
);
3258 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3261 sctx
->ps_shader
.cso
->db_shader_control
|
3262 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3264 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
3265 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3266 sctx
->flatshade
!= rs
->flatshade
) {
3267 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3268 sctx
->flatshade
= rs
->flatshade
;
3269 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.spi_map
);
3272 if (sctx
->screen
->rbplus_allowed
&&
3273 si_pm4_state_changed(sctx
, ps
) &&
3275 old_spi_shader_col_format
!=
3276 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
3277 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3279 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3280 sctx
->ps_db_shader_control
= db_shader_control
;
3281 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3282 if (sctx
->screen
->dpbb_allowed
)
3283 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3286 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3287 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3288 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3290 if (sctx
->chip_class
== SI
)
3291 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3293 if (sctx
->framebuffer
.nr_samples
<= 1)
3294 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3298 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
3299 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
3300 si_pm4_state_enabled_and_changed(sctx
, es
) ||
3301 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
3302 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
3303 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
3304 if (!si_update_spi_tmpring_size(sctx
))
3308 if (sctx
->chip_class
>= CIK
) {
3309 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
3310 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
3311 else if (!sctx
->queued
.named
.ls
)
3312 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
3314 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
3315 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
3316 else if (!sctx
->queued
.named
.hs
)
3317 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
3319 if (si_pm4_state_enabled_and_changed(sctx
, es
))
3320 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
3321 else if (!sctx
->queued
.named
.es
)
3322 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
3324 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
3325 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
3326 else if (!sctx
->queued
.named
.gs
)
3327 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
3329 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
3330 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
3331 else if (!sctx
->queued
.named
.vs
)
3332 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
3334 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
3335 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
3336 else if (!sctx
->queued
.named
.ps
)
3337 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
3340 sctx
->do_update_shaders
= false;
3344 static void si_emit_scratch_state(struct si_context
*sctx
)
3346 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3348 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3349 sctx
->spi_tmpring_size
);
3351 if (sctx
->scratch_buffer
) {
3352 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3353 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
3354 RADEON_PRIO_SCRATCH_BUFFER
);
3358 void si_init_shader_functions(struct si_context
*sctx
)
3360 sctx
->atoms
.s
.spi_map
.emit
= si_emit_spi_map
;
3361 sctx
->atoms
.s
.scratch_state
.emit
= si_emit_scratch_state
;
3363 sctx
->b
.create_vs_state
= si_create_shader_selector
;
3364 sctx
->b
.create_tcs_state
= si_create_shader_selector
;
3365 sctx
->b
.create_tes_state
= si_create_shader_selector
;
3366 sctx
->b
.create_gs_state
= si_create_shader_selector
;
3367 sctx
->b
.create_fs_state
= si_create_shader_selector
;
3369 sctx
->b
.bind_vs_state
= si_bind_vs_shader
;
3370 sctx
->b
.bind_tcs_state
= si_bind_tcs_shader
;
3371 sctx
->b
.bind_tes_state
= si_bind_tes_shader
;
3372 sctx
->b
.bind_gs_state
= si_bind_gs_shader
;
3373 sctx
->b
.bind_fs_state
= si_bind_ps_shader
;
3375 sctx
->b
.delete_vs_state
= si_delete_shader_selector
;
3376 sctx
->b
.delete_tcs_state
= si_delete_shader_selector
;
3377 sctx
->b
.delete_tes_state
= si_delete_shader_selector
;
3378 sctx
->b
.delete_gs_state
= si_delete_shader_selector
;
3379 sctx
->b
.delete_fs_state
= si_delete_shader_selector
;