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radeonsi: split descriptor list dumping
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "sid.h"
30 #include "gfx9d.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/crc32.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
39
40 #include "util/disk_cache.h"
41 #include "util/mesa-sha1.h"
42 #include "ac_exp_param.h"
43
44 /* SHADER_CACHE */
45
46 /**
47 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
48 * integer.
49 */
50 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
51 {
52 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
53 sizeof(struct tgsi_token);
54 unsigned size = 4 + tgsi_size + sizeof(sel->so);
55 char *result = (char*)MALLOC(size);
56
57 if (!result)
58 return NULL;
59
60 *((uint32_t*)result) = size;
61 memcpy(result + 4, sel->tokens, tgsi_size);
62 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
63 return result;
64 }
65
66 /** Copy "data" to "ptr" and return the next dword following copied data. */
67 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
68 {
69 /* data may be NULL if size == 0 */
70 if (size)
71 memcpy(ptr, data, size);
72 ptr += DIV_ROUND_UP(size, 4);
73 return ptr;
74 }
75
76 /** Read data from "ptr". Return the next dword following the data. */
77 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
78 {
79 memcpy(data, ptr, size);
80 ptr += DIV_ROUND_UP(size, 4);
81 return ptr;
82 }
83
84 /**
85 * Write the size as uint followed by the data. Return the next dword
86 * following the copied data.
87 */
88 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
89 {
90 *ptr++ = size;
91 return write_data(ptr, data, size);
92 }
93
94 /**
95 * Read the size as uint followed by the data. Return both via parameters.
96 * Return the next dword following the data.
97 */
98 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
99 {
100 *size = *ptr++;
101 assert(*data == NULL);
102 if (!*size)
103 return ptr;
104 *data = malloc(*size);
105 return read_data(ptr, *data, *size);
106 }
107
108 /**
109 * Return the shader binary in a buffer. The first 4 bytes contain its size
110 * as integer.
111 */
112 static void *si_get_shader_binary(struct si_shader *shader)
113 {
114 /* There is always a size of data followed by the data itself. */
115 unsigned relocs_size = shader->binary.reloc_count *
116 sizeof(shader->binary.relocs[0]);
117 unsigned disasm_size = shader->binary.disasm_string ?
118 strlen(shader->binary.disasm_string) + 1 : 0;
119 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
120 strlen(shader->binary.llvm_ir_string) + 1 : 0;
121 unsigned size =
122 4 + /* total size */
123 4 + /* CRC32 of the data below */
124 align(sizeof(shader->config), 4) +
125 align(sizeof(shader->info), 4) +
126 4 + align(shader->binary.code_size, 4) +
127 4 + align(shader->binary.rodata_size, 4) +
128 4 + align(relocs_size, 4) +
129 4 + align(disasm_size, 4) +
130 4 + align(llvm_ir_size, 4);
131 void *buffer = CALLOC(1, size);
132 uint32_t *ptr = (uint32_t*)buffer;
133
134 if (!buffer)
135 return NULL;
136
137 *ptr++ = size;
138 ptr++; /* CRC32 is calculated at the end. */
139
140 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
141 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
142 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
143 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
144 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
145 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
146 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
147 assert((char *)ptr - (char *)buffer == size);
148
149 /* Compute CRC32. */
150 ptr = (uint32_t*)buffer;
151 ptr++;
152 *ptr = util_hash_crc32(ptr + 1, size - 8);
153
154 return buffer;
155 }
156
157 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
158 {
159 uint32_t *ptr = (uint32_t*)binary;
160 uint32_t size = *ptr++;
161 uint32_t crc32 = *ptr++;
162 unsigned chunk_size;
163
164 if (util_hash_crc32(ptr, size - 8) != crc32) {
165 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
166 return false;
167 }
168
169 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
170 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
171 ptr = read_chunk(ptr, (void**)&shader->binary.code,
172 &shader->binary.code_size);
173 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
174 &shader->binary.rodata_size);
175 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
176 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
177 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
178 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
179
180 return true;
181 }
182
183 /**
184 * Insert a shader into the cache. It's assumed the shader is not in the cache.
185 * Use si_shader_cache_load_shader before calling this.
186 *
187 * Returns false on failure, in which case the tgsi_binary should be freed.
188 */
189 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
190 void *tgsi_binary,
191 struct si_shader *shader,
192 bool insert_into_disk_cache)
193 {
194 void *hw_binary;
195 struct hash_entry *entry;
196 uint8_t key[CACHE_KEY_SIZE];
197
198 entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
199 if (entry)
200 return false; /* already added */
201
202 hw_binary = si_get_shader_binary(shader);
203 if (!hw_binary)
204 return false;
205
206 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
207 hw_binary) == NULL) {
208 FREE(hw_binary);
209 return false;
210 }
211
212 if (sscreen->b.disk_shader_cache && insert_into_disk_cache) {
213 disk_cache_compute_key(sscreen->b.disk_shader_cache, tgsi_binary,
214 *((uint32_t *)tgsi_binary), key);
215 disk_cache_put(sscreen->b.disk_shader_cache, key, hw_binary,
216 *((uint32_t *) hw_binary));
217 }
218
219 return true;
220 }
221
222 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
223 void *tgsi_binary,
224 struct si_shader *shader)
225 {
226 struct hash_entry *entry =
227 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
228 if (!entry) {
229 if (sscreen->b.disk_shader_cache) {
230 unsigned char sha1[CACHE_KEY_SIZE];
231 size_t tg_size = *((uint32_t *) tgsi_binary);
232
233 disk_cache_compute_key(sscreen->b.disk_shader_cache,
234 tgsi_binary, tg_size, sha1);
235
236 size_t binary_size;
237 uint8_t *buffer =
238 disk_cache_get(sscreen->b.disk_shader_cache,
239 sha1, &binary_size);
240 if (!buffer)
241 return false;
242
243 if (binary_size < sizeof(uint32_t) ||
244 *((uint32_t*)buffer) != binary_size) {
245 /* Something has gone wrong discard the item
246 * from the cache and rebuild/link from
247 * source.
248 */
249 assert(!"Invalid radeonsi shader disk cache "
250 "item!");
251
252 disk_cache_remove(sscreen->b.disk_shader_cache,
253 sha1);
254 free(buffer);
255
256 return false;
257 }
258
259 if (!si_load_shader_binary(shader, buffer)) {
260 free(buffer);
261 return false;
262 }
263 free(buffer);
264
265 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary,
266 shader, false))
267 FREE(tgsi_binary);
268 } else {
269 return false;
270 }
271 } else {
272 if (si_load_shader_binary(shader, entry->data))
273 FREE(tgsi_binary);
274 else
275 return false;
276 }
277 p_atomic_inc(&sscreen->b.num_shader_cache_hits);
278 return true;
279 }
280
281 static uint32_t si_shader_cache_key_hash(const void *key)
282 {
283 /* The first dword is the key size. */
284 return util_hash_crc32(key, *(uint32_t*)key);
285 }
286
287 static bool si_shader_cache_key_equals(const void *a, const void *b)
288 {
289 uint32_t *keya = (uint32_t*)a;
290 uint32_t *keyb = (uint32_t*)b;
291
292 /* The first dword is the key size. */
293 if (*keya != *keyb)
294 return false;
295
296 return memcmp(keya, keyb, *keya) == 0;
297 }
298
299 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
300 {
301 FREE((void*)entry->key);
302 FREE(entry->data);
303 }
304
305 bool si_init_shader_cache(struct si_screen *sscreen)
306 {
307 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
308 sscreen->shader_cache =
309 _mesa_hash_table_create(NULL,
310 si_shader_cache_key_hash,
311 si_shader_cache_key_equals);
312
313 return sscreen->shader_cache != NULL;
314 }
315
316 void si_destroy_shader_cache(struct si_screen *sscreen)
317 {
318 if (sscreen->shader_cache)
319 _mesa_hash_table_destroy(sscreen->shader_cache,
320 si_destroy_shader_cache_entry);
321 mtx_destroy(&sscreen->shader_cache_mutex);
322 }
323
324 /* SHADER STATES */
325
326 static void si_set_tesseval_regs(struct si_screen *sscreen,
327 struct si_shader_selector *tes,
328 struct si_pm4_state *pm4)
329 {
330 struct tgsi_shader_info *info = &tes->info;
331 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
332 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
333 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
334 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
335 unsigned type, partitioning, topology, distribution_mode;
336
337 switch (tes_prim_mode) {
338 case PIPE_PRIM_LINES:
339 type = V_028B6C_TESS_ISOLINE;
340 break;
341 case PIPE_PRIM_TRIANGLES:
342 type = V_028B6C_TESS_TRIANGLE;
343 break;
344 case PIPE_PRIM_QUADS:
345 type = V_028B6C_TESS_QUAD;
346 break;
347 default:
348 assert(0);
349 return;
350 }
351
352 switch (tes_spacing) {
353 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
354 partitioning = V_028B6C_PART_FRAC_ODD;
355 break;
356 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
357 partitioning = V_028B6C_PART_FRAC_EVEN;
358 break;
359 case PIPE_TESS_SPACING_EQUAL:
360 partitioning = V_028B6C_PART_INTEGER;
361 break;
362 default:
363 assert(0);
364 return;
365 }
366
367 if (tes_point_mode)
368 topology = V_028B6C_OUTPUT_POINT;
369 else if (tes_prim_mode == PIPE_PRIM_LINES)
370 topology = V_028B6C_OUTPUT_LINE;
371 else if (tes_vertex_order_cw)
372 /* for some reason, this must be the other way around */
373 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
374 else
375 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
376
377 if (sscreen->has_distributed_tess) {
378 if (sscreen->b.family == CHIP_FIJI ||
379 sscreen->b.family >= CHIP_POLARIS10)
380 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
381 else
382 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
383 } else
384 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
385
386 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
387 S_028B6C_TYPE(type) |
388 S_028B6C_PARTITIONING(partitioning) |
389 S_028B6C_TOPOLOGY(topology) |
390 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
391 }
392
393 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
394 * whether the "fractional odd" tessellation spacing is used.
395 *
396 * Possible VGT configurations and which state should set the register:
397 *
398 * Reg set in | VGT shader configuration | Value
399 * ------------------------------------------------------
400 * VS as VS | VS | 30
401 * VS as ES | ES -> GS -> VS | 30
402 * TES as VS | LS -> HS -> VS | 14 or 30
403 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
404 *
405 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
406 */
407 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
408 struct si_shader_selector *sel,
409 struct si_shader *shader,
410 struct si_pm4_state *pm4)
411 {
412 unsigned type = sel->type;
413
414 if (sscreen->b.family < CHIP_POLARIS10)
415 return;
416
417 /* VS as VS, or VS as ES: */
418 if ((type == PIPE_SHADER_VERTEX &&
419 (!shader ||
420 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
421 /* TES as VS, or TES as ES: */
422 type == PIPE_SHADER_TESS_EVAL) {
423 unsigned vtx_reuse_depth = 30;
424
425 if (type == PIPE_SHADER_TESS_EVAL &&
426 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
427 PIPE_TESS_SPACING_FRACTIONAL_ODD)
428 vtx_reuse_depth = 14;
429
430 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
431 vtx_reuse_depth);
432 }
433 }
434
435 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
436 {
437 if (shader->pm4)
438 si_pm4_clear_state(shader->pm4);
439 else
440 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
441
442 return shader->pm4;
443 }
444
445 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
446 {
447 struct si_pm4_state *pm4;
448 unsigned vgpr_comp_cnt;
449 uint64_t va;
450
451 assert(sscreen->b.chip_class <= VI);
452
453 pm4 = si_get_shader_pm4_state(shader);
454 if (!pm4)
455 return;
456
457 va = shader->bo->gpu_address;
458 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
459
460 /* We need at least 2 components for LS.
461 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
462 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
463 */
464 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
465
466 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
467 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
468
469 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
470 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
471 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
472 S_00B528_DX10_CLAMP(1) |
473 S_00B528_FLOAT_MODE(shader->config.float_mode);
474 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR) |
475 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
476 }
477
478 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
479 {
480 struct si_pm4_state *pm4;
481 uint64_t va;
482 unsigned ls_vgpr_comp_cnt = 0;
483
484 pm4 = si_get_shader_pm4_state(shader);
485 if (!pm4)
486 return;
487
488 va = shader->bo->gpu_address;
489 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
490
491 if (sscreen->b.chip_class >= GFX9) {
492 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
493 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, va >> 40);
494
495 /* We need at least 2 components for LS.
496 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
497 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
498 */
499 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
500
501 shader->config.rsrc2 =
502 S_00B42C_USER_SGPR(GFX9_TCS_NUM_USER_SGPR) |
503 S_00B42C_USER_SGPR_MSB(GFX9_TCS_NUM_USER_SGPR >> 5) |
504 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
505 } else {
506 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
507 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
508
509 shader->config.rsrc2 =
510 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
511 S_00B42C_OC_LDS_EN(1) |
512 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
513 }
514
515 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
516 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
517 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
518 S_00B428_DX10_CLAMP(1) |
519 S_00B428_FLOAT_MODE(shader->config.float_mode) |
520 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
521
522 if (sscreen->b.chip_class <= VI) {
523 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
524 shader->config.rsrc2);
525 }
526 }
527
528 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
529 {
530 struct si_pm4_state *pm4;
531 unsigned num_user_sgprs;
532 unsigned vgpr_comp_cnt;
533 uint64_t va;
534 unsigned oc_lds_en;
535
536 assert(sscreen->b.chip_class <= VI);
537
538 pm4 = si_get_shader_pm4_state(shader);
539 if (!pm4)
540 return;
541
542 va = shader->bo->gpu_address;
543 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
544
545 if (shader->selector->type == PIPE_SHADER_VERTEX) {
546 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
547 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
548 num_user_sgprs = SI_VS_NUM_USER_SGPR;
549 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
550 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
551 num_user_sgprs = SI_TES_NUM_USER_SGPR;
552 } else
553 unreachable("invalid shader selector type");
554
555 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
556
557 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
558 shader->selector->esgs_itemsize / 4);
559 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
560 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
561 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
562 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
563 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
564 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
565 S_00B328_DX10_CLAMP(1) |
566 S_00B328_FLOAT_MODE(shader->config.float_mode));
567 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
568 S_00B32C_USER_SGPR(num_user_sgprs) |
569 S_00B32C_OC_LDS_EN(oc_lds_en) |
570 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
571
572 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
573 si_set_tesseval_regs(sscreen, shader->selector, pm4);
574
575 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
576 }
577
578 /**
579 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
580 * geometry shader.
581 */
582 static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
583 {
584 enum chip_class chip_class = sel->screen->b.chip_class;
585 unsigned gs_max_vert_out = sel->gs_max_out_vertices;
586 unsigned cut_mode;
587
588 if (gs_max_vert_out <= 128) {
589 cut_mode = V_028A40_GS_CUT_128;
590 } else if (gs_max_vert_out <= 256) {
591 cut_mode = V_028A40_GS_CUT_256;
592 } else if (gs_max_vert_out <= 512) {
593 cut_mode = V_028A40_GS_CUT_512;
594 } else {
595 assert(gs_max_vert_out <= 1024);
596 cut_mode = V_028A40_GS_CUT_1024;
597 }
598
599 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
600 S_028A40_CUT_MODE(cut_mode)|
601 S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
602 S_028A40_GS_WRITE_OPTIMIZE(1) |
603 S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
604 }
605
606 struct gfx9_gs_info {
607 unsigned es_verts_per_subgroup;
608 unsigned gs_prims_per_subgroup;
609 unsigned gs_inst_prims_in_subgroup;
610 unsigned max_prims_per_subgroup;
611 unsigned lds_size;
612 };
613
614 static void gfx9_get_gs_info(struct si_shader_selector *es,
615 struct si_shader_selector *gs,
616 struct gfx9_gs_info *out)
617 {
618 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
619 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
620 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
621 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
622
623 /* All these are in dwords: */
624 /* We can't allow using the whole LDS, because GS waves compete with
625 * other shader stages for LDS space. */
626 const unsigned max_lds_size = 8 * 1024;
627 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
628 unsigned esgs_lds_size;
629
630 /* All these are per subgroup: */
631 const unsigned max_out_prims = 32 * 1024;
632 const unsigned max_es_verts = 255;
633 const unsigned ideal_gs_prims = 64;
634 unsigned max_gs_prims, gs_prims;
635 unsigned min_es_verts, es_verts, worst_case_es_verts;
636
637 assert(gs_num_invocations <= 32); /* GL maximum */
638
639 if (uses_adjacency || gs_num_invocations > 1)
640 max_gs_prims = 127 / gs_num_invocations;
641 else
642 max_gs_prims = 255;
643
644 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
645 * Make sure we don't go over the maximum value.
646 */
647 max_gs_prims = MIN2(max_gs_prims,
648 max_out_prims /
649 (gs->gs_max_out_vertices * gs_num_invocations));
650 assert(max_gs_prims > 0);
651
652 /* If the primitive has adjacency, halve the number of vertices
653 * that will be reused in multiple primitives.
654 */
655 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
656
657 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
658 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
659
660 /* Compute ESGS LDS size based on the worst case number of ES vertices
661 * needed to create the target number of GS prims per subgroup.
662 */
663 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
664
665 /* If total LDS usage is too big, refactor partitions based on ratio
666 * of ESGS item sizes.
667 */
668 if (esgs_lds_size > max_lds_size) {
669 /* Our target GS Prims Per Subgroup was too large. Calculate
670 * the maximum number of GS Prims Per Subgroup that will fit
671 * into LDS, capped by the maximum that the hardware can support.
672 */
673 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
674 max_gs_prims);
675 assert(gs_prims > 0);
676 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
677 max_es_verts);
678
679 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
680 assert(esgs_lds_size <= max_lds_size);
681 }
682
683 /* Now calculate remaining ESGS information. */
684 if (esgs_lds_size)
685 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
686 else
687 es_verts = max_es_verts;
688
689 /* Vertices for adjacency primitives are not always reused, so restore
690 * it for ES_VERTS_PER_SUBGRP.
691 */
692 min_es_verts = gs->gs_input_verts_per_prim;
693
694 /* For normal primitives, the VGT only checks if they are past the ES
695 * verts per subgroup after allocating a full GS primitive and if they
696 * are, kick off a new subgroup. But if those additional ES verts are
697 * unique (e.g. not reused) we need to make sure there is enough LDS
698 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
699 */
700 es_verts -= min_es_verts - 1;
701
702 out->es_verts_per_subgroup = es_verts;
703 out->gs_prims_per_subgroup = gs_prims;
704 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
705 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
706 gs->gs_max_out_vertices;
707 out->lds_size = align(esgs_lds_size, 128) / 128;
708
709 assert(out->max_prims_per_subgroup <= max_out_prims);
710 }
711
712 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
713 {
714 struct si_shader_selector *sel = shader->selector;
715 const ubyte *num_components = sel->info.num_stream_output_components;
716 unsigned gs_num_invocations = sel->gs_num_invocations;
717 struct si_pm4_state *pm4;
718 uint64_t va;
719 unsigned max_stream = sel->max_gs_stream;
720 unsigned offset;
721
722 pm4 = si_get_shader_pm4_state(shader);
723 if (!pm4)
724 return;
725
726 offset = num_components[0] * sel->gs_max_out_vertices;
727 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
728 if (max_stream >= 1)
729 offset += num_components[1] * sel->gs_max_out_vertices;
730 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
731 if (max_stream >= 2)
732 offset += num_components[2] * sel->gs_max_out_vertices;
733 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
734 if (max_stream >= 3)
735 offset += num_components[3] * sel->gs_max_out_vertices;
736 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
737
738 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
739 assert(offset < (1 << 15));
740
741 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, sel->gs_max_out_vertices);
742
743 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
744 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
745 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
746 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
747
748 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
749 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
750 S_028B90_ENABLE(gs_num_invocations > 0));
751
752 va = shader->bo->gpu_address;
753 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
754
755 if (sscreen->b.chip_class >= GFX9) {
756 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
757 unsigned es_type = shader->key.part.gs.es->type;
758 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
759 struct gfx9_gs_info gs_info;
760
761 if (es_type == PIPE_SHADER_VERTEX)
762 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
763 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
764 else if (es_type == PIPE_SHADER_TESS_EVAL)
765 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
766 else
767 unreachable("invalid shader selector type");
768
769 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
770 * VGPR[0:4] are always loaded.
771 */
772 if (sel->info.uses_invocationid)
773 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
774 else if (sel->info.uses_primid)
775 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
776 else if (input_prim >= PIPE_PRIM_TRIANGLES)
777 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
778 else
779 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
780
781 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
782
783 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
784 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, va >> 40);
785
786 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
787 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
788 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
789 S_00B228_DX10_CLAMP(1) |
790 S_00B228_FLOAT_MODE(shader->config.float_mode) |
791 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
792 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
793 S_00B22C_USER_SGPR(GFX9_GS_NUM_USER_SGPR) |
794 S_00B22C_USER_SGPR_MSB(GFX9_GS_NUM_USER_SGPR >> 5) |
795 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
796 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
797 S_00B22C_LDS_SIZE(gs_info.lds_size) |
798 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
799
800 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
801 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
802 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
803 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup));
804 si_pm4_set_reg(pm4, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
805 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup));
806 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
807 shader->key.part.gs.es->esgs_itemsize / 4);
808
809 if (es_type == PIPE_SHADER_TESS_EVAL)
810 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
811
812 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
813 NULL, pm4);
814 } else {
815 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
816 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
817
818 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
819 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
820 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
821 S_00B228_DX10_CLAMP(1) |
822 S_00B228_FLOAT_MODE(shader->config.float_mode));
823 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
824 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
825 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
826 }
827 }
828
829 /**
830 * Compute the state for \p shader, which will run as a vertex shader on the
831 * hardware.
832 *
833 * If \p gs is non-NULL, it points to the geometry shader for which this shader
834 * is the copy shader.
835 */
836 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
837 struct si_shader_selector *gs)
838 {
839 struct si_pm4_state *pm4;
840 unsigned num_user_sgprs;
841 unsigned nparams, vgpr_comp_cnt;
842 uint64_t va;
843 unsigned oc_lds_en;
844 unsigned window_space =
845 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
846 bool enable_prim_id = shader->key.mono.vs_export_prim_id || shader->selector->info.uses_primid;
847
848 pm4 = si_get_shader_pm4_state(shader);
849 if (!pm4)
850 return;
851
852 /* We always write VGT_GS_MODE in the VS state, because every switch
853 * between different shader pipelines involving a different GS or no
854 * GS at all involves a switch of the VS (different GS use different
855 * copy shaders). On the other hand, when the API switches from a GS to
856 * no GS and then back to the same GS used originally, the GS state is
857 * not sent again.
858 */
859 if (!gs) {
860 unsigned mode = 0;
861
862 /* PrimID needs GS scenario A.
863 * GFX9 also needs it when ViewportIndex is enabled.
864 */
865 if (enable_prim_id ||
866 (sscreen->b.chip_class >= GFX9 &&
867 shader->selector->info.writes_viewport_index))
868 mode = V_028A40_GS_SCENARIO_A;
869
870 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
871 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
872 } else {
873 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
874 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
875 }
876
877 va = shader->bo->gpu_address;
878 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
879
880 if (gs) {
881 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
882 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
883 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
884 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
885 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
886 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
887 */
888 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
889 num_user_sgprs = SI_VS_NUM_USER_SGPR;
890 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
891 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
892 num_user_sgprs = SI_TES_NUM_USER_SGPR;
893 } else
894 unreachable("invalid shader selector type");
895
896 /* VS is required to export at least one param. */
897 nparams = MAX2(shader->info.nr_param_exports, 1);
898 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
899 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
900
901 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
902 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
903 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
904 V_02870C_SPI_SHADER_4COMP :
905 V_02870C_SPI_SHADER_NONE) |
906 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
907 V_02870C_SPI_SHADER_4COMP :
908 V_02870C_SPI_SHADER_NONE) |
909 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
910 V_02870C_SPI_SHADER_4COMP :
911 V_02870C_SPI_SHADER_NONE));
912
913 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
914
915 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
916 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
917 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
918 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
919 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
920 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
921 S_00B128_DX10_CLAMP(1) |
922 S_00B128_FLOAT_MODE(shader->config.float_mode));
923 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
924 S_00B12C_USER_SGPR(num_user_sgprs) |
925 S_00B12C_OC_LDS_EN(oc_lds_en) |
926 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
927 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
928 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
929 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
930 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
931 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
932 if (window_space)
933 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
934 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
935 else
936 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
937 S_028818_VTX_W0_FMT(1) |
938 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
939 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
940 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
941
942 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
943 si_set_tesseval_regs(sscreen, shader->selector, pm4);
944
945 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
946 }
947
948 static unsigned si_get_ps_num_interp(struct si_shader *ps)
949 {
950 struct tgsi_shader_info *info = &ps->selector->info;
951 unsigned num_colors = !!(info->colors_read & 0x0f) +
952 !!(info->colors_read & 0xf0);
953 unsigned num_interp = ps->selector->info.num_inputs +
954 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
955
956 assert(num_interp <= 32);
957 return MIN2(num_interp, 32);
958 }
959
960 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
961 {
962 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
963 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
964
965 /* If the i-th target format is set, all previous target formats must
966 * be non-zero to avoid hangs.
967 */
968 for (i = 0; i < num_targets; i++)
969 if (!(value & (0xf << (i * 4))))
970 value |= V_028714_SPI_SHADER_32_R << (i * 4);
971
972 return value;
973 }
974
975 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
976 {
977 unsigned i, cb_shader_mask = 0;
978
979 for (i = 0; i < 8; i++) {
980 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
981 case V_028714_SPI_SHADER_ZERO:
982 break;
983 case V_028714_SPI_SHADER_32_R:
984 cb_shader_mask |= 0x1 << (i * 4);
985 break;
986 case V_028714_SPI_SHADER_32_GR:
987 cb_shader_mask |= 0x3 << (i * 4);
988 break;
989 case V_028714_SPI_SHADER_32_AR:
990 cb_shader_mask |= 0x9 << (i * 4);
991 break;
992 case V_028714_SPI_SHADER_FP16_ABGR:
993 case V_028714_SPI_SHADER_UNORM16_ABGR:
994 case V_028714_SPI_SHADER_SNORM16_ABGR:
995 case V_028714_SPI_SHADER_UINT16_ABGR:
996 case V_028714_SPI_SHADER_SINT16_ABGR:
997 case V_028714_SPI_SHADER_32_ABGR:
998 cb_shader_mask |= 0xf << (i * 4);
999 break;
1000 default:
1001 assert(0);
1002 }
1003 }
1004 return cb_shader_mask;
1005 }
1006
1007 static void si_shader_ps(struct si_shader *shader)
1008 {
1009 struct tgsi_shader_info *info = &shader->selector->info;
1010 struct si_pm4_state *pm4;
1011 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1012 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1013 uint64_t va;
1014 unsigned input_ena = shader->config.spi_ps_input_ena;
1015
1016 /* we need to enable at least one of them, otherwise we hang the GPU */
1017 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1018 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1019 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1020 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1021 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1022 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1023 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1024 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1025 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1026 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1027 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1028 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1029 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1030 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1031
1032 /* Validate interpolation optimization flags (read as implications). */
1033 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1034 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1035 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1036 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1037 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1038 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1039 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1040 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1041 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1042 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1043 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1044 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1045 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1046 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1047 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1048 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1049 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1050 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1051
1052 /* Validate cases when the optimizations are off (read as implications). */
1053 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1054 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1055 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1056 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1057 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1058 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1059
1060 pm4 = si_get_shader_pm4_state(shader);
1061 if (!pm4)
1062 return;
1063
1064 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1065 * Possible vaules:
1066 * 0 -> Position = pixel center
1067 * 1 -> Position = pixel centroid
1068 * 2 -> Position = at sample position
1069 *
1070 * From GLSL 4.5 specification, section 7.1:
1071 * "The variable gl_FragCoord is available as an input variable from
1072 * within fragment shaders and it holds the window relative coordinates
1073 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1074 * value can be for any location within the pixel, or one of the
1075 * fragment samples. The use of centroid does not further restrict
1076 * this value to be inside the current primitive."
1077 *
1078 * Meaning that centroid has no effect and we can return anything within
1079 * the pixel. Thus, return the value at sample position, because that's
1080 * the most accurate one shaders can get.
1081 */
1082 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1083
1084 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1085 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1086 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1087
1088 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1089 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
1090
1091 /* Ensure that some export memory is always allocated, for two reasons:
1092 *
1093 * 1) Correctness: The hardware ignores the EXEC mask if no export
1094 * memory is allocated, so KILL and alpha test do not work correctly
1095 * without this.
1096 * 2) Performance: Every shader needs at least a NULL export, even when
1097 * it writes no color/depth output. The NULL export instruction
1098 * stalls without this setting.
1099 *
1100 * Don't add this to CB_SHADER_MASK.
1101 */
1102 if (!spi_shader_col_format &&
1103 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1104 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1105
1106 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
1107 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
1108 shader->config.spi_ps_input_addr);
1109
1110 /* Set interpolation controls. */
1111 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1112
1113 /* Set registers. */
1114 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1115 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
1116
1117 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
1118 si_get_spi_shader_z_format(info->writes_z,
1119 info->writes_stencil,
1120 info->writes_samplemask));
1121
1122 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
1123 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
1124
1125 va = shader->bo->gpu_address;
1126 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1127 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1128 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
1129
1130 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1131 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1132 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1133 S_00B028_DX10_CLAMP(1) |
1134 S_00B028_FLOAT_MODE(shader->config.float_mode));
1135 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1136 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1137 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1138 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1139 }
1140
1141 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1142 struct si_shader *shader)
1143 {
1144 switch (shader->selector->type) {
1145 case PIPE_SHADER_VERTEX:
1146 if (shader->key.as_ls)
1147 si_shader_ls(sscreen, shader);
1148 else if (shader->key.as_es)
1149 si_shader_es(sscreen, shader);
1150 else
1151 si_shader_vs(sscreen, shader, NULL);
1152 break;
1153 case PIPE_SHADER_TESS_CTRL:
1154 si_shader_hs(sscreen, shader);
1155 break;
1156 case PIPE_SHADER_TESS_EVAL:
1157 if (shader->key.as_es)
1158 si_shader_es(sscreen, shader);
1159 else
1160 si_shader_vs(sscreen, shader, NULL);
1161 break;
1162 case PIPE_SHADER_GEOMETRY:
1163 si_shader_gs(sscreen, shader);
1164 break;
1165 case PIPE_SHADER_FRAGMENT:
1166 si_shader_ps(shader);
1167 break;
1168 default:
1169 assert(0);
1170 }
1171 }
1172
1173 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1174 {
1175 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1176 if (sctx->queued.named.dsa)
1177 return sctx->queued.named.dsa->alpha_func;
1178
1179 return PIPE_FUNC_ALWAYS;
1180 }
1181
1182 static void si_shader_selector_key_vs(struct si_context *sctx,
1183 struct si_shader_selector *vs,
1184 struct si_shader_key *key,
1185 struct si_vs_prolog_bits *prolog_key)
1186 {
1187 if (!sctx->vertex_elements)
1188 return;
1189
1190 unsigned count = MIN2(vs->info.num_inputs,
1191 sctx->vertex_elements->count);
1192 for (unsigned i = 0; i < count; ++i) {
1193 prolog_key->instance_divisors[i] =
1194 sctx->vertex_elements->elements[i].instance_divisor;
1195 }
1196
1197 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1198 }
1199
1200 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1201 struct si_shader_selector *vs,
1202 struct si_shader_key *key)
1203 {
1204 struct si_shader_selector *ps = sctx->ps_shader.cso;
1205
1206 key->opt.hw_vs.clip_disable =
1207 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1208 (vs->info.clipdist_writemask ||
1209 vs->info.writes_clipvertex) &&
1210 !vs->info.culldist_writemask;
1211
1212 /* Find out if PS is disabled. */
1213 bool ps_disabled = true;
1214 if (ps) {
1215 bool ps_modifies_zs = ps->info.uses_kill ||
1216 ps->info.writes_z ||
1217 ps->info.writes_stencil ||
1218 ps->info.writes_samplemask ||
1219 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1220
1221 unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1222 sctx->queued.named.blend->cb_target_mask;
1223 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1224 ps_colormask &= ps->colors_written_4bit;
1225
1226 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1227 (!ps_colormask &&
1228 !ps_modifies_zs &&
1229 !ps->info.writes_memory);
1230 }
1231
1232 /* Find out which VS outputs aren't used by the PS. */
1233 uint64_t outputs_written = vs->outputs_written;
1234 uint32_t outputs_written2 = vs->outputs_written2;
1235 uint64_t inputs_read = 0;
1236 uint32_t inputs_read2 = 0;
1237
1238 outputs_written &= ~0x3; /* ignore POSITION, PSIZE */
1239
1240 if (!ps_disabled) {
1241 inputs_read = ps->inputs_read;
1242 inputs_read2 = ps->inputs_read2;
1243 }
1244
1245 uint64_t linked = outputs_written & inputs_read;
1246 uint32_t linked2 = outputs_written2 & inputs_read2;
1247
1248 key->opt.hw_vs.kill_outputs = ~linked & outputs_written;
1249 key->opt.hw_vs.kill_outputs2 = ~linked2 & outputs_written2;
1250 }
1251
1252 /* Compute the key for the hw shader variant */
1253 static inline void si_shader_selector_key(struct pipe_context *ctx,
1254 struct si_shader_selector *sel,
1255 struct si_shader_key *key)
1256 {
1257 struct si_context *sctx = (struct si_context *)ctx;
1258
1259 memset(key, 0, sizeof(*key));
1260
1261 switch (sel->type) {
1262 case PIPE_SHADER_VERTEX:
1263 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1264
1265 if (sctx->tes_shader.cso)
1266 key->as_ls = 1;
1267 else if (sctx->gs_shader.cso)
1268 key->as_es = 1;
1269 else {
1270 si_shader_selector_key_hw_vs(sctx, sel, key);
1271
1272 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1273 key->mono.vs_export_prim_id = 1;
1274 }
1275 break;
1276 case PIPE_SHADER_TESS_CTRL:
1277 if (sctx->b.chip_class >= GFX9) {
1278 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1279 key, &key->part.tcs.ls_prolog);
1280 key->part.tcs.ls = sctx->vs_shader.cso;
1281 }
1282
1283 key->part.tcs.epilog.prim_mode =
1284 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1285 key->part.tcs.epilog.tes_reads_tess_factors =
1286 sctx->tes_shader.cso->info.reads_tess_factors;
1287
1288 if (sel == sctx->fixed_func_tcs_shader.cso)
1289 key->mono.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1290 break;
1291 case PIPE_SHADER_TESS_EVAL:
1292 if (sctx->gs_shader.cso)
1293 key->as_es = 1;
1294 else {
1295 si_shader_selector_key_hw_vs(sctx, sel, key);
1296
1297 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1298 key->mono.vs_export_prim_id = 1;
1299 }
1300 break;
1301 case PIPE_SHADER_GEOMETRY:
1302 if (sctx->b.chip_class >= GFX9) {
1303 if (sctx->tes_shader.cso) {
1304 key->part.gs.es = sctx->tes_shader.cso;
1305 } else {
1306 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1307 key, &key->part.gs.vs_prolog);
1308 key->part.gs.es = sctx->vs_shader.cso;
1309 }
1310
1311 /* Merged ES-GS can have unbalanced wave usage.
1312 *
1313 * ES threads are per-vertex, while GS threads are
1314 * per-primitive. So without any amplification, there
1315 * are fewer GS threads than ES threads, which can result
1316 * in empty (no-op) GS waves. With too much amplification,
1317 * there are more GS threads than ES threads, which
1318 * can result in empty (no-op) ES waves.
1319 *
1320 * Non-monolithic shaders are implemented by setting EXEC
1321 * at the beginning of shader parts, and don't jump to
1322 * the end if EXEC is 0.
1323 *
1324 * Monolithic shaders use conditional blocks, so they can
1325 * jump and skip empty waves of ES or GS. So set this to
1326 * always use optimized variants, which are monolithic.
1327 */
1328 key->opt.prefer_mono = 1;
1329 }
1330 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1331 break;
1332 case PIPE_SHADER_FRAGMENT: {
1333 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1334 struct si_state_blend *blend = sctx->queued.named.blend;
1335
1336 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1337 sel->info.colors_written == 0x1)
1338 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1339
1340 if (blend) {
1341 /* Select the shader color format based on whether
1342 * blending or alpha are needed.
1343 */
1344 key->part.ps.epilog.spi_shader_col_format =
1345 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1346 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1347 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1348 sctx->framebuffer.spi_shader_col_format_blend) |
1349 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1350 sctx->framebuffer.spi_shader_col_format_alpha) |
1351 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1352 sctx->framebuffer.spi_shader_col_format);
1353
1354 /* The output for dual source blending should have
1355 * the same format as the first output.
1356 */
1357 if (blend->dual_src_blend)
1358 key->part.ps.epilog.spi_shader_col_format |=
1359 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1360 } else
1361 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1362
1363 /* If alpha-to-coverage is enabled, we have to export alpha
1364 * even if there is no color buffer.
1365 */
1366 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1367 blend && blend->alpha_to_coverage)
1368 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1369
1370 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1371 * to the range supported by the type if a channel has less
1372 * than 16 bits and the export format is 16_ABGR.
1373 */
1374 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
1375 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1376 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1377 }
1378
1379 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1380 if (!key->part.ps.epilog.last_cbuf) {
1381 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1382 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1383 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1384 }
1385
1386 if (rs) {
1387 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1388 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1389 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1390 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1391
1392 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1393 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1394
1395 if (sctx->queued.named.blend) {
1396 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1397 rs->multisample_enable;
1398 }
1399
1400 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1401 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1402 (is_line && rs->line_smooth)) &&
1403 sctx->framebuffer.nr_samples <= 1;
1404 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1405
1406 if (rs->force_persample_interp &&
1407 rs->multisample_enable &&
1408 sctx->framebuffer.nr_samples > 1 &&
1409 sctx->ps_iter_samples > 1) {
1410 key->part.ps.prolog.force_persp_sample_interp =
1411 sel->info.uses_persp_center ||
1412 sel->info.uses_persp_centroid;
1413
1414 key->part.ps.prolog.force_linear_sample_interp =
1415 sel->info.uses_linear_center ||
1416 sel->info.uses_linear_centroid;
1417 } else if (rs->multisample_enable &&
1418 sctx->framebuffer.nr_samples > 1) {
1419 key->part.ps.prolog.bc_optimize_for_persp =
1420 sel->info.uses_persp_center &&
1421 sel->info.uses_persp_centroid;
1422 key->part.ps.prolog.bc_optimize_for_linear =
1423 sel->info.uses_linear_center &&
1424 sel->info.uses_linear_centroid;
1425 } else {
1426 /* Make sure SPI doesn't compute more than 1 pair
1427 * of (i,j), which is the optimization here. */
1428 key->part.ps.prolog.force_persp_center_interp =
1429 sel->info.uses_persp_center +
1430 sel->info.uses_persp_centroid +
1431 sel->info.uses_persp_sample > 1;
1432
1433 key->part.ps.prolog.force_linear_center_interp =
1434 sel->info.uses_linear_center +
1435 sel->info.uses_linear_centroid +
1436 sel->info.uses_linear_sample > 1;
1437 }
1438 }
1439
1440 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1441 break;
1442 }
1443 default:
1444 assert(0);
1445 }
1446 }
1447
1448 static void si_build_shader_variant(void *job, int thread_index)
1449 {
1450 struct si_shader *shader = (struct si_shader *)job;
1451 struct si_shader_selector *sel = shader->selector;
1452 struct si_screen *sscreen = sel->screen;
1453 LLVMTargetMachineRef tm;
1454 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1455 int r;
1456
1457 if (thread_index >= 0) {
1458 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1459 tm = sscreen->tm[thread_index];
1460 if (!debug->async)
1461 debug = NULL;
1462 } else {
1463 tm = shader->compiler_ctx_state.tm;
1464 }
1465
1466 r = si_shader_create(sscreen, tm, shader, debug);
1467 if (unlikely(r)) {
1468 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1469 sel->type, r);
1470 shader->compilation_failed = true;
1471 return;
1472 }
1473
1474 if (shader->compiler_ctx_state.is_debug_context) {
1475 FILE *f = open_memstream(&shader->shader_log,
1476 &shader->shader_log_size);
1477 if (f) {
1478 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1479 fclose(f);
1480 }
1481 }
1482
1483 si_shader_init_pm4_state(sscreen, shader);
1484 }
1485
1486 static const struct si_shader_key zeroed;
1487
1488 static bool si_check_missing_main_part(struct si_screen *sscreen,
1489 struct si_shader_selector *sel,
1490 struct si_compiler_ctx_state *compiler_state,
1491 struct si_shader_key *key)
1492 {
1493 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1494
1495 if (!*mainp) {
1496 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1497
1498 if (!main_part)
1499 return false;
1500
1501 main_part->selector = sel;
1502 main_part->key.as_es = key->as_es;
1503 main_part->key.as_ls = key->as_ls;
1504
1505 if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
1506 main_part, false,
1507 &compiler_state->debug) != 0) {
1508 FREE(main_part);
1509 return false;
1510 }
1511 *mainp = main_part;
1512 }
1513 return true;
1514 }
1515
1516 static void si_destroy_shader_selector(struct si_context *sctx,
1517 struct si_shader_selector *sel);
1518
1519 static void si_shader_selector_reference(struct si_context *sctx,
1520 struct si_shader_selector **dst,
1521 struct si_shader_selector *src)
1522 {
1523 if (pipe_reference(&(*dst)->reference, &src->reference))
1524 si_destroy_shader_selector(sctx, *dst);
1525
1526 *dst = src;
1527 }
1528
1529 /* Select the hw shader variant depending on the current state. */
1530 static int si_shader_select_with_key(struct si_screen *sscreen,
1531 struct si_shader_ctx_state *state,
1532 struct si_compiler_ctx_state *compiler_state,
1533 struct si_shader_key *key,
1534 int thread_index)
1535 {
1536 struct si_shader_selector *sel = state->cso;
1537 struct si_shader_selector *previous_stage_sel = NULL;
1538 struct si_shader *current = state->current;
1539 struct si_shader *iter, *shader = NULL;
1540
1541 if (unlikely(sscreen->b.debug_flags & DBG_NO_OPT_VARIANT)) {
1542 memset(&key->opt, 0, sizeof(key->opt));
1543 }
1544
1545 again:
1546 /* Check if we don't need to change anything.
1547 * This path is also used for most shaders that don't need multiple
1548 * variants, it will cost just a computation of the key and this
1549 * test. */
1550 if (likely(current &&
1551 memcmp(&current->key, key, sizeof(*key)) == 0 &&
1552 (!current->is_optimized ||
1553 util_queue_fence_is_signalled(&current->optimized_ready))))
1554 return current->compilation_failed ? -1 : 0;
1555
1556 /* This must be done before the mutex is locked, because async GS
1557 * compilation calls this function too, and therefore must enter
1558 * the mutex first.
1559 *
1560 * Only wait if we are in a draw call. Don't wait if we are
1561 * in a compiler thread.
1562 */
1563 if (thread_index < 0)
1564 util_queue_fence_wait(&sel->ready);
1565
1566 mtx_lock(&sel->mutex);
1567
1568 /* Find the shader variant. */
1569 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1570 /* Don't check the "current" shader. We checked it above. */
1571 if (current != iter &&
1572 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1573 /* If it's an optimized shader and its compilation has
1574 * been started but isn't done, use the unoptimized
1575 * shader so as not to cause a stall due to compilation.
1576 */
1577 if (iter->is_optimized &&
1578 !util_queue_fence_is_signalled(&iter->optimized_ready)) {
1579 memset(&key->opt, 0, sizeof(key->opt));
1580 mtx_unlock(&sel->mutex);
1581 goto again;
1582 }
1583
1584 if (iter->compilation_failed) {
1585 mtx_unlock(&sel->mutex);
1586 return -1; /* skip the draw call */
1587 }
1588
1589 state->current = iter;
1590 mtx_unlock(&sel->mutex);
1591 return 0;
1592 }
1593 }
1594
1595 /* Build a new shader. */
1596 shader = CALLOC_STRUCT(si_shader);
1597 if (!shader) {
1598 mtx_unlock(&sel->mutex);
1599 return -ENOMEM;
1600 }
1601 shader->selector = sel;
1602 shader->key = *key;
1603 shader->compiler_ctx_state = *compiler_state;
1604
1605 /* If this is a merged shader, get the first shader's selector. */
1606 if (sscreen->b.chip_class >= GFX9) {
1607 if (sel->type == PIPE_SHADER_TESS_CTRL)
1608 previous_stage_sel = key->part.tcs.ls;
1609 else if (sel->type == PIPE_SHADER_GEOMETRY)
1610 previous_stage_sel = key->part.gs.es;
1611 }
1612
1613 /* Compile the main shader part if it doesn't exist. This can happen
1614 * if the initial guess was wrong. */
1615 bool is_pure_monolithic =
1616 sscreen->use_monolithic_shaders ||
1617 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1618
1619 if (!is_pure_monolithic) {
1620 bool ok;
1621
1622 /* Make sure the main shader part is present. This is needed
1623 * for shaders that can be compiled as VS, LS, or ES, and only
1624 * one of them is compiled at creation.
1625 *
1626 * For merged shaders, check that the starting shader's main
1627 * part is present.
1628 */
1629 if (previous_stage_sel) {
1630 struct si_shader_key shader1_key = zeroed;
1631
1632 if (sel->type == PIPE_SHADER_TESS_CTRL)
1633 shader1_key.as_ls = 1;
1634 else if (sel->type == PIPE_SHADER_GEOMETRY)
1635 shader1_key.as_es = 1;
1636 else
1637 assert(0);
1638
1639 ok = si_check_missing_main_part(sscreen,
1640 previous_stage_sel,
1641 compiler_state, &shader1_key);
1642 } else {
1643 ok = si_check_missing_main_part(sscreen, sel,
1644 compiler_state, key);
1645 }
1646 if (!ok) {
1647 FREE(shader);
1648 mtx_unlock(&sel->mutex);
1649 return -ENOMEM; /* skip the draw call */
1650 }
1651 }
1652
1653 /* Keep the reference to the 1st shader of merged shaders, so that
1654 * Gallium can't destroy it before we destroy the 2nd shader.
1655 *
1656 * Set sctx = NULL, because it's unused if we're not releasing
1657 * the shader, and we don't have any sctx here.
1658 */
1659 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1660 previous_stage_sel);
1661
1662 /* Monolithic-only shaders don't make a distinction between optimized
1663 * and unoptimized. */
1664 shader->is_monolithic =
1665 is_pure_monolithic ||
1666 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1667
1668 shader->is_optimized =
1669 !is_pure_monolithic &&
1670 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1671 if (shader->is_optimized)
1672 util_queue_fence_init(&shader->optimized_ready);
1673
1674 if (!sel->last_variant) {
1675 sel->first_variant = shader;
1676 sel->last_variant = shader;
1677 } else {
1678 sel->last_variant->next_variant = shader;
1679 sel->last_variant = shader;
1680 }
1681
1682 /* If it's an optimized shader, compile it asynchronously. */
1683 if (shader->is_optimized &&
1684 !is_pure_monolithic &&
1685 thread_index < 0) {
1686 /* Compile it asynchronously. */
1687 util_queue_add_job(&sscreen->shader_compiler_queue,
1688 shader, &shader->optimized_ready,
1689 si_build_shader_variant, NULL);
1690
1691 /* Use the default (unoptimized) shader for now. */
1692 memset(&key->opt, 0, sizeof(key->opt));
1693 mtx_unlock(&sel->mutex);
1694 goto again;
1695 }
1696
1697 assert(!shader->is_optimized);
1698 si_build_shader_variant(shader, thread_index);
1699
1700 if (!shader->compilation_failed)
1701 state->current = shader;
1702
1703 mtx_unlock(&sel->mutex);
1704 return shader->compilation_failed ? -1 : 0;
1705 }
1706
1707 static int si_shader_select(struct pipe_context *ctx,
1708 struct si_shader_ctx_state *state,
1709 struct si_compiler_ctx_state *compiler_state)
1710 {
1711 struct si_context *sctx = (struct si_context *)ctx;
1712 struct si_shader_key key;
1713
1714 si_shader_selector_key(ctx, state->cso, &key);
1715 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1716 &key, -1);
1717 }
1718
1719 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1720 struct si_shader_key *key)
1721 {
1722 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1723
1724 switch (info->processor) {
1725 case PIPE_SHADER_VERTEX:
1726 switch (next_shader) {
1727 case PIPE_SHADER_GEOMETRY:
1728 key->as_es = 1;
1729 break;
1730 case PIPE_SHADER_TESS_CTRL:
1731 case PIPE_SHADER_TESS_EVAL:
1732 key->as_ls = 1;
1733 break;
1734 default:
1735 /* If POSITION isn't written, it can't be a HW VS.
1736 * Assume that it's a HW LS. (the next shader is TCS)
1737 * This heuristic is needed for separate shader objects.
1738 */
1739 if (!info->writes_position)
1740 key->as_ls = 1;
1741 }
1742 break;
1743
1744 case PIPE_SHADER_TESS_EVAL:
1745 if (next_shader == PIPE_SHADER_GEOMETRY ||
1746 !info->writes_position)
1747 key->as_es = 1;
1748 break;
1749 }
1750 }
1751
1752 /**
1753 * Compile the main shader part or the monolithic shader as part of
1754 * si_shader_selector initialization. Since it can be done asynchronously,
1755 * there is no way to report compile failures to applications.
1756 */
1757 void si_init_shader_selector_async(void *job, int thread_index)
1758 {
1759 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1760 struct si_screen *sscreen = sel->screen;
1761 LLVMTargetMachineRef tm;
1762 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1763 unsigned i;
1764
1765 if (thread_index >= 0) {
1766 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1767 tm = sscreen->tm[thread_index];
1768 if (!debug->async)
1769 debug = NULL;
1770 } else {
1771 tm = sel->compiler_ctx_state.tm;
1772 }
1773
1774 /* Compile the main shader part for use with a prolog and/or epilog.
1775 * If this fails, the driver will try to compile a monolithic shader
1776 * on demand.
1777 */
1778 if (!sscreen->use_monolithic_shaders) {
1779 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1780 void *tgsi_binary;
1781
1782 if (!shader) {
1783 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1784 return;
1785 }
1786
1787 shader->selector = sel;
1788 si_parse_next_shader_property(&sel->info, &shader->key);
1789
1790 tgsi_binary = si_get_tgsi_binary(sel);
1791
1792 /* Try to load the shader from the shader cache. */
1793 mtx_lock(&sscreen->shader_cache_mutex);
1794
1795 if (tgsi_binary &&
1796 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1797 mtx_unlock(&sscreen->shader_cache_mutex);
1798 } else {
1799 mtx_unlock(&sscreen->shader_cache_mutex);
1800
1801 /* Compile the shader if it hasn't been loaded from the cache. */
1802 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1803 debug) != 0) {
1804 FREE(shader);
1805 FREE(tgsi_binary);
1806 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1807 return;
1808 }
1809
1810 if (tgsi_binary) {
1811 mtx_lock(&sscreen->shader_cache_mutex);
1812 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader, true))
1813 FREE(tgsi_binary);
1814 mtx_unlock(&sscreen->shader_cache_mutex);
1815 }
1816 }
1817
1818 *si_get_main_shader_part(sel, &shader->key) = shader;
1819
1820 /* Unset "outputs_written" flags for outputs converted to
1821 * DEFAULT_VAL, so that later inter-shader optimizations don't
1822 * try to eliminate outputs that don't exist in the final
1823 * shader.
1824 *
1825 * This is only done if non-monolithic shaders are enabled.
1826 */
1827 if ((sel->type == PIPE_SHADER_VERTEX ||
1828 sel->type == PIPE_SHADER_TESS_EVAL) &&
1829 !shader->key.as_ls &&
1830 !shader->key.as_es) {
1831 unsigned i;
1832
1833 for (i = 0; i < sel->info.num_outputs; i++) {
1834 unsigned offset = shader->info.vs_output_param_offset[i];
1835
1836 if (offset <= AC_EXP_PARAM_OFFSET_31)
1837 continue;
1838
1839 unsigned name = sel->info.output_semantic_name[i];
1840 unsigned index = sel->info.output_semantic_index[i];
1841 unsigned id;
1842
1843 switch (name) {
1844 case TGSI_SEMANTIC_GENERIC:
1845 /* don't process indices the function can't handle */
1846 if (index >= 60)
1847 break;
1848 /* fall through */
1849 case TGSI_SEMANTIC_CLIPDIST:
1850 id = si_shader_io_get_unique_index(name, index);
1851 sel->outputs_written &= ~(1ull << id);
1852 break;
1853 case TGSI_SEMANTIC_POSITION: /* ignore these */
1854 case TGSI_SEMANTIC_PSIZE:
1855 case TGSI_SEMANTIC_CLIPVERTEX:
1856 case TGSI_SEMANTIC_EDGEFLAG:
1857 break;
1858 default:
1859 id = si_shader_io_get_unique_index2(name, index);
1860 sel->outputs_written2 &= ~(1u << id);
1861 }
1862 }
1863 }
1864 }
1865
1866 /* Pre-compilation. */
1867 if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
1868 struct si_shader_ctx_state state = {sel};
1869 struct si_shader_key key;
1870
1871 memset(&key, 0, sizeof(key));
1872 si_parse_next_shader_property(&sel->info, &key);
1873
1874 /* Set reasonable defaults, so that the shader key doesn't
1875 * cause any code to be eliminated.
1876 */
1877 switch (sel->type) {
1878 case PIPE_SHADER_TESS_CTRL:
1879 key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1880 break;
1881 case PIPE_SHADER_FRAGMENT:
1882 key.part.ps.prolog.bc_optimize_for_persp =
1883 sel->info.uses_persp_center &&
1884 sel->info.uses_persp_centroid;
1885 key.part.ps.prolog.bc_optimize_for_linear =
1886 sel->info.uses_linear_center &&
1887 sel->info.uses_linear_centroid;
1888 key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1889 for (i = 0; i < 8; i++)
1890 if (sel->info.colors_written & (1 << i))
1891 key.part.ps.epilog.spi_shader_col_format |=
1892 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1893 break;
1894 }
1895
1896 if (si_shader_select_with_key(sscreen, &state,
1897 &sel->compiler_ctx_state, &key,
1898 thread_index))
1899 fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
1900 }
1901
1902 /* The GS copy shader is always pre-compiled. */
1903 if (sel->type == PIPE_SHADER_GEOMETRY) {
1904 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1905 if (!sel->gs_copy_shader) {
1906 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1907 return;
1908 }
1909
1910 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1911 }
1912 }
1913
1914 static void *si_create_shader_selector(struct pipe_context *ctx,
1915 const struct pipe_shader_state *state)
1916 {
1917 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1918 struct si_context *sctx = (struct si_context*)ctx;
1919 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1920 int i;
1921
1922 if (!sel)
1923 return NULL;
1924
1925 pipe_reference_init(&sel->reference, 1);
1926 sel->screen = sscreen;
1927 sel->compiler_ctx_state.tm = sctx->tm;
1928 sel->compiler_ctx_state.debug = sctx->b.debug;
1929 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
1930 sel->tokens = tgsi_dup_tokens(state->tokens);
1931 if (!sel->tokens) {
1932 FREE(sel);
1933 return NULL;
1934 }
1935
1936 sel->so = state->stream_output;
1937 tgsi_scan_shader(state->tokens, &sel->info);
1938 sel->type = sel->info.processor;
1939 p_atomic_inc(&sscreen->b.num_shaders_created);
1940
1941 /* The prolog is a no-op if there are no inputs. */
1942 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
1943 sel->info.num_inputs;
1944
1945 /* Set which opcode uses which (i,j) pair. */
1946 if (sel->info.uses_persp_opcode_interp_centroid)
1947 sel->info.uses_persp_centroid = true;
1948
1949 if (sel->info.uses_linear_opcode_interp_centroid)
1950 sel->info.uses_linear_centroid = true;
1951
1952 if (sel->info.uses_persp_opcode_interp_offset ||
1953 sel->info.uses_persp_opcode_interp_sample)
1954 sel->info.uses_persp_center = true;
1955
1956 if (sel->info.uses_linear_opcode_interp_offset ||
1957 sel->info.uses_linear_opcode_interp_sample)
1958 sel->info.uses_linear_center = true;
1959
1960 switch (sel->type) {
1961 case PIPE_SHADER_GEOMETRY:
1962 sel->gs_output_prim =
1963 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1964 sel->gs_max_out_vertices =
1965 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1966 sel->gs_num_invocations =
1967 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1968 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
1969 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
1970 sel->gs_max_out_vertices;
1971
1972 sel->max_gs_stream = 0;
1973 for (i = 0; i < sel->so.num_outputs; i++)
1974 sel->max_gs_stream = MAX2(sel->max_gs_stream,
1975 sel->so.output[i].stream);
1976
1977 sel->gs_input_verts_per_prim =
1978 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
1979 break;
1980
1981 case PIPE_SHADER_TESS_CTRL:
1982 /* Always reserve space for these. */
1983 sel->patch_outputs_written |=
1984 (1llu << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
1985 (1llu << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
1986 /* fall through */
1987 case PIPE_SHADER_VERTEX:
1988 case PIPE_SHADER_TESS_EVAL:
1989 for (i = 0; i < sel->info.num_outputs; i++) {
1990 unsigned name = sel->info.output_semantic_name[i];
1991 unsigned index = sel->info.output_semantic_index[i];
1992
1993 switch (name) {
1994 case TGSI_SEMANTIC_TESSINNER:
1995 case TGSI_SEMANTIC_TESSOUTER:
1996 case TGSI_SEMANTIC_PATCH:
1997 sel->patch_outputs_written |=
1998 1llu << si_shader_io_get_unique_index_patch(name, index);
1999 break;
2000
2001 case TGSI_SEMANTIC_GENERIC:
2002 /* don't process indices the function can't handle */
2003 if (index >= 60)
2004 break;
2005 /* fall through */
2006 case TGSI_SEMANTIC_POSITION:
2007 case TGSI_SEMANTIC_PSIZE:
2008 case TGSI_SEMANTIC_CLIPDIST:
2009 sel->outputs_written |=
2010 1llu << si_shader_io_get_unique_index(name, index);
2011 break;
2012 case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
2013 case TGSI_SEMANTIC_EDGEFLAG:
2014 break;
2015 default:
2016 sel->outputs_written2 |=
2017 1u << si_shader_io_get_unique_index2(name, index);
2018 }
2019 }
2020 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2021
2022 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2023 * conflicts, i.e. each vertex will start at a different bank.
2024 */
2025 if (sctx->b.chip_class >= GFX9)
2026 sel->esgs_itemsize += 4;
2027 break;
2028
2029 case PIPE_SHADER_FRAGMENT:
2030 for (i = 0; i < sel->info.num_inputs; i++) {
2031 unsigned name = sel->info.input_semantic_name[i];
2032 unsigned index = sel->info.input_semantic_index[i];
2033
2034 switch (name) {
2035 case TGSI_SEMANTIC_CLIPDIST:
2036 case TGSI_SEMANTIC_GENERIC:
2037 sel->inputs_read |=
2038 1llu << si_shader_io_get_unique_index(name, index);
2039 break;
2040 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2041 break;
2042 default:
2043 sel->inputs_read2 |=
2044 1u << si_shader_io_get_unique_index2(name, index);
2045 }
2046 }
2047
2048 for (i = 0; i < 8; i++)
2049 if (sel->info.colors_written & (1 << i))
2050 sel->colors_written_4bit |= 0xf << (4 * i);
2051
2052 for (i = 0; i < sel->info.num_inputs; i++) {
2053 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2054 int index = sel->info.input_semantic_index[i];
2055 sel->color_attr_index[index] = i;
2056 }
2057 }
2058 break;
2059 }
2060
2061 /* DB_SHADER_CONTROL */
2062 sel->db_shader_control =
2063 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2064 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2065 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2066 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2067
2068 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2069 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2070 sel->db_shader_control |=
2071 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2072 break;
2073 case TGSI_FS_DEPTH_LAYOUT_LESS:
2074 sel->db_shader_control |=
2075 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2076 break;
2077 }
2078
2079 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2080 *
2081 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2082 * --|-----------|------------|------------|--------------------|-------------------|-------------
2083 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2084 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2085 * 2 | false | true | n/a | LateZ | 1 | 0
2086 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2087 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2088 *
2089 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2090 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2091 *
2092 * Don't use ReZ without profiling !!!
2093 *
2094 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2095 * shaders.
2096 */
2097 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2098 /* Cases 3, 4. */
2099 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2100 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2101 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2102 } else if (sel->info.writes_memory) {
2103 /* Case 2. */
2104 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2105 S_02880C_EXEC_ON_HIER_FAIL(1);
2106 } else {
2107 /* Case 1. */
2108 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2109 }
2110
2111 (void) mtx_init(&sel->mutex, mtx_plain);
2112 util_queue_fence_init(&sel->ready);
2113
2114 if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
2115 sctx->is_debug ||
2116 r600_can_dump_shader(&sscreen->b, sel->info.processor))
2117 si_init_shader_selector_async(sel, -1);
2118 else
2119 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
2120 &sel->ready, si_init_shader_selector_async,
2121 NULL);
2122
2123 return sel;
2124 }
2125
2126 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2127 {
2128 struct si_context *sctx = (struct si_context *)ctx;
2129 struct si_shader_selector *sel = state;
2130
2131 if (sctx->vs_shader.cso == sel)
2132 return;
2133
2134 sctx->vs_shader.cso = sel;
2135 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2136 sctx->do_update_shaders = true;
2137 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2138 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
2139 }
2140
2141 static void si_update_tcs_tes_uses_prim_id(struct si_context *sctx)
2142 {
2143 sctx->ia_multi_vgt_param_key.u.tcs_tes_uses_prim_id =
2144 (sctx->tes_shader.cso &&
2145 sctx->tes_shader.cso->info.uses_primid) ||
2146 (sctx->tcs_shader.cso &&
2147 sctx->tcs_shader.cso->info.uses_primid) ||
2148 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2149 sctx->ps_shader.cso->info.uses_primid);
2150 }
2151
2152 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2153 {
2154 struct si_context *sctx = (struct si_context *)ctx;
2155 struct si_shader_selector *sel = state;
2156 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2157
2158 if (sctx->gs_shader.cso == sel)
2159 return;
2160
2161 sctx->gs_shader.cso = sel;
2162 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2163 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2164 sctx->do_update_shaders = true;
2165 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2166 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2167
2168 if (enable_changed) {
2169 si_shader_change_notify(sctx);
2170 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2171 si_update_tcs_tes_uses_prim_id(sctx);
2172 }
2173 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
2174 }
2175
2176 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2177 {
2178 struct si_context *sctx = (struct si_context *)ctx;
2179 struct si_shader_selector *sel = state;
2180 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2181
2182 if (sctx->tcs_shader.cso == sel)
2183 return;
2184
2185 sctx->tcs_shader.cso = sel;
2186 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2187 si_update_tcs_tes_uses_prim_id(sctx);
2188 sctx->do_update_shaders = true;
2189
2190 if (enable_changed)
2191 sctx->last_tcs = NULL; /* invalidate derived tess state */
2192 }
2193
2194 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2195 {
2196 struct si_context *sctx = (struct si_context *)ctx;
2197 struct si_shader_selector *sel = state;
2198 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2199
2200 if (sctx->tes_shader.cso == sel)
2201 return;
2202
2203 sctx->tes_shader.cso = sel;
2204 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2205 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2206 si_update_tcs_tes_uses_prim_id(sctx);
2207 sctx->do_update_shaders = true;
2208 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2209 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2210
2211 if (enable_changed) {
2212 si_shader_change_notify(sctx);
2213 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2214 }
2215 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
2216 }
2217
2218 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2219 {
2220 struct si_context *sctx = (struct si_context *)ctx;
2221 struct si_shader_selector *sel = state;
2222
2223 /* skip if supplied shader is one already in use */
2224 if (sctx->ps_shader.cso == sel)
2225 return;
2226
2227 sctx->ps_shader.cso = sel;
2228 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2229 sctx->do_update_shaders = true;
2230 if (sel && sctx->ia_multi_vgt_param_key.u.uses_tess)
2231 si_update_tcs_tes_uses_prim_id(sctx);
2232 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2233 }
2234
2235 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2236 {
2237 if (shader->is_optimized) {
2238 util_queue_fence_wait(&shader->optimized_ready);
2239 util_queue_fence_destroy(&shader->optimized_ready);
2240 }
2241
2242 if (shader->pm4) {
2243 switch (shader->selector->type) {
2244 case PIPE_SHADER_VERTEX:
2245 if (shader->key.as_ls) {
2246 assert(sctx->b.chip_class <= VI);
2247 si_pm4_delete_state(sctx, ls, shader->pm4);
2248 } else if (shader->key.as_es) {
2249 assert(sctx->b.chip_class <= VI);
2250 si_pm4_delete_state(sctx, es, shader->pm4);
2251 } else {
2252 si_pm4_delete_state(sctx, vs, shader->pm4);
2253 }
2254 break;
2255 case PIPE_SHADER_TESS_CTRL:
2256 si_pm4_delete_state(sctx, hs, shader->pm4);
2257 break;
2258 case PIPE_SHADER_TESS_EVAL:
2259 if (shader->key.as_es) {
2260 assert(sctx->b.chip_class <= VI);
2261 si_pm4_delete_state(sctx, es, shader->pm4);
2262 } else {
2263 si_pm4_delete_state(sctx, vs, shader->pm4);
2264 }
2265 break;
2266 case PIPE_SHADER_GEOMETRY:
2267 if (shader->is_gs_copy_shader)
2268 si_pm4_delete_state(sctx, vs, shader->pm4);
2269 else
2270 si_pm4_delete_state(sctx, gs, shader->pm4);
2271 break;
2272 case PIPE_SHADER_FRAGMENT:
2273 si_pm4_delete_state(sctx, ps, shader->pm4);
2274 break;
2275 }
2276 }
2277
2278 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2279 si_shader_destroy(shader);
2280 free(shader);
2281 }
2282
2283 static void si_destroy_shader_selector(struct si_context *sctx,
2284 struct si_shader_selector *sel)
2285 {
2286 struct si_shader *p = sel->first_variant, *c;
2287 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2288 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2289 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2290 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2291 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2292 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2293 };
2294
2295 util_queue_fence_wait(&sel->ready);
2296
2297 if (current_shader[sel->type]->cso == sel) {
2298 current_shader[sel->type]->cso = NULL;
2299 current_shader[sel->type]->current = NULL;
2300 }
2301
2302 while (p) {
2303 c = p->next_variant;
2304 si_delete_shader(sctx, p);
2305 p = c;
2306 }
2307
2308 if (sel->main_shader_part)
2309 si_delete_shader(sctx, sel->main_shader_part);
2310 if (sel->main_shader_part_ls)
2311 si_delete_shader(sctx, sel->main_shader_part_ls);
2312 if (sel->main_shader_part_es)
2313 si_delete_shader(sctx, sel->main_shader_part_es);
2314 if (sel->gs_copy_shader)
2315 si_delete_shader(sctx, sel->gs_copy_shader);
2316
2317 util_queue_fence_destroy(&sel->ready);
2318 mtx_destroy(&sel->mutex);
2319 free(sel->tokens);
2320 free(sel);
2321 }
2322
2323 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2324 {
2325 struct si_context *sctx = (struct si_context *)ctx;
2326 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2327
2328 si_shader_selector_reference(sctx, &sel, NULL);
2329 }
2330
2331 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2332 struct si_shader *vs, unsigned name,
2333 unsigned index, unsigned interpolate)
2334 {
2335 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2336 unsigned j, offset, ps_input_cntl = 0;
2337
2338 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2339 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2340 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2341
2342 if (name == TGSI_SEMANTIC_PCOORD ||
2343 (name == TGSI_SEMANTIC_TEXCOORD &&
2344 sctx->sprite_coord_enable & (1 << index))) {
2345 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2346 }
2347
2348 for (j = 0; j < vsinfo->num_outputs; j++) {
2349 if (name == vsinfo->output_semantic_name[j] &&
2350 index == vsinfo->output_semantic_index[j]) {
2351 offset = vs->info.vs_output_param_offset[j];
2352
2353 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2354 /* The input is loaded from parameter memory. */
2355 ps_input_cntl |= S_028644_OFFSET(offset);
2356 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2357 if (offset == AC_EXP_PARAM_UNDEFINED) {
2358 /* This can happen with depth-only rendering. */
2359 offset = 0;
2360 } else {
2361 /* The input is a DEFAULT_VAL constant. */
2362 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2363 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2364 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2365 }
2366
2367 ps_input_cntl = S_028644_OFFSET(0x20) |
2368 S_028644_DEFAULT_VAL(offset);
2369 }
2370 break;
2371 }
2372 }
2373
2374 if (name == TGSI_SEMANTIC_PRIMID)
2375 /* PrimID is written after the last output. */
2376 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2377 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2378 /* No corresponding output found, load defaults into input.
2379 * Don't set any other bits.
2380 * (FLAT_SHADE=1 completely changes behavior) */
2381 ps_input_cntl = S_028644_OFFSET(0x20);
2382 /* D3D 9 behaviour. GL is undefined */
2383 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2384 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2385 }
2386 return ps_input_cntl;
2387 }
2388
2389 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
2390 {
2391 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2392 struct si_shader *ps = sctx->ps_shader.current;
2393 struct si_shader *vs = si_get_vs_state(sctx);
2394 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2395 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2396
2397 if (!ps || !ps->selector->info.num_inputs)
2398 return;
2399
2400 num_interp = si_get_ps_num_interp(ps);
2401 assert(num_interp > 0);
2402 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
2403
2404 for (i = 0; i < psinfo->num_inputs; i++) {
2405 unsigned name = psinfo->input_semantic_name[i];
2406 unsigned index = psinfo->input_semantic_index[i];
2407 unsigned interpolate = psinfo->input_interpolate[i];
2408
2409 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
2410 interpolate));
2411 num_written++;
2412
2413 if (name == TGSI_SEMANTIC_COLOR) {
2414 assert(index < ARRAY_SIZE(bcol_interp));
2415 bcol_interp[index] = interpolate;
2416 }
2417 }
2418
2419 if (ps->key.part.ps.prolog.color_two_side) {
2420 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2421
2422 for (i = 0; i < 2; i++) {
2423 if (!(psinfo->colors_read & (0xf << (i * 4))))
2424 continue;
2425
2426 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
2427 i, bcol_interp[i]));
2428 num_written++;
2429 }
2430 }
2431 assert(num_interp == num_written);
2432 }
2433
2434 /**
2435 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2436 */
2437 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2438 {
2439 if (sctx->init_config_has_vgt_flush)
2440 return;
2441
2442 /* Done by Vulkan before VGT_FLUSH. */
2443 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2444 si_pm4_cmd_add(sctx->init_config,
2445 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2446 si_pm4_cmd_end(sctx->init_config, false);
2447
2448 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2449 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2450 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2451 si_pm4_cmd_end(sctx->init_config, false);
2452 sctx->init_config_has_vgt_flush = true;
2453 }
2454
2455 /* Initialize state related to ESGS / GSVS ring buffers */
2456 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2457 {
2458 struct si_shader_selector *es =
2459 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2460 struct si_shader_selector *gs = sctx->gs_shader.cso;
2461 struct si_pm4_state *pm4;
2462
2463 /* Chip constants. */
2464 unsigned num_se = sctx->screen->b.info.max_se;
2465 unsigned wave_size = 64;
2466 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2467 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2468 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2469 */
2470 unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se;
2471 unsigned alignment = 256 * num_se;
2472 /* The maximum size is 63.999 MB per SE. */
2473 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2474
2475 /* Calculate the minimum size. */
2476 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2477 wave_size, alignment);
2478
2479 /* These are recommended sizes, not minimum sizes. */
2480 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2481 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2482 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2483 gs->max_gsvs_emit_size;
2484
2485 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2486 esgs_ring_size = align(esgs_ring_size, alignment);
2487 gsvs_ring_size = align(gsvs_ring_size, alignment);
2488
2489 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2490 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2491
2492 /* Some rings don't have to be allocated if shaders don't use them.
2493 * (e.g. no varyings between ES and GS or GS and VS)
2494 *
2495 * GFX9 doesn't have the ESGS ring.
2496 */
2497 bool update_esgs = sctx->b.chip_class <= VI &&
2498 esgs_ring_size &&
2499 (!sctx->esgs_ring ||
2500 sctx->esgs_ring->width0 < esgs_ring_size);
2501 bool update_gsvs = gsvs_ring_size &&
2502 (!sctx->gsvs_ring ||
2503 sctx->gsvs_ring->width0 < gsvs_ring_size);
2504
2505 if (!update_esgs && !update_gsvs)
2506 return true;
2507
2508 if (update_esgs) {
2509 pipe_resource_reference(&sctx->esgs_ring, NULL);
2510 sctx->esgs_ring =
2511 r600_aligned_buffer_create(sctx->b.b.screen,
2512 R600_RESOURCE_FLAG_UNMAPPABLE,
2513 PIPE_USAGE_DEFAULT,
2514 esgs_ring_size, alignment);
2515 if (!sctx->esgs_ring)
2516 return false;
2517 }
2518
2519 if (update_gsvs) {
2520 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2521 sctx->gsvs_ring =
2522 r600_aligned_buffer_create(sctx->b.b.screen,
2523 R600_RESOURCE_FLAG_UNMAPPABLE,
2524 PIPE_USAGE_DEFAULT,
2525 gsvs_ring_size, alignment);
2526 if (!sctx->gsvs_ring)
2527 return false;
2528 }
2529
2530 /* Create the "init_config_gs_rings" state. */
2531 pm4 = CALLOC_STRUCT(si_pm4_state);
2532 if (!pm4)
2533 return false;
2534
2535 if (sctx->b.chip_class >= CIK) {
2536 if (sctx->esgs_ring) {
2537 assert(sctx->b.chip_class <= VI);
2538 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2539 sctx->esgs_ring->width0 / 256);
2540 }
2541 if (sctx->gsvs_ring)
2542 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2543 sctx->gsvs_ring->width0 / 256);
2544 } else {
2545 if (sctx->esgs_ring)
2546 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2547 sctx->esgs_ring->width0 / 256);
2548 if (sctx->gsvs_ring)
2549 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2550 sctx->gsvs_ring->width0 / 256);
2551 }
2552
2553 /* Set the state. */
2554 if (sctx->init_config_gs_rings)
2555 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2556 sctx->init_config_gs_rings = pm4;
2557
2558 if (!sctx->init_config_has_vgt_flush) {
2559 si_init_config_add_vgt_flush(sctx);
2560 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2561 }
2562
2563 /* Flush the context to re-emit both init_config states. */
2564 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2565 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2566
2567 /* Set ring bindings. */
2568 if (sctx->esgs_ring) {
2569 assert(sctx->b.chip_class <= VI);
2570 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
2571 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2572 true, true, 4, 64, 0);
2573 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
2574 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2575 false, false, 0, 0, 0);
2576 }
2577 if (sctx->gsvs_ring) {
2578 si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
2579 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2580 false, false, 0, 0, 0);
2581 }
2582
2583 return true;
2584 }
2585
2586 static void si_shader_lock(struct si_shader *shader)
2587 {
2588 mtx_lock(&shader->selector->mutex);
2589 if (shader->previous_stage_sel) {
2590 assert(shader->previous_stage_sel != shader->selector);
2591 mtx_lock(&shader->previous_stage_sel->mutex);
2592 }
2593 }
2594
2595 static void si_shader_unlock(struct si_shader *shader)
2596 {
2597 if (shader->previous_stage_sel)
2598 mtx_unlock(&shader->previous_stage_sel->mutex);
2599 mtx_unlock(&shader->selector->mutex);
2600 }
2601
2602 /**
2603 * @returns 1 if \p sel has been updated to use a new scratch buffer
2604 * 0 if not
2605 * < 0 if there was a failure
2606 */
2607 static int si_update_scratch_buffer(struct si_context *sctx,
2608 struct si_shader *shader)
2609 {
2610 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2611 int r;
2612
2613 if (!shader)
2614 return 0;
2615
2616 /* This shader doesn't need a scratch buffer */
2617 if (shader->config.scratch_bytes_per_wave == 0)
2618 return 0;
2619
2620 /* Prevent race conditions when updating:
2621 * - si_shader::scratch_bo
2622 * - si_shader::binary::code
2623 * - si_shader::previous_stage::binary::code.
2624 */
2625 si_shader_lock(shader);
2626
2627 /* This shader is already configured to use the current
2628 * scratch buffer. */
2629 if (shader->scratch_bo == sctx->scratch_buffer) {
2630 si_shader_unlock(shader);
2631 return 0;
2632 }
2633
2634 assert(sctx->scratch_buffer);
2635
2636 if (shader->previous_stage)
2637 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
2638
2639 si_shader_apply_scratch_relocs(shader, scratch_va);
2640
2641 /* Replace the shader bo with a new bo that has the relocs applied. */
2642 r = si_shader_binary_upload(sctx->screen, shader);
2643 if (r) {
2644 si_shader_unlock(shader);
2645 return r;
2646 }
2647
2648 /* Update the shader state to use the new shader bo. */
2649 si_shader_init_pm4_state(sctx->screen, shader);
2650
2651 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2652
2653 si_shader_unlock(shader);
2654 return 1;
2655 }
2656
2657 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2658 {
2659 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2660 }
2661
2662 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2663 {
2664 return shader ? shader->config.scratch_bytes_per_wave : 0;
2665 }
2666
2667 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2668 {
2669 unsigned bytes = 0;
2670
2671 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2672 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2673 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2674 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
2675 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2676 return bytes;
2677 }
2678
2679 static bool si_update_scratch_relocs(struct si_context *sctx)
2680 {
2681 int r;
2682
2683 /* Update the shaders, so that they are using the latest scratch.
2684 * The scratch buffer may have been changed since these shaders were
2685 * last used, so we still need to try to update them, even if they
2686 * require scratch buffers smaller than the current size.
2687 */
2688 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2689 if (r < 0)
2690 return false;
2691 if (r == 1)
2692 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2693
2694 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2695 if (r < 0)
2696 return false;
2697 if (r == 1)
2698 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2699
2700 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
2701 if (r < 0)
2702 return false;
2703 if (r == 1)
2704 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2705
2706 /* VS can be bound as LS, ES, or VS. */
2707 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2708 if (r < 0)
2709 return false;
2710 if (r == 1) {
2711 if (sctx->tes_shader.current)
2712 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2713 else if (sctx->gs_shader.current)
2714 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2715 else
2716 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2717 }
2718
2719 /* TES can be bound as ES or VS. */
2720 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2721 if (r < 0)
2722 return false;
2723 if (r == 1) {
2724 if (sctx->gs_shader.current)
2725 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2726 else
2727 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2728 }
2729
2730 return true;
2731 }
2732
2733 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2734 {
2735 unsigned current_scratch_buffer_size =
2736 si_get_current_scratch_buffer_size(sctx);
2737 unsigned scratch_bytes_per_wave =
2738 si_get_max_scratch_bytes_per_wave(sctx);
2739 unsigned scratch_needed_size = scratch_bytes_per_wave *
2740 sctx->scratch_waves;
2741 unsigned spi_tmpring_size;
2742
2743 if (scratch_needed_size > 0) {
2744 if (scratch_needed_size > current_scratch_buffer_size) {
2745 /* Create a bigger scratch buffer */
2746 r600_resource_reference(&sctx->scratch_buffer, NULL);
2747
2748 sctx->scratch_buffer = (struct r600_resource*)
2749 r600_aligned_buffer_create(&sctx->screen->b.b,
2750 R600_RESOURCE_FLAG_UNMAPPABLE,
2751 PIPE_USAGE_DEFAULT,
2752 scratch_needed_size, 256);
2753 if (!sctx->scratch_buffer)
2754 return false;
2755
2756 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2757 r600_context_add_resource_size(&sctx->b.b,
2758 &sctx->scratch_buffer->b.b);
2759 }
2760
2761 if (!si_update_scratch_relocs(sctx))
2762 return false;
2763 }
2764
2765 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2766 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
2767 "scratch size should already be aligned correctly.");
2768
2769 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
2770 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
2771 if (spi_tmpring_size != sctx->spi_tmpring_size) {
2772 sctx->spi_tmpring_size = spi_tmpring_size;
2773 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2774 }
2775 return true;
2776 }
2777
2778 static void si_init_tess_factor_ring(struct si_context *sctx)
2779 {
2780 bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
2781 sctx->b.family != CHIP_CARRIZO &&
2782 sctx->b.family != CHIP_STONEY;
2783 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2784 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
2785 sctx->screen->b.info.max_se;
2786 unsigned offchip_granularity;
2787
2788 switch (sctx->screen->tess_offchip_block_dw_size) {
2789 default:
2790 assert(0);
2791 /* fall through */
2792 case 8192:
2793 offchip_granularity = V_03093C_X_8K_DWORDS;
2794 break;
2795 case 4096:
2796 offchip_granularity = V_03093C_X_4K_DWORDS;
2797 break;
2798 }
2799
2800 switch (sctx->b.chip_class) {
2801 case SI:
2802 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2803 break;
2804 case CIK:
2805 case VI:
2806 case GFX9:
2807 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2808 break;
2809 default:
2810 assert(0);
2811 return;
2812 }
2813
2814 assert(!sctx->tf_ring);
2815 /* Use 64K alignment for both rings, so that we can pass the address
2816 * to shaders as one SGPR containing bits [16:47].
2817 */
2818 sctx->tf_ring = r600_aligned_buffer_create(sctx->b.b.screen,
2819 R600_RESOURCE_FLAG_UNMAPPABLE,
2820 PIPE_USAGE_DEFAULT,
2821 32768 * sctx->screen->b.info.max_se,
2822 64 * 1024);
2823 if (!sctx->tf_ring)
2824 return;
2825
2826 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
2827
2828 sctx->tess_offchip_ring =
2829 r600_aligned_buffer_create(sctx->b.b.screen,
2830 R600_RESOURCE_FLAG_UNMAPPABLE,
2831 PIPE_USAGE_DEFAULT,
2832 max_offchip_buffers *
2833 sctx->screen->tess_offchip_block_dw_size * 4,
2834 64 * 1024);
2835 if (!sctx->tess_offchip_ring)
2836 return;
2837
2838 si_init_config_add_vgt_flush(sctx);
2839
2840 uint64_t offchip_va = r600_resource(sctx->tess_offchip_ring)->gpu_address;
2841 uint64_t factor_va = r600_resource(sctx->tf_ring)->gpu_address;
2842 assert((offchip_va & 0xffff) == 0);
2843 assert((factor_va & 0xffff) == 0);
2844
2845 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_offchip_ring),
2846 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
2847 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tf_ring),
2848 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
2849
2850 /* Append these registers to the init config state. */
2851 if (sctx->b.chip_class >= CIK) {
2852 if (sctx->b.chip_class >= VI)
2853 --max_offchip_buffers;
2854
2855 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
2856 S_030938_SIZE(sctx->tf_ring->width0 / 4));
2857 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
2858 factor_va >> 8);
2859 if (sctx->b.chip_class >= GFX9)
2860 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
2861 factor_va >> 40);
2862 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
2863 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2864 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
2865 } else {
2866 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
2867 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
2868 S_008988_SIZE(sctx->tf_ring->width0 / 4));
2869 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
2870 factor_va >> 8);
2871 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2872 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
2873 }
2874
2875 if (sctx->b.chip_class >= GFX9) {
2876 si_pm4_set_reg(sctx->init_config,
2877 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
2878 GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
2879 offchip_va >> 16);
2880 si_pm4_set_reg(sctx->init_config,
2881 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
2882 GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
2883 factor_va >> 16);
2884 } else {
2885 si_pm4_set_reg(sctx->init_config,
2886 R_00B430_SPI_SHADER_USER_DATA_HS_0 +
2887 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
2888 offchip_va >> 16);
2889 si_pm4_set_reg(sctx->init_config,
2890 R_00B430_SPI_SHADER_USER_DATA_HS_0 +
2891 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
2892 factor_va >> 16);
2893 }
2894
2895 /* Flush the context to re-emit the init_config state.
2896 * This is done only once in a lifetime of a context.
2897 */
2898 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2899 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2900 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2901 }
2902
2903 /**
2904 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
2905 * VS passes its outputs to TES directly, so the fixed-function shader only
2906 * has to write TESSOUTER and TESSINNER.
2907 */
2908 static void si_generate_fixed_func_tcs(struct si_context *sctx)
2909 {
2910 struct ureg_src outer, inner;
2911 struct ureg_dst tessouter, tessinner;
2912 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
2913
2914 if (!ureg)
2915 return; /* if we get here, we're screwed */
2916
2917 assert(!sctx->fixed_func_tcs_shader.cso);
2918
2919 outer = ureg_DECL_system_value(ureg,
2920 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
2921 inner = ureg_DECL_system_value(ureg,
2922 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
2923
2924 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
2925 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
2926
2927 ureg_MOV(ureg, tessouter, outer);
2928 ureg_MOV(ureg, tessinner, inner);
2929 ureg_END(ureg);
2930
2931 sctx->fixed_func_tcs_shader.cso =
2932 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
2933 }
2934
2935 static void si_update_vgt_shader_config(struct si_context *sctx)
2936 {
2937 /* Calculate the index of the config.
2938 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
2939 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
2940 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
2941
2942 if (!*pm4) {
2943 uint32_t stages = 0;
2944
2945 *pm4 = CALLOC_STRUCT(si_pm4_state);
2946
2947 if (sctx->tes_shader.cso) {
2948 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2949 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2950
2951 if (sctx->gs_shader.cso)
2952 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2953 S_028B54_GS_EN(1) |
2954 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2955 else
2956 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2957 } else if (sctx->gs_shader.cso) {
2958 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2959 S_028B54_GS_EN(1) |
2960 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2961 }
2962
2963 if (sctx->b.chip_class >= GFX9)
2964 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2965
2966 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
2967 }
2968 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
2969 }
2970
2971 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
2972 {
2973 struct pipe_stream_output_info *so = &shader->so;
2974 uint32_t enabled_stream_buffers_mask = 0;
2975 int i;
2976
2977 for (i = 0; i < so->num_outputs; i++)
2978 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
2979 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
2980 sctx->b.streamout.stride_in_dw = shader->so.stride;
2981 }
2982
2983 bool si_update_shaders(struct si_context *sctx)
2984 {
2985 struct pipe_context *ctx = (struct pipe_context*)sctx;
2986 struct si_compiler_ctx_state compiler_state;
2987 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2988 struct si_shader *old_vs = si_get_vs_state(sctx);
2989 bool old_clip_disable = old_vs ? old_vs->key.opt.hw_vs.clip_disable : false;
2990 int r;
2991
2992 compiler_state.tm = sctx->tm;
2993 compiler_state.debug = sctx->b.debug;
2994 compiler_state.is_debug_context = sctx->is_debug;
2995
2996 /* Update stages before GS. */
2997 if (sctx->tes_shader.cso) {
2998 if (!sctx->tf_ring) {
2999 si_init_tess_factor_ring(sctx);
3000 if (!sctx->tf_ring)
3001 return false;
3002 }
3003
3004 /* VS as LS */
3005 if (sctx->b.chip_class <= VI) {
3006 r = si_shader_select(ctx, &sctx->vs_shader,
3007 &compiler_state);
3008 if (r)
3009 return false;
3010 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3011 }
3012
3013 if (sctx->tcs_shader.cso) {
3014 r = si_shader_select(ctx, &sctx->tcs_shader,
3015 &compiler_state);
3016 if (r)
3017 return false;
3018 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3019 } else {
3020 if (!sctx->fixed_func_tcs_shader.cso) {
3021 si_generate_fixed_func_tcs(sctx);
3022 if (!sctx->fixed_func_tcs_shader.cso)
3023 return false;
3024 }
3025
3026 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3027 &compiler_state);
3028 if (r)
3029 return false;
3030 si_pm4_bind_state(sctx, hs,
3031 sctx->fixed_func_tcs_shader.current->pm4);
3032 }
3033
3034 if (sctx->gs_shader.cso) {
3035 /* TES as ES */
3036 if (sctx->b.chip_class <= VI) {
3037 r = si_shader_select(ctx, &sctx->tes_shader,
3038 &compiler_state);
3039 if (r)
3040 return false;
3041 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3042 }
3043 } else {
3044 /* TES as VS */
3045 r = si_shader_select(ctx, &sctx->tes_shader,
3046 &compiler_state);
3047 if (r)
3048 return false;
3049 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3050 si_update_so(sctx, sctx->tes_shader.cso);
3051 }
3052 } else if (sctx->gs_shader.cso) {
3053 if (sctx->b.chip_class <= VI) {
3054 /* VS as ES */
3055 r = si_shader_select(ctx, &sctx->vs_shader,
3056 &compiler_state);
3057 if (r)
3058 return false;
3059 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3060
3061 si_pm4_bind_state(sctx, ls, NULL);
3062 si_pm4_bind_state(sctx, hs, NULL);
3063 }
3064 } else {
3065 /* VS as VS */
3066 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3067 if (r)
3068 return false;
3069 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3070 si_update_so(sctx, sctx->vs_shader.cso);
3071
3072 si_pm4_bind_state(sctx, ls, NULL);
3073 si_pm4_bind_state(sctx, hs, NULL);
3074 }
3075
3076 /* Update GS. */
3077 if (sctx->gs_shader.cso) {
3078 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3079 if (r)
3080 return false;
3081 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3082 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3083 si_update_so(sctx, sctx->gs_shader.cso);
3084
3085 if (!si_update_gs_ring_buffers(sctx))
3086 return false;
3087 } else {
3088 si_pm4_bind_state(sctx, gs, NULL);
3089 if (sctx->b.chip_class <= VI)
3090 si_pm4_bind_state(sctx, es, NULL);
3091 }
3092
3093 si_update_vgt_shader_config(sctx);
3094
3095 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.hw_vs.clip_disable)
3096 si_mark_atom_dirty(sctx, &sctx->clip_regs);
3097
3098 if (sctx->ps_shader.cso) {
3099 unsigned db_shader_control;
3100
3101 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3102 if (r)
3103 return false;
3104 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3105
3106 db_shader_control =
3107 sctx->ps_shader.cso->db_shader_control |
3108 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3109
3110 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3111 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3112 sctx->flatshade != rs->flatshade) {
3113 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3114 sctx->flatshade = rs->flatshade;
3115 si_mark_atom_dirty(sctx, &sctx->spi_map);
3116 }
3117
3118 if (sctx->screen->b.rbplus_allowed && si_pm4_state_changed(sctx, ps))
3119 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
3120
3121 if (sctx->ps_db_shader_control != db_shader_control) {
3122 sctx->ps_db_shader_control = db_shader_control;
3123 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3124 }
3125
3126 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3127 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3128 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3129
3130 if (sctx->b.chip_class == SI)
3131 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3132
3133 if (sctx->framebuffer.nr_samples <= 1)
3134 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
3135 }
3136 }
3137
3138 if (si_pm4_state_changed(sctx, ls) ||
3139 si_pm4_state_changed(sctx, hs) ||
3140 si_pm4_state_changed(sctx, es) ||
3141 si_pm4_state_changed(sctx, gs) ||
3142 si_pm4_state_changed(sctx, vs) ||
3143 si_pm4_state_changed(sctx, ps)) {
3144 if (!si_update_spi_tmpring_size(sctx))
3145 return false;
3146 }
3147
3148 if (sctx->b.chip_class >= CIK)
3149 si_mark_atom_dirty(sctx, &sctx->prefetch_L2);
3150
3151 sctx->do_update_shaders = false;
3152 return true;
3153 }
3154
3155 static void si_emit_scratch_state(struct si_context *sctx,
3156 struct r600_atom *atom)
3157 {
3158 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3159
3160 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3161 sctx->spi_tmpring_size);
3162
3163 if (sctx->scratch_buffer) {
3164 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
3165 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3166 RADEON_PRIO_SCRATCH_BUFFER);
3167 }
3168 }
3169
3170 void si_init_shader_functions(struct si_context *sctx)
3171 {
3172 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
3173 si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
3174 si_emit_scratch_state);
3175
3176 sctx->b.b.create_vs_state = si_create_shader_selector;
3177 sctx->b.b.create_tcs_state = si_create_shader_selector;
3178 sctx->b.b.create_tes_state = si_create_shader_selector;
3179 sctx->b.b.create_gs_state = si_create_shader_selector;
3180 sctx->b.b.create_fs_state = si_create_shader_selector;
3181
3182 sctx->b.b.bind_vs_state = si_bind_vs_shader;
3183 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
3184 sctx->b.b.bind_tes_state = si_bind_tes_shader;
3185 sctx->b.b.bind_gs_state = si_bind_gs_shader;
3186 sctx->b.b.bind_fs_state = si_bind_ps_shader;
3187
3188 sctx->b.b.delete_vs_state = si_delete_shader_selector;
3189 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
3190 sctx->b.b.delete_tes_state = si_delete_shader_selector;
3191 sctx->b.b.delete_gs_state = si_delete_shader_selector;
3192 sctx->b.b.delete_fs_state = si_delete_shader_selector;
3193 }