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radeonsi: add new SDMA texture copy code
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/u_hash.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
39 #include "util/u_simple_shaders.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
45 * integer.
46 */
47 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
48 {
49 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
50 sizeof(struct tgsi_token);
51 unsigned size = 4 + tgsi_size + sizeof(sel->so);
52 char *result = (char*)MALLOC(size);
53
54 if (!result)
55 return NULL;
56
57 *((uint32_t*)result) = size;
58 memcpy(result + 4, sel->tokens, tgsi_size);
59 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
60 return result;
61 }
62
63 /** Copy "data" to "ptr" and return the next dword following copied data. */
64 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
65 {
66 /* data may be NULL if size == 0 */
67 if (size)
68 memcpy(ptr, data, size);
69 ptr += DIV_ROUND_UP(size, 4);
70 return ptr;
71 }
72
73 /** Read data from "ptr". Return the next dword following the data. */
74 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
75 {
76 memcpy(data, ptr, size);
77 ptr += DIV_ROUND_UP(size, 4);
78 return ptr;
79 }
80
81 /**
82 * Write the size as uint followed by the data. Return the next dword
83 * following the copied data.
84 */
85 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
86 {
87 *ptr++ = size;
88 return write_data(ptr, data, size);
89 }
90
91 /**
92 * Read the size as uint followed by the data. Return both via parameters.
93 * Return the next dword following the data.
94 */
95 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
96 {
97 *size = *ptr++;
98 assert(*data == NULL);
99 *data = malloc(*size);
100 return read_data(ptr, *data, *size);
101 }
102
103 /**
104 * Return the shader binary in a buffer. The first 4 bytes contain its size
105 * as integer.
106 */
107 static void *si_get_shader_binary(struct si_shader *shader)
108 {
109 /* There is always a size of data followed by the data itself. */
110 unsigned relocs_size = shader->binary.reloc_count *
111 sizeof(shader->binary.relocs[0]);
112 unsigned disasm_size = strlen(shader->binary.disasm_string) + 1;
113 unsigned size =
114 4 + /* total size */
115 4 + /* CRC32 of the data below */
116 align(sizeof(shader->config), 4) +
117 align(sizeof(shader->info), 4) +
118 4 + align(shader->binary.code_size, 4) +
119 4 + align(shader->binary.rodata_size, 4) +
120 4 + align(relocs_size, 4) +
121 4 + align(disasm_size, 4);
122 void *buffer = CALLOC(1, size);
123 uint32_t *ptr = (uint32_t*)buffer;
124
125 if (!buffer)
126 return NULL;
127
128 *ptr++ = size;
129 ptr++; /* CRC32 is calculated at the end. */
130
131 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
132 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
133 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
134 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
135 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
136 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
137 assert((char *)ptr - (char *)buffer == size);
138
139 /* Compute CRC32. */
140 ptr = (uint32_t*)buffer;
141 ptr++;
142 *ptr = util_hash_crc32(ptr + 1, size - 8);
143
144 return buffer;
145 }
146
147 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
148 {
149 uint32_t *ptr = (uint32_t*)binary;
150 uint32_t size = *ptr++;
151 uint32_t crc32 = *ptr++;
152 unsigned chunk_size;
153
154 if (util_hash_crc32(ptr, size - 8) != crc32) {
155 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
156 return false;
157 }
158
159 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
160 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
161 ptr = read_chunk(ptr, (void**)&shader->binary.code,
162 &shader->binary.code_size);
163 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
164 &shader->binary.rodata_size);
165 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
166 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
167 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
168
169 return true;
170 }
171
172 /**
173 * Insert a shader into the cache. It's assumed the shader is not in the cache.
174 * Use si_shader_cache_load_shader before calling this.
175 *
176 * Returns false on failure, in which case the tgsi_binary should be freed.
177 */
178 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
179 void *tgsi_binary,
180 struct si_shader *shader)
181 {
182 void *hw_binary = si_get_shader_binary(shader);
183
184 if (!hw_binary)
185 return false;
186
187 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
188 hw_binary) == NULL) {
189 FREE(hw_binary);
190 return false;
191 }
192
193 return true;
194 }
195
196 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
197 void *tgsi_binary,
198 struct si_shader *shader)
199 {
200 struct hash_entry *entry =
201 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
202 if (!entry)
203 return false;
204
205 return si_load_shader_binary(shader, entry->data);
206 }
207
208 static uint32_t si_shader_cache_key_hash(const void *key)
209 {
210 /* The first dword is the key size. */
211 return util_hash_crc32(key, *(uint32_t*)key);
212 }
213
214 static bool si_shader_cache_key_equals(const void *a, const void *b)
215 {
216 uint32_t *keya = (uint32_t*)a;
217 uint32_t *keyb = (uint32_t*)b;
218
219 /* The first dword is the key size. */
220 if (*keya != *keyb)
221 return false;
222
223 return memcmp(keya, keyb, *keya) == 0;
224 }
225
226 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
227 {
228 FREE((void*)entry->key);
229 FREE(entry->data);
230 }
231
232 bool si_init_shader_cache(struct si_screen *sscreen)
233 {
234 pipe_mutex_init(sscreen->shader_cache_mutex);
235 sscreen->shader_cache =
236 _mesa_hash_table_create(NULL,
237 si_shader_cache_key_hash,
238 si_shader_cache_key_equals);
239 return sscreen->shader_cache != NULL;
240 }
241
242 void si_destroy_shader_cache(struct si_screen *sscreen)
243 {
244 if (sscreen->shader_cache)
245 _mesa_hash_table_destroy(sscreen->shader_cache,
246 si_destroy_shader_cache_entry);
247 pipe_mutex_destroy(sscreen->shader_cache_mutex);
248 }
249
250 /* SHADER STATES */
251
252 static void si_set_tesseval_regs(struct si_shader *shader,
253 struct si_pm4_state *pm4)
254 {
255 struct tgsi_shader_info *info = &shader->selector->info;
256 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
257 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
258 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
259 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
260 unsigned type, partitioning, topology;
261
262 switch (tes_prim_mode) {
263 case PIPE_PRIM_LINES:
264 type = V_028B6C_TESS_ISOLINE;
265 break;
266 case PIPE_PRIM_TRIANGLES:
267 type = V_028B6C_TESS_TRIANGLE;
268 break;
269 case PIPE_PRIM_QUADS:
270 type = V_028B6C_TESS_QUAD;
271 break;
272 default:
273 assert(0);
274 return;
275 }
276
277 switch (tes_spacing) {
278 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
279 partitioning = V_028B6C_PART_FRAC_ODD;
280 break;
281 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
282 partitioning = V_028B6C_PART_FRAC_EVEN;
283 break;
284 case PIPE_TESS_SPACING_EQUAL:
285 partitioning = V_028B6C_PART_INTEGER;
286 break;
287 default:
288 assert(0);
289 return;
290 }
291
292 if (tes_point_mode)
293 topology = V_028B6C_OUTPUT_POINT;
294 else if (tes_prim_mode == PIPE_PRIM_LINES)
295 topology = V_028B6C_OUTPUT_LINE;
296 else if (tes_vertex_order_cw)
297 /* for some reason, this must be the other way around */
298 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
299 else
300 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
301
302 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
303 S_028B6C_TYPE(type) |
304 S_028B6C_PARTITIONING(partitioning) |
305 S_028B6C_TOPOLOGY(topology));
306 }
307
308 static void si_shader_ls(struct si_shader *shader)
309 {
310 struct si_pm4_state *pm4;
311 unsigned vgpr_comp_cnt;
312 uint64_t va;
313
314 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
315 if (!pm4)
316 return;
317
318 va = shader->bo->gpu_address;
319 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
320
321 /* We need at least 2 components for LS.
322 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
323 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 1;
324
325 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
326 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
327
328 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
329 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
330 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
331 S_00B528_DX10_CLAMP(1) |
332 S_00B528_FLOAT_MODE(shader->config.float_mode);
333 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_LS_NUM_USER_SGPR) |
334 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
335 }
336
337 static void si_shader_hs(struct si_shader *shader)
338 {
339 struct si_pm4_state *pm4;
340 uint64_t va;
341
342 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
343 if (!pm4)
344 return;
345
346 va = shader->bo->gpu_address;
347 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
348
349 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
350 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
351 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
352 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
353 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
354 S_00B428_DX10_CLAMP(1) |
355 S_00B428_FLOAT_MODE(shader->config.float_mode));
356 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
357 S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR) |
358 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
359 }
360
361 static void si_shader_es(struct si_shader *shader)
362 {
363 struct si_pm4_state *pm4;
364 unsigned num_user_sgprs;
365 unsigned vgpr_comp_cnt;
366 uint64_t va;
367
368 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
369
370 if (!pm4)
371 return;
372
373 va = shader->bo->gpu_address;
374 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
375
376 if (shader->selector->type == PIPE_SHADER_VERTEX) {
377 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
378 num_user_sgprs = SI_ES_NUM_USER_SGPR;
379 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
380 vgpr_comp_cnt = 3; /* all components are needed for TES */
381 num_user_sgprs = SI_TES_NUM_USER_SGPR;
382 } else
383 unreachable("invalid shader selector type");
384
385 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
386 shader->selector->esgs_itemsize / 4);
387 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
388 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
389 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
390 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
391 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
392 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
393 S_00B328_DX10_CLAMP(1) |
394 S_00B328_FLOAT_MODE(shader->config.float_mode));
395 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
396 S_00B32C_USER_SGPR(num_user_sgprs) |
397 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
398
399 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
400 si_set_tesseval_regs(shader, pm4);
401 }
402
403 /**
404 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
405 * geometry shader.
406 */
407 static uint32_t si_vgt_gs_mode(struct si_shader *shader)
408 {
409 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
410 unsigned cut_mode;
411
412 if (gs_max_vert_out <= 128) {
413 cut_mode = V_028A40_GS_CUT_128;
414 } else if (gs_max_vert_out <= 256) {
415 cut_mode = V_028A40_GS_CUT_256;
416 } else if (gs_max_vert_out <= 512) {
417 cut_mode = V_028A40_GS_CUT_512;
418 } else {
419 assert(gs_max_vert_out <= 1024);
420 cut_mode = V_028A40_GS_CUT_1024;
421 }
422
423 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
424 S_028A40_CUT_MODE(cut_mode)|
425 S_028A40_ES_WRITE_OPTIMIZE(1) |
426 S_028A40_GS_WRITE_OPTIMIZE(1);
427 }
428
429 static void si_shader_gs(struct si_shader *shader)
430 {
431 unsigned gs_vert_itemsize = shader->selector->gsvs_vertex_size;
432 unsigned gsvs_itemsize = shader->selector->max_gsvs_emit_size >> 2;
433 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
434 struct si_pm4_state *pm4;
435 uint64_t va;
436 unsigned max_stream = shader->selector->max_gs_stream;
437
438 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
439 assert(gsvs_itemsize < (1 << 15));
440
441 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
442
443 if (!pm4)
444 return;
445
446 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader));
447
448 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
449 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
450 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
451
452 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
453
454 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, shader->selector->gs_max_out_vertices);
455
456 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
457 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
458 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
459 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
460
461 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
462 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
463 S_028B90_ENABLE(gs_num_invocations > 0));
464
465 va = shader->bo->gpu_address;
466 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
467 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
468 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
469
470 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
471 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
472 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
473 S_00B228_DX10_CLAMP(1) |
474 S_00B228_FLOAT_MODE(shader->config.float_mode));
475 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
476 S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR) |
477 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
478 }
479
480 /**
481 * Compute the state for \p shader, which will run as a vertex shader on the
482 * hardware.
483 *
484 * If \p gs is non-NULL, it points to the geometry shader for which this shader
485 * is the copy shader.
486 */
487 static void si_shader_vs(struct si_shader *shader, struct si_shader *gs)
488 {
489 struct si_pm4_state *pm4;
490 unsigned num_user_sgprs;
491 unsigned nparams, vgpr_comp_cnt;
492 uint64_t va;
493 unsigned window_space =
494 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
495 bool enable_prim_id = si_vs_exports_prim_id(shader);
496
497 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
498
499 if (!pm4)
500 return;
501
502 /* We always write VGT_GS_MODE in the VS state, because every switch
503 * between different shader pipelines involving a different GS or no
504 * GS at all involves a switch of the VS (different GS use different
505 * copy shaders). On the other hand, when the API switches from a GS to
506 * no GS and then back to the same GS used originally, the GS state is
507 * not sent again.
508 */
509 if (!gs) {
510 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
511 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
512 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
513 } else {
514 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
515 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
516 }
517
518 va = shader->bo->gpu_address;
519 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
520
521 if (gs) {
522 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
523 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
524 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
525 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
526 num_user_sgprs = SI_VS_NUM_USER_SGPR;
527 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
528 vgpr_comp_cnt = 3; /* all components are needed for TES */
529 num_user_sgprs = SI_TES_NUM_USER_SGPR;
530 } else
531 unreachable("invalid shader selector type");
532
533 /* VS is required to export at least one param. */
534 nparams = MAX2(shader->info.nr_param_exports, 1);
535 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
536 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
537
538 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
539 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
540 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
541 V_02870C_SPI_SHADER_4COMP :
542 V_02870C_SPI_SHADER_NONE) |
543 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
544 V_02870C_SPI_SHADER_4COMP :
545 V_02870C_SPI_SHADER_NONE) |
546 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
547 V_02870C_SPI_SHADER_4COMP :
548 V_02870C_SPI_SHADER_NONE));
549
550 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
551 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
552 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
553 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
554 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
555 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
556 S_00B128_DX10_CLAMP(1) |
557 S_00B128_FLOAT_MODE(shader->config.float_mode));
558 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
559 S_00B12C_USER_SGPR(num_user_sgprs) |
560 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
561 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
562 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
563 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
564 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
565 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
566 if (window_space)
567 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
568 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
569 else
570 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
571 S_028818_VTX_W0_FMT(1) |
572 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
573 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
574 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
575
576 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
577 si_set_tesseval_regs(shader, pm4);
578 }
579
580 static unsigned si_get_ps_num_interp(struct si_shader *ps)
581 {
582 struct tgsi_shader_info *info = &ps->selector->info;
583 unsigned num_colors = !!(info->colors_read & 0x0f) +
584 !!(info->colors_read & 0xf0);
585 unsigned num_interp = ps->selector->info.num_inputs +
586 (ps->key.ps.prolog.color_two_side ? num_colors : 0);
587
588 assert(num_interp <= 32);
589 return MIN2(num_interp, 32);
590 }
591
592 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
593 {
594 unsigned value = shader->key.ps.epilog.spi_shader_col_format;
595 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
596
597 /* If the i-th target format is set, all previous target formats must
598 * be non-zero to avoid hangs.
599 */
600 for (i = 0; i < num_targets; i++)
601 if (!(value & (0xf << (i * 4))))
602 value |= V_028714_SPI_SHADER_32_R << (i * 4);
603
604 return value;
605 }
606
607 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
608 {
609 unsigned i, cb_shader_mask = 0;
610
611 for (i = 0; i < 8; i++) {
612 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
613 case V_028714_SPI_SHADER_ZERO:
614 break;
615 case V_028714_SPI_SHADER_32_R:
616 cb_shader_mask |= 0x1 << (i * 4);
617 break;
618 case V_028714_SPI_SHADER_32_GR:
619 cb_shader_mask |= 0x3 << (i * 4);
620 break;
621 case V_028714_SPI_SHADER_32_AR:
622 cb_shader_mask |= 0x9 << (i * 4);
623 break;
624 case V_028714_SPI_SHADER_FP16_ABGR:
625 case V_028714_SPI_SHADER_UNORM16_ABGR:
626 case V_028714_SPI_SHADER_SNORM16_ABGR:
627 case V_028714_SPI_SHADER_UINT16_ABGR:
628 case V_028714_SPI_SHADER_SINT16_ABGR:
629 case V_028714_SPI_SHADER_32_ABGR:
630 cb_shader_mask |= 0xf << (i * 4);
631 break;
632 default:
633 assert(0);
634 }
635 }
636 return cb_shader_mask;
637 }
638
639 static void si_shader_ps(struct si_shader *shader)
640 {
641 struct tgsi_shader_info *info = &shader->selector->info;
642 struct si_pm4_state *pm4;
643 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
644 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
645 uint64_t va;
646 bool has_centroid;
647 unsigned input_ena = shader->config.spi_ps_input_ena;
648
649 /* we need to enable at least one of them, otherwise we hang the GPU */
650 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
651 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
652 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
653 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
654 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
655 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
656 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
657 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
658
659 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
660
661 if (!pm4)
662 return;
663
664 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
665 * Possible vaules:
666 * 0 -> Position = pixel center
667 * 1 -> Position = pixel centroid
668 * 2 -> Position = at sample position
669 *
670 * From GLSL 4.5 specification, section 7.1:
671 * "The variable gl_FragCoord is available as an input variable from
672 * within fragment shaders and it holds the window relative coordinates
673 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
674 * value can be for any location within the pixel, or one of the
675 * fragment samples. The use of centroid does not further restrict
676 * this value to be inside the current primitive."
677 *
678 * Meaning that centroid has no effect and we can return anything within
679 * the pixel. Thus, return the value at sample position, because that's
680 * the most accurate one shaders can get.
681 */
682 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
683
684 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
685 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
686 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
687
688 spi_shader_col_format = si_get_spi_shader_col_format(shader);
689 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
690
691 /* Ensure that some export memory is always allocated, for two reasons:
692 *
693 * 1) Correctness: The hardware ignores the EXEC mask if no export
694 * memory is allocated, so KILL and alpha test do not work correctly
695 * without this.
696 * 2) Performance: Every shader needs at least a NULL export, even when
697 * it writes no color/depth output. The NULL export instruction
698 * stalls without this setting.
699 *
700 * Don't add this to CB_SHADER_MASK.
701 */
702 if (!spi_shader_col_format &&
703 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
704 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
705
706 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
707 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
708 shader->config.spi_ps_input_addr);
709
710 /* Set interpolation controls. */
711 has_centroid = G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena) ||
712 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena);
713
714 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
715 S_0286D8_BC_OPTIMIZE_DISABLE(has_centroid);
716
717 /* Set registers. */
718 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
719 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
720
721 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
722 info->writes_samplemask ? V_028710_SPI_SHADER_32_ABGR :
723 info->writes_stencil ? V_028710_SPI_SHADER_32_GR :
724 info->writes_z ? V_028710_SPI_SHADER_32_R :
725 V_028710_SPI_SHADER_ZERO);
726
727 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
728 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
729
730 va = shader->bo->gpu_address;
731 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
732 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
733 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
734
735 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
736 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
737 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
738 S_00B028_DX10_CLAMP(1) |
739 S_00B028_FLOAT_MODE(shader->config.float_mode));
740 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
741 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
742 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
743 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
744
745 /* Prefer RE_Z if the shader is complex enough. The requirement is either:
746 * - the shader uses at least 2 VMEM instructions, or
747 * - the code size is at least 50 2-dword instructions or 100 1-dword
748 * instructions.
749 *
750 * Shaders with side effects that must execute independently of the
751 * depth test require LATE_Z.
752 */
753 if (info->writes_memory &&
754 !info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL])
755 shader->z_order = V_02880C_LATE_Z;
756 else if (info->num_memory_instructions >= 2 ||
757 shader->binary.code_size > 100*4)
758 shader->z_order = V_02880C_EARLY_Z_THEN_RE_Z;
759 else
760 shader->z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
761 }
762
763 static void si_shader_init_pm4_state(struct si_shader *shader)
764 {
765
766 if (shader->pm4)
767 si_pm4_free_state_simple(shader->pm4);
768
769 switch (shader->selector->type) {
770 case PIPE_SHADER_VERTEX:
771 if (shader->key.vs.as_ls)
772 si_shader_ls(shader);
773 else if (shader->key.vs.as_es)
774 si_shader_es(shader);
775 else
776 si_shader_vs(shader, NULL);
777 break;
778 case PIPE_SHADER_TESS_CTRL:
779 si_shader_hs(shader);
780 break;
781 case PIPE_SHADER_TESS_EVAL:
782 if (shader->key.tes.as_es)
783 si_shader_es(shader);
784 else
785 si_shader_vs(shader, NULL);
786 break;
787 case PIPE_SHADER_GEOMETRY:
788 si_shader_gs(shader);
789 si_shader_vs(shader->gs_copy_shader, shader);
790 break;
791 case PIPE_SHADER_FRAGMENT:
792 si_shader_ps(shader);
793 break;
794 default:
795 assert(0);
796 }
797 }
798
799 static unsigned si_get_alpha_test_func(struct si_context *sctx)
800 {
801 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
802 if (sctx->queued.named.dsa &&
803 !sctx->framebuffer.cb0_is_integer)
804 return sctx->queued.named.dsa->alpha_func;
805
806 return PIPE_FUNC_ALWAYS;
807 }
808
809 /* Compute the key for the hw shader variant */
810 static inline void si_shader_selector_key(struct pipe_context *ctx,
811 struct si_shader_selector *sel,
812 union si_shader_key *key)
813 {
814 struct si_context *sctx = (struct si_context *)ctx;
815 unsigned i;
816
817 memset(key, 0, sizeof(*key));
818
819 switch (sel->type) {
820 case PIPE_SHADER_VERTEX:
821 if (sctx->vertex_elements) {
822 unsigned count = MIN2(sel->info.num_inputs,
823 sctx->vertex_elements->count);
824 for (i = 0; i < count; ++i)
825 key->vs.prolog.instance_divisors[i] =
826 sctx->vertex_elements->elements[i].instance_divisor;
827 }
828 if (sctx->tes_shader.cso)
829 key->vs.as_ls = 1;
830 else if (sctx->gs_shader.cso)
831 key->vs.as_es = 1;
832
833 if (!sctx->gs_shader.cso && sctx->ps_shader.cso &&
834 sctx->ps_shader.cso->info.uses_primid)
835 key->vs.epilog.export_prim_id = 1;
836 break;
837 case PIPE_SHADER_TESS_CTRL:
838 key->tcs.epilog.prim_mode =
839 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
840 break;
841 case PIPE_SHADER_TESS_EVAL:
842 if (sctx->gs_shader.cso)
843 key->tes.as_es = 1;
844 else if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
845 key->tes.epilog.export_prim_id = 1;
846 break;
847 case PIPE_SHADER_GEOMETRY:
848 break;
849 case PIPE_SHADER_FRAGMENT: {
850 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
851 struct si_state_blend *blend = sctx->queued.named.blend;
852
853 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
854 sel->info.colors_written == 0x1)
855 key->ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
856
857 if (blend) {
858 /* Select the shader color format based on whether
859 * blending or alpha are needed.
860 */
861 key->ps.epilog.spi_shader_col_format =
862 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
863 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
864 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
865 sctx->framebuffer.spi_shader_col_format_blend) |
866 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
867 sctx->framebuffer.spi_shader_col_format_alpha) |
868 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
869 sctx->framebuffer.spi_shader_col_format);
870 } else
871 key->ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
872
873 /* If alpha-to-coverage is enabled, we have to export alpha
874 * even if there is no color buffer.
875 */
876 if (!(key->ps.epilog.spi_shader_col_format & 0xf) &&
877 blend && blend->alpha_to_coverage)
878 key->ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
879
880 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
881 * to the range supported by the type if a channel has less
882 * than 16 bits and the export format is 16_ABGR.
883 */
884 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII)
885 key->ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
886
887 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
888 if (!key->ps.epilog.last_cbuf) {
889 key->ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
890 key->ps.epilog.color_is_int8 &= sel->info.colors_written;
891 }
892
893 if (rs) {
894 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
895 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
896 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
897 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
898
899 key->ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
900
901 if (sctx->queued.named.blend) {
902 key->ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
903 rs->multisample_enable &&
904 !sctx->framebuffer.cb0_is_integer;
905 }
906
907 key->ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
908 key->ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
909 (is_line && rs->line_smooth)) &&
910 sctx->framebuffer.nr_samples <= 1;
911 key->ps.epilog.clamp_color = rs->clamp_fragment_color;
912
913 key->ps.prolog.force_persample_interp =
914 rs->force_persample_interp &&
915 rs->multisample_enable &&
916 sctx->framebuffer.nr_samples > 1 &&
917 sctx->ps_iter_samples > 1 &&
918 (sel->info.uses_persp_center ||
919 sel->info.uses_persp_centroid ||
920 sel->info.uses_linear_center ||
921 sel->info.uses_linear_centroid);
922 }
923
924 key->ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
925 break;
926 }
927 default:
928 assert(0);
929 }
930 }
931
932 /* Select the hw shader variant depending on the current state. */
933 static int si_shader_select_with_key(struct pipe_context *ctx,
934 struct si_shader_ctx_state *state,
935 union si_shader_key *key)
936 {
937 struct si_context *sctx = (struct si_context *)ctx;
938 struct si_shader_selector *sel = state->cso;
939 struct si_shader *current = state->current;
940 struct si_shader *iter, *shader = NULL;
941 int r;
942
943 /* Check if we don't need to change anything.
944 * This path is also used for most shaders that don't need multiple
945 * variants, it will cost just a computation of the key and this
946 * test. */
947 if (likely(current && memcmp(&current->key, key, sizeof(*key)) == 0))
948 return 0;
949
950 pipe_mutex_lock(sel->mutex);
951
952 /* Find the shader variant. */
953 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
954 /* Don't check the "current" shader. We checked it above. */
955 if (current != iter &&
956 memcmp(&iter->key, key, sizeof(*key)) == 0) {
957 state->current = iter;
958 pipe_mutex_unlock(sel->mutex);
959 return 0;
960 }
961 }
962
963 /* Build a new shader. */
964 shader = CALLOC_STRUCT(si_shader);
965 if (!shader) {
966 pipe_mutex_unlock(sel->mutex);
967 return -ENOMEM;
968 }
969 shader->selector = sel;
970 shader->key = *key;
971
972 r = si_shader_create(sctx->screen, sctx->tm, shader, &sctx->b.debug);
973 if (unlikely(r)) {
974 R600_ERR("Failed to build shader variant (type=%u) %d\n",
975 sel->type, r);
976 FREE(shader);
977 pipe_mutex_unlock(sel->mutex);
978 return r;
979 }
980 si_shader_init_pm4_state(shader);
981
982 if (!sel->last_variant) {
983 sel->first_variant = shader;
984 sel->last_variant = shader;
985 } else {
986 sel->last_variant->next_variant = shader;
987 sel->last_variant = shader;
988 }
989 state->current = shader;
990 pipe_mutex_unlock(sel->mutex);
991 return 0;
992 }
993
994 static int si_shader_select(struct pipe_context *ctx,
995 struct si_shader_ctx_state *state)
996 {
997 union si_shader_key key;
998
999 si_shader_selector_key(ctx, state->cso, &key);
1000 return si_shader_select_with_key(ctx, state, &key);
1001 }
1002
1003 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1004 union si_shader_key *key)
1005 {
1006 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1007
1008 switch (info->processor) {
1009 case PIPE_SHADER_VERTEX:
1010 switch (next_shader) {
1011 case PIPE_SHADER_GEOMETRY:
1012 key->vs.as_es = 1;
1013 break;
1014 case PIPE_SHADER_TESS_CTRL:
1015 case PIPE_SHADER_TESS_EVAL:
1016 key->vs.as_ls = 1;
1017 break;
1018 }
1019 break;
1020
1021 case PIPE_SHADER_TESS_EVAL:
1022 if (next_shader == PIPE_SHADER_GEOMETRY)
1023 key->tes.as_es = 1;
1024 break;
1025 }
1026 }
1027
1028 static void *si_create_shader_selector(struct pipe_context *ctx,
1029 const struct pipe_shader_state *state)
1030 {
1031 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1032 struct si_context *sctx = (struct si_context*)ctx;
1033 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1034 int i;
1035
1036 if (!sel)
1037 return NULL;
1038
1039 sel->tokens = tgsi_dup_tokens(state->tokens);
1040 if (!sel->tokens) {
1041 FREE(sel);
1042 return NULL;
1043 }
1044
1045 sel->so = state->stream_output;
1046 tgsi_scan_shader(state->tokens, &sel->info);
1047 sel->type = sel->info.processor;
1048 p_atomic_inc(&sscreen->b.num_shaders_created);
1049
1050 /* Set which opcode uses which (i,j) pair. */
1051 if (sel->info.uses_persp_opcode_interp_centroid)
1052 sel->info.uses_persp_centroid = true;
1053
1054 if (sel->info.uses_linear_opcode_interp_centroid)
1055 sel->info.uses_linear_centroid = true;
1056
1057 if (sel->info.uses_persp_opcode_interp_offset ||
1058 sel->info.uses_persp_opcode_interp_sample)
1059 sel->info.uses_persp_center = true;
1060
1061 if (sel->info.uses_linear_opcode_interp_offset ||
1062 sel->info.uses_linear_opcode_interp_sample)
1063 sel->info.uses_linear_center = true;
1064
1065 switch (sel->type) {
1066 case PIPE_SHADER_GEOMETRY:
1067 sel->gs_output_prim =
1068 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1069 sel->gs_max_out_vertices =
1070 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1071 sel->gs_num_invocations =
1072 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1073 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
1074 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
1075 sel->gs_max_out_vertices;
1076
1077 sel->max_gs_stream = 0;
1078 for (i = 0; i < sel->so.num_outputs; i++)
1079 sel->max_gs_stream = MAX2(sel->max_gs_stream,
1080 sel->so.output[i].stream);
1081
1082 sel->gs_input_verts_per_prim =
1083 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
1084 break;
1085
1086 case PIPE_SHADER_VERTEX:
1087 case PIPE_SHADER_TESS_CTRL:
1088 case PIPE_SHADER_TESS_EVAL:
1089 for (i = 0; i < sel->info.num_outputs; i++) {
1090 unsigned name = sel->info.output_semantic_name[i];
1091 unsigned index = sel->info.output_semantic_index[i];
1092
1093 switch (name) {
1094 case TGSI_SEMANTIC_TESSINNER:
1095 case TGSI_SEMANTIC_TESSOUTER:
1096 case TGSI_SEMANTIC_PATCH:
1097 sel->patch_outputs_written |=
1098 1llu << si_shader_io_get_unique_index(name, index);
1099 break;
1100 default:
1101 sel->outputs_written |=
1102 1llu << si_shader_io_get_unique_index(name, index);
1103 }
1104 }
1105 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
1106 break;
1107
1108 case PIPE_SHADER_FRAGMENT:
1109 for (i = 0; i < 8; i++)
1110 if (sel->info.colors_written & (1 << i))
1111 sel->colors_written_4bit |= 0xf << (4 * i);
1112
1113 for (i = 0; i < sel->info.num_inputs; i++) {
1114 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
1115 int index = sel->info.input_semantic_index[i];
1116 sel->color_attr_index[index] = i;
1117 }
1118 }
1119 break;
1120 }
1121
1122 /* DB_SHADER_CONTROL */
1123 sel->db_shader_control =
1124 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
1125 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
1126 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
1127 S_02880C_KILL_ENABLE(sel->info.uses_kill);
1128
1129 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
1130 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1131 sel->db_shader_control |=
1132 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
1133 break;
1134 case TGSI_FS_DEPTH_LAYOUT_LESS:
1135 sel->db_shader_control |=
1136 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
1137 break;
1138 }
1139
1140 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL])
1141 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1);
1142
1143 if (sel->info.writes_memory)
1144 sel->db_shader_control |= S_02880C_EXEC_ON_HIER_FAIL(1) |
1145 S_02880C_EXEC_ON_NOOP(1);
1146
1147 /* Compile the main shader part for use with a prolog and/or epilog. */
1148 if (sel->type != PIPE_SHADER_GEOMETRY &&
1149 !sscreen->use_monolithic_shaders) {
1150 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1151 void *tgsi_binary;
1152
1153 if (!shader)
1154 goto error;
1155
1156 shader->selector = sel;
1157 si_parse_next_shader_property(&sel->info, &shader->key);
1158
1159 tgsi_binary = si_get_tgsi_binary(sel);
1160
1161 /* Try to load the shader from the shader cache. */
1162 pipe_mutex_lock(sscreen->shader_cache_mutex);
1163
1164 if (tgsi_binary &&
1165 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1166 FREE(tgsi_binary);
1167 } else {
1168 /* Compile the shader if it hasn't been loaded from the cache. */
1169 if (si_compile_tgsi_shader(sscreen, sctx->tm, shader, false,
1170 &sctx->b.debug) != 0) {
1171 FREE(shader);
1172 FREE(tgsi_binary);
1173 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1174 goto error;
1175 }
1176
1177 if (tgsi_binary &&
1178 !si_shader_cache_insert_shader(sscreen, tgsi_binary, shader))
1179 FREE(tgsi_binary);
1180 }
1181 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1182
1183 sel->main_shader_part = shader;
1184 }
1185
1186 /* Pre-compilation. */
1187 if (sel->type == PIPE_SHADER_GEOMETRY ||
1188 sscreen->b.debug_flags & DBG_PRECOMPILE) {
1189 struct si_shader_ctx_state state = {sel};
1190 union si_shader_key key;
1191
1192 memset(&key, 0, sizeof(key));
1193 si_parse_next_shader_property(&sel->info, &key);
1194
1195 /* Set reasonable defaults, so that the shader key doesn't
1196 * cause any code to be eliminated.
1197 */
1198 switch (sel->type) {
1199 case PIPE_SHADER_TESS_CTRL:
1200 key.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1201 break;
1202 case PIPE_SHADER_FRAGMENT:
1203 key.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1204 for (i = 0; i < 8; i++)
1205 if (sel->info.colors_written & (1 << i))
1206 key.ps.epilog.spi_shader_col_format |=
1207 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1208 break;
1209 }
1210
1211 if (si_shader_select_with_key(ctx, &state, &key))
1212 goto error;
1213 }
1214
1215 pipe_mutex_init(sel->mutex);
1216 return sel;
1217
1218 error:
1219 fprintf(stderr, "radeonsi: can't create a shader\n");
1220 tgsi_free_tokens(sel->tokens);
1221 FREE(sel);
1222 return NULL;
1223 }
1224
1225 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1226 {
1227 struct si_context *sctx = (struct si_context *)ctx;
1228 struct si_shader_selector *sel = state;
1229
1230 if (sctx->vs_shader.cso == sel)
1231 return;
1232
1233 sctx->vs_shader.cso = sel;
1234 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
1235 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1236 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1237 }
1238
1239 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
1240 {
1241 struct si_context *sctx = (struct si_context *)ctx;
1242 struct si_shader_selector *sel = state;
1243 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
1244
1245 if (sctx->gs_shader.cso == sel)
1246 return;
1247
1248 sctx->gs_shader.cso = sel;
1249 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
1250 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1251 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1252
1253 if (enable_changed)
1254 si_shader_change_notify(sctx);
1255 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1256 }
1257
1258 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
1259 {
1260 struct si_context *sctx = (struct si_context *)ctx;
1261 struct si_shader_selector *sel = state;
1262 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
1263
1264 if (sctx->tcs_shader.cso == sel)
1265 return;
1266
1267 sctx->tcs_shader.cso = sel;
1268 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
1269
1270 if (enable_changed)
1271 sctx->last_tcs = NULL; /* invalidate derived tess state */
1272 }
1273
1274 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
1275 {
1276 struct si_context *sctx = (struct si_context *)ctx;
1277 struct si_shader_selector *sel = state;
1278 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
1279
1280 if (sctx->tes_shader.cso == sel)
1281 return;
1282
1283 sctx->tes_shader.cso = sel;
1284 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
1285 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1286 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1287
1288 if (enable_changed) {
1289 si_shader_change_notify(sctx);
1290 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
1291 }
1292 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1293 }
1294
1295 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1296 {
1297 struct si_context *sctx = (struct si_context *)ctx;
1298 struct si_shader_selector *sel = state;
1299
1300 /* skip if supplied shader is one already in use */
1301 if (sctx->ps_shader.cso == sel)
1302 return;
1303
1304 sctx->ps_shader.cso = sel;
1305 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
1306 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1307 }
1308
1309 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
1310 {
1311 if (shader->pm4) {
1312 switch (shader->selector->type) {
1313 case PIPE_SHADER_VERTEX:
1314 if (shader->key.vs.as_ls)
1315 si_pm4_delete_state(sctx, ls, shader->pm4);
1316 else if (shader->key.vs.as_es)
1317 si_pm4_delete_state(sctx, es, shader->pm4);
1318 else
1319 si_pm4_delete_state(sctx, vs, shader->pm4);
1320 break;
1321 case PIPE_SHADER_TESS_CTRL:
1322 si_pm4_delete_state(sctx, hs, shader->pm4);
1323 break;
1324 case PIPE_SHADER_TESS_EVAL:
1325 if (shader->key.tes.as_es)
1326 si_pm4_delete_state(sctx, es, shader->pm4);
1327 else
1328 si_pm4_delete_state(sctx, vs, shader->pm4);
1329 break;
1330 case PIPE_SHADER_GEOMETRY:
1331 si_pm4_delete_state(sctx, gs, shader->pm4);
1332 si_pm4_delete_state(sctx, vs, shader->gs_copy_shader->pm4);
1333 break;
1334 case PIPE_SHADER_FRAGMENT:
1335 si_pm4_delete_state(sctx, ps, shader->pm4);
1336 break;
1337 }
1338 }
1339
1340 si_shader_destroy(shader);
1341 free(shader);
1342 }
1343
1344 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
1345 {
1346 struct si_context *sctx = (struct si_context *)ctx;
1347 struct si_shader_selector *sel = (struct si_shader_selector *)state;
1348 struct si_shader *p = sel->first_variant, *c;
1349 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
1350 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
1351 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
1352 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
1353 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
1354 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
1355 };
1356
1357 if (current_shader[sel->type]->cso == sel) {
1358 current_shader[sel->type]->cso = NULL;
1359 current_shader[sel->type]->current = NULL;
1360 }
1361
1362 while (p) {
1363 c = p->next_variant;
1364 si_delete_shader(sctx, p);
1365 p = c;
1366 }
1367
1368 if (sel->main_shader_part)
1369 si_delete_shader(sctx, sel->main_shader_part);
1370
1371 pipe_mutex_destroy(sel->mutex);
1372 free(sel->tokens);
1373 free(sel);
1374 }
1375
1376 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
1377 struct si_shader *vs, unsigned name,
1378 unsigned index, unsigned interpolate)
1379 {
1380 struct tgsi_shader_info *vsinfo = &vs->selector->info;
1381 unsigned j, ps_input_cntl = 0;
1382
1383 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
1384 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
1385 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1386
1387 if (name == TGSI_SEMANTIC_PCOORD ||
1388 (name == TGSI_SEMANTIC_TEXCOORD &&
1389 sctx->sprite_coord_enable & (1 << index))) {
1390 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
1391 }
1392
1393 for (j = 0; j < vsinfo->num_outputs; j++) {
1394 if (name == vsinfo->output_semantic_name[j] &&
1395 index == vsinfo->output_semantic_index[j]) {
1396 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[j]);
1397 break;
1398 }
1399 }
1400
1401 if (name == TGSI_SEMANTIC_PRIMID)
1402 /* PrimID is written after the last output. */
1403 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
1404 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
1405 /* No corresponding output found, load defaults into input.
1406 * Don't set any other bits.
1407 * (FLAT_SHADE=1 completely changes behavior) */
1408 ps_input_cntl = S_028644_OFFSET(0x20);
1409 }
1410 return ps_input_cntl;
1411 }
1412
1413 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
1414 {
1415 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1416 struct si_shader *ps = sctx->ps_shader.current;
1417 struct si_shader *vs = si_get_vs_state(sctx);
1418 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
1419 unsigned i, num_interp, num_written = 0, bcol_interp[2];
1420
1421 if (!ps || !ps->selector->info.num_inputs)
1422 return;
1423
1424 num_interp = si_get_ps_num_interp(ps);
1425 assert(num_interp > 0);
1426 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
1427
1428 for (i = 0; i < psinfo->num_inputs; i++) {
1429 unsigned name = psinfo->input_semantic_name[i];
1430 unsigned index = psinfo->input_semantic_index[i];
1431 unsigned interpolate = psinfo->input_interpolate[i];
1432
1433 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
1434 interpolate));
1435 num_written++;
1436
1437 if (name == TGSI_SEMANTIC_COLOR) {
1438 assert(index < ARRAY_SIZE(bcol_interp));
1439 bcol_interp[index] = interpolate;
1440 }
1441 }
1442
1443 if (ps->key.ps.prolog.color_two_side) {
1444 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
1445
1446 for (i = 0; i < 2; i++) {
1447 if (!(psinfo->colors_read & (0xf << (i * 4))))
1448 continue;
1449
1450 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
1451 i, bcol_interp[i]));
1452 num_written++;
1453 }
1454 }
1455 assert(num_interp == num_written);
1456 }
1457
1458 /**
1459 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1460 */
1461 static void si_init_config_add_vgt_flush(struct si_context *sctx)
1462 {
1463 if (sctx->init_config_has_vgt_flush)
1464 return;
1465
1466 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1467 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1468 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1469 si_pm4_cmd_end(sctx->init_config, false);
1470 sctx->init_config_has_vgt_flush = true;
1471 }
1472
1473 /* Initialize state related to ESGS / GSVS ring buffers */
1474 static bool si_update_gs_ring_buffers(struct si_context *sctx)
1475 {
1476 struct si_shader_selector *es =
1477 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
1478 struct si_shader_selector *gs = sctx->gs_shader.cso;
1479 struct si_pm4_state *pm4;
1480
1481 /* Chip constants. */
1482 unsigned num_se = sctx->screen->b.info.max_se;
1483 unsigned wave_size = 64;
1484 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1485 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1486 unsigned alignment = 256 * num_se;
1487 /* The maximum size is 63.999 MB per SE. */
1488 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1489
1490 /* Calculate the minimum size. */
1491 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
1492 wave_size, alignment);
1493
1494 /* These are recommended sizes, not minimum sizes. */
1495 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1496 es->esgs_itemsize * gs->gs_input_verts_per_prim;
1497 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1498 gs->max_gsvs_emit_size * (gs->max_gs_stream + 1);
1499
1500 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1501 esgs_ring_size = align(esgs_ring_size, alignment);
1502 gsvs_ring_size = align(gsvs_ring_size, alignment);
1503
1504 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1505 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1506
1507 /* Some rings don't have to be allocated if shaders don't use them.
1508 * (e.g. no varyings between ES and GS or GS and VS)
1509 */
1510 bool update_esgs = esgs_ring_size &&
1511 (!sctx->esgs_ring ||
1512 sctx->esgs_ring->width0 < esgs_ring_size);
1513 bool update_gsvs = gsvs_ring_size &&
1514 (!sctx->gsvs_ring ||
1515 sctx->gsvs_ring->width0 < gsvs_ring_size);
1516
1517 if (!update_esgs && !update_gsvs)
1518 return true;
1519
1520 if (update_esgs) {
1521 pipe_resource_reference(&sctx->esgs_ring, NULL);
1522 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1523 PIPE_USAGE_DEFAULT,
1524 esgs_ring_size);
1525 if (!sctx->esgs_ring)
1526 return false;
1527 }
1528
1529 if (update_gsvs) {
1530 pipe_resource_reference(&sctx->gsvs_ring, NULL);
1531 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1532 PIPE_USAGE_DEFAULT,
1533 gsvs_ring_size);
1534 if (!sctx->gsvs_ring)
1535 return false;
1536 }
1537
1538 /* Create the "init_config_gs_rings" state. */
1539 pm4 = CALLOC_STRUCT(si_pm4_state);
1540 if (!pm4)
1541 return false;
1542
1543 if (sctx->b.chip_class >= CIK) {
1544 if (sctx->esgs_ring)
1545 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
1546 sctx->esgs_ring->width0 / 256);
1547 if (sctx->gsvs_ring)
1548 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
1549 sctx->gsvs_ring->width0 / 256);
1550 } else {
1551 if (sctx->esgs_ring)
1552 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
1553 sctx->esgs_ring->width0 / 256);
1554 if (sctx->gsvs_ring)
1555 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
1556 sctx->gsvs_ring->width0 / 256);
1557 }
1558
1559 /* Set the state. */
1560 if (sctx->init_config_gs_rings)
1561 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
1562 sctx->init_config_gs_rings = pm4;
1563
1564 if (!sctx->init_config_has_vgt_flush) {
1565 si_init_config_add_vgt_flush(sctx);
1566 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1567 }
1568
1569 /* Flush the context to re-emit both init_config states. */
1570 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1571 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1572
1573 /* Set ring bindings. */
1574 if (sctx->esgs_ring) {
1575 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
1576 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1577 true, true, 4, 64, 0);
1578 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
1579 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1580 false, false, 0, 0, 0);
1581 }
1582 if (sctx->gsvs_ring)
1583 si_set_ring_buffer(&sctx->b.b, SI_VS_RING_GSVS,
1584 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
1585 false, false, 0, 0, 0);
1586 return true;
1587 }
1588
1589 static void si_update_gsvs_ring_bindings(struct si_context *sctx)
1590 {
1591 unsigned gsvs_itemsize = sctx->gs_shader.cso->max_gsvs_emit_size;
1592 uint64_t offset;
1593
1594 if (!sctx->gsvs_ring || gsvs_itemsize == sctx->last_gsvs_itemsize)
1595 return;
1596
1597 sctx->last_gsvs_itemsize = gsvs_itemsize;
1598
1599 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS0,
1600 sctx->gsvs_ring, gsvs_itemsize,
1601 64, true, true, 4, 16, 0);
1602
1603 offset = gsvs_itemsize * 64;
1604 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS1,
1605 sctx->gsvs_ring, gsvs_itemsize,
1606 64, true, true, 4, 16, offset);
1607
1608 offset = (gsvs_itemsize * 2) * 64;
1609 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS2,
1610 sctx->gsvs_ring, gsvs_itemsize,
1611 64, true, true, 4, 16, offset);
1612
1613 offset = (gsvs_itemsize * 3) * 64;
1614 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS3,
1615 sctx->gsvs_ring, gsvs_itemsize,
1616 64, true, true, 4, 16, offset);
1617 }
1618
1619 /**
1620 * @returns 1 if \p sel has been updated to use a new scratch buffer
1621 * 0 if not
1622 * < 0 if there was a failure
1623 */
1624 static int si_update_scratch_buffer(struct si_context *sctx,
1625 struct si_shader *shader)
1626 {
1627 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1628 int r;
1629
1630 if (!shader)
1631 return 0;
1632
1633 /* This shader doesn't need a scratch buffer */
1634 if (shader->config.scratch_bytes_per_wave == 0)
1635 return 0;
1636
1637 /* This shader is already configured to use the current
1638 * scratch buffer. */
1639 if (shader->scratch_bo == sctx->scratch_buffer)
1640 return 0;
1641
1642 assert(sctx->scratch_buffer);
1643
1644 si_shader_apply_scratch_relocs(sctx, shader, &shader->config, scratch_va);
1645
1646 /* Replace the shader bo with a new bo that has the relocs applied. */
1647 r = si_shader_binary_upload(sctx->screen, shader);
1648 if (r)
1649 return r;
1650
1651 /* Update the shader state to use the new shader bo. */
1652 si_shader_init_pm4_state(shader);
1653
1654 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1655
1656 return 1;
1657 }
1658
1659 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1660 {
1661 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
1662 }
1663
1664 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
1665 {
1666 return shader ? shader->config.scratch_bytes_per_wave : 0;
1667 }
1668
1669 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1670 {
1671 unsigned bytes = 0;
1672
1673 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
1674 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
1675 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
1676 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
1677 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
1678 return bytes;
1679 }
1680
1681 static bool si_update_spi_tmpring_size(struct si_context *sctx)
1682 {
1683 unsigned current_scratch_buffer_size =
1684 si_get_current_scratch_buffer_size(sctx);
1685 unsigned scratch_bytes_per_wave =
1686 si_get_max_scratch_bytes_per_wave(sctx);
1687 unsigned scratch_needed_size = scratch_bytes_per_wave *
1688 sctx->scratch_waves;
1689 unsigned spi_tmpring_size;
1690 int r;
1691
1692 if (scratch_needed_size > 0) {
1693 if (scratch_needed_size > current_scratch_buffer_size) {
1694 /* Create a bigger scratch buffer */
1695 pipe_resource_reference(
1696 (struct pipe_resource**)&sctx->scratch_buffer,
1697 NULL);
1698
1699 sctx->scratch_buffer =
1700 si_resource_create_custom(&sctx->screen->b.b,
1701 PIPE_USAGE_DEFAULT, scratch_needed_size);
1702 if (!sctx->scratch_buffer)
1703 return false;
1704 sctx->emit_scratch_reloc = true;
1705 }
1706
1707 /* Update the shaders, so they are using the latest scratch. The
1708 * scratch buffer may have been changed since these shaders were
1709 * last used, so we still need to try to update them, even if
1710 * they require scratch buffers smaller than the current size.
1711 */
1712 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
1713 if (r < 0)
1714 return false;
1715 if (r == 1)
1716 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1717
1718 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
1719 if (r < 0)
1720 return false;
1721 if (r == 1)
1722 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1723
1724 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
1725 if (r < 0)
1726 return false;
1727 if (r == 1)
1728 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1729
1730 /* VS can be bound as LS, ES, or VS. */
1731 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
1732 if (r < 0)
1733 return false;
1734 if (r == 1) {
1735 if (sctx->tes_shader.current)
1736 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1737 else if (sctx->gs_shader.current)
1738 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1739 else
1740 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1741 }
1742
1743 /* TES can be bound as ES or VS. */
1744 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
1745 if (r < 0)
1746 return false;
1747 if (r == 1) {
1748 if (sctx->gs_shader.current)
1749 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1750 else
1751 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1752 }
1753 }
1754
1755 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1756 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1757 "scratch size should already be aligned correctly.");
1758
1759 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1760 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1761 if (spi_tmpring_size != sctx->spi_tmpring_size) {
1762 sctx->spi_tmpring_size = spi_tmpring_size;
1763 sctx->emit_scratch_reloc = true;
1764 }
1765 return true;
1766 }
1767
1768 static void si_init_tess_factor_ring(struct si_context *sctx)
1769 {
1770 assert(!sctx->tf_ring);
1771
1772 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1773 PIPE_USAGE_DEFAULT,
1774 32768 * sctx->screen->b.info.max_se);
1775 if (!sctx->tf_ring)
1776 return;
1777
1778 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1779
1780 si_init_config_add_vgt_flush(sctx);
1781
1782 /* Append these registers to the init config state. */
1783 if (sctx->b.chip_class >= CIK) {
1784 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
1785 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1786 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
1787 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1788 } else {
1789 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
1790 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1791 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
1792 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1793 }
1794
1795 /* Flush the context to re-emit the init_config state.
1796 * This is done only once in a lifetime of a context.
1797 */
1798 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1799 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1800 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1801
1802 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
1803 0, sctx->tf_ring->width0, false, false, 0, 0, 0);
1804 }
1805
1806 /**
1807 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1808 * VS passes its outputs to TES directly, so the fixed-function shader only
1809 * has to write TESSOUTER and TESSINNER.
1810 */
1811 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1812 {
1813 struct ureg_src outer, inner;
1814 struct ureg_dst tessouter, tessinner;
1815 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
1816
1817 if (!ureg)
1818 return; /* if we get here, we're screwed */
1819
1820 assert(!sctx->fixed_func_tcs_shader.cso);
1821
1822 outer = ureg_DECL_system_value(ureg,
1823 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
1824 inner = ureg_DECL_system_value(ureg,
1825 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
1826
1827 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1828 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1829
1830 ureg_MOV(ureg, tessouter, outer);
1831 ureg_MOV(ureg, tessinner, inner);
1832 ureg_END(ureg);
1833
1834 sctx->fixed_func_tcs_shader.cso =
1835 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1836 }
1837
1838 static void si_update_vgt_shader_config(struct si_context *sctx)
1839 {
1840 /* Calculate the index of the config.
1841 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1842 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
1843 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1844
1845 if (!*pm4) {
1846 uint32_t stages = 0;
1847
1848 *pm4 = CALLOC_STRUCT(si_pm4_state);
1849
1850 if (sctx->tes_shader.cso) {
1851 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1852 S_028B54_HS_EN(1);
1853
1854 if (sctx->gs_shader.cso)
1855 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1856 S_028B54_GS_EN(1) |
1857 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1858 else
1859 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1860 } else if (sctx->gs_shader.cso) {
1861 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1862 S_028B54_GS_EN(1) |
1863 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1864 }
1865
1866 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1867 }
1868 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1869 }
1870
1871 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
1872 {
1873 struct pipe_stream_output_info *so = &shader->so;
1874 uint32_t enabled_stream_buffers_mask = 0;
1875 int i;
1876
1877 for (i = 0; i < so->num_outputs; i++)
1878 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
1879 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
1880 sctx->b.streamout.stride_in_dw = shader->so.stride;
1881 }
1882
1883 bool si_update_shaders(struct si_context *sctx)
1884 {
1885 struct pipe_context *ctx = (struct pipe_context*)sctx;
1886 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1887 int r;
1888
1889 /* Update stages before GS. */
1890 if (sctx->tes_shader.cso) {
1891 if (!sctx->tf_ring) {
1892 si_init_tess_factor_ring(sctx);
1893 if (!sctx->tf_ring)
1894 return false;
1895 }
1896
1897 /* VS as LS */
1898 r = si_shader_select(ctx, &sctx->vs_shader);
1899 if (r)
1900 return false;
1901 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1902
1903 if (sctx->tcs_shader.cso) {
1904 r = si_shader_select(ctx, &sctx->tcs_shader);
1905 if (r)
1906 return false;
1907 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1908 } else {
1909 if (!sctx->fixed_func_tcs_shader.cso) {
1910 si_generate_fixed_func_tcs(sctx);
1911 if (!sctx->fixed_func_tcs_shader.cso)
1912 return false;
1913 }
1914
1915 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader);
1916 if (r)
1917 return false;
1918 si_pm4_bind_state(sctx, hs,
1919 sctx->fixed_func_tcs_shader.current->pm4);
1920 }
1921
1922 r = si_shader_select(ctx, &sctx->tes_shader);
1923 if (r)
1924 return false;
1925
1926 if (sctx->gs_shader.cso) {
1927 /* TES as ES */
1928 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1929 } else {
1930 /* TES as VS */
1931 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1932 si_update_so(sctx, sctx->tes_shader.cso);
1933 }
1934 } else if (sctx->gs_shader.cso) {
1935 /* VS as ES */
1936 r = si_shader_select(ctx, &sctx->vs_shader);
1937 if (r)
1938 return false;
1939 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1940 } else {
1941 /* VS as VS */
1942 r = si_shader_select(ctx, &sctx->vs_shader);
1943 if (r)
1944 return false;
1945 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1946 si_update_so(sctx, sctx->vs_shader.cso);
1947 }
1948
1949 /* Update GS. */
1950 if (sctx->gs_shader.cso) {
1951 r = si_shader_select(ctx, &sctx->gs_shader);
1952 if (r)
1953 return false;
1954 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1955 si_pm4_bind_state(sctx, vs, sctx->gs_shader.current->gs_copy_shader->pm4);
1956 si_update_so(sctx, sctx->gs_shader.cso);
1957
1958 if (!si_update_gs_ring_buffers(sctx))
1959 return false;
1960
1961 si_update_gsvs_ring_bindings(sctx);
1962 } else {
1963 si_pm4_bind_state(sctx, gs, NULL);
1964 si_pm4_bind_state(sctx, es, NULL);
1965 }
1966
1967 si_update_vgt_shader_config(sctx);
1968
1969 if (sctx->ps_shader.cso) {
1970 unsigned db_shader_control;
1971
1972 r = si_shader_select(ctx, &sctx->ps_shader);
1973 if (r)
1974 return false;
1975 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1976
1977 db_shader_control =
1978 sctx->ps_shader.cso->db_shader_control |
1979 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS) |
1980 S_02880C_Z_ORDER(sctx->ps_shader.current->z_order);
1981
1982 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1983 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
1984 sctx->flatshade != rs->flatshade) {
1985 sctx->sprite_coord_enable = rs->sprite_coord_enable;
1986 sctx->flatshade = rs->flatshade;
1987 si_mark_atom_dirty(sctx, &sctx->spi_map);
1988 }
1989
1990 if (sctx->b.family == CHIP_STONEY && si_pm4_state_changed(sctx, ps))
1991 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1992
1993 if (sctx->ps_db_shader_control != db_shader_control) {
1994 sctx->ps_db_shader_control = db_shader_control;
1995 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1996 }
1997
1998 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.ps.epilog.poly_line_smoothing) {
1999 sctx->smoothing_enabled = sctx->ps_shader.current->key.ps.epilog.poly_line_smoothing;
2000 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2001
2002 if (sctx->b.chip_class == SI)
2003 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2004 }
2005 }
2006
2007 if (si_pm4_state_changed(sctx, ls) ||
2008 si_pm4_state_changed(sctx, hs) ||
2009 si_pm4_state_changed(sctx, es) ||
2010 si_pm4_state_changed(sctx, gs) ||
2011 si_pm4_state_changed(sctx, vs) ||
2012 si_pm4_state_changed(sctx, ps)) {
2013 if (!si_update_spi_tmpring_size(sctx))
2014 return false;
2015 }
2016 return true;
2017 }
2018
2019 void si_init_shader_functions(struct si_context *sctx)
2020 {
2021 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
2022
2023 sctx->b.b.create_vs_state = si_create_shader_selector;
2024 sctx->b.b.create_tcs_state = si_create_shader_selector;
2025 sctx->b.b.create_tes_state = si_create_shader_selector;
2026 sctx->b.b.create_gs_state = si_create_shader_selector;
2027 sctx->b.b.create_fs_state = si_create_shader_selector;
2028
2029 sctx->b.b.bind_vs_state = si_bind_vs_shader;
2030 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
2031 sctx->b.b.bind_tes_state = si_bind_tes_shader;
2032 sctx->b.b.bind_gs_state = si_bind_gs_shader;
2033 sctx->b.b.bind_fs_state = si_bind_ps_shader;
2034
2035 sctx->b.b.delete_vs_state = si_delete_shader_selector;
2036 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
2037 sctx->b.b.delete_tes_state = si_delete_shader_selector;
2038 sctx->b.b.delete_gs_state = si_delete_shader_selector;
2039 sctx->b.b.delete_fs_state = si_delete_shader_selector;
2040 }