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gallium/radeon: remove build_intrinsic and build_tgsi_intrinsic
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_ureg.h"
34 #include "util/u_memory.h"
35 #include "util/u_simple_shaders.h"
36
37 static void si_set_tesseval_regs(struct si_shader *shader,
38 struct si_pm4_state *pm4)
39 {
40 struct tgsi_shader_info *info = &shader->selector->info;
41 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
42 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
43 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
44 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
45 unsigned type, partitioning, topology;
46
47 switch (tes_prim_mode) {
48 case PIPE_PRIM_LINES:
49 type = V_028B6C_TESS_ISOLINE;
50 break;
51 case PIPE_PRIM_TRIANGLES:
52 type = V_028B6C_TESS_TRIANGLE;
53 break;
54 case PIPE_PRIM_QUADS:
55 type = V_028B6C_TESS_QUAD;
56 break;
57 default:
58 assert(0);
59 return;
60 }
61
62 switch (tes_spacing) {
63 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
64 partitioning = V_028B6C_PART_FRAC_ODD;
65 break;
66 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
67 partitioning = V_028B6C_PART_FRAC_EVEN;
68 break;
69 case PIPE_TESS_SPACING_EQUAL:
70 partitioning = V_028B6C_PART_INTEGER;
71 break;
72 default:
73 assert(0);
74 return;
75 }
76
77 if (tes_point_mode)
78 topology = V_028B6C_OUTPUT_POINT;
79 else if (tes_prim_mode == PIPE_PRIM_LINES)
80 topology = V_028B6C_OUTPUT_LINE;
81 else if (tes_vertex_order_cw)
82 /* for some reason, this must be the other way around */
83 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
84 else
85 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
86
87 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
88 S_028B6C_TYPE(type) |
89 S_028B6C_PARTITIONING(partitioning) |
90 S_028B6C_TOPOLOGY(topology));
91 }
92
93 static void si_shader_ls(struct si_shader *shader)
94 {
95 struct si_pm4_state *pm4;
96 unsigned num_sgprs, num_user_sgprs;
97 unsigned vgpr_comp_cnt;
98 uint64_t va;
99
100 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
101 if (pm4 == NULL)
102 return;
103
104 va = shader->bo->gpu_address;
105 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
106
107 /* We need at least 2 components for LS.
108 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
109 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 1;
110
111 num_user_sgprs = SI_LS_NUM_USER_SGPR;
112 num_sgprs = shader->num_sgprs;
113 if (num_user_sgprs > num_sgprs) {
114 /* Last 2 reserved SGPRs are used for VCC */
115 num_sgprs = num_user_sgprs + 2;
116 }
117 assert(num_sgprs <= 104);
118
119 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
120 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
121
122 shader->ls_rsrc1 = S_00B528_VGPRS((shader->num_vgprs - 1) / 4) |
123 S_00B528_SGPRS((num_sgprs - 1) / 8) |
124 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt);
125 shader->ls_rsrc2 = S_00B52C_USER_SGPR(num_user_sgprs) |
126 S_00B52C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0);
127 }
128
129 static void si_shader_hs(struct si_shader *shader)
130 {
131 struct si_pm4_state *pm4;
132 unsigned num_sgprs, num_user_sgprs;
133 uint64_t va;
134
135 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
136 if (pm4 == NULL)
137 return;
138
139 va = shader->bo->gpu_address;
140 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
141
142 num_user_sgprs = SI_TCS_NUM_USER_SGPR;
143 num_sgprs = shader->num_sgprs;
144 /* One SGPR after user SGPRs is pre-loaded with tessellation factor
145 * buffer offset. */
146 if ((num_user_sgprs + 1) > num_sgprs) {
147 /* Last 2 reserved SGPRs are used for VCC */
148 num_sgprs = num_user_sgprs + 1 + 2;
149 }
150 assert(num_sgprs <= 104);
151
152 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
153 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
154 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
155 S_00B428_VGPRS((shader->num_vgprs - 1) / 4) |
156 S_00B428_SGPRS((num_sgprs - 1) / 8));
157 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
158 S_00B42C_USER_SGPR(num_user_sgprs) |
159 S_00B42C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
160 }
161
162 static void si_shader_es(struct si_shader *shader)
163 {
164 struct si_pm4_state *pm4;
165 unsigned num_sgprs, num_user_sgprs;
166 unsigned vgpr_comp_cnt;
167 uint64_t va;
168
169 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
170
171 if (pm4 == NULL)
172 return;
173
174 va = shader->bo->gpu_address;
175 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
176
177 if (shader->selector->type == PIPE_SHADER_VERTEX) {
178 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
179 num_user_sgprs = SI_VS_NUM_USER_SGPR;
180 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
181 vgpr_comp_cnt = 3; /* all components are needed for TES */
182 num_user_sgprs = SI_TES_NUM_USER_SGPR;
183 } else
184 assert(0);
185
186 num_sgprs = shader->num_sgprs;
187 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
188 if ((num_user_sgprs + 1) > num_sgprs) {
189 /* Last 2 reserved SGPRs are used for VCC */
190 num_sgprs = num_user_sgprs + 1 + 2;
191 }
192 assert(num_sgprs <= 104);
193
194 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
195 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
196 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
197 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
198 S_00B328_SGPRS((num_sgprs - 1) / 8) |
199 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
200 S_00B328_DX10_CLAMP(shader->dx10_clamp_mode));
201 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
202 S_00B32C_USER_SGPR(num_user_sgprs) |
203 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
204
205 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
206 si_set_tesseval_regs(shader, pm4);
207 }
208
209 static unsigned si_gs_get_max_stream(struct si_shader *shader)
210 {
211 struct pipe_stream_output_info *so = &shader->selector->so;
212 unsigned max_stream = 0, i;
213
214 if (so->num_outputs == 0)
215 return 0;
216
217 for (i = 0; i < so->num_outputs; i++) {
218 if (so->output[i].stream > max_stream)
219 max_stream = so->output[i].stream;
220 }
221 return max_stream;
222 }
223
224 static void si_shader_gs(struct si_shader *shader)
225 {
226 unsigned gs_vert_itemsize = shader->selector->info.num_outputs * 16;
227 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
228 unsigned gsvs_itemsize = (gs_vert_itemsize * gs_max_vert_out) >> 2;
229 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
230 unsigned cut_mode;
231 struct si_pm4_state *pm4;
232 unsigned num_sgprs, num_user_sgprs;
233 uint64_t va;
234 unsigned max_stream = si_gs_get_max_stream(shader);
235
236 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
237 assert(gsvs_itemsize < (1 << 15));
238
239 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
240
241 if (pm4 == NULL)
242 return;
243
244 if (gs_max_vert_out <= 128) {
245 cut_mode = V_028A40_GS_CUT_128;
246 } else if (gs_max_vert_out <= 256) {
247 cut_mode = V_028A40_GS_CUT_256;
248 } else if (gs_max_vert_out <= 512) {
249 cut_mode = V_028A40_GS_CUT_512;
250 } else {
251 assert(gs_max_vert_out <= 1024);
252 cut_mode = V_028A40_GS_CUT_1024;
253 }
254
255 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
256 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
257 S_028A40_CUT_MODE(cut_mode)|
258 S_028A40_ES_WRITE_OPTIMIZE(1) |
259 S_028A40_GS_WRITE_OPTIMIZE(1));
260
261 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
262 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
263 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
264
265 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
266 util_bitcount64(shader->selector->inputs_read) * (16 >> 2));
267 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
268
269 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
270
271 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
272 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
273 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
274 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
275
276 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
277 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
278 S_028B90_ENABLE(gs_num_invocations > 0));
279
280 va = shader->bo->gpu_address;
281 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
282 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
283 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
284
285 num_user_sgprs = SI_GS_NUM_USER_SGPR;
286 num_sgprs = shader->num_sgprs;
287 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
288 if ((num_user_sgprs + 2) > num_sgprs) {
289 /* Last 2 reserved SGPRs are used for VCC */
290 num_sgprs = num_user_sgprs + 2 + 2;
291 }
292 assert(num_sgprs <= 104);
293
294 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
295 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
296 S_00B228_SGPRS((num_sgprs - 1) / 8) |
297 S_00B228_DX10_CLAMP(shader->dx10_clamp_mode));
298 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
299 S_00B22C_USER_SGPR(num_user_sgprs) |
300 S_00B22C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
301 }
302
303 static void si_shader_vs(struct si_shader *shader)
304 {
305 struct si_pm4_state *pm4;
306 unsigned num_sgprs, num_user_sgprs;
307 unsigned nparams, vgpr_comp_cnt;
308 uint64_t va;
309 unsigned window_space =
310 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
311
312 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
313
314 if (pm4 == NULL)
315 return;
316
317 va = shader->bo->gpu_address;
318 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
319
320 if (shader->is_gs_copy_shader) {
321 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
322 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
323 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
324 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
325 num_user_sgprs = SI_VS_NUM_USER_SGPR;
326 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
327 vgpr_comp_cnt = 3; /* all components are needed for TES */
328 num_user_sgprs = SI_TES_NUM_USER_SGPR;
329 } else
330 assert(0);
331
332 num_sgprs = shader->num_sgprs;
333 if (num_user_sgprs > num_sgprs) {
334 /* Last 2 reserved SGPRs are used for VCC */
335 num_sgprs = num_user_sgprs + 2;
336 }
337 assert(num_sgprs <= 104);
338
339 /* VS is required to export at least one param. */
340 nparams = MAX2(shader->nr_param_exports, 1);
341 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
342 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
343
344 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
345 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
346 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
347 V_02870C_SPI_SHADER_4COMP :
348 V_02870C_SPI_SHADER_NONE) |
349 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
350 V_02870C_SPI_SHADER_4COMP :
351 V_02870C_SPI_SHADER_NONE) |
352 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
353 V_02870C_SPI_SHADER_4COMP :
354 V_02870C_SPI_SHADER_NONE));
355
356 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
357 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
358 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
359 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
360 S_00B128_SGPRS((num_sgprs - 1) / 8) |
361 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
362 S_00B128_DX10_CLAMP(shader->dx10_clamp_mode));
363 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
364 S_00B12C_USER_SGPR(num_user_sgprs) |
365 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
366 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
367 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
368 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
369 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
370 S_00B12C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
371 if (window_space)
372 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
373 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
374 else
375 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
376 S_028818_VTX_W0_FMT(1) |
377 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
378 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
379 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
380
381 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
382 si_set_tesseval_regs(shader, pm4);
383 }
384
385 static void si_shader_ps(struct si_shader *shader)
386 {
387 struct tgsi_shader_info *info = &shader->selector->info;
388 struct si_pm4_state *pm4;
389 unsigned i, spi_ps_in_control;
390 unsigned num_sgprs, num_user_sgprs;
391 unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
392 uint64_t va;
393
394 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
395
396 if (pm4 == NULL)
397 return;
398
399 for (i = 0; i < info->num_inputs; i++) {
400 switch (info->input_semantic_name[i]) {
401 case TGSI_SEMANTIC_POSITION:
402 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
403 * Possible vaules:
404 * 0 -> Position = pixel center (default)
405 * 1 -> Position = pixel centroid
406 * 2 -> Position = at sample position
407 */
408 switch (info->input_interpolate_loc[i]) {
409 case TGSI_INTERPOLATE_LOC_CENTROID:
410 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
411 break;
412 case TGSI_INTERPOLATE_LOC_SAMPLE:
413 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
414 break;
415 }
416
417 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
418 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
419 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
420 break;
421 }
422 }
423
424 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
425 S_0286D8_BC_OPTIMIZE_DISABLE(1);
426
427 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
428 spi_ps_input_ena = shader->spi_ps_input_ena;
429 /* we need to enable at least one of them, otherwise we hang the GPU */
430 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
431 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
432 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
433 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
434 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
435 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
436 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
437 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
438
439 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
440 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
441 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
442
443 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
444 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
445 shader->spi_shader_col_format);
446 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
447
448 va = shader->bo->gpu_address;
449 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
450 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
451 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
452
453 num_user_sgprs = SI_PS_NUM_USER_SGPR;
454 num_sgprs = shader->num_sgprs;
455 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
456 if ((num_user_sgprs + 1) > num_sgprs) {
457 /* Last 2 reserved SGPRs are used for VCC */
458 num_sgprs = num_user_sgprs + 1 + 2;
459 }
460 assert(num_sgprs <= 104);
461
462 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
463 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
464 S_00B028_SGPRS((num_sgprs - 1) / 8) |
465 S_00B028_DX10_CLAMP(shader->dx10_clamp_mode));
466 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
467 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
468 S_00B02C_USER_SGPR(num_user_sgprs) |
469 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
470 }
471
472 static void si_shader_init_pm4_state(struct si_shader *shader)
473 {
474
475 if (shader->pm4)
476 si_pm4_free_state_simple(shader->pm4);
477
478 switch (shader->selector->type) {
479 case PIPE_SHADER_VERTEX:
480 if (shader->key.vs.as_ls)
481 si_shader_ls(shader);
482 else if (shader->key.vs.as_es)
483 si_shader_es(shader);
484 else
485 si_shader_vs(shader);
486 break;
487 case PIPE_SHADER_TESS_CTRL:
488 si_shader_hs(shader);
489 break;
490 case PIPE_SHADER_TESS_EVAL:
491 if (shader->key.tes.as_es)
492 si_shader_es(shader);
493 else
494 si_shader_vs(shader);
495 break;
496 case PIPE_SHADER_GEOMETRY:
497 si_shader_gs(shader);
498 si_shader_vs(shader->gs_copy_shader);
499 break;
500 case PIPE_SHADER_FRAGMENT:
501 si_shader_ps(shader);
502 break;
503 default:
504 assert(0);
505 }
506 }
507
508 /* Compute the key for the hw shader variant */
509 static inline void si_shader_selector_key(struct pipe_context *ctx,
510 struct si_shader_selector *sel,
511 union si_shader_key *key)
512 {
513 struct si_context *sctx = (struct si_context *)ctx;
514 unsigned i;
515
516 memset(key, 0, sizeof(*key));
517
518 switch (sel->type) {
519 case PIPE_SHADER_VERTEX:
520 if (sctx->vertex_elements)
521 for (i = 0; i < sctx->vertex_elements->count; ++i)
522 key->vs.instance_divisors[i] =
523 sctx->vertex_elements->elements[i].instance_divisor;
524
525 if (sctx->tes_shader)
526 key->vs.as_ls = 1;
527 else if (sctx->gs_shader) {
528 key->vs.as_es = 1;
529 key->vs.es_enabled_outputs = sctx->gs_shader->inputs_read;
530 }
531 break;
532 case PIPE_SHADER_TESS_CTRL:
533 key->tcs.prim_mode =
534 sctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
535 break;
536 case PIPE_SHADER_TESS_EVAL:
537 if (sctx->gs_shader) {
538 key->tes.as_es = 1;
539 key->tes.es_enabled_outputs = sctx->gs_shader->inputs_read;
540 }
541 break;
542 case PIPE_SHADER_GEOMETRY:
543 break;
544 case PIPE_SHADER_FRAGMENT: {
545 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
546
547 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
548 key->ps.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
549 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
550
551 if (rs) {
552 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
553 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
554 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
555 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
556
557 key->ps.color_two_side = rs->two_side;
558
559 if (sctx->queued.named.blend) {
560 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
561 rs->multisample_enable &&
562 !sctx->framebuffer.cb0_is_integer;
563 }
564
565 key->ps.poly_stipple = rs->poly_stipple_enable && is_poly;
566 key->ps.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
567 (is_line && rs->line_smooth)) &&
568 sctx->framebuffer.nr_samples <= 1;
569 }
570
571 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
572 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
573 if (sctx->queued.named.dsa &&
574 !sctx->framebuffer.cb0_is_integer)
575 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
576 break;
577 }
578 default:
579 assert(0);
580 }
581 }
582
583 /* Select the hw shader variant depending on the current state. */
584 static int si_shader_select(struct pipe_context *ctx,
585 struct si_shader_selector *sel)
586 {
587 struct si_context *sctx = (struct si_context *)ctx;
588 union si_shader_key key;
589 struct si_shader * shader = NULL;
590 int r;
591
592 si_shader_selector_key(ctx, sel, &key);
593
594 /* Check if we don't need to change anything.
595 * This path is also used for most shaders that don't need multiple
596 * variants, it will cost just a computation of the key and this
597 * test. */
598 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
599 return 0;
600 }
601
602 /* lookup if we have other variants in the list */
603 if (sel->num_shaders > 1) {
604 struct si_shader *p = sel->current, *c = p->next_variant;
605
606 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
607 p = c;
608 c = c->next_variant;
609 }
610
611 if (c) {
612 p->next_variant = c->next_variant;
613 shader = c;
614 }
615 }
616
617 if (shader) {
618 shader->next_variant = sel->current;
619 sel->current = shader;
620 } else {
621 shader = CALLOC(1, sizeof(struct si_shader));
622 shader->selector = sel;
623 shader->key = key;
624
625 shader->next_variant = sel->current;
626 sel->current = shader;
627 r = si_shader_create((struct si_screen*)ctx->screen, sctx->tm,
628 shader);
629 if (unlikely(r)) {
630 R600_ERR("Failed to build shader variant (type=%u) %d\n",
631 sel->type, r);
632 sel->current = NULL;
633 FREE(shader);
634 return r;
635 }
636 si_shader_init_pm4_state(shader);
637 sel->num_shaders++;
638 }
639
640 return 0;
641 }
642
643 static void *si_create_shader_state(struct pipe_context *ctx,
644 const struct pipe_shader_state *state,
645 unsigned pipe_shader_type)
646 {
647 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
648 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
649 int i;
650
651 sel->type = pipe_shader_type;
652 sel->tokens = tgsi_dup_tokens(state->tokens);
653 sel->so = state->stream_output;
654 tgsi_scan_shader(state->tokens, &sel->info);
655
656 switch (pipe_shader_type) {
657 case PIPE_SHADER_GEOMETRY:
658 sel->gs_output_prim =
659 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
660 sel->gs_max_out_vertices =
661 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
662 sel->gs_num_invocations =
663 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
664
665 for (i = 0; i < sel->info.num_inputs; i++) {
666 unsigned name = sel->info.input_semantic_name[i];
667 unsigned index = sel->info.input_semantic_index[i];
668
669 switch (name) {
670 case TGSI_SEMANTIC_PRIMID:
671 break;
672 default:
673 sel->inputs_read |=
674 1llu << si_shader_io_get_unique_index(name, index);
675 }
676 }
677 break;
678
679 case PIPE_SHADER_VERTEX:
680 case PIPE_SHADER_TESS_CTRL:
681 for (i = 0; i < sel->info.num_outputs; i++) {
682 unsigned name = sel->info.output_semantic_name[i];
683 unsigned index = sel->info.output_semantic_index[i];
684
685 switch (name) {
686 case TGSI_SEMANTIC_TESSINNER:
687 case TGSI_SEMANTIC_TESSOUTER:
688 case TGSI_SEMANTIC_PATCH:
689 sel->patch_outputs_written |=
690 1llu << si_shader_io_get_unique_index(name, index);
691 break;
692 default:
693 sel->outputs_written |=
694 1llu << si_shader_io_get_unique_index(name, index);
695 }
696 }
697 break;
698 }
699
700 if (sscreen->b.debug_flags & DBG_PRECOMPILE)
701 si_shader_select(ctx, sel);
702
703 return sel;
704 }
705
706 static void *si_create_fs_state(struct pipe_context *ctx,
707 const struct pipe_shader_state *state)
708 {
709 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
710 }
711
712 static void *si_create_gs_state(struct pipe_context *ctx,
713 const struct pipe_shader_state *state)
714 {
715 return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
716 }
717
718 static void *si_create_vs_state(struct pipe_context *ctx,
719 const struct pipe_shader_state *state)
720 {
721 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
722 }
723
724 static void *si_create_tcs_state(struct pipe_context *ctx,
725 const struct pipe_shader_state *state)
726 {
727 return si_create_shader_state(ctx, state, PIPE_SHADER_TESS_CTRL);
728 }
729
730 static void *si_create_tes_state(struct pipe_context *ctx,
731 const struct pipe_shader_state *state)
732 {
733 return si_create_shader_state(ctx, state, PIPE_SHADER_TESS_EVAL);
734 }
735
736 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
737 {
738 struct si_context *sctx = (struct si_context *)ctx;
739 struct si_shader_selector *sel = state;
740
741 if (sctx->vs_shader == sel || !sel)
742 return;
743
744 sctx->vs_shader = sel;
745 sctx->clip_regs.dirty = true;
746 }
747
748 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
749 {
750 struct si_context *sctx = (struct si_context *)ctx;
751 struct si_shader_selector *sel = state;
752 bool enable_changed = !!sctx->gs_shader != !!sel;
753
754 if (sctx->gs_shader == sel)
755 return;
756
757 sctx->gs_shader = sel;
758 sctx->clip_regs.dirty = true;
759 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
760
761 if (enable_changed)
762 si_shader_change_notify(sctx);
763 }
764
765 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
766 {
767 struct si_context *sctx = (struct si_context *)ctx;
768 struct si_shader_selector *sel = state;
769 bool enable_changed = !!sctx->tcs_shader != !!sel;
770
771 if (sctx->tcs_shader == sel)
772 return;
773
774 sctx->tcs_shader = sel;
775
776 if (enable_changed)
777 sctx->last_tcs = NULL; /* invalidate derived tess state */
778 }
779
780 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
781 {
782 struct si_context *sctx = (struct si_context *)ctx;
783 struct si_shader_selector *sel = state;
784 bool enable_changed = !!sctx->tes_shader != !!sel;
785
786 if (sctx->tes_shader == sel)
787 return;
788
789 sctx->tes_shader = sel;
790 sctx->clip_regs.dirty = true;
791 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
792
793 if (enable_changed) {
794 si_shader_change_notify(sctx);
795 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
796 }
797 }
798
799 static void si_make_dummy_ps(struct si_context *sctx)
800 {
801 if (!sctx->dummy_pixel_shader) {
802 sctx->dummy_pixel_shader =
803 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
804 TGSI_SEMANTIC_GENERIC,
805 TGSI_INTERPOLATE_CONSTANT);
806 }
807 }
808
809 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
810 {
811 struct si_context *sctx = (struct si_context *)ctx;
812 struct si_shader_selector *sel = state;
813
814 /* skip if supplied shader is one already in use */
815 if (sctx->ps_shader == sel)
816 return;
817
818 /* use a dummy shader if binding a NULL shader */
819 if (!sel) {
820 si_make_dummy_ps(sctx);
821 sel = sctx->dummy_pixel_shader;
822 }
823
824 sctx->ps_shader = sel;
825 }
826
827 static void si_delete_shader_selector(struct pipe_context *ctx,
828 struct si_shader_selector *sel)
829 {
830 struct si_context *sctx = (struct si_context *)ctx;
831 struct si_shader *p = sel->current, *c;
832
833 while (p) {
834 c = p->next_variant;
835 switch (sel->type) {
836 case PIPE_SHADER_VERTEX:
837 if (p->key.vs.as_ls)
838 si_pm4_delete_state(sctx, ls, p->pm4);
839 else if (p->key.vs.as_es)
840 si_pm4_delete_state(sctx, es, p->pm4);
841 else
842 si_pm4_delete_state(sctx, vs, p->pm4);
843 break;
844 case PIPE_SHADER_TESS_CTRL:
845 si_pm4_delete_state(sctx, hs, p->pm4);
846 break;
847 case PIPE_SHADER_TESS_EVAL:
848 if (p->key.tes.as_es)
849 si_pm4_delete_state(sctx, es, p->pm4);
850 else
851 si_pm4_delete_state(sctx, vs, p->pm4);
852 break;
853 case PIPE_SHADER_GEOMETRY:
854 si_pm4_delete_state(sctx, gs, p->pm4);
855 si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
856 break;
857 case PIPE_SHADER_FRAGMENT:
858 si_pm4_delete_state(sctx, ps, p->pm4);
859 break;
860 }
861
862 si_shader_destroy(ctx, p);
863 free(p);
864 p = c;
865 }
866
867 free(sel->tokens);
868 free(sel);
869 }
870
871 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
872 {
873 struct si_context *sctx = (struct si_context *)ctx;
874 struct si_shader_selector *sel = (struct si_shader_selector *)state;
875
876 if (sctx->vs_shader == sel) {
877 sctx->vs_shader = NULL;
878 }
879
880 si_delete_shader_selector(ctx, sel);
881 }
882
883 static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
884 {
885 struct si_context *sctx = (struct si_context *)ctx;
886 struct si_shader_selector *sel = (struct si_shader_selector *)state;
887
888 if (sctx->gs_shader == sel) {
889 sctx->gs_shader = NULL;
890 }
891
892 si_delete_shader_selector(ctx, sel);
893 }
894
895 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
896 {
897 struct si_context *sctx = (struct si_context *)ctx;
898 struct si_shader_selector *sel = (struct si_shader_selector *)state;
899
900 if (sctx->ps_shader == sel) {
901 sctx->ps_shader = NULL;
902 }
903
904 si_delete_shader_selector(ctx, sel);
905 }
906
907 static void si_delete_tcs_shader(struct pipe_context *ctx, void *state)
908 {
909 struct si_context *sctx = (struct si_context *)ctx;
910 struct si_shader_selector *sel = (struct si_shader_selector *)state;
911
912 if (sctx->tcs_shader == sel) {
913 sctx->tcs_shader = NULL;
914 }
915
916 si_delete_shader_selector(ctx, sel);
917 }
918
919 static void si_delete_tes_shader(struct pipe_context *ctx, void *state)
920 {
921 struct si_context *sctx = (struct si_context *)ctx;
922 struct si_shader_selector *sel = (struct si_shader_selector *)state;
923
924 if (sctx->tes_shader == sel) {
925 sctx->tes_shader = NULL;
926 }
927
928 si_delete_shader_selector(ctx, sel);
929 }
930
931 static void si_update_spi_map(struct si_context *sctx)
932 {
933 struct si_shader *ps = sctx->ps_shader->current;
934 struct si_shader *vs = si_get_vs_state(sctx);
935 struct tgsi_shader_info *psinfo = &ps->selector->info;
936 struct tgsi_shader_info *vsinfo = &vs->selector->info;
937 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
938 unsigned i, j, tmp;
939
940 for (i = 0; i < psinfo->num_inputs; i++) {
941 unsigned name = psinfo->input_semantic_name[i];
942 unsigned index = psinfo->input_semantic_index[i];
943 unsigned interpolate = psinfo->input_interpolate[i];
944 unsigned param_offset = ps->ps_input_param_offset[i];
945
946 if (name == TGSI_SEMANTIC_POSITION ||
947 name == TGSI_SEMANTIC_FACE)
948 /* Read from preloaded VGPRs, not parameters */
949 continue;
950
951 bcolor:
952 tmp = 0;
953
954 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
955 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
956 tmp |= S_028644_FLAT_SHADE(1);
957
958 if (name == TGSI_SEMANTIC_PCOORD ||
959 (name == TGSI_SEMANTIC_TEXCOORD &&
960 sctx->sprite_coord_enable & (1 << index))) {
961 tmp |= S_028644_PT_SPRITE_TEX(1);
962 }
963
964 for (j = 0; j < vsinfo->num_outputs; j++) {
965 if (name == vsinfo->output_semantic_name[j] &&
966 index == vsinfo->output_semantic_index[j]) {
967 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
968 break;
969 }
970 }
971
972 if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(tmp)) {
973 /* No corresponding output found, load defaults into input.
974 * Don't set any other bits.
975 * (FLAT_SHADE=1 completely changes behavior) */
976 tmp = S_028644_OFFSET(0x20);
977 }
978
979 si_pm4_set_reg(pm4,
980 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
981 tmp);
982
983 if (name == TGSI_SEMANTIC_COLOR &&
984 ps->key.ps.color_two_side) {
985 name = TGSI_SEMANTIC_BCOLOR;
986 param_offset++;
987 goto bcolor;
988 }
989 }
990
991 si_pm4_set_state(sctx, spi, pm4);
992 }
993
994 /* Initialize state related to ESGS / GSVS ring buffers */
995 static void si_init_gs_rings(struct si_context *sctx)
996 {
997 unsigned esgs_ring_size = 128 * 1024;
998 unsigned gsvs_ring_size = 64 * 1024 * 1024;
999
1000 assert(!sctx->gs_rings);
1001 sctx->gs_rings = CALLOC_STRUCT(si_pm4_state);
1002
1003 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1004 PIPE_USAGE_DEFAULT, esgs_ring_size);
1005
1006 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1007 PIPE_USAGE_DEFAULT, gsvs_ring_size);
1008
1009 if (sctx->b.chip_class >= CIK) {
1010 si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
1011 esgs_ring_size / 256);
1012 si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
1013 gsvs_ring_size / 256);
1014 } else {
1015 si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
1016 esgs_ring_size / 256);
1017 si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
1018 gsvs_ring_size / 256);
1019 }
1020
1021 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
1022 sctx->esgs_ring, 0, esgs_ring_size,
1023 true, true, 4, 64, 0);
1024 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
1025 sctx->esgs_ring, 0, esgs_ring_size,
1026 false, false, 0, 0, 0);
1027 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
1028 sctx->gsvs_ring, 0, gsvs_ring_size,
1029 false, false, 0, 0, 0);
1030 }
1031
1032 static void si_update_gs_rings(struct si_context *sctx)
1033 {
1034 unsigned gs_vert_itemsize = sctx->gs_shader->info.num_outputs * 16;
1035 unsigned gs_max_vert_out = sctx->gs_shader->gs_max_out_vertices;
1036 unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
1037 uint64_t offset;
1038
1039 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
1040 sctx->gsvs_ring, gsvs_itemsize,
1041 64, true, true, 4, 16, 0);
1042
1043 offset = gsvs_itemsize * 64;
1044 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_1,
1045 sctx->gsvs_ring, gsvs_itemsize,
1046 64, true, true, 4, 16, offset);
1047
1048 offset = (gsvs_itemsize * 2) * 64;
1049 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_2,
1050 sctx->gsvs_ring, gsvs_itemsize,
1051 64, true, true, 4, 16, offset);
1052
1053 offset = (gsvs_itemsize * 3) * 64;
1054 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_3,
1055 sctx->gsvs_ring, gsvs_itemsize,
1056 64, true, true, 4, 16, offset);
1057
1058 }
1059 /**
1060 * @returns 1 if \p sel has been updated to use a new scratch buffer and 0
1061 * otherwise.
1062 */
1063 static unsigned si_update_scratch_buffer(struct si_context *sctx,
1064 struct si_shader_selector *sel)
1065 {
1066 struct si_shader *shader;
1067 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1068
1069 if (!sel)
1070 return 0;
1071
1072 shader = sel->current;
1073
1074 /* This shader doesn't need a scratch buffer */
1075 if (shader->scratch_bytes_per_wave == 0)
1076 return 0;
1077
1078 /* This shader is already configured to use the current
1079 * scratch buffer. */
1080 if (shader->scratch_bo == sctx->scratch_buffer)
1081 return 0;
1082
1083 assert(sctx->scratch_buffer);
1084
1085 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
1086
1087 /* Replace the shader bo with a new bo that has the relocs applied. */
1088 si_shader_binary_upload(sctx->screen, shader);
1089
1090 /* Update the shader state to use the new shader bo. */
1091 si_shader_init_pm4_state(shader);
1092
1093 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1094
1095 return 1;
1096 }
1097
1098 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1099 {
1100 if (!sctx->scratch_buffer)
1101 return 0;
1102
1103 return sctx->scratch_buffer->b.b.width0;
1104 }
1105
1106 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_context *sctx,
1107 struct si_shader_selector *sel)
1108 {
1109 if (!sel)
1110 return 0;
1111
1112 return sel->current->scratch_bytes_per_wave;
1113 }
1114
1115 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1116 {
1117 unsigned bytes = 0;
1118
1119 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->ps_shader));
1120 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->gs_shader));
1121 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->vs_shader));
1122 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->tcs_shader));
1123 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->tes_shader));
1124 return bytes;
1125 }
1126
1127 static void si_update_spi_tmpring_size(struct si_context *sctx)
1128 {
1129 unsigned current_scratch_buffer_size =
1130 si_get_current_scratch_buffer_size(sctx);
1131 unsigned scratch_bytes_per_wave =
1132 si_get_max_scratch_bytes_per_wave(sctx);
1133 unsigned scratch_needed_size = scratch_bytes_per_wave *
1134 sctx->scratch_waves;
1135
1136 if (scratch_needed_size > 0) {
1137
1138 if (scratch_needed_size > current_scratch_buffer_size) {
1139 /* Create a bigger scratch buffer */
1140 pipe_resource_reference(
1141 (struct pipe_resource**)&sctx->scratch_buffer,
1142 NULL);
1143
1144 sctx->scratch_buffer =
1145 si_resource_create_custom(&sctx->screen->b.b,
1146 PIPE_USAGE_DEFAULT, scratch_needed_size);
1147 }
1148
1149 /* Update the shaders, so they are using the latest scratch. The
1150 * scratch buffer may have been changed since these shaders were
1151 * last used, so we still need to try to update them, even if
1152 * they require scratch buffers smaller than the current size.
1153 */
1154 if (si_update_scratch_buffer(sctx, sctx->ps_shader))
1155 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
1156 if (si_update_scratch_buffer(sctx, sctx->gs_shader))
1157 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
1158 if (si_update_scratch_buffer(sctx, sctx->tcs_shader))
1159 si_pm4_bind_state(sctx, hs, sctx->tcs_shader->current->pm4);
1160
1161 /* VS can be bound as LS, ES, or VS. */
1162 if (sctx->tes_shader) {
1163 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
1164 si_pm4_bind_state(sctx, ls, sctx->vs_shader->current->pm4);
1165 } else if (sctx->gs_shader) {
1166 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
1167 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
1168 } else {
1169 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
1170 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
1171 }
1172
1173 /* TES can be bound as ES or VS. */
1174 if (sctx->gs_shader) {
1175 if (si_update_scratch_buffer(sctx, sctx->tes_shader))
1176 si_pm4_bind_state(sctx, es, sctx->tes_shader->current->pm4);
1177 } else {
1178 if (si_update_scratch_buffer(sctx, sctx->tes_shader))
1179 si_pm4_bind_state(sctx, vs, sctx->tes_shader->current->pm4);
1180 }
1181 }
1182
1183 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1184 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1185 "scratch size should already be aligned correctly.");
1186
1187 sctx->spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1188 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1189 }
1190
1191 static void si_init_tess_factor_ring(struct si_context *sctx)
1192 {
1193 assert(!sctx->tf_state);
1194 sctx->tf_state = CALLOC_STRUCT(si_pm4_state);
1195
1196 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1197 PIPE_USAGE_DEFAULT,
1198 32768 * sctx->screen->b.info.max_se);
1199 sctx->b.clear_buffer(&sctx->b.b, sctx->tf_ring, 0,
1200 sctx->tf_ring->width0, fui(0), false);
1201 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1202
1203 if (sctx->b.chip_class >= CIK) {
1204 si_pm4_set_reg(sctx->tf_state, R_030938_VGT_TF_RING_SIZE,
1205 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1206 si_pm4_set_reg(sctx->tf_state, R_030940_VGT_TF_MEMORY_BASE,
1207 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1208 } else {
1209 si_pm4_set_reg(sctx->tf_state, R_008988_VGT_TF_RING_SIZE,
1210 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1211 si_pm4_set_reg(sctx->tf_state, R_0089B8_VGT_TF_MEMORY_BASE,
1212 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1213 }
1214 si_pm4_add_bo(sctx->tf_state, r600_resource(sctx->tf_ring),
1215 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
1216 si_pm4_bind_state(sctx, tf_ring, sctx->tf_state);
1217
1218 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
1219 SI_RING_TESS_FACTOR, sctx->tf_ring, 0,
1220 sctx->tf_ring->width0, false, false, 0, 0, 0);
1221
1222 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
1223 }
1224
1225 /**
1226 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1227 * VS passes its outputs to TES directly, so the fixed-function shader only
1228 * has to write TESSOUTER and TESSINNER.
1229 */
1230 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1231 {
1232 struct ureg_src const0, const1;
1233 struct ureg_dst tessouter, tessinner;
1234 struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
1235
1236 if (!ureg)
1237 return; /* if we get here, we're screwed */
1238
1239 assert(!sctx->fixed_func_tcs_shader);
1240
1241 ureg_DECL_constant2D(ureg, 0, 1, SI_DRIVER_STATE_CONST_BUF);
1242 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1243 SI_DRIVER_STATE_CONST_BUF);
1244 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1245 SI_DRIVER_STATE_CONST_BUF);
1246
1247 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1248 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1249
1250 ureg_MOV(ureg, tessouter, const0);
1251 ureg_MOV(ureg, tessinner, const1);
1252 ureg_END(ureg);
1253
1254 sctx->fixed_func_tcs_shader =
1255 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1256 assert(sctx->fixed_func_tcs_shader);
1257 }
1258
1259 static void si_update_vgt_shader_config(struct si_context *sctx)
1260 {
1261 /* Calculate the index of the config.
1262 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1263 unsigned index = 2*!!sctx->tes_shader + !!sctx->gs_shader;
1264 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1265
1266 if (!*pm4) {
1267 uint32_t stages = 0;
1268
1269 *pm4 = CALLOC_STRUCT(si_pm4_state);
1270
1271 if (sctx->tes_shader) {
1272 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1273 S_028B54_HS_EN(1);
1274
1275 if (sctx->gs_shader)
1276 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1277 S_028B54_GS_EN(1) |
1278 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1279 else
1280 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1281 } else if (sctx->gs_shader) {
1282 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1283 S_028B54_GS_EN(1) |
1284 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1285 }
1286
1287 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1288 if (!sctx->gs_shader)
1289 si_pm4_set_reg(*pm4, R_028A40_VGT_GS_MODE, 0);
1290 }
1291 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1292 }
1293
1294 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
1295 {
1296 struct pipe_stream_output_info *so = &shader->so;
1297 uint32_t enabled_stream_buffers_mask = 0;
1298 int i;
1299
1300 for (i = 0; i < so->num_outputs; i++)
1301 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
1302 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
1303 sctx->b.streamout.stride_in_dw = shader->so.stride;
1304 }
1305
1306 void si_update_shaders(struct si_context *sctx)
1307 {
1308 struct pipe_context *ctx = (struct pipe_context*)sctx;
1309 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1310
1311 /* Update stages before GS. */
1312 if (sctx->tes_shader) {
1313 if (!sctx->tf_state)
1314 si_init_tess_factor_ring(sctx);
1315
1316 /* VS as LS */
1317 si_shader_select(ctx, sctx->vs_shader);
1318 si_pm4_bind_state(sctx, ls, sctx->vs_shader->current->pm4);
1319
1320 if (sctx->tcs_shader) {
1321 si_shader_select(ctx, sctx->tcs_shader);
1322 si_pm4_bind_state(sctx, hs, sctx->tcs_shader->current->pm4);
1323 } else {
1324 if (!sctx->fixed_func_tcs_shader)
1325 si_generate_fixed_func_tcs(sctx);
1326 si_shader_select(ctx, sctx->fixed_func_tcs_shader);
1327 si_pm4_bind_state(sctx, hs,
1328 sctx->fixed_func_tcs_shader->current->pm4);
1329 }
1330
1331 si_shader_select(ctx, sctx->tes_shader);
1332 if (sctx->gs_shader) {
1333 /* TES as ES */
1334 si_pm4_bind_state(sctx, es, sctx->tes_shader->current->pm4);
1335 } else {
1336 /* TES as VS */
1337 si_pm4_bind_state(sctx, vs, sctx->tes_shader->current->pm4);
1338 si_update_so(sctx, sctx->tes_shader);
1339 }
1340 } else if (sctx->gs_shader) {
1341 /* VS as ES */
1342 si_shader_select(ctx, sctx->vs_shader);
1343 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
1344 } else {
1345 /* VS as VS */
1346 si_shader_select(ctx, sctx->vs_shader);
1347 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
1348 si_update_so(sctx, sctx->vs_shader);
1349 }
1350
1351 /* Update GS. */
1352 if (sctx->gs_shader) {
1353 si_shader_select(ctx, sctx->gs_shader);
1354 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
1355 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
1356 si_update_so(sctx, sctx->gs_shader);
1357
1358 if (!sctx->gs_rings)
1359 si_init_gs_rings(sctx);
1360
1361 if (sctx->emitted.named.gs_rings != sctx->gs_rings)
1362 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
1363 si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
1364
1365 si_update_gs_rings(sctx);
1366 } else {
1367 si_pm4_bind_state(sctx, gs_rings, NULL);
1368 si_pm4_bind_state(sctx, gs, NULL);
1369 si_pm4_bind_state(sctx, es, NULL);
1370 }
1371
1372 si_update_vgt_shader_config(sctx);
1373
1374 si_shader_select(ctx, sctx->ps_shader);
1375
1376 if (!sctx->ps_shader->current) {
1377 struct si_shader_selector *sel;
1378
1379 /* use a dummy shader if compiling the shader (variant) failed */
1380 si_make_dummy_ps(sctx);
1381 sel = sctx->dummy_pixel_shader;
1382 si_shader_select(ctx, sel);
1383 sctx->ps_shader->current = sel->current;
1384 }
1385
1386 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
1387
1388 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1389 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
1390 sctx->flatshade != rs->flatshade) {
1391 sctx->sprite_coord_enable = rs->sprite_coord_enable;
1392 sctx->flatshade = rs->flatshade;
1393 si_update_spi_map(sctx);
1394 }
1395
1396 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1397 si_pm4_state_changed(sctx, gs)) {
1398 si_update_spi_tmpring_size(sctx);
1399 }
1400
1401 if (sctx->ps_db_shader_control != sctx->ps_shader->current->db_shader_control) {
1402 sctx->ps_db_shader_control = sctx->ps_shader->current->db_shader_control;
1403 sctx->db_render_state.dirty = true;
1404 }
1405
1406 if (sctx->smoothing_enabled != sctx->ps_shader->current->key.ps.poly_line_smoothing) {
1407 sctx->smoothing_enabled = sctx->ps_shader->current->key.ps.poly_line_smoothing;
1408 sctx->msaa_config.dirty = true;
1409
1410 if (sctx->b.chip_class == SI)
1411 sctx->db_render_state.dirty = true;
1412 }
1413 }
1414
1415 void si_init_shader_functions(struct si_context *sctx)
1416 {
1417 sctx->b.b.create_vs_state = si_create_vs_state;
1418 sctx->b.b.create_tcs_state = si_create_tcs_state;
1419 sctx->b.b.create_tes_state = si_create_tes_state;
1420 sctx->b.b.create_gs_state = si_create_gs_state;
1421 sctx->b.b.create_fs_state = si_create_fs_state;
1422
1423 sctx->b.b.bind_vs_state = si_bind_vs_shader;
1424 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
1425 sctx->b.b.bind_tes_state = si_bind_tes_shader;
1426 sctx->b.b.bind_gs_state = si_bind_gs_shader;
1427 sctx->b.b.bind_fs_state = si_bind_ps_shader;
1428
1429 sctx->b.b.delete_vs_state = si_delete_vs_shader;
1430 sctx->b.b.delete_tcs_state = si_delete_tcs_shader;
1431 sctx->b.b.delete_tes_state = si_delete_tes_shader;
1432 sctx->b.b.delete_gs_state = si_delete_gs_shader;
1433 sctx->b.b.delete_fs_state = si_delete_ps_shader;
1434 }