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radeonsi: use a switch statement in si_delete_shader_selector
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "util/u_memory.h"
34 #include "util/u_simple_shaders.h"
35
36 static void si_shader_es(struct si_shader *shader)
37 {
38 struct si_pm4_state *pm4;
39 unsigned num_sgprs, num_user_sgprs;
40 unsigned vgpr_comp_cnt;
41 uint64_t va;
42
43 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
44
45 if (pm4 == NULL)
46 return;
47
48 va = shader->bo->gpu_address;
49 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
50
51 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
52
53 num_user_sgprs = SI_VS_NUM_USER_SGPR;
54 num_sgprs = shader->num_sgprs;
55 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
56 if ((num_user_sgprs + 1) > num_sgprs) {
57 /* Last 2 reserved SGPRs are used for VCC */
58 num_sgprs = num_user_sgprs + 1 + 2;
59 }
60 assert(num_sgprs <= 104);
61
62 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
63 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
64 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
65 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
66 S_00B328_SGPRS((num_sgprs - 1) / 8) |
67 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
68 S_00B328_DX10_CLAMP(shader->dx10_clamp_mode));
69 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
70 S_00B32C_USER_SGPR(num_user_sgprs) |
71 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
72 }
73
74 static void si_shader_gs(struct si_shader *shader)
75 {
76 unsigned gs_vert_itemsize = shader->selector->info.num_outputs * (16 >> 2);
77 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
78 unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
79 unsigned cut_mode;
80 struct si_pm4_state *pm4;
81 unsigned num_sgprs, num_user_sgprs;
82 uint64_t va;
83
84 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
85 assert(gsvs_itemsize < (1 << 15));
86
87 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
88
89 if (pm4 == NULL)
90 return;
91
92 if (gs_max_vert_out <= 128) {
93 cut_mode = V_028A40_GS_CUT_128;
94 } else if (gs_max_vert_out <= 256) {
95 cut_mode = V_028A40_GS_CUT_256;
96 } else if (gs_max_vert_out <= 512) {
97 cut_mode = V_028A40_GS_CUT_512;
98 } else {
99 assert(gs_max_vert_out <= 1024);
100 cut_mode = V_028A40_GS_CUT_1024;
101 }
102
103 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
104 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
105 S_028A40_CUT_MODE(cut_mode)|
106 S_028A40_ES_WRITE_OPTIMIZE(1) |
107 S_028A40_GS_WRITE_OPTIMIZE(1));
108
109 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
110 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize);
111 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize);
112
113 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
114 util_bitcount64(shader->selector->gs_used_inputs) * (16 >> 2));
115 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
116
117 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
118
119 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
120
121 va = shader->bo->gpu_address;
122 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
123 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
124 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
125
126 num_user_sgprs = SI_GS_NUM_USER_SGPR;
127 num_sgprs = shader->num_sgprs;
128 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
129 if ((num_user_sgprs + 2) > num_sgprs) {
130 /* Last 2 reserved SGPRs are used for VCC */
131 num_sgprs = num_user_sgprs + 2 + 2;
132 }
133 assert(num_sgprs <= 104);
134
135 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
136 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
137 S_00B228_SGPRS((num_sgprs - 1) / 8) |
138 S_00B228_DX10_CLAMP(shader->dx10_clamp_mode));
139 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
140 S_00B22C_USER_SGPR(num_user_sgprs) |
141 S_00B22C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
142 }
143
144 static void si_shader_vs(struct si_shader *shader)
145 {
146 struct tgsi_shader_info *info = &shader->selector->info;
147 struct si_pm4_state *pm4;
148 unsigned num_sgprs, num_user_sgprs;
149 unsigned nparams, i, vgpr_comp_cnt;
150 uint64_t va;
151 unsigned window_space =
152 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
153
154 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
155
156 if (pm4 == NULL)
157 return;
158
159 va = shader->bo->gpu_address;
160 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
161
162 if (shader->is_gs_copy_shader) {
163 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
164 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
165 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
166 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
167 num_user_sgprs = SI_VS_NUM_USER_SGPR;
168 } else
169 assert(0);
170
171 num_sgprs = shader->num_sgprs;
172 if (num_user_sgprs > num_sgprs) {
173 /* Last 2 reserved SGPRs are used for VCC */
174 num_sgprs = num_user_sgprs + 2;
175 }
176 assert(num_sgprs <= 104);
177
178 /* Certain attributes (position, psize, etc.) don't count as params.
179 * VS is required to export at least one param and r600_shader_from_tgsi()
180 * takes care of adding a dummy export.
181 */
182 for (nparams = 0, i = 0 ; i < info->num_outputs; i++) {
183 switch (info->output_semantic_name[i]) {
184 case TGSI_SEMANTIC_CLIPVERTEX:
185 case TGSI_SEMANTIC_CLIPDIST:
186 case TGSI_SEMANTIC_CULLDIST:
187 case TGSI_SEMANTIC_POSITION:
188 case TGSI_SEMANTIC_PSIZE:
189 case TGSI_SEMANTIC_EDGEFLAG:
190 case TGSI_SEMANTIC_VIEWPORT_INDEX:
191 case TGSI_SEMANTIC_LAYER:
192 break;
193 default:
194 nparams++;
195 }
196 }
197 if (nparams < 1)
198 nparams = 1;
199
200 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
201 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
202
203 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
204 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
205 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
206 V_02870C_SPI_SHADER_4COMP :
207 V_02870C_SPI_SHADER_NONE) |
208 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
209 V_02870C_SPI_SHADER_4COMP :
210 V_02870C_SPI_SHADER_NONE) |
211 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
212 V_02870C_SPI_SHADER_4COMP :
213 V_02870C_SPI_SHADER_NONE));
214
215 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
216 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
217 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
218 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
219 S_00B128_SGPRS((num_sgprs - 1) / 8) |
220 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
221 S_00B128_DX10_CLAMP(shader->dx10_clamp_mode));
222 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
223 S_00B12C_USER_SGPR(num_user_sgprs) |
224 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
225 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
226 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
227 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
228 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
229 S_00B12C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
230 if (window_space)
231 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
232 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
233 else
234 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
235 S_028818_VTX_W0_FMT(1) |
236 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
237 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
238 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
239 }
240
241 static void si_shader_ps(struct si_shader *shader)
242 {
243 struct tgsi_shader_info *info = &shader->selector->info;
244 struct si_pm4_state *pm4;
245 unsigned i, spi_ps_in_control;
246 unsigned num_sgprs, num_user_sgprs;
247 unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
248 uint64_t va;
249
250 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
251
252 if (pm4 == NULL)
253 return;
254
255 for (i = 0; i < info->num_inputs; i++) {
256 switch (info->input_semantic_name[i]) {
257 case TGSI_SEMANTIC_POSITION:
258 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
259 * Possible vaules:
260 * 0 -> Position = pixel center (default)
261 * 1 -> Position = pixel centroid
262 * 2 -> Position = at sample position
263 */
264 switch (info->input_interpolate_loc[i]) {
265 case TGSI_INTERPOLATE_LOC_CENTROID:
266 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
267 break;
268 case TGSI_INTERPOLATE_LOC_SAMPLE:
269 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
270 break;
271 }
272
273 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
274 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
275 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
276 break;
277 }
278 }
279
280 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
281 S_0286D8_BC_OPTIMIZE_DISABLE(1);
282
283 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
284 spi_ps_input_ena = shader->spi_ps_input_ena;
285 /* we need to enable at least one of them, otherwise we hang the GPU */
286 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
287 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
288 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
289 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
290 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
291 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
292 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
293 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
294
295 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
296 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
297 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
298
299 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
300 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
301 shader->spi_shader_col_format);
302 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
303
304 va = shader->bo->gpu_address;
305 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
306 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
307 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
308
309 num_user_sgprs = SI_PS_NUM_USER_SGPR;
310 num_sgprs = shader->num_sgprs;
311 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
312 if ((num_user_sgprs + 1) > num_sgprs) {
313 /* Last 2 reserved SGPRs are used for VCC */
314 num_sgprs = num_user_sgprs + 1 + 2;
315 }
316 assert(num_sgprs <= 104);
317
318 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
319 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
320 S_00B028_SGPRS((num_sgprs - 1) / 8) |
321 S_00B028_DX10_CLAMP(shader->dx10_clamp_mode));
322 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
323 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
324 S_00B02C_USER_SGPR(num_user_sgprs) |
325 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
326 }
327
328 static void si_shader_init_pm4_state(struct si_shader *shader)
329 {
330
331 if (shader->pm4)
332 si_pm4_free_state_simple(shader->pm4);
333
334 switch (shader->selector->type) {
335 case PIPE_SHADER_VERTEX:
336 if (shader->key.vs.as_es)
337 si_shader_es(shader);
338 else
339 si_shader_vs(shader);
340 break;
341 case PIPE_SHADER_GEOMETRY:
342 si_shader_gs(shader);
343 si_shader_vs(shader->gs_copy_shader);
344 break;
345 case PIPE_SHADER_FRAGMENT:
346 si_shader_ps(shader);
347 break;
348 default:
349 assert(0);
350 }
351 }
352
353 /* Compute the key for the hw shader variant */
354 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
355 struct si_shader_selector *sel,
356 union si_shader_key *key)
357 {
358 struct si_context *sctx = (struct si_context *)ctx;
359 unsigned i;
360
361 memset(key, 0, sizeof(*key));
362
363 switch (sel->type) {
364 case PIPE_SHADER_VERTEX:
365 if (sctx->vertex_elements)
366 for (i = 0; i < sctx->vertex_elements->count; ++i)
367 key->vs.instance_divisors[i] =
368 sctx->vertex_elements->elements[i].instance_divisor;
369
370 if (sctx->gs_shader) {
371 key->vs.as_es = 1;
372 key->vs.gs_used_inputs = sctx->gs_shader->gs_used_inputs;
373 }
374 break;
375 case PIPE_SHADER_GEOMETRY:
376 break;
377 case PIPE_SHADER_FRAGMENT: {
378 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
379
380 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
381 key->ps.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
382 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
383
384 if (rs) {
385 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
386 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
387 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
388 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
389
390 key->ps.color_two_side = rs->two_side;
391
392 if (sctx->queued.named.blend) {
393 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
394 rs->multisample_enable &&
395 !sctx->framebuffer.cb0_is_integer;
396 }
397
398 key->ps.poly_stipple = rs->poly_stipple_enable && is_poly;
399 key->ps.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
400 (is_line && rs->line_smooth)) &&
401 sctx->framebuffer.nr_samples <= 1;
402 }
403
404 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
405 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
406 if (sctx->queued.named.dsa &&
407 !sctx->framebuffer.cb0_is_integer)
408 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
409 break;
410 }
411 default:
412 assert(0);
413 }
414 }
415
416 /* Select the hw shader variant depending on the current state. */
417 static int si_shader_select(struct pipe_context *ctx,
418 struct si_shader_selector *sel)
419 {
420 struct si_context *sctx = (struct si_context *)ctx;
421 union si_shader_key key;
422 struct si_shader * shader = NULL;
423 int r;
424
425 si_shader_selector_key(ctx, sel, &key);
426
427 /* Check if we don't need to change anything.
428 * This path is also used for most shaders that don't need multiple
429 * variants, it will cost just a computation of the key and this
430 * test. */
431 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
432 return 0;
433 }
434
435 /* lookup if we have other variants in the list */
436 if (sel->num_shaders > 1) {
437 struct si_shader *p = sel->current, *c = p->next_variant;
438
439 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
440 p = c;
441 c = c->next_variant;
442 }
443
444 if (c) {
445 p->next_variant = c->next_variant;
446 shader = c;
447 }
448 }
449
450 if (shader) {
451 shader->next_variant = sel->current;
452 sel->current = shader;
453 } else {
454 shader = CALLOC(1, sizeof(struct si_shader));
455 shader->selector = sel;
456 shader->key = key;
457
458 shader->next_variant = sel->current;
459 sel->current = shader;
460 r = si_shader_create((struct si_screen*)ctx->screen, sctx->tm,
461 shader);
462 if (unlikely(r)) {
463 R600_ERR("Failed to build shader variant (type=%u) %d\n",
464 sel->type, r);
465 sel->current = NULL;
466 FREE(shader);
467 return r;
468 }
469 si_shader_init_pm4_state(shader);
470 sel->num_shaders++;
471 }
472
473 return 0;
474 }
475
476 static void *si_create_shader_state(struct pipe_context *ctx,
477 const struct pipe_shader_state *state,
478 unsigned pipe_shader_type)
479 {
480 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
481 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
482 int i;
483
484 sel->type = pipe_shader_type;
485 sel->tokens = tgsi_dup_tokens(state->tokens);
486 sel->so = state->stream_output;
487 tgsi_scan_shader(state->tokens, &sel->info);
488
489 switch (pipe_shader_type) {
490 case PIPE_SHADER_GEOMETRY:
491 sel->gs_output_prim =
492 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
493 sel->gs_max_out_vertices =
494 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
495
496 for (i = 0; i < sel->info.num_inputs; i++) {
497 unsigned name = sel->info.input_semantic_name[i];
498 unsigned index = sel->info.input_semantic_index[i];
499
500 switch (name) {
501 case TGSI_SEMANTIC_PRIMID:
502 break;
503 default:
504 sel->gs_used_inputs |=
505 1llu << si_shader_io_get_unique_index(name, index);
506 }
507 }
508 }
509
510 if (sscreen->b.debug_flags & DBG_PRECOMPILE)
511 si_shader_select(ctx, sel);
512
513 return sel;
514 }
515
516 static void *si_create_fs_state(struct pipe_context *ctx,
517 const struct pipe_shader_state *state)
518 {
519 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
520 }
521
522 static void *si_create_gs_state(struct pipe_context *ctx,
523 const struct pipe_shader_state *state)
524 {
525 return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
526 }
527
528 static void *si_create_vs_state(struct pipe_context *ctx,
529 const struct pipe_shader_state *state)
530 {
531 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
532 }
533
534 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
535 {
536 struct si_context *sctx = (struct si_context *)ctx;
537 struct si_shader_selector *sel = state;
538
539 if (sctx->vs_shader == sel || !sel)
540 return;
541
542 sctx->vs_shader = sel;
543 sctx->clip_regs.dirty = true;
544 }
545
546 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
547 {
548 struct si_context *sctx = (struct si_context *)ctx;
549 struct si_shader_selector *sel = state;
550
551 if (sctx->gs_shader == sel)
552 return;
553
554 sctx->gs_shader = sel;
555 sctx->clip_regs.dirty = true;
556 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
557 }
558
559 static void si_make_dummy_ps(struct si_context *sctx)
560 {
561 if (!sctx->dummy_pixel_shader) {
562 sctx->dummy_pixel_shader =
563 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
564 TGSI_SEMANTIC_GENERIC,
565 TGSI_INTERPOLATE_CONSTANT);
566 }
567 }
568
569 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
570 {
571 struct si_context *sctx = (struct si_context *)ctx;
572 struct si_shader_selector *sel = state;
573
574 /* skip if supplied shader is one already in use */
575 if (sctx->ps_shader == sel)
576 return;
577
578 /* use a dummy shader if binding a NULL shader */
579 if (!sel) {
580 si_make_dummy_ps(sctx);
581 sel = sctx->dummy_pixel_shader;
582 }
583
584 sctx->ps_shader = sel;
585 }
586
587 static void si_delete_shader_selector(struct pipe_context *ctx,
588 struct si_shader_selector *sel)
589 {
590 struct si_context *sctx = (struct si_context *)ctx;
591 struct si_shader *p = sel->current, *c;
592
593 while (p) {
594 c = p->next_variant;
595 switch (sel->type) {
596 case PIPE_SHADER_VERTEX:
597 if (p->key.vs.as_es)
598 si_pm4_delete_state(sctx, es, p->pm4);
599 else
600 si_pm4_delete_state(sctx, vs, p->pm4);
601 break;
602 case PIPE_SHADER_GEOMETRY:
603 si_pm4_delete_state(sctx, gs, p->pm4);
604 si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
605 break;
606 case PIPE_SHADER_FRAGMENT:
607 si_pm4_delete_state(sctx, ps, p->pm4);
608 break;
609 }
610
611 si_shader_destroy(ctx, p);
612 free(p);
613 p = c;
614 }
615
616 free(sel->tokens);
617 free(sel);
618 }
619
620 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
621 {
622 struct si_context *sctx = (struct si_context *)ctx;
623 struct si_shader_selector *sel = (struct si_shader_selector *)state;
624
625 if (sctx->vs_shader == sel) {
626 sctx->vs_shader = NULL;
627 }
628
629 si_delete_shader_selector(ctx, sel);
630 }
631
632 static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
633 {
634 struct si_context *sctx = (struct si_context *)ctx;
635 struct si_shader_selector *sel = (struct si_shader_selector *)state;
636
637 if (sctx->gs_shader == sel) {
638 sctx->gs_shader = NULL;
639 }
640
641 si_delete_shader_selector(ctx, sel);
642 }
643
644 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
645 {
646 struct si_context *sctx = (struct si_context *)ctx;
647 struct si_shader_selector *sel = (struct si_shader_selector *)state;
648
649 if (sctx->ps_shader == sel) {
650 sctx->ps_shader = NULL;
651 }
652
653 si_delete_shader_selector(ctx, sel);
654 }
655
656 static void si_update_spi_map(struct si_context *sctx)
657 {
658 struct si_shader *ps = sctx->ps_shader->current;
659 struct si_shader *vs = si_get_vs_state(sctx);
660 struct tgsi_shader_info *psinfo = &ps->selector->info;
661 struct tgsi_shader_info *vsinfo = &vs->selector->info;
662 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
663 unsigned i, j, tmp;
664
665 for (i = 0; i < psinfo->num_inputs; i++) {
666 unsigned name = psinfo->input_semantic_name[i];
667 unsigned index = psinfo->input_semantic_index[i];
668 unsigned interpolate = psinfo->input_interpolate[i];
669 unsigned param_offset = ps->ps_input_param_offset[i];
670
671 if (name == TGSI_SEMANTIC_POSITION ||
672 name == TGSI_SEMANTIC_FACE)
673 /* Read from preloaded VGPRs, not parameters */
674 continue;
675
676 bcolor:
677 tmp = 0;
678
679 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
680 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
681 tmp |= S_028644_FLAT_SHADE(1);
682
683 if (name == TGSI_SEMANTIC_PCOORD ||
684 (name == TGSI_SEMANTIC_TEXCOORD &&
685 sctx->sprite_coord_enable & (1 << index))) {
686 tmp |= S_028644_PT_SPRITE_TEX(1);
687 }
688
689 for (j = 0; j < vsinfo->num_outputs; j++) {
690 if (name == vsinfo->output_semantic_name[j] &&
691 index == vsinfo->output_semantic_index[j]) {
692 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
693 break;
694 }
695 }
696
697 if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(tmp)) {
698 /* No corresponding output found, load defaults into input.
699 * Don't set any other bits.
700 * (FLAT_SHADE=1 completely changes behavior) */
701 tmp = S_028644_OFFSET(0x20);
702 }
703
704 si_pm4_set_reg(pm4,
705 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
706 tmp);
707
708 if (name == TGSI_SEMANTIC_COLOR &&
709 ps->key.ps.color_two_side) {
710 name = TGSI_SEMANTIC_BCOLOR;
711 param_offset++;
712 goto bcolor;
713 }
714 }
715
716 si_pm4_set_state(sctx, spi, pm4);
717 }
718
719 /* Initialize state related to ESGS / GSVS ring buffers */
720 static void si_init_gs_rings(struct si_context *sctx)
721 {
722 unsigned esgs_ring_size = 128 * 1024;
723 unsigned gsvs_ring_size = 64 * 1024 * 1024;
724
725 assert(!sctx->gs_rings);
726 sctx->gs_rings = CALLOC_STRUCT(si_pm4_state);
727
728 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
729 PIPE_USAGE_DEFAULT, esgs_ring_size);
730
731 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
732 PIPE_USAGE_DEFAULT, gsvs_ring_size);
733
734 if (sctx->b.chip_class >= CIK) {
735 si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
736 esgs_ring_size / 256);
737 si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
738 gsvs_ring_size / 256);
739 } else {
740 si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
741 esgs_ring_size / 256);
742 si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
743 gsvs_ring_size / 256);
744 }
745
746 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
747 sctx->esgs_ring, 0, esgs_ring_size,
748 true, true, 4, 64);
749 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
750 sctx->esgs_ring, 0, esgs_ring_size,
751 false, false, 0, 0);
752 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
753 sctx->gsvs_ring, 0, gsvs_ring_size,
754 false, false, 0, 0);
755 }
756
757 /**
758 * @returns 1 if \p sel has been updated to use a new scratch buffer and 0
759 * otherwise.
760 */
761 static unsigned si_update_scratch_buffer(struct si_context *sctx,
762 struct si_shader_selector *sel)
763 {
764 struct si_shader *shader;
765 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
766 unsigned char *ptr;
767
768 if (!sel)
769 return 0;
770
771 shader = sel->current;
772
773 /* This shader doesn't need a scratch buffer */
774 if (shader->scratch_bytes_per_wave == 0)
775 return 0;
776
777 /* This shader is already configured to use the current
778 * scratch buffer. */
779 if (shader->scratch_bo == sctx->scratch_buffer)
780 return 0;
781
782 assert(sctx->scratch_buffer);
783
784 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
785
786 /* Replace the shader bo with a new bo that has the relocs applied. */
787 r600_resource_reference(&shader->bo, NULL);
788 shader->bo = si_resource_create_custom(&sctx->screen->b.b, PIPE_USAGE_IMMUTABLE,
789 shader->binary.code_size);
790 ptr = sctx->screen->b.ws->buffer_map(shader->bo->cs_buf, NULL, PIPE_TRANSFER_WRITE);
791 util_memcpy_cpu_to_le32(ptr, shader->binary.code, shader->binary.code_size);
792 sctx->screen->b.ws->buffer_unmap(shader->bo->cs_buf);
793
794 /* Update the shader state to use the new shader bo. */
795 si_shader_init_pm4_state(shader);
796
797 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
798
799 return 1;
800 }
801
802 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
803 {
804 if (!sctx->scratch_buffer)
805 return 0;
806
807 return sctx->scratch_buffer->b.b.width0;
808 }
809
810 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_context *sctx,
811 struct si_shader_selector *sel)
812 {
813 if (!sel)
814 return 0;
815
816 return sel->current->scratch_bytes_per_wave;
817 }
818
819 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
820 {
821
822 return MAX3(si_get_scratch_buffer_bytes_per_wave(sctx, sctx->ps_shader),
823 si_get_scratch_buffer_bytes_per_wave(sctx, sctx->gs_shader),
824 si_get_scratch_buffer_bytes_per_wave(sctx, sctx->vs_shader));
825 }
826
827 static void si_update_spi_tmpring_size(struct si_context *sctx)
828 {
829 unsigned current_scratch_buffer_size =
830 si_get_current_scratch_buffer_size(sctx);
831 unsigned scratch_bytes_per_wave =
832 si_get_max_scratch_bytes_per_wave(sctx);
833 unsigned scratch_needed_size = scratch_bytes_per_wave *
834 sctx->scratch_waves;
835
836 if (scratch_needed_size > 0) {
837
838 if (scratch_needed_size > current_scratch_buffer_size) {
839 /* Create a bigger scratch buffer */
840 pipe_resource_reference(
841 (struct pipe_resource**)&sctx->scratch_buffer,
842 NULL);
843
844 sctx->scratch_buffer =
845 si_resource_create_custom(&sctx->screen->b.b,
846 PIPE_USAGE_DEFAULT, scratch_needed_size);
847 }
848
849 /* Update the shaders, so they are using the latest scratch. The
850 * scratch buffer may have been changed since these shaders were
851 * last used, so we still need to try to update them, even if
852 * they require scratch buffers smaller than the current size.
853 */
854 if (si_update_scratch_buffer(sctx, sctx->ps_shader))
855 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
856 if (si_update_scratch_buffer(sctx, sctx->gs_shader))
857 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
858
859 /* VS can be bound as ES or VS. */
860 if (sctx->gs_shader) {
861 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
862 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
863 } else {
864 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
865 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
866 }
867 }
868
869 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
870 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
871 "scratch size should already be aligned correctly.");
872
873 sctx->spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
874 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
875 }
876
877 void si_update_shaders(struct si_context *sctx)
878 {
879 struct pipe_context *ctx = (struct pipe_context*)sctx;
880 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
881
882 if (sctx->gs_shader) {
883 si_shader_select(ctx, sctx->gs_shader);
884 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
885 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
886
887 sctx->b.streamout.stride_in_dw = sctx->gs_shader->so.stride;
888
889 si_shader_select(ctx, sctx->vs_shader);
890 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
891
892 if (!sctx->gs_rings)
893 si_init_gs_rings(sctx);
894 if (sctx->emitted.named.gs_rings != sctx->gs_rings)
895 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
896 si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
897
898 si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
899 sctx->gsvs_ring,
900 sctx->gs_shader->gs_max_out_vertices *
901 sctx->gs_shader->info.num_outputs * 16,
902 64, true, true, 4, 16);
903
904 if (!sctx->gs_on) {
905 sctx->gs_on = CALLOC_STRUCT(si_pm4_state);
906
907 si_pm4_set_reg(sctx->gs_on, R_028B54_VGT_SHADER_STAGES_EN,
908 S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
909 S_028B54_GS_EN(1) |
910 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER));
911 }
912 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_on);
913 } else {
914 si_shader_select(ctx, sctx->vs_shader);
915 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
916
917 sctx->b.streamout.stride_in_dw = sctx->vs_shader->so.stride;
918
919 if (!sctx->gs_off) {
920 sctx->gs_off = CALLOC_STRUCT(si_pm4_state);
921
922 si_pm4_set_reg(sctx->gs_off, R_028A40_VGT_GS_MODE, 0);
923 si_pm4_set_reg(sctx->gs_off, R_028B54_VGT_SHADER_STAGES_EN, 0);
924 }
925 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_off);
926 si_pm4_bind_state(sctx, gs_rings, NULL);
927 si_pm4_bind_state(sctx, gs, NULL);
928 si_pm4_bind_state(sctx, es, NULL);
929 }
930
931 si_shader_select(ctx, sctx->ps_shader);
932
933 if (!sctx->ps_shader->current) {
934 struct si_shader_selector *sel;
935
936 /* use a dummy shader if compiling the shader (variant) failed */
937 si_make_dummy_ps(sctx);
938 sel = sctx->dummy_pixel_shader;
939 si_shader_select(ctx, sel);
940 sctx->ps_shader->current = sel->current;
941 }
942
943 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
944
945 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
946 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
947 sctx->flatshade != rs->flatshade) {
948 sctx->sprite_coord_enable = rs->sprite_coord_enable;
949 sctx->flatshade = rs->flatshade;
950 si_update_spi_map(sctx);
951 }
952
953 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
954 si_pm4_state_changed(sctx, gs)) {
955 si_update_spi_tmpring_size(sctx);
956 }
957
958 if (sctx->ps_db_shader_control != sctx->ps_shader->current->db_shader_control) {
959 sctx->ps_db_shader_control = sctx->ps_shader->current->db_shader_control;
960 sctx->db_render_state.dirty = true;
961 }
962
963 if (sctx->smoothing_enabled != sctx->ps_shader->current->key.ps.poly_line_smoothing) {
964 sctx->smoothing_enabled = sctx->ps_shader->current->key.ps.poly_line_smoothing;
965 sctx->msaa_config.dirty = true;
966
967 if (sctx->b.chip_class == SI)
968 sctx->db_render_state.dirty = true;
969 }
970 }
971
972 void si_init_shader_functions(struct si_context *sctx)
973 {
974 sctx->b.b.create_vs_state = si_create_vs_state;
975 sctx->b.b.create_gs_state = si_create_gs_state;
976 sctx->b.b.create_fs_state = si_create_fs_state;
977
978 sctx->b.b.bind_vs_state = si_bind_vs_shader;
979 sctx->b.b.bind_gs_state = si_bind_gs_shader;
980 sctx->b.b.bind_fs_state = si_bind_ps_shader;
981
982 sctx->b.b.delete_vs_state = si_delete_vs_shader;
983 sctx->b.b.delete_gs_state = si_delete_gs_shader;
984 sctx->b.b.delete_fs_state = si_delete_ps_shader;
985 }