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[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "sid.h"
30 #include "gfx9d.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/crc32.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
39
40 #include "util/disk_cache.h"
41 #include "util/mesa-sha1.h"
42 #include "ac_exp_param.h"
43
44 /* SHADER_CACHE */
45
46 /**
47 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
48 * integer.
49 */
50 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
51 {
52 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
53 sizeof(struct tgsi_token);
54 unsigned size = 4 + tgsi_size + sizeof(sel->so);
55 char *result = (char*)MALLOC(size);
56
57 if (!result)
58 return NULL;
59
60 *((uint32_t*)result) = size;
61 memcpy(result + 4, sel->tokens, tgsi_size);
62 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
63 return result;
64 }
65
66 /** Copy "data" to "ptr" and return the next dword following copied data. */
67 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
68 {
69 /* data may be NULL if size == 0 */
70 if (size)
71 memcpy(ptr, data, size);
72 ptr += DIV_ROUND_UP(size, 4);
73 return ptr;
74 }
75
76 /** Read data from "ptr". Return the next dword following the data. */
77 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
78 {
79 memcpy(data, ptr, size);
80 ptr += DIV_ROUND_UP(size, 4);
81 return ptr;
82 }
83
84 /**
85 * Write the size as uint followed by the data. Return the next dword
86 * following the copied data.
87 */
88 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
89 {
90 *ptr++ = size;
91 return write_data(ptr, data, size);
92 }
93
94 /**
95 * Read the size as uint followed by the data. Return both via parameters.
96 * Return the next dword following the data.
97 */
98 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
99 {
100 *size = *ptr++;
101 assert(*data == NULL);
102 if (!*size)
103 return ptr;
104 *data = malloc(*size);
105 return read_data(ptr, *data, *size);
106 }
107
108 /**
109 * Return the shader binary in a buffer. The first 4 bytes contain its size
110 * as integer.
111 */
112 static void *si_get_shader_binary(struct si_shader *shader)
113 {
114 /* There is always a size of data followed by the data itself. */
115 unsigned relocs_size = shader->binary.reloc_count *
116 sizeof(shader->binary.relocs[0]);
117 unsigned disasm_size = shader->binary.disasm_string ?
118 strlen(shader->binary.disasm_string) + 1 : 0;
119 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
120 strlen(shader->binary.llvm_ir_string) + 1 : 0;
121 unsigned size =
122 4 + /* total size */
123 4 + /* CRC32 of the data below */
124 align(sizeof(shader->config), 4) +
125 align(sizeof(shader->info), 4) +
126 4 + align(shader->binary.code_size, 4) +
127 4 + align(shader->binary.rodata_size, 4) +
128 4 + align(relocs_size, 4) +
129 4 + align(disasm_size, 4) +
130 4 + align(llvm_ir_size, 4);
131 void *buffer = CALLOC(1, size);
132 uint32_t *ptr = (uint32_t*)buffer;
133
134 if (!buffer)
135 return NULL;
136
137 *ptr++ = size;
138 ptr++; /* CRC32 is calculated at the end. */
139
140 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
141 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
142 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
143 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
144 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
145 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
146 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
147 assert((char *)ptr - (char *)buffer == size);
148
149 /* Compute CRC32. */
150 ptr = (uint32_t*)buffer;
151 ptr++;
152 *ptr = util_hash_crc32(ptr + 1, size - 8);
153
154 return buffer;
155 }
156
157 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
158 {
159 uint32_t *ptr = (uint32_t*)binary;
160 uint32_t size = *ptr++;
161 uint32_t crc32 = *ptr++;
162 unsigned chunk_size;
163
164 if (util_hash_crc32(ptr, size - 8) != crc32) {
165 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
166 return false;
167 }
168
169 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
170 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
171 ptr = read_chunk(ptr, (void**)&shader->binary.code,
172 &shader->binary.code_size);
173 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
174 &shader->binary.rodata_size);
175 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
176 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
177 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
178 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
179
180 return true;
181 }
182
183 /**
184 * Insert a shader into the cache. It's assumed the shader is not in the cache.
185 * Use si_shader_cache_load_shader before calling this.
186 *
187 * Returns false on failure, in which case the tgsi_binary should be freed.
188 */
189 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
190 void *tgsi_binary,
191 struct si_shader *shader,
192 bool insert_into_disk_cache)
193 {
194 void *hw_binary;
195 struct hash_entry *entry;
196 uint8_t key[CACHE_KEY_SIZE];
197
198 entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
199 if (entry)
200 return false; /* already added */
201
202 hw_binary = si_get_shader_binary(shader);
203 if (!hw_binary)
204 return false;
205
206 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
207 hw_binary) == NULL) {
208 FREE(hw_binary);
209 return false;
210 }
211
212 if (sscreen->b.disk_shader_cache && insert_into_disk_cache) {
213 disk_cache_compute_key(sscreen->b.disk_shader_cache, tgsi_binary,
214 *((uint32_t *)tgsi_binary), key);
215 disk_cache_put(sscreen->b.disk_shader_cache, key, hw_binary,
216 *((uint32_t *) hw_binary));
217 }
218
219 return true;
220 }
221
222 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
223 void *tgsi_binary,
224 struct si_shader *shader)
225 {
226 struct hash_entry *entry =
227 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
228 if (!entry) {
229 if (sscreen->b.disk_shader_cache) {
230 unsigned char sha1[CACHE_KEY_SIZE];
231 size_t tg_size = *((uint32_t *) tgsi_binary);
232
233 disk_cache_compute_key(sscreen->b.disk_shader_cache,
234 tgsi_binary, tg_size, sha1);
235
236 size_t binary_size;
237 uint8_t *buffer =
238 disk_cache_get(sscreen->b.disk_shader_cache,
239 sha1, &binary_size);
240 if (!buffer)
241 return false;
242
243 if (binary_size < sizeof(uint32_t) ||
244 *((uint32_t*)buffer) != binary_size) {
245 /* Something has gone wrong discard the item
246 * from the cache and rebuild/link from
247 * source.
248 */
249 assert(!"Invalid radeonsi shader disk cache "
250 "item!");
251
252 disk_cache_remove(sscreen->b.disk_shader_cache,
253 sha1);
254 free(buffer);
255
256 return false;
257 }
258
259 if (!si_load_shader_binary(shader, buffer)) {
260 free(buffer);
261 return false;
262 }
263 free(buffer);
264
265 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary,
266 shader, false))
267 FREE(tgsi_binary);
268 } else {
269 return false;
270 }
271 } else {
272 if (si_load_shader_binary(shader, entry->data))
273 FREE(tgsi_binary);
274 else
275 return false;
276 }
277 p_atomic_inc(&sscreen->b.num_shader_cache_hits);
278 return true;
279 }
280
281 static uint32_t si_shader_cache_key_hash(const void *key)
282 {
283 /* The first dword is the key size. */
284 return util_hash_crc32(key, *(uint32_t*)key);
285 }
286
287 static bool si_shader_cache_key_equals(const void *a, const void *b)
288 {
289 uint32_t *keya = (uint32_t*)a;
290 uint32_t *keyb = (uint32_t*)b;
291
292 /* The first dword is the key size. */
293 if (*keya != *keyb)
294 return false;
295
296 return memcmp(keya, keyb, *keya) == 0;
297 }
298
299 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
300 {
301 FREE((void*)entry->key);
302 FREE(entry->data);
303 }
304
305 bool si_init_shader_cache(struct si_screen *sscreen)
306 {
307 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
308 sscreen->shader_cache =
309 _mesa_hash_table_create(NULL,
310 si_shader_cache_key_hash,
311 si_shader_cache_key_equals);
312
313 return sscreen->shader_cache != NULL;
314 }
315
316 void si_destroy_shader_cache(struct si_screen *sscreen)
317 {
318 if (sscreen->shader_cache)
319 _mesa_hash_table_destroy(sscreen->shader_cache,
320 si_destroy_shader_cache_entry);
321 mtx_destroy(&sscreen->shader_cache_mutex);
322 }
323
324 /* SHADER STATES */
325
326 static void si_set_tesseval_regs(struct si_screen *sscreen,
327 struct si_shader_selector *tes,
328 struct si_pm4_state *pm4)
329 {
330 struct tgsi_shader_info *info = &tes->info;
331 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
332 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
333 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
334 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
335 unsigned type, partitioning, topology, distribution_mode;
336
337 switch (tes_prim_mode) {
338 case PIPE_PRIM_LINES:
339 type = V_028B6C_TESS_ISOLINE;
340 break;
341 case PIPE_PRIM_TRIANGLES:
342 type = V_028B6C_TESS_TRIANGLE;
343 break;
344 case PIPE_PRIM_QUADS:
345 type = V_028B6C_TESS_QUAD;
346 break;
347 default:
348 assert(0);
349 return;
350 }
351
352 switch (tes_spacing) {
353 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
354 partitioning = V_028B6C_PART_FRAC_ODD;
355 break;
356 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
357 partitioning = V_028B6C_PART_FRAC_EVEN;
358 break;
359 case PIPE_TESS_SPACING_EQUAL:
360 partitioning = V_028B6C_PART_INTEGER;
361 break;
362 default:
363 assert(0);
364 return;
365 }
366
367 if (tes_point_mode)
368 topology = V_028B6C_OUTPUT_POINT;
369 else if (tes_prim_mode == PIPE_PRIM_LINES)
370 topology = V_028B6C_OUTPUT_LINE;
371 else if (tes_vertex_order_cw)
372 /* for some reason, this must be the other way around */
373 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
374 else
375 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
376
377 if (sscreen->has_distributed_tess) {
378 if (sscreen->b.family == CHIP_FIJI ||
379 sscreen->b.family >= CHIP_POLARIS10)
380 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
381 else
382 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
383 } else
384 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
385
386 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
387 S_028B6C_TYPE(type) |
388 S_028B6C_PARTITIONING(partitioning) |
389 S_028B6C_TOPOLOGY(topology) |
390 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
391 }
392
393 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
394 * whether the "fractional odd" tessellation spacing is used.
395 *
396 * Possible VGT configurations and which state should set the register:
397 *
398 * Reg set in | VGT shader configuration | Value
399 * ------------------------------------------------------
400 * VS as VS | VS | 30
401 * VS as ES | ES -> GS -> VS | 30
402 * TES as VS | LS -> HS -> VS | 14 or 30
403 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
404 *
405 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
406 */
407 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
408 struct si_shader_selector *sel,
409 struct si_shader *shader,
410 struct si_pm4_state *pm4)
411 {
412 unsigned type = sel->type;
413
414 if (sscreen->b.family < CHIP_POLARIS10)
415 return;
416
417 /* VS as VS, or VS as ES: */
418 if ((type == PIPE_SHADER_VERTEX &&
419 (!shader ||
420 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
421 /* TES as VS, or TES as ES: */
422 type == PIPE_SHADER_TESS_EVAL) {
423 unsigned vtx_reuse_depth = 30;
424
425 if (type == PIPE_SHADER_TESS_EVAL &&
426 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
427 PIPE_TESS_SPACING_FRACTIONAL_ODD)
428 vtx_reuse_depth = 14;
429
430 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
431 vtx_reuse_depth);
432 }
433 }
434
435 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
436 {
437 if (shader->pm4)
438 si_pm4_clear_state(shader->pm4);
439 else
440 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
441
442 return shader->pm4;
443 }
444
445 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
446 {
447 struct si_pm4_state *pm4;
448 unsigned vgpr_comp_cnt;
449 uint64_t va;
450
451 assert(sscreen->b.chip_class <= VI);
452
453 pm4 = si_get_shader_pm4_state(shader);
454 if (!pm4)
455 return;
456
457 va = shader->bo->gpu_address;
458 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
459
460 /* We need at least 2 components for LS.
461 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
462 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
463 */
464 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
465
466 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
467 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
468
469 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
470 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
471 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
472 S_00B528_DX10_CLAMP(1) |
473 S_00B528_FLOAT_MODE(shader->config.float_mode);
474 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR) |
475 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
476 }
477
478 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
479 {
480 struct si_pm4_state *pm4;
481 uint64_t va;
482 unsigned ls_vgpr_comp_cnt = 0;
483
484 pm4 = si_get_shader_pm4_state(shader);
485 if (!pm4)
486 return;
487
488 va = shader->bo->gpu_address;
489 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
490
491 if (sscreen->b.chip_class >= GFX9) {
492 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
493 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, va >> 40);
494
495 /* We need at least 2 components for LS.
496 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
497 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
498 */
499 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
500
501 if (shader->config.scratch_bytes_per_wave) {
502 fprintf(stderr, "HS: scratch buffer unsupported");
503 abort();
504 }
505
506 shader->config.rsrc2 =
507 S_00B42C_USER_SGPR(GFX9_TCS_NUM_USER_SGPR) |
508 S_00B42C_USER_SGPR_MSB(GFX9_TCS_NUM_USER_SGPR >> 5) |
509 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
510 } else {
511 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
512 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
513
514 shader->config.rsrc2 =
515 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
516 S_00B42C_OC_LDS_EN(1) |
517 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
518 }
519
520 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
521 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
522 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
523 S_00B428_DX10_CLAMP(1) |
524 S_00B428_FLOAT_MODE(shader->config.float_mode) |
525 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
526
527 if (sscreen->b.chip_class <= VI) {
528 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
529 shader->config.rsrc2);
530 }
531 }
532
533 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
534 {
535 struct si_pm4_state *pm4;
536 unsigned num_user_sgprs;
537 unsigned vgpr_comp_cnt;
538 uint64_t va;
539 unsigned oc_lds_en;
540
541 assert(sscreen->b.chip_class <= VI);
542
543 pm4 = si_get_shader_pm4_state(shader);
544 if (!pm4)
545 return;
546
547 va = shader->bo->gpu_address;
548 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
549
550 if (shader->selector->type == PIPE_SHADER_VERTEX) {
551 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
552 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
553 num_user_sgprs = SI_VS_NUM_USER_SGPR;
554 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
555 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
556 num_user_sgprs = SI_TES_NUM_USER_SGPR;
557 } else
558 unreachable("invalid shader selector type");
559
560 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
561
562 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
563 shader->selector->esgs_itemsize / 4);
564 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
565 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
566 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
567 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
568 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
569 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
570 S_00B328_DX10_CLAMP(1) |
571 S_00B328_FLOAT_MODE(shader->config.float_mode));
572 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
573 S_00B32C_USER_SGPR(num_user_sgprs) |
574 S_00B32C_OC_LDS_EN(oc_lds_en) |
575 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
576
577 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
578 si_set_tesseval_regs(sscreen, shader->selector, pm4);
579
580 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
581 }
582
583 /**
584 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
585 * geometry shader.
586 */
587 static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
588 {
589 enum chip_class chip_class = sel->screen->b.chip_class;
590 unsigned gs_max_vert_out = sel->gs_max_out_vertices;
591 unsigned cut_mode;
592
593 if (gs_max_vert_out <= 128) {
594 cut_mode = V_028A40_GS_CUT_128;
595 } else if (gs_max_vert_out <= 256) {
596 cut_mode = V_028A40_GS_CUT_256;
597 } else if (gs_max_vert_out <= 512) {
598 cut_mode = V_028A40_GS_CUT_512;
599 } else {
600 assert(gs_max_vert_out <= 1024);
601 cut_mode = V_028A40_GS_CUT_1024;
602 }
603
604 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
605 S_028A40_CUT_MODE(cut_mode)|
606 S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
607 S_028A40_GS_WRITE_OPTIMIZE(1) |
608 S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
609 }
610
611 struct gfx9_gs_info {
612 unsigned es_verts_per_subgroup;
613 unsigned gs_prims_per_subgroup;
614 unsigned gs_inst_prims_in_subgroup;
615 unsigned max_prims_per_subgroup;
616 unsigned lds_size;
617 };
618
619 static void gfx9_get_gs_info(struct si_shader_selector *es,
620 struct si_shader_selector *gs,
621 struct gfx9_gs_info *out)
622 {
623 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
624 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
625 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
626 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
627
628 /* All these are in dwords: */
629 /* We can't allow using the whole LDS, because GS waves compete with
630 * other shader stages for LDS space. */
631 const unsigned max_lds_size = 8 * 1024;
632 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
633 unsigned esgs_lds_size;
634
635 /* All these are per subgroup: */
636 const unsigned max_out_prims = 32 * 1024;
637 const unsigned max_es_verts = 255;
638 const unsigned ideal_gs_prims = 64;
639 unsigned max_gs_prims, gs_prims;
640 unsigned min_es_verts, es_verts, worst_case_es_verts;
641
642 assert(gs_num_invocations <= 32); /* GL maximum */
643
644 if (uses_adjacency || gs_num_invocations > 1)
645 max_gs_prims = 127 / gs_num_invocations;
646 else
647 max_gs_prims = 255;
648
649 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
650 * Make sure we don't go over the maximum value.
651 */
652 max_gs_prims = MIN2(max_gs_prims,
653 max_out_prims /
654 (gs->gs_max_out_vertices * gs_num_invocations));
655 assert(max_gs_prims > 0);
656
657 /* If the primitive has adjacency, halve the number of vertices
658 * that will be reused in multiple primitives.
659 */
660 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
661
662 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
663 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
664
665 /* Compute ESGS LDS size based on the worst case number of ES vertices
666 * needed to create the target number of GS prims per subgroup.
667 */
668 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
669
670 /* If total LDS usage is too big, refactor partitions based on ratio
671 * of ESGS item sizes.
672 */
673 if (esgs_lds_size > max_lds_size) {
674 /* Our target GS Prims Per Subgroup was too large. Calculate
675 * the maximum number of GS Prims Per Subgroup that will fit
676 * into LDS, capped by the maximum that the hardware can support.
677 */
678 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
679 max_gs_prims);
680 assert(gs_prims > 0);
681 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
682 max_es_verts);
683
684 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
685 assert(esgs_lds_size <= max_lds_size);
686 }
687
688 /* Now calculate remaining ESGS information. */
689 if (esgs_lds_size)
690 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
691 else
692 es_verts = max_es_verts;
693
694 /* Vertices for adjacency primitives are not always reused, so restore
695 * it for ES_VERTS_PER_SUBGRP.
696 */
697 min_es_verts = gs->gs_input_verts_per_prim;
698
699 /* For normal primitives, the VGT only checks if they are past the ES
700 * verts per subgroup after allocating a full GS primitive and if they
701 * are, kick off a new subgroup. But if those additional ES verts are
702 * unique (e.g. not reused) we need to make sure there is enough LDS
703 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
704 */
705 es_verts -= min_es_verts - 1;
706
707 out->es_verts_per_subgroup = es_verts;
708 out->gs_prims_per_subgroup = gs_prims;
709 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
710 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
711 gs->gs_max_out_vertices;
712 out->lds_size = align(esgs_lds_size, 128) / 128;
713
714 assert(out->max_prims_per_subgroup <= max_out_prims);
715 }
716
717 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
718 {
719 struct si_shader_selector *sel = shader->selector;
720 const ubyte *num_components = sel->info.num_stream_output_components;
721 unsigned gs_num_invocations = sel->gs_num_invocations;
722 struct si_pm4_state *pm4;
723 uint64_t va;
724 unsigned max_stream = sel->max_gs_stream;
725 unsigned offset;
726
727 pm4 = si_get_shader_pm4_state(shader);
728 if (!pm4)
729 return;
730
731 offset = num_components[0] * sel->gs_max_out_vertices;
732 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
733 if (max_stream >= 1)
734 offset += num_components[1] * sel->gs_max_out_vertices;
735 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
736 if (max_stream >= 2)
737 offset += num_components[2] * sel->gs_max_out_vertices;
738 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
739 if (max_stream >= 3)
740 offset += num_components[3] * sel->gs_max_out_vertices;
741 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
742
743 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
744 assert(offset < (1 << 15));
745
746 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, sel->gs_max_out_vertices);
747
748 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
749 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
750 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
751 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
752
753 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
754 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
755 S_028B90_ENABLE(gs_num_invocations > 0));
756
757 va = shader->bo->gpu_address;
758 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
759
760 if (sscreen->b.chip_class >= GFX9) {
761 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
762 unsigned es_type = shader->key.part.gs.es->type;
763 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
764 struct gfx9_gs_info gs_info;
765
766 if (es_type == PIPE_SHADER_VERTEX)
767 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
768 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
769 else if (es_type == PIPE_SHADER_TESS_EVAL)
770 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
771 else
772 unreachable("invalid shader selector type");
773
774 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
775 * VGPR[0:4] are always loaded.
776 */
777 if (sel->info.uses_invocationid)
778 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
779 else if (sel->info.uses_primid)
780 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
781 else if (input_prim >= PIPE_PRIM_TRIANGLES)
782 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
783 else
784 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
785
786 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
787
788 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
789 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, va >> 40);
790
791 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
792 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
793 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
794 S_00B228_DX10_CLAMP(1) |
795 S_00B228_FLOAT_MODE(shader->config.float_mode) |
796 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
797 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
798 S_00B22C_USER_SGPR(GFX9_GS_NUM_USER_SGPR) |
799 S_00B22C_USER_SGPR_MSB(GFX9_GS_NUM_USER_SGPR >> 5) |
800 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
801 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
802 S_00B22C_LDS_SIZE(gs_info.lds_size) |
803 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
804
805 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
806 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
807 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
808 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup));
809 si_pm4_set_reg(pm4, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
810 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup));
811 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
812 shader->key.part.gs.es->esgs_itemsize / 4);
813
814 if (es_type == PIPE_SHADER_TESS_EVAL)
815 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
816
817 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
818 NULL, pm4);
819
820 if (shader->config.scratch_bytes_per_wave) {
821 fprintf(stderr, "GS: scratch buffer unsupported");
822 abort();
823 }
824 } else {
825 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
826 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
827
828 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
829 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
830 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
831 S_00B228_DX10_CLAMP(1) |
832 S_00B228_FLOAT_MODE(shader->config.float_mode));
833 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
834 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
835 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
836 }
837 }
838
839 /**
840 * Compute the state for \p shader, which will run as a vertex shader on the
841 * hardware.
842 *
843 * If \p gs is non-NULL, it points to the geometry shader for which this shader
844 * is the copy shader.
845 */
846 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
847 struct si_shader_selector *gs)
848 {
849 struct si_pm4_state *pm4;
850 unsigned num_user_sgprs;
851 unsigned nparams, vgpr_comp_cnt;
852 uint64_t va;
853 unsigned oc_lds_en;
854 unsigned window_space =
855 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
856 bool enable_prim_id = shader->key.mono.vs_export_prim_id;
857
858 pm4 = si_get_shader_pm4_state(shader);
859 if (!pm4)
860 return;
861
862 /* We always write VGT_GS_MODE in the VS state, because every switch
863 * between different shader pipelines involving a different GS or no
864 * GS at all involves a switch of the VS (different GS use different
865 * copy shaders). On the other hand, when the API switches from a GS to
866 * no GS and then back to the same GS used originally, the GS state is
867 * not sent again.
868 */
869 if (!gs) {
870 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
871 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
872 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
873 } else {
874 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
875 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
876 }
877
878 va = shader->bo->gpu_address;
879 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
880
881 if (gs) {
882 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
883 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
884 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
885 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
886 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
887 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
888 */
889 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
890 num_user_sgprs = SI_VS_NUM_USER_SGPR;
891 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
892 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
893 num_user_sgprs = SI_TES_NUM_USER_SGPR;
894 } else
895 unreachable("invalid shader selector type");
896
897 /* VS is required to export at least one param. */
898 nparams = MAX2(shader->info.nr_param_exports, 1);
899 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
900 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
901
902 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
903 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
904 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
905 V_02870C_SPI_SHADER_4COMP :
906 V_02870C_SPI_SHADER_NONE) |
907 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
908 V_02870C_SPI_SHADER_4COMP :
909 V_02870C_SPI_SHADER_NONE) |
910 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
911 V_02870C_SPI_SHADER_4COMP :
912 V_02870C_SPI_SHADER_NONE));
913
914 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
915
916 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
917 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
918 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
919 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
920 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
921 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
922 S_00B128_DX10_CLAMP(1) |
923 S_00B128_FLOAT_MODE(shader->config.float_mode));
924 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
925 S_00B12C_USER_SGPR(num_user_sgprs) |
926 S_00B12C_OC_LDS_EN(oc_lds_en) |
927 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
928 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
929 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
930 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
931 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
932 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
933 if (window_space)
934 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
935 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
936 else
937 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
938 S_028818_VTX_W0_FMT(1) |
939 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
940 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
941 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
942
943 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
944 si_set_tesseval_regs(sscreen, shader->selector, pm4);
945
946 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
947 }
948
949 static unsigned si_get_ps_num_interp(struct si_shader *ps)
950 {
951 struct tgsi_shader_info *info = &ps->selector->info;
952 unsigned num_colors = !!(info->colors_read & 0x0f) +
953 !!(info->colors_read & 0xf0);
954 unsigned num_interp = ps->selector->info.num_inputs +
955 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
956
957 assert(num_interp <= 32);
958 return MIN2(num_interp, 32);
959 }
960
961 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
962 {
963 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
964 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
965
966 /* If the i-th target format is set, all previous target formats must
967 * be non-zero to avoid hangs.
968 */
969 for (i = 0; i < num_targets; i++)
970 if (!(value & (0xf << (i * 4))))
971 value |= V_028714_SPI_SHADER_32_R << (i * 4);
972
973 return value;
974 }
975
976 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
977 {
978 unsigned i, cb_shader_mask = 0;
979
980 for (i = 0; i < 8; i++) {
981 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
982 case V_028714_SPI_SHADER_ZERO:
983 break;
984 case V_028714_SPI_SHADER_32_R:
985 cb_shader_mask |= 0x1 << (i * 4);
986 break;
987 case V_028714_SPI_SHADER_32_GR:
988 cb_shader_mask |= 0x3 << (i * 4);
989 break;
990 case V_028714_SPI_SHADER_32_AR:
991 cb_shader_mask |= 0x9 << (i * 4);
992 break;
993 case V_028714_SPI_SHADER_FP16_ABGR:
994 case V_028714_SPI_SHADER_UNORM16_ABGR:
995 case V_028714_SPI_SHADER_SNORM16_ABGR:
996 case V_028714_SPI_SHADER_UINT16_ABGR:
997 case V_028714_SPI_SHADER_SINT16_ABGR:
998 case V_028714_SPI_SHADER_32_ABGR:
999 cb_shader_mask |= 0xf << (i * 4);
1000 break;
1001 default:
1002 assert(0);
1003 }
1004 }
1005 return cb_shader_mask;
1006 }
1007
1008 static void si_shader_ps(struct si_shader *shader)
1009 {
1010 struct tgsi_shader_info *info = &shader->selector->info;
1011 struct si_pm4_state *pm4;
1012 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1013 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1014 uint64_t va;
1015 unsigned input_ena = shader->config.spi_ps_input_ena;
1016
1017 /* we need to enable at least one of them, otherwise we hang the GPU */
1018 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1019 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1020 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1021 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1022 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1023 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1024 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1025 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1026 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1027 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1028 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1029 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1030 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1031 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1032
1033 /* Validate interpolation optimization flags (read as implications). */
1034 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1035 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1036 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1037 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1038 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1039 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1040 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1041 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1042 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1043 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1044 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1045 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1046 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1047 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1048 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1049 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1050 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1051 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1052
1053 /* Validate cases when the optimizations are off (read as implications). */
1054 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1055 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1056 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1057 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1058 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1059 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1060
1061 pm4 = si_get_shader_pm4_state(shader);
1062 if (!pm4)
1063 return;
1064
1065 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1066 * Possible vaules:
1067 * 0 -> Position = pixel center
1068 * 1 -> Position = pixel centroid
1069 * 2 -> Position = at sample position
1070 *
1071 * From GLSL 4.5 specification, section 7.1:
1072 * "The variable gl_FragCoord is available as an input variable from
1073 * within fragment shaders and it holds the window relative coordinates
1074 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1075 * value can be for any location within the pixel, or one of the
1076 * fragment samples. The use of centroid does not further restrict
1077 * this value to be inside the current primitive."
1078 *
1079 * Meaning that centroid has no effect and we can return anything within
1080 * the pixel. Thus, return the value at sample position, because that's
1081 * the most accurate one shaders can get.
1082 */
1083 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1084
1085 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1086 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1087 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1088
1089 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1090 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
1091
1092 /* Ensure that some export memory is always allocated, for two reasons:
1093 *
1094 * 1) Correctness: The hardware ignores the EXEC mask if no export
1095 * memory is allocated, so KILL and alpha test do not work correctly
1096 * without this.
1097 * 2) Performance: Every shader needs at least a NULL export, even when
1098 * it writes no color/depth output. The NULL export instruction
1099 * stalls without this setting.
1100 *
1101 * Don't add this to CB_SHADER_MASK.
1102 */
1103 if (!spi_shader_col_format &&
1104 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1105 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1106
1107 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
1108 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
1109 shader->config.spi_ps_input_addr);
1110
1111 /* Set interpolation controls. */
1112 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1113
1114 /* Set registers. */
1115 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1116 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
1117
1118 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
1119 si_get_spi_shader_z_format(info->writes_z,
1120 info->writes_stencil,
1121 info->writes_samplemask));
1122
1123 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
1124 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
1125
1126 va = shader->bo->gpu_address;
1127 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1128 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1129 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
1130
1131 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1132 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1133 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1134 S_00B028_DX10_CLAMP(1) |
1135 S_00B028_FLOAT_MODE(shader->config.float_mode));
1136 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1137 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1138 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1139 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1140 }
1141
1142 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1143 struct si_shader *shader)
1144 {
1145 switch (shader->selector->type) {
1146 case PIPE_SHADER_VERTEX:
1147 if (shader->key.as_ls)
1148 si_shader_ls(sscreen, shader);
1149 else if (shader->key.as_es)
1150 si_shader_es(sscreen, shader);
1151 else
1152 si_shader_vs(sscreen, shader, NULL);
1153 break;
1154 case PIPE_SHADER_TESS_CTRL:
1155 si_shader_hs(sscreen, shader);
1156 break;
1157 case PIPE_SHADER_TESS_EVAL:
1158 if (shader->key.as_es)
1159 si_shader_es(sscreen, shader);
1160 else
1161 si_shader_vs(sscreen, shader, NULL);
1162 break;
1163 case PIPE_SHADER_GEOMETRY:
1164 si_shader_gs(sscreen, shader);
1165 break;
1166 case PIPE_SHADER_FRAGMENT:
1167 si_shader_ps(shader);
1168 break;
1169 default:
1170 assert(0);
1171 }
1172 }
1173
1174 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1175 {
1176 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1177 if (sctx->queued.named.dsa)
1178 return sctx->queued.named.dsa->alpha_func;
1179
1180 return PIPE_FUNC_ALWAYS;
1181 }
1182
1183 static void si_shader_selector_key_vs(struct si_context *sctx,
1184 struct si_shader_selector *vs,
1185 struct si_shader_key *key,
1186 struct si_vs_prolog_bits *prolog_key)
1187 {
1188 if (!sctx->vertex_elements)
1189 return;
1190
1191 unsigned count = MIN2(vs->info.num_inputs,
1192 sctx->vertex_elements->count);
1193 for (unsigned i = 0; i < count; ++i) {
1194 prolog_key->instance_divisors[i] =
1195 sctx->vertex_elements->elements[i].instance_divisor;
1196 }
1197
1198 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1199 }
1200
1201 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1202 struct si_shader_selector *vs,
1203 struct si_shader_key *key)
1204 {
1205 struct si_shader_selector *ps = sctx->ps_shader.cso;
1206
1207 key->opt.hw_vs.clip_disable =
1208 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1209 (vs->info.clipdist_writemask ||
1210 vs->info.writes_clipvertex) &&
1211 !vs->info.culldist_writemask;
1212
1213 /* Find out if PS is disabled. */
1214 bool ps_disabled = true;
1215 if (ps) {
1216 bool ps_modifies_zs = ps->info.uses_kill ||
1217 ps->info.writes_z ||
1218 ps->info.writes_stencil ||
1219 ps->info.writes_samplemask ||
1220 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1221
1222 unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1223 sctx->queued.named.blend->cb_target_mask;
1224 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1225 ps_colormask &= ps->colors_written_4bit;
1226
1227 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1228 (!ps_colormask &&
1229 !ps_modifies_zs &&
1230 !ps->info.writes_memory);
1231 }
1232
1233 /* Find out which VS outputs aren't used by the PS. */
1234 uint64_t outputs_written = vs->outputs_written;
1235 uint32_t outputs_written2 = vs->outputs_written2;
1236 uint64_t inputs_read = 0;
1237 uint32_t inputs_read2 = 0;
1238
1239 outputs_written &= ~0x3; /* ignore POSITION, PSIZE */
1240
1241 if (!ps_disabled) {
1242 inputs_read = ps->inputs_read;
1243 inputs_read2 = ps->inputs_read2;
1244 }
1245
1246 uint64_t linked = outputs_written & inputs_read;
1247 uint32_t linked2 = outputs_written2 & inputs_read2;
1248
1249 key->opt.hw_vs.kill_outputs = ~linked & outputs_written;
1250 key->opt.hw_vs.kill_outputs2 = ~linked2 & outputs_written2;
1251 }
1252
1253 /* Compute the key for the hw shader variant */
1254 static inline void si_shader_selector_key(struct pipe_context *ctx,
1255 struct si_shader_selector *sel,
1256 struct si_shader_key *key)
1257 {
1258 struct si_context *sctx = (struct si_context *)ctx;
1259
1260 memset(key, 0, sizeof(*key));
1261
1262 switch (sel->type) {
1263 case PIPE_SHADER_VERTEX:
1264 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1265
1266 if (sctx->tes_shader.cso)
1267 key->as_ls = 1;
1268 else if (sctx->gs_shader.cso)
1269 key->as_es = 1;
1270 else {
1271 si_shader_selector_key_hw_vs(sctx, sel, key);
1272
1273 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1274 key->mono.vs_export_prim_id = 1;
1275 }
1276 break;
1277 case PIPE_SHADER_TESS_CTRL:
1278 if (sctx->b.chip_class >= GFX9) {
1279 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1280 key, &key->part.tcs.ls_prolog);
1281 key->part.tcs.ls = sctx->vs_shader.cso;
1282 }
1283
1284 key->part.tcs.epilog.prim_mode =
1285 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1286 key->part.tcs.epilog.tes_reads_tess_factors =
1287 sctx->tes_shader.cso->info.reads_tess_factors;
1288
1289 if (sel == sctx->fixed_func_tcs_shader.cso)
1290 key->mono.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1291 break;
1292 case PIPE_SHADER_TESS_EVAL:
1293 if (sctx->gs_shader.cso)
1294 key->as_es = 1;
1295 else {
1296 si_shader_selector_key_hw_vs(sctx, sel, key);
1297
1298 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1299 key->mono.vs_export_prim_id = 1;
1300 }
1301 break;
1302 case PIPE_SHADER_GEOMETRY:
1303 if (sctx->b.chip_class >= GFX9) {
1304 if (sctx->tes_shader.cso) {
1305 key->part.gs.es = sctx->tes_shader.cso;
1306 } else {
1307 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1308 key, &key->part.gs.vs_prolog);
1309 key->part.gs.es = sctx->vs_shader.cso;
1310 }
1311
1312 /* Merged ES-GS can have unbalanced wave usage.
1313 *
1314 * ES threads are per-vertex, while GS threads are
1315 * per-primitive. So without any amplification, there
1316 * are fewer GS threads than ES threads, which can result
1317 * in empty (no-op) GS waves. With too much amplification,
1318 * there are more GS threads than ES threads, which
1319 * can result in empty (no-op) ES waves.
1320 *
1321 * Non-monolithic shaders are implemented by setting EXEC
1322 * at the beginning of shader parts, and don't jump to
1323 * the end if EXEC is 0.
1324 *
1325 * Monolithic shaders use conditional blocks, so they can
1326 * jump and skip empty waves of ES or GS. So set this to
1327 * always use optimized variants, which are monolithic.
1328 */
1329 key->opt.prefer_mono = 1;
1330 }
1331 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1332 break;
1333 case PIPE_SHADER_FRAGMENT: {
1334 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1335 struct si_state_blend *blend = sctx->queued.named.blend;
1336
1337 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1338 sel->info.colors_written == 0x1)
1339 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1340
1341 if (blend) {
1342 /* Select the shader color format based on whether
1343 * blending or alpha are needed.
1344 */
1345 key->part.ps.epilog.spi_shader_col_format =
1346 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1347 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1348 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1349 sctx->framebuffer.spi_shader_col_format_blend) |
1350 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1351 sctx->framebuffer.spi_shader_col_format_alpha) |
1352 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1353 sctx->framebuffer.spi_shader_col_format);
1354
1355 /* The output for dual source blending should have
1356 * the same format as the first output.
1357 */
1358 if (blend->dual_src_blend)
1359 key->part.ps.epilog.spi_shader_col_format |=
1360 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1361 } else
1362 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1363
1364 /* If alpha-to-coverage is enabled, we have to export alpha
1365 * even if there is no color buffer.
1366 */
1367 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1368 blend && blend->alpha_to_coverage)
1369 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1370
1371 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1372 * to the range supported by the type if a channel has less
1373 * than 16 bits and the export format is 16_ABGR.
1374 */
1375 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
1376 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1377 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1378 }
1379
1380 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1381 if (!key->part.ps.epilog.last_cbuf) {
1382 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1383 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1384 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1385 }
1386
1387 if (rs) {
1388 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1389 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1390 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1391 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1392
1393 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1394 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1395
1396 if (sctx->queued.named.blend) {
1397 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1398 rs->multisample_enable;
1399 }
1400
1401 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1402 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1403 (is_line && rs->line_smooth)) &&
1404 sctx->framebuffer.nr_samples <= 1;
1405 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1406
1407 if (rs->force_persample_interp &&
1408 rs->multisample_enable &&
1409 sctx->framebuffer.nr_samples > 1 &&
1410 sctx->ps_iter_samples > 1) {
1411 key->part.ps.prolog.force_persp_sample_interp =
1412 sel->info.uses_persp_center ||
1413 sel->info.uses_persp_centroid;
1414
1415 key->part.ps.prolog.force_linear_sample_interp =
1416 sel->info.uses_linear_center ||
1417 sel->info.uses_linear_centroid;
1418 } else if (rs->multisample_enable &&
1419 sctx->framebuffer.nr_samples > 1) {
1420 key->part.ps.prolog.bc_optimize_for_persp =
1421 sel->info.uses_persp_center &&
1422 sel->info.uses_persp_centroid;
1423 key->part.ps.prolog.bc_optimize_for_linear =
1424 sel->info.uses_linear_center &&
1425 sel->info.uses_linear_centroid;
1426 } else {
1427 /* Make sure SPI doesn't compute more than 1 pair
1428 * of (i,j), which is the optimization here. */
1429 key->part.ps.prolog.force_persp_center_interp =
1430 sel->info.uses_persp_center +
1431 sel->info.uses_persp_centroid +
1432 sel->info.uses_persp_sample > 1;
1433
1434 key->part.ps.prolog.force_linear_center_interp =
1435 sel->info.uses_linear_center +
1436 sel->info.uses_linear_centroid +
1437 sel->info.uses_linear_sample > 1;
1438 }
1439 }
1440
1441 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1442 break;
1443 }
1444 default:
1445 assert(0);
1446 }
1447 }
1448
1449 static void si_build_shader_variant(void *job, int thread_index)
1450 {
1451 struct si_shader *shader = (struct si_shader *)job;
1452 struct si_shader_selector *sel = shader->selector;
1453 struct si_screen *sscreen = sel->screen;
1454 LLVMTargetMachineRef tm;
1455 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1456 int r;
1457
1458 if (thread_index >= 0) {
1459 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1460 tm = sscreen->tm[thread_index];
1461 if (!debug->async)
1462 debug = NULL;
1463 } else {
1464 tm = shader->compiler_ctx_state.tm;
1465 }
1466
1467 r = si_shader_create(sscreen, tm, shader, debug);
1468 if (unlikely(r)) {
1469 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1470 sel->type, r);
1471 shader->compilation_failed = true;
1472 return;
1473 }
1474
1475 if (shader->compiler_ctx_state.is_debug_context) {
1476 FILE *f = open_memstream(&shader->shader_log,
1477 &shader->shader_log_size);
1478 if (f) {
1479 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1480 fclose(f);
1481 }
1482 }
1483
1484 si_shader_init_pm4_state(sscreen, shader);
1485 }
1486
1487 static const struct si_shader_key zeroed;
1488
1489 static bool si_check_missing_main_part(struct si_screen *sscreen,
1490 struct si_shader_selector *sel,
1491 struct si_compiler_ctx_state *compiler_state,
1492 struct si_shader_key *key)
1493 {
1494 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1495
1496 if (!*mainp) {
1497 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1498
1499 if (!main_part)
1500 return false;
1501
1502 main_part->selector = sel;
1503 main_part->key.as_es = key->as_es;
1504 main_part->key.as_ls = key->as_ls;
1505
1506 if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
1507 main_part, false,
1508 &compiler_state->debug) != 0) {
1509 FREE(main_part);
1510 return false;
1511 }
1512 *mainp = main_part;
1513 }
1514 return true;
1515 }
1516
1517 static void si_destroy_shader_selector(struct si_context *sctx,
1518 struct si_shader_selector *sel);
1519
1520 static void si_shader_selector_reference(struct si_context *sctx,
1521 struct si_shader_selector **dst,
1522 struct si_shader_selector *src)
1523 {
1524 if (pipe_reference(&(*dst)->reference, &src->reference))
1525 si_destroy_shader_selector(sctx, *dst);
1526
1527 *dst = src;
1528 }
1529
1530 /* Select the hw shader variant depending on the current state. */
1531 static int si_shader_select_with_key(struct si_screen *sscreen,
1532 struct si_shader_ctx_state *state,
1533 struct si_compiler_ctx_state *compiler_state,
1534 struct si_shader_key *key,
1535 int thread_index)
1536 {
1537 struct si_shader_selector *sel = state->cso;
1538 struct si_shader_selector *previous_stage_sel = NULL;
1539 struct si_shader *current = state->current;
1540 struct si_shader *iter, *shader = NULL;
1541
1542 if (unlikely(sscreen->b.debug_flags & DBG_NO_OPT_VARIANT)) {
1543 memset(&key->opt, 0, sizeof(key->opt));
1544 }
1545
1546 again:
1547 /* Check if we don't need to change anything.
1548 * This path is also used for most shaders that don't need multiple
1549 * variants, it will cost just a computation of the key and this
1550 * test. */
1551 if (likely(current &&
1552 memcmp(&current->key, key, sizeof(*key)) == 0 &&
1553 (!current->is_optimized ||
1554 util_queue_fence_is_signalled(&current->optimized_ready))))
1555 return current->compilation_failed ? -1 : 0;
1556
1557 /* This must be done before the mutex is locked, because async GS
1558 * compilation calls this function too, and therefore must enter
1559 * the mutex first.
1560 *
1561 * Only wait if we are in a draw call. Don't wait if we are
1562 * in a compiler thread.
1563 */
1564 if (thread_index < 0)
1565 util_queue_fence_wait(&sel->ready);
1566
1567 mtx_lock(&sel->mutex);
1568
1569 /* Find the shader variant. */
1570 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1571 /* Don't check the "current" shader. We checked it above. */
1572 if (current != iter &&
1573 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1574 /* If it's an optimized shader and its compilation has
1575 * been started but isn't done, use the unoptimized
1576 * shader so as not to cause a stall due to compilation.
1577 */
1578 if (iter->is_optimized &&
1579 !util_queue_fence_is_signalled(&iter->optimized_ready)) {
1580 memset(&key->opt, 0, sizeof(key->opt));
1581 mtx_unlock(&sel->mutex);
1582 goto again;
1583 }
1584
1585 if (iter->compilation_failed) {
1586 mtx_unlock(&sel->mutex);
1587 return -1; /* skip the draw call */
1588 }
1589
1590 state->current = iter;
1591 mtx_unlock(&sel->mutex);
1592 return 0;
1593 }
1594 }
1595
1596 /* Build a new shader. */
1597 shader = CALLOC_STRUCT(si_shader);
1598 if (!shader) {
1599 mtx_unlock(&sel->mutex);
1600 return -ENOMEM;
1601 }
1602 shader->selector = sel;
1603 shader->key = *key;
1604 shader->compiler_ctx_state = *compiler_state;
1605
1606 /* If this is a merged shader, get the first shader's selector. */
1607 if (sscreen->b.chip_class >= GFX9) {
1608 if (sel->type == PIPE_SHADER_TESS_CTRL)
1609 previous_stage_sel = key->part.tcs.ls;
1610 else if (sel->type == PIPE_SHADER_GEOMETRY)
1611 previous_stage_sel = key->part.gs.es;
1612 }
1613
1614 /* Compile the main shader part if it doesn't exist. This can happen
1615 * if the initial guess was wrong. */
1616 bool is_pure_monolithic =
1617 sscreen->use_monolithic_shaders ||
1618 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1619
1620 if (!is_pure_monolithic) {
1621 bool ok;
1622
1623 /* Make sure the main shader part is present. This is needed
1624 * for shaders that can be compiled as VS, LS, or ES, and only
1625 * one of them is compiled at creation.
1626 *
1627 * For merged shaders, check that the starting shader's main
1628 * part is present.
1629 */
1630 if (previous_stage_sel) {
1631 struct si_shader_key shader1_key = zeroed;
1632
1633 if (sel->type == PIPE_SHADER_TESS_CTRL)
1634 shader1_key.as_ls = 1;
1635 else if (sel->type == PIPE_SHADER_GEOMETRY)
1636 shader1_key.as_es = 1;
1637 else
1638 assert(0);
1639
1640 ok = si_check_missing_main_part(sscreen,
1641 previous_stage_sel,
1642 compiler_state, &shader1_key);
1643 } else {
1644 ok = si_check_missing_main_part(sscreen, sel,
1645 compiler_state, key);
1646 }
1647 if (!ok) {
1648 FREE(shader);
1649 mtx_unlock(&sel->mutex);
1650 return -ENOMEM; /* skip the draw call */
1651 }
1652 }
1653
1654 /* Keep the reference to the 1st shader of merged shaders, so that
1655 * Gallium can't destroy it before we destroy the 2nd shader.
1656 *
1657 * Set sctx = NULL, because it's unused if we're not releasing
1658 * the shader, and we don't have any sctx here.
1659 */
1660 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1661 previous_stage_sel);
1662
1663 /* Monolithic-only shaders don't make a distinction between optimized
1664 * and unoptimized. */
1665 shader->is_monolithic =
1666 is_pure_monolithic ||
1667 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1668
1669 shader->is_optimized =
1670 !is_pure_monolithic &&
1671 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1672 if (shader->is_optimized)
1673 util_queue_fence_init(&shader->optimized_ready);
1674
1675 if (!sel->last_variant) {
1676 sel->first_variant = shader;
1677 sel->last_variant = shader;
1678 } else {
1679 sel->last_variant->next_variant = shader;
1680 sel->last_variant = shader;
1681 }
1682
1683 /* If it's an optimized shader, compile it asynchronously. */
1684 if (shader->is_optimized &&
1685 !is_pure_monolithic &&
1686 thread_index < 0) {
1687 /* Compile it asynchronously. */
1688 util_queue_add_job(&sscreen->shader_compiler_queue,
1689 shader, &shader->optimized_ready,
1690 si_build_shader_variant, NULL);
1691
1692 /* Use the default (unoptimized) shader for now. */
1693 memset(&key->opt, 0, sizeof(key->opt));
1694 mtx_unlock(&sel->mutex);
1695 goto again;
1696 }
1697
1698 assert(!shader->is_optimized);
1699 si_build_shader_variant(shader, thread_index);
1700
1701 if (!shader->compilation_failed)
1702 state->current = shader;
1703
1704 mtx_unlock(&sel->mutex);
1705 return shader->compilation_failed ? -1 : 0;
1706 }
1707
1708 static int si_shader_select(struct pipe_context *ctx,
1709 struct si_shader_ctx_state *state,
1710 struct si_compiler_ctx_state *compiler_state)
1711 {
1712 struct si_context *sctx = (struct si_context *)ctx;
1713 struct si_shader_key key;
1714
1715 si_shader_selector_key(ctx, state->cso, &key);
1716 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1717 &key, -1);
1718 }
1719
1720 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1721 struct si_shader_key *key)
1722 {
1723 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1724
1725 switch (info->processor) {
1726 case PIPE_SHADER_VERTEX:
1727 switch (next_shader) {
1728 case PIPE_SHADER_GEOMETRY:
1729 key->as_es = 1;
1730 break;
1731 case PIPE_SHADER_TESS_CTRL:
1732 case PIPE_SHADER_TESS_EVAL:
1733 key->as_ls = 1;
1734 break;
1735 default:
1736 /* If POSITION isn't written, it can't be a HW VS.
1737 * Assume that it's a HW LS. (the next shader is TCS)
1738 * This heuristic is needed for separate shader objects.
1739 */
1740 if (!info->writes_position)
1741 key->as_ls = 1;
1742 }
1743 break;
1744
1745 case PIPE_SHADER_TESS_EVAL:
1746 if (next_shader == PIPE_SHADER_GEOMETRY ||
1747 !info->writes_position)
1748 key->as_es = 1;
1749 break;
1750 }
1751 }
1752
1753 /**
1754 * Compile the main shader part or the monolithic shader as part of
1755 * si_shader_selector initialization. Since it can be done asynchronously,
1756 * there is no way to report compile failures to applications.
1757 */
1758 void si_init_shader_selector_async(void *job, int thread_index)
1759 {
1760 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1761 struct si_screen *sscreen = sel->screen;
1762 LLVMTargetMachineRef tm;
1763 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1764 unsigned i;
1765
1766 if (thread_index >= 0) {
1767 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1768 tm = sscreen->tm[thread_index];
1769 if (!debug->async)
1770 debug = NULL;
1771 } else {
1772 tm = sel->compiler_ctx_state.tm;
1773 }
1774
1775 /* Compile the main shader part for use with a prolog and/or epilog.
1776 * If this fails, the driver will try to compile a monolithic shader
1777 * on demand.
1778 */
1779 if (!sscreen->use_monolithic_shaders) {
1780 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1781 void *tgsi_binary;
1782
1783 if (!shader) {
1784 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1785 return;
1786 }
1787
1788 shader->selector = sel;
1789 si_parse_next_shader_property(&sel->info, &shader->key);
1790
1791 tgsi_binary = si_get_tgsi_binary(sel);
1792
1793 /* Try to load the shader from the shader cache. */
1794 mtx_lock(&sscreen->shader_cache_mutex);
1795
1796 if (tgsi_binary &&
1797 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1798 mtx_unlock(&sscreen->shader_cache_mutex);
1799 } else {
1800 mtx_unlock(&sscreen->shader_cache_mutex);
1801
1802 /* Compile the shader if it hasn't been loaded from the cache. */
1803 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1804 debug) != 0) {
1805 FREE(shader);
1806 FREE(tgsi_binary);
1807 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1808 return;
1809 }
1810
1811 if (tgsi_binary) {
1812 mtx_lock(&sscreen->shader_cache_mutex);
1813 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader, true))
1814 FREE(tgsi_binary);
1815 mtx_unlock(&sscreen->shader_cache_mutex);
1816 }
1817 }
1818
1819 *si_get_main_shader_part(sel, &shader->key) = shader;
1820
1821 /* Unset "outputs_written" flags for outputs converted to
1822 * DEFAULT_VAL, so that later inter-shader optimizations don't
1823 * try to eliminate outputs that don't exist in the final
1824 * shader.
1825 *
1826 * This is only done if non-monolithic shaders are enabled.
1827 */
1828 if ((sel->type == PIPE_SHADER_VERTEX ||
1829 sel->type == PIPE_SHADER_TESS_EVAL) &&
1830 !shader->key.as_ls &&
1831 !shader->key.as_es) {
1832 unsigned i;
1833
1834 for (i = 0; i < sel->info.num_outputs; i++) {
1835 unsigned offset = shader->info.vs_output_param_offset[i];
1836
1837 if (offset <= AC_EXP_PARAM_OFFSET_31)
1838 continue;
1839
1840 unsigned name = sel->info.output_semantic_name[i];
1841 unsigned index = sel->info.output_semantic_index[i];
1842 unsigned id;
1843
1844 switch (name) {
1845 case TGSI_SEMANTIC_GENERIC:
1846 /* don't process indices the function can't handle */
1847 if (index >= 60)
1848 break;
1849 /* fall through */
1850 case TGSI_SEMANTIC_CLIPDIST:
1851 id = si_shader_io_get_unique_index(name, index);
1852 sel->outputs_written &= ~(1ull << id);
1853 break;
1854 case TGSI_SEMANTIC_POSITION: /* ignore these */
1855 case TGSI_SEMANTIC_PSIZE:
1856 case TGSI_SEMANTIC_CLIPVERTEX:
1857 case TGSI_SEMANTIC_EDGEFLAG:
1858 break;
1859 default:
1860 id = si_shader_io_get_unique_index2(name, index);
1861 sel->outputs_written2 &= ~(1u << id);
1862 }
1863 }
1864 }
1865 }
1866
1867 /* Pre-compilation. */
1868 if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
1869 struct si_shader_ctx_state state = {sel};
1870 struct si_shader_key key;
1871
1872 memset(&key, 0, sizeof(key));
1873 si_parse_next_shader_property(&sel->info, &key);
1874
1875 /* Set reasonable defaults, so that the shader key doesn't
1876 * cause any code to be eliminated.
1877 */
1878 switch (sel->type) {
1879 case PIPE_SHADER_TESS_CTRL:
1880 key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1881 break;
1882 case PIPE_SHADER_FRAGMENT:
1883 key.part.ps.prolog.bc_optimize_for_persp =
1884 sel->info.uses_persp_center &&
1885 sel->info.uses_persp_centroid;
1886 key.part.ps.prolog.bc_optimize_for_linear =
1887 sel->info.uses_linear_center &&
1888 sel->info.uses_linear_centroid;
1889 key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1890 for (i = 0; i < 8; i++)
1891 if (sel->info.colors_written & (1 << i))
1892 key.part.ps.epilog.spi_shader_col_format |=
1893 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1894 break;
1895 }
1896
1897 if (si_shader_select_with_key(sscreen, &state,
1898 &sel->compiler_ctx_state, &key,
1899 thread_index))
1900 fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
1901 }
1902
1903 /* The GS copy shader is always pre-compiled. */
1904 if (sel->type == PIPE_SHADER_GEOMETRY) {
1905 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1906 if (!sel->gs_copy_shader) {
1907 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1908 return;
1909 }
1910
1911 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1912 }
1913 }
1914
1915 static void *si_create_shader_selector(struct pipe_context *ctx,
1916 const struct pipe_shader_state *state)
1917 {
1918 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1919 struct si_context *sctx = (struct si_context*)ctx;
1920 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1921 int i;
1922
1923 if (!sel)
1924 return NULL;
1925
1926 pipe_reference_init(&sel->reference, 1);
1927 sel->screen = sscreen;
1928 sel->compiler_ctx_state.tm = sctx->tm;
1929 sel->compiler_ctx_state.debug = sctx->b.debug;
1930 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
1931 sel->tokens = tgsi_dup_tokens(state->tokens);
1932 if (!sel->tokens) {
1933 FREE(sel);
1934 return NULL;
1935 }
1936
1937 sel->so = state->stream_output;
1938 tgsi_scan_shader(state->tokens, &sel->info);
1939 sel->type = sel->info.processor;
1940 p_atomic_inc(&sscreen->b.num_shaders_created);
1941
1942 /* The prolog is a no-op if there are no inputs. */
1943 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
1944 sel->info.num_inputs;
1945
1946 /* Set which opcode uses which (i,j) pair. */
1947 if (sel->info.uses_persp_opcode_interp_centroid)
1948 sel->info.uses_persp_centroid = true;
1949
1950 if (sel->info.uses_linear_opcode_interp_centroid)
1951 sel->info.uses_linear_centroid = true;
1952
1953 if (sel->info.uses_persp_opcode_interp_offset ||
1954 sel->info.uses_persp_opcode_interp_sample)
1955 sel->info.uses_persp_center = true;
1956
1957 if (sel->info.uses_linear_opcode_interp_offset ||
1958 sel->info.uses_linear_opcode_interp_sample)
1959 sel->info.uses_linear_center = true;
1960
1961 switch (sel->type) {
1962 case PIPE_SHADER_GEOMETRY:
1963 sel->gs_output_prim =
1964 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1965 sel->gs_max_out_vertices =
1966 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1967 sel->gs_num_invocations =
1968 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1969 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
1970 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
1971 sel->gs_max_out_vertices;
1972
1973 sel->max_gs_stream = 0;
1974 for (i = 0; i < sel->so.num_outputs; i++)
1975 sel->max_gs_stream = MAX2(sel->max_gs_stream,
1976 sel->so.output[i].stream);
1977
1978 sel->gs_input_verts_per_prim =
1979 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
1980 break;
1981
1982 case PIPE_SHADER_TESS_CTRL:
1983 /* Always reserve space for these. */
1984 sel->patch_outputs_written |=
1985 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0)) |
1986 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0));
1987 /* fall through */
1988 case PIPE_SHADER_VERTEX:
1989 case PIPE_SHADER_TESS_EVAL:
1990 for (i = 0; i < sel->info.num_outputs; i++) {
1991 unsigned name = sel->info.output_semantic_name[i];
1992 unsigned index = sel->info.output_semantic_index[i];
1993
1994 switch (name) {
1995 case TGSI_SEMANTIC_TESSINNER:
1996 case TGSI_SEMANTIC_TESSOUTER:
1997 case TGSI_SEMANTIC_PATCH:
1998 sel->patch_outputs_written |=
1999 1llu << si_shader_io_get_unique_index(name, index);
2000 break;
2001
2002 case TGSI_SEMANTIC_GENERIC:
2003 /* don't process indices the function can't handle */
2004 if (index >= 60)
2005 break;
2006 /* fall through */
2007 case TGSI_SEMANTIC_POSITION:
2008 case TGSI_SEMANTIC_PSIZE:
2009 case TGSI_SEMANTIC_CLIPDIST:
2010 sel->outputs_written |=
2011 1llu << si_shader_io_get_unique_index(name, index);
2012 break;
2013 case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
2014 case TGSI_SEMANTIC_EDGEFLAG:
2015 break;
2016 default:
2017 sel->outputs_written2 |=
2018 1u << si_shader_io_get_unique_index2(name, index);
2019 }
2020 }
2021 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2022
2023 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2024 * conflicts, i.e. each vertex will start at a different bank.
2025 */
2026 if (sctx->b.chip_class >= GFX9)
2027 sel->esgs_itemsize += 4;
2028 break;
2029
2030 case PIPE_SHADER_FRAGMENT:
2031 for (i = 0; i < sel->info.num_inputs; i++) {
2032 unsigned name = sel->info.input_semantic_name[i];
2033 unsigned index = sel->info.input_semantic_index[i];
2034
2035 switch (name) {
2036 case TGSI_SEMANTIC_CLIPDIST:
2037 case TGSI_SEMANTIC_GENERIC:
2038 sel->inputs_read |=
2039 1llu << si_shader_io_get_unique_index(name, index);
2040 break;
2041 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2042 break;
2043 default:
2044 sel->inputs_read2 |=
2045 1u << si_shader_io_get_unique_index2(name, index);
2046 }
2047 }
2048
2049 for (i = 0; i < 8; i++)
2050 if (sel->info.colors_written & (1 << i))
2051 sel->colors_written_4bit |= 0xf << (4 * i);
2052
2053 for (i = 0; i < sel->info.num_inputs; i++) {
2054 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2055 int index = sel->info.input_semantic_index[i];
2056 sel->color_attr_index[index] = i;
2057 }
2058 }
2059 break;
2060 }
2061
2062 /* DB_SHADER_CONTROL */
2063 sel->db_shader_control =
2064 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2065 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2066 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2067 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2068
2069 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2070 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2071 sel->db_shader_control |=
2072 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2073 break;
2074 case TGSI_FS_DEPTH_LAYOUT_LESS:
2075 sel->db_shader_control |=
2076 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2077 break;
2078 }
2079
2080 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2081 *
2082 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2083 * --|-----------|------------|------------|--------------------|-------------------|-------------
2084 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2085 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2086 * 2 | false | true | n/a | LateZ | 1 | 0
2087 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2088 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2089 *
2090 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2091 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2092 *
2093 * Don't use ReZ without profiling !!!
2094 *
2095 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2096 * shaders.
2097 */
2098 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2099 /* Cases 3, 4. */
2100 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2101 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2102 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2103 } else if (sel->info.writes_memory) {
2104 /* Case 2. */
2105 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2106 S_02880C_EXEC_ON_HIER_FAIL(1);
2107 } else {
2108 /* Case 1. */
2109 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2110 }
2111
2112 (void) mtx_init(&sel->mutex, mtx_plain);
2113 util_queue_fence_init(&sel->ready);
2114
2115 if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
2116 sctx->is_debug ||
2117 r600_can_dump_shader(&sscreen->b, sel->info.processor))
2118 si_init_shader_selector_async(sel, -1);
2119 else
2120 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
2121 &sel->ready, si_init_shader_selector_async,
2122 NULL);
2123
2124 return sel;
2125 }
2126
2127 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2128 {
2129 struct si_context *sctx = (struct si_context *)ctx;
2130 struct si_shader_selector *sel = state;
2131
2132 if (sctx->vs_shader.cso == sel)
2133 return;
2134
2135 sctx->vs_shader.cso = sel;
2136 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2137 sctx->do_update_shaders = true;
2138 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2139 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
2140 }
2141
2142 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2143 {
2144 struct si_context *sctx = (struct si_context *)ctx;
2145 struct si_shader_selector *sel = state;
2146 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2147
2148 if (sctx->gs_shader.cso == sel)
2149 return;
2150
2151 sctx->gs_shader.cso = sel;
2152 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2153 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2154 sctx->do_update_shaders = true;
2155 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2156 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2157
2158 if (enable_changed)
2159 si_shader_change_notify(sctx);
2160 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
2161 }
2162
2163 static void si_update_tcs_tes_uses_prim_id(struct si_context *sctx)
2164 {
2165 sctx->ia_multi_vgt_param_key.u.tcs_tes_uses_prim_id =
2166 (sctx->tes_shader.cso &&
2167 sctx->tes_shader.cso->info.uses_primid) ||
2168 (sctx->tcs_shader.cso &&
2169 sctx->tcs_shader.cso->info.uses_primid);
2170 }
2171
2172 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2173 {
2174 struct si_context *sctx = (struct si_context *)ctx;
2175 struct si_shader_selector *sel = state;
2176 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2177
2178 if (sctx->tcs_shader.cso == sel)
2179 return;
2180
2181 sctx->tcs_shader.cso = sel;
2182 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2183 si_update_tcs_tes_uses_prim_id(sctx);
2184 sctx->do_update_shaders = true;
2185
2186 if (enable_changed)
2187 sctx->last_tcs = NULL; /* invalidate derived tess state */
2188 }
2189
2190 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2191 {
2192 struct si_context *sctx = (struct si_context *)ctx;
2193 struct si_shader_selector *sel = state;
2194 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2195
2196 if (sctx->tes_shader.cso == sel)
2197 return;
2198
2199 sctx->tes_shader.cso = sel;
2200 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2201 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2202 si_update_tcs_tes_uses_prim_id(sctx);
2203 sctx->do_update_shaders = true;
2204 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2205 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2206
2207 if (enable_changed) {
2208 si_shader_change_notify(sctx);
2209 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2210 }
2211 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
2212 }
2213
2214 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2215 {
2216 struct si_context *sctx = (struct si_context *)ctx;
2217 struct si_shader_selector *sel = state;
2218
2219 /* skip if supplied shader is one already in use */
2220 if (sctx->ps_shader.cso == sel)
2221 return;
2222
2223 sctx->ps_shader.cso = sel;
2224 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2225 sctx->do_update_shaders = true;
2226 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2227 }
2228
2229 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2230 {
2231 if (shader->is_optimized) {
2232 util_queue_fence_wait(&shader->optimized_ready);
2233 util_queue_fence_destroy(&shader->optimized_ready);
2234 }
2235
2236 if (shader->pm4) {
2237 switch (shader->selector->type) {
2238 case PIPE_SHADER_VERTEX:
2239 if (shader->key.as_ls) {
2240 assert(sctx->b.chip_class <= VI);
2241 si_pm4_delete_state(sctx, ls, shader->pm4);
2242 } else if (shader->key.as_es) {
2243 assert(sctx->b.chip_class <= VI);
2244 si_pm4_delete_state(sctx, es, shader->pm4);
2245 } else {
2246 si_pm4_delete_state(sctx, vs, shader->pm4);
2247 }
2248 break;
2249 case PIPE_SHADER_TESS_CTRL:
2250 si_pm4_delete_state(sctx, hs, shader->pm4);
2251 break;
2252 case PIPE_SHADER_TESS_EVAL:
2253 if (shader->key.as_es) {
2254 assert(sctx->b.chip_class <= VI);
2255 si_pm4_delete_state(sctx, es, shader->pm4);
2256 } else {
2257 si_pm4_delete_state(sctx, vs, shader->pm4);
2258 }
2259 break;
2260 case PIPE_SHADER_GEOMETRY:
2261 if (shader->is_gs_copy_shader)
2262 si_pm4_delete_state(sctx, vs, shader->pm4);
2263 else
2264 si_pm4_delete_state(sctx, gs, shader->pm4);
2265 break;
2266 case PIPE_SHADER_FRAGMENT:
2267 si_pm4_delete_state(sctx, ps, shader->pm4);
2268 break;
2269 }
2270 }
2271
2272 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2273 si_shader_destroy(shader);
2274 free(shader);
2275 }
2276
2277 static void si_destroy_shader_selector(struct si_context *sctx,
2278 struct si_shader_selector *sel)
2279 {
2280 struct si_shader *p = sel->first_variant, *c;
2281 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2282 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2283 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2284 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2285 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2286 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2287 };
2288
2289 util_queue_fence_wait(&sel->ready);
2290
2291 if (current_shader[sel->type]->cso == sel) {
2292 current_shader[sel->type]->cso = NULL;
2293 current_shader[sel->type]->current = NULL;
2294 }
2295
2296 while (p) {
2297 c = p->next_variant;
2298 si_delete_shader(sctx, p);
2299 p = c;
2300 }
2301
2302 if (sel->main_shader_part)
2303 si_delete_shader(sctx, sel->main_shader_part);
2304 if (sel->main_shader_part_ls)
2305 si_delete_shader(sctx, sel->main_shader_part_ls);
2306 if (sel->main_shader_part_es)
2307 si_delete_shader(sctx, sel->main_shader_part_es);
2308 if (sel->gs_copy_shader)
2309 si_delete_shader(sctx, sel->gs_copy_shader);
2310
2311 util_queue_fence_destroy(&sel->ready);
2312 mtx_destroy(&sel->mutex);
2313 free(sel->tokens);
2314 free(sel);
2315 }
2316
2317 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2318 {
2319 struct si_context *sctx = (struct si_context *)ctx;
2320 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2321
2322 si_shader_selector_reference(sctx, &sel, NULL);
2323 }
2324
2325 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2326 struct si_shader *vs, unsigned name,
2327 unsigned index, unsigned interpolate)
2328 {
2329 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2330 unsigned j, offset, ps_input_cntl = 0;
2331
2332 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2333 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2334 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2335
2336 if (name == TGSI_SEMANTIC_PCOORD ||
2337 (name == TGSI_SEMANTIC_TEXCOORD &&
2338 sctx->sprite_coord_enable & (1 << index))) {
2339 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2340 }
2341
2342 for (j = 0; j < vsinfo->num_outputs; j++) {
2343 if (name == vsinfo->output_semantic_name[j] &&
2344 index == vsinfo->output_semantic_index[j]) {
2345 offset = vs->info.vs_output_param_offset[j];
2346
2347 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2348 /* The input is loaded from parameter memory. */
2349 ps_input_cntl |= S_028644_OFFSET(offset);
2350 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2351 if (offset == AC_EXP_PARAM_UNDEFINED) {
2352 /* This can happen with depth-only rendering. */
2353 offset = 0;
2354 } else {
2355 /* The input is a DEFAULT_VAL constant. */
2356 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2357 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2358 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2359 }
2360
2361 ps_input_cntl = S_028644_OFFSET(0x20) |
2362 S_028644_DEFAULT_VAL(offset);
2363 }
2364 break;
2365 }
2366 }
2367
2368 if (name == TGSI_SEMANTIC_PRIMID)
2369 /* PrimID is written after the last output. */
2370 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2371 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2372 /* No corresponding output found, load defaults into input.
2373 * Don't set any other bits.
2374 * (FLAT_SHADE=1 completely changes behavior) */
2375 ps_input_cntl = S_028644_OFFSET(0x20);
2376 /* D3D 9 behaviour. GL is undefined */
2377 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2378 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2379 }
2380 return ps_input_cntl;
2381 }
2382
2383 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
2384 {
2385 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2386 struct si_shader *ps = sctx->ps_shader.current;
2387 struct si_shader *vs = si_get_vs_state(sctx);
2388 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2389 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2390
2391 if (!ps || !ps->selector->info.num_inputs)
2392 return;
2393
2394 num_interp = si_get_ps_num_interp(ps);
2395 assert(num_interp > 0);
2396 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
2397
2398 for (i = 0; i < psinfo->num_inputs; i++) {
2399 unsigned name = psinfo->input_semantic_name[i];
2400 unsigned index = psinfo->input_semantic_index[i];
2401 unsigned interpolate = psinfo->input_interpolate[i];
2402
2403 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
2404 interpolate));
2405 num_written++;
2406
2407 if (name == TGSI_SEMANTIC_COLOR) {
2408 assert(index < ARRAY_SIZE(bcol_interp));
2409 bcol_interp[index] = interpolate;
2410 }
2411 }
2412
2413 if (ps->key.part.ps.prolog.color_two_side) {
2414 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2415
2416 for (i = 0; i < 2; i++) {
2417 if (!(psinfo->colors_read & (0xf << (i * 4))))
2418 continue;
2419
2420 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
2421 i, bcol_interp[i]));
2422 num_written++;
2423 }
2424 }
2425 assert(num_interp == num_written);
2426 }
2427
2428 /**
2429 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2430 */
2431 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2432 {
2433 if (sctx->init_config_has_vgt_flush)
2434 return;
2435
2436 /* Done by Vulkan before VGT_FLUSH. */
2437 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2438 si_pm4_cmd_add(sctx->init_config,
2439 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2440 si_pm4_cmd_end(sctx->init_config, false);
2441
2442 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2443 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2444 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2445 si_pm4_cmd_end(sctx->init_config, false);
2446 sctx->init_config_has_vgt_flush = true;
2447 }
2448
2449 /* Initialize state related to ESGS / GSVS ring buffers */
2450 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2451 {
2452 struct si_shader_selector *es =
2453 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2454 struct si_shader_selector *gs = sctx->gs_shader.cso;
2455 struct si_pm4_state *pm4;
2456
2457 /* Chip constants. */
2458 unsigned num_se = sctx->screen->b.info.max_se;
2459 unsigned wave_size = 64;
2460 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2461 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2462 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2463 */
2464 unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se;
2465 unsigned alignment = 256 * num_se;
2466 /* The maximum size is 63.999 MB per SE. */
2467 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2468
2469 /* Calculate the minimum size. */
2470 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2471 wave_size, alignment);
2472
2473 /* These are recommended sizes, not minimum sizes. */
2474 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2475 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2476 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2477 gs->max_gsvs_emit_size;
2478
2479 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2480 esgs_ring_size = align(esgs_ring_size, alignment);
2481 gsvs_ring_size = align(gsvs_ring_size, alignment);
2482
2483 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2484 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2485
2486 /* Some rings don't have to be allocated if shaders don't use them.
2487 * (e.g. no varyings between ES and GS or GS and VS)
2488 *
2489 * GFX9 doesn't have the ESGS ring.
2490 */
2491 bool update_esgs = sctx->b.chip_class <= VI &&
2492 esgs_ring_size &&
2493 (!sctx->esgs_ring ||
2494 sctx->esgs_ring->width0 < esgs_ring_size);
2495 bool update_gsvs = gsvs_ring_size &&
2496 (!sctx->gsvs_ring ||
2497 sctx->gsvs_ring->width0 < gsvs_ring_size);
2498
2499 if (!update_esgs && !update_gsvs)
2500 return true;
2501
2502 if (update_esgs) {
2503 pipe_resource_reference(&sctx->esgs_ring, NULL);
2504 sctx->esgs_ring =
2505 r600_aligned_buffer_create(sctx->b.b.screen,
2506 R600_RESOURCE_FLAG_UNMAPPABLE,
2507 PIPE_USAGE_DEFAULT,
2508 esgs_ring_size, alignment);
2509 if (!sctx->esgs_ring)
2510 return false;
2511 }
2512
2513 if (update_gsvs) {
2514 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2515 sctx->gsvs_ring =
2516 r600_aligned_buffer_create(sctx->b.b.screen,
2517 R600_RESOURCE_FLAG_UNMAPPABLE,
2518 PIPE_USAGE_DEFAULT,
2519 gsvs_ring_size, alignment);
2520 if (!sctx->gsvs_ring)
2521 return false;
2522 }
2523
2524 /* Create the "init_config_gs_rings" state. */
2525 pm4 = CALLOC_STRUCT(si_pm4_state);
2526 if (!pm4)
2527 return false;
2528
2529 if (sctx->b.chip_class >= CIK) {
2530 if (sctx->esgs_ring) {
2531 assert(sctx->b.chip_class <= VI);
2532 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2533 sctx->esgs_ring->width0 / 256);
2534 }
2535 if (sctx->gsvs_ring)
2536 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2537 sctx->gsvs_ring->width0 / 256);
2538 } else {
2539 if (sctx->esgs_ring)
2540 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2541 sctx->esgs_ring->width0 / 256);
2542 if (sctx->gsvs_ring)
2543 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2544 sctx->gsvs_ring->width0 / 256);
2545 }
2546
2547 /* Set the state. */
2548 if (sctx->init_config_gs_rings)
2549 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2550 sctx->init_config_gs_rings = pm4;
2551
2552 if (!sctx->init_config_has_vgt_flush) {
2553 si_init_config_add_vgt_flush(sctx);
2554 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2555 }
2556
2557 /* Flush the context to re-emit both init_config states. */
2558 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2559 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2560
2561 /* Set ring bindings. */
2562 if (sctx->esgs_ring) {
2563 assert(sctx->b.chip_class <= VI);
2564 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
2565 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2566 true, true, 4, 64, 0);
2567 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
2568 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2569 false, false, 0, 0, 0);
2570 }
2571 if (sctx->gsvs_ring) {
2572 si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
2573 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2574 false, false, 0, 0, 0);
2575 }
2576
2577 return true;
2578 }
2579
2580 /**
2581 * @returns 1 if \p sel has been updated to use a new scratch buffer
2582 * 0 if not
2583 * < 0 if there was a failure
2584 */
2585 static int si_update_scratch_buffer(struct si_context *sctx,
2586 struct si_shader *shader)
2587 {
2588 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2589 int r;
2590
2591 if (!shader)
2592 return 0;
2593
2594 /* This shader doesn't need a scratch buffer */
2595 if (shader->config.scratch_bytes_per_wave == 0)
2596 return 0;
2597
2598 /* This shader is already configured to use the current
2599 * scratch buffer. */
2600 if (shader->scratch_bo == sctx->scratch_buffer)
2601 return 0;
2602
2603 assert(sctx->scratch_buffer);
2604
2605 si_shader_apply_scratch_relocs(sctx, shader, &shader->config, scratch_va);
2606
2607 /* Replace the shader bo with a new bo that has the relocs applied. */
2608 r = si_shader_binary_upload(sctx->screen, shader);
2609 if (r)
2610 return r;
2611
2612 /* Update the shader state to use the new shader bo. */
2613 si_shader_init_pm4_state(sctx->screen, shader);
2614
2615 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2616
2617 return 1;
2618 }
2619
2620 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2621 {
2622 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2623 }
2624
2625 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2626 {
2627 return shader ? shader->config.scratch_bytes_per_wave : 0;
2628 }
2629
2630 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2631 {
2632 unsigned bytes = 0;
2633
2634 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2635 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2636 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2637 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
2638 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2639 return bytes;
2640 }
2641
2642 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2643 {
2644 unsigned current_scratch_buffer_size =
2645 si_get_current_scratch_buffer_size(sctx);
2646 unsigned scratch_bytes_per_wave =
2647 si_get_max_scratch_bytes_per_wave(sctx);
2648 unsigned scratch_needed_size = scratch_bytes_per_wave *
2649 sctx->scratch_waves;
2650 unsigned spi_tmpring_size;
2651 int r;
2652
2653 if (scratch_needed_size > 0) {
2654 if (scratch_needed_size > current_scratch_buffer_size) {
2655 /* Create a bigger scratch buffer */
2656 r600_resource_reference(&sctx->scratch_buffer, NULL);
2657
2658 sctx->scratch_buffer = (struct r600_resource*)
2659 r600_aligned_buffer_create(&sctx->screen->b.b,
2660 R600_RESOURCE_FLAG_UNMAPPABLE,
2661 PIPE_USAGE_DEFAULT,
2662 scratch_needed_size, 256);
2663 if (!sctx->scratch_buffer)
2664 return false;
2665
2666 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2667 r600_context_add_resource_size(&sctx->b.b,
2668 &sctx->scratch_buffer->b.b);
2669 }
2670
2671 /* Update the shaders, so they are using the latest scratch. The
2672 * scratch buffer may have been changed since these shaders were
2673 * last used, so we still need to try to update them, even if
2674 * they require scratch buffers smaller than the current size.
2675 */
2676 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2677 if (r < 0)
2678 return false;
2679 if (r == 1)
2680 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2681
2682 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2683 if (r < 0)
2684 return false;
2685 if (r == 1)
2686 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2687
2688 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
2689 if (r < 0)
2690 return false;
2691 if (r == 1)
2692 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2693
2694 /* VS can be bound as LS, ES, or VS. */
2695 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2696 if (r < 0)
2697 return false;
2698 if (r == 1) {
2699 if (sctx->tes_shader.current)
2700 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2701 else if (sctx->gs_shader.current)
2702 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2703 else
2704 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2705 }
2706
2707 /* TES can be bound as ES or VS. */
2708 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2709 if (r < 0)
2710 return false;
2711 if (r == 1) {
2712 if (sctx->gs_shader.current)
2713 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2714 else
2715 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2716 }
2717 }
2718
2719 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2720 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
2721 "scratch size should already be aligned correctly.");
2722
2723 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
2724 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
2725 if (spi_tmpring_size != sctx->spi_tmpring_size) {
2726 sctx->spi_tmpring_size = spi_tmpring_size;
2727 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2728 }
2729 return true;
2730 }
2731
2732 static void si_init_tess_factor_ring(struct si_context *sctx)
2733 {
2734 bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
2735 sctx->b.family != CHIP_CARRIZO &&
2736 sctx->b.family != CHIP_STONEY;
2737 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2738 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
2739 sctx->screen->b.info.max_se;
2740 unsigned offchip_granularity;
2741
2742 switch (sctx->screen->tess_offchip_block_dw_size) {
2743 default:
2744 assert(0);
2745 /* fall through */
2746 case 8192:
2747 offchip_granularity = V_03093C_X_8K_DWORDS;
2748 break;
2749 case 4096:
2750 offchip_granularity = V_03093C_X_4K_DWORDS;
2751 break;
2752 }
2753
2754 switch (sctx->b.chip_class) {
2755 case SI:
2756 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2757 break;
2758 case CIK:
2759 case VI:
2760 case GFX9:
2761 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2762 break;
2763 default:
2764 assert(0);
2765 return;
2766 }
2767
2768 assert(!sctx->tf_ring);
2769 sctx->tf_ring = r600_aligned_buffer_create(sctx->b.b.screen,
2770 R600_RESOURCE_FLAG_UNMAPPABLE,
2771 PIPE_USAGE_DEFAULT,
2772 32768 * sctx->screen->b.info.max_se,
2773 256);
2774 if (!sctx->tf_ring)
2775 return;
2776
2777 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
2778
2779 sctx->tess_offchip_ring =
2780 r600_aligned_buffer_create(sctx->b.b.screen,
2781 R600_RESOURCE_FLAG_UNMAPPABLE,
2782 PIPE_USAGE_DEFAULT,
2783 max_offchip_buffers *
2784 sctx->screen->tess_offchip_block_dw_size * 4,
2785 256);
2786 if (!sctx->tess_offchip_ring)
2787 return;
2788
2789 si_init_config_add_vgt_flush(sctx);
2790
2791 /* Append these registers to the init config state. */
2792 if (sctx->b.chip_class >= CIK) {
2793 if (sctx->b.chip_class >= VI)
2794 --max_offchip_buffers;
2795
2796 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
2797 S_030938_SIZE(sctx->tf_ring->width0 / 4));
2798 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
2799 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2800 if (sctx->b.chip_class >= GFX9)
2801 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
2802 r600_resource(sctx->tf_ring)->gpu_address >> 40);
2803 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
2804 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2805 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
2806 } else {
2807 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
2808 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
2809 S_008988_SIZE(sctx->tf_ring->width0 / 4));
2810 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
2811 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2812 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2813 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
2814 }
2815
2816 /* Flush the context to re-emit the init_config state.
2817 * This is done only once in a lifetime of a context.
2818 */
2819 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2820 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2821 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2822
2823 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
2824 0, sctx->tf_ring->width0, false, false, 0, 0, 0);
2825
2826 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_OFFCHIP,
2827 sctx->tess_offchip_ring, 0,
2828 sctx->tess_offchip_ring->width0, false, false, 0, 0, 0);
2829 }
2830
2831 /**
2832 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
2833 * VS passes its outputs to TES directly, so the fixed-function shader only
2834 * has to write TESSOUTER and TESSINNER.
2835 */
2836 static void si_generate_fixed_func_tcs(struct si_context *sctx)
2837 {
2838 struct ureg_src outer, inner;
2839 struct ureg_dst tessouter, tessinner;
2840 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
2841
2842 if (!ureg)
2843 return; /* if we get here, we're screwed */
2844
2845 assert(!sctx->fixed_func_tcs_shader.cso);
2846
2847 outer = ureg_DECL_system_value(ureg,
2848 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
2849 inner = ureg_DECL_system_value(ureg,
2850 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
2851
2852 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
2853 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
2854
2855 ureg_MOV(ureg, tessouter, outer);
2856 ureg_MOV(ureg, tessinner, inner);
2857 ureg_END(ureg);
2858
2859 sctx->fixed_func_tcs_shader.cso =
2860 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
2861 }
2862
2863 static void si_update_vgt_shader_config(struct si_context *sctx)
2864 {
2865 /* Calculate the index of the config.
2866 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
2867 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
2868 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
2869
2870 if (!*pm4) {
2871 uint32_t stages = 0;
2872
2873 *pm4 = CALLOC_STRUCT(si_pm4_state);
2874
2875 if (sctx->tes_shader.cso) {
2876 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2877 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2878
2879 if (sctx->gs_shader.cso)
2880 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2881 S_028B54_GS_EN(1) |
2882 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2883 else
2884 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2885 } else if (sctx->gs_shader.cso) {
2886 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2887 S_028B54_GS_EN(1) |
2888 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2889 }
2890
2891 if (sctx->b.chip_class >= GFX9)
2892 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2893
2894 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
2895 }
2896 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
2897 }
2898
2899 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
2900 {
2901 struct pipe_stream_output_info *so = &shader->so;
2902 uint32_t enabled_stream_buffers_mask = 0;
2903 int i;
2904
2905 for (i = 0; i < so->num_outputs; i++)
2906 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
2907 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
2908 sctx->b.streamout.stride_in_dw = shader->so.stride;
2909 }
2910
2911 bool si_update_shaders(struct si_context *sctx)
2912 {
2913 struct pipe_context *ctx = (struct pipe_context*)sctx;
2914 struct si_compiler_ctx_state compiler_state;
2915 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2916 struct si_shader *old_vs = si_get_vs_state(sctx);
2917 bool old_clip_disable = old_vs ? old_vs->key.opt.hw_vs.clip_disable : false;
2918 int r;
2919
2920 compiler_state.tm = sctx->tm;
2921 compiler_state.debug = sctx->b.debug;
2922 compiler_state.is_debug_context = sctx->is_debug;
2923
2924 /* Update stages before GS. */
2925 if (sctx->tes_shader.cso) {
2926 if (!sctx->tf_ring) {
2927 si_init_tess_factor_ring(sctx);
2928 if (!sctx->tf_ring)
2929 return false;
2930 }
2931
2932 /* VS as LS */
2933 if (sctx->b.chip_class <= VI) {
2934 r = si_shader_select(ctx, &sctx->vs_shader,
2935 &compiler_state);
2936 if (r)
2937 return false;
2938 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2939 }
2940
2941 if (sctx->tcs_shader.cso) {
2942 r = si_shader_select(ctx, &sctx->tcs_shader,
2943 &compiler_state);
2944 if (r)
2945 return false;
2946 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2947 } else {
2948 if (!sctx->fixed_func_tcs_shader.cso) {
2949 si_generate_fixed_func_tcs(sctx);
2950 if (!sctx->fixed_func_tcs_shader.cso)
2951 return false;
2952 }
2953
2954 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
2955 &compiler_state);
2956 if (r)
2957 return false;
2958 si_pm4_bind_state(sctx, hs,
2959 sctx->fixed_func_tcs_shader.current->pm4);
2960 }
2961
2962 if (sctx->gs_shader.cso) {
2963 /* TES as ES */
2964 if (sctx->b.chip_class <= VI) {
2965 r = si_shader_select(ctx, &sctx->tes_shader,
2966 &compiler_state);
2967 if (r)
2968 return false;
2969 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2970 }
2971 } else {
2972 /* TES as VS */
2973 r = si_shader_select(ctx, &sctx->tes_shader,
2974 &compiler_state);
2975 if (r)
2976 return false;
2977 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2978 si_update_so(sctx, sctx->tes_shader.cso);
2979 }
2980 } else if (sctx->gs_shader.cso) {
2981 if (sctx->b.chip_class <= VI) {
2982 /* VS as ES */
2983 r = si_shader_select(ctx, &sctx->vs_shader,
2984 &compiler_state);
2985 if (r)
2986 return false;
2987 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2988
2989 si_pm4_bind_state(sctx, ls, NULL);
2990 si_pm4_bind_state(sctx, hs, NULL);
2991 }
2992 } else {
2993 /* VS as VS */
2994 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
2995 if (r)
2996 return false;
2997 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2998 si_update_so(sctx, sctx->vs_shader.cso);
2999
3000 si_pm4_bind_state(sctx, ls, NULL);
3001 si_pm4_bind_state(sctx, hs, NULL);
3002 }
3003
3004 /* Update GS. */
3005 if (sctx->gs_shader.cso) {
3006 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3007 if (r)
3008 return false;
3009 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3010 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3011 si_update_so(sctx, sctx->gs_shader.cso);
3012
3013 if (!si_update_gs_ring_buffers(sctx))
3014 return false;
3015 } else {
3016 si_pm4_bind_state(sctx, gs, NULL);
3017 if (sctx->b.chip_class <= VI)
3018 si_pm4_bind_state(sctx, es, NULL);
3019 }
3020
3021 si_update_vgt_shader_config(sctx);
3022
3023 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.hw_vs.clip_disable)
3024 si_mark_atom_dirty(sctx, &sctx->clip_regs);
3025
3026 if (sctx->ps_shader.cso) {
3027 unsigned db_shader_control;
3028
3029 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3030 if (r)
3031 return false;
3032 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3033
3034 db_shader_control =
3035 sctx->ps_shader.cso->db_shader_control |
3036 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3037
3038 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3039 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3040 sctx->flatshade != rs->flatshade) {
3041 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3042 sctx->flatshade = rs->flatshade;
3043 si_mark_atom_dirty(sctx, &sctx->spi_map);
3044 }
3045
3046 if (sctx->screen->b.rbplus_allowed && si_pm4_state_changed(sctx, ps))
3047 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
3048
3049 if (sctx->ps_db_shader_control != db_shader_control) {
3050 sctx->ps_db_shader_control = db_shader_control;
3051 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3052 }
3053
3054 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3055 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3056 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3057
3058 if (sctx->b.chip_class == SI)
3059 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3060
3061 if (sctx->framebuffer.nr_samples <= 1)
3062 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
3063 }
3064 }
3065
3066 if (si_pm4_state_changed(sctx, ls) ||
3067 si_pm4_state_changed(sctx, hs) ||
3068 si_pm4_state_changed(sctx, es) ||
3069 si_pm4_state_changed(sctx, gs) ||
3070 si_pm4_state_changed(sctx, vs) ||
3071 si_pm4_state_changed(sctx, ps)) {
3072 if (!si_update_spi_tmpring_size(sctx))
3073 return false;
3074 }
3075
3076 if (sctx->b.chip_class >= CIK)
3077 si_mark_atom_dirty(sctx, &sctx->prefetch_L2);
3078
3079 sctx->do_update_shaders = false;
3080 return true;
3081 }
3082
3083 static void si_emit_scratch_state(struct si_context *sctx,
3084 struct r600_atom *atom)
3085 {
3086 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3087
3088 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3089 sctx->spi_tmpring_size);
3090
3091 if (sctx->scratch_buffer) {
3092 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
3093 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3094 RADEON_PRIO_SCRATCH_BUFFER);
3095 }
3096 }
3097
3098 void si_init_shader_functions(struct si_context *sctx)
3099 {
3100 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
3101 si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
3102 si_emit_scratch_state);
3103
3104 sctx->b.b.create_vs_state = si_create_shader_selector;
3105 sctx->b.b.create_tcs_state = si_create_shader_selector;
3106 sctx->b.b.create_tes_state = si_create_shader_selector;
3107 sctx->b.b.create_gs_state = si_create_shader_selector;
3108 sctx->b.b.create_fs_state = si_create_shader_selector;
3109
3110 sctx->b.b.bind_vs_state = si_bind_vs_shader;
3111 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
3112 sctx->b.b.bind_tes_state = si_bind_tes_shader;
3113 sctx->b.b.bind_gs_state = si_bind_gs_shader;
3114 sctx->b.b.bind_fs_state = si_bind_ps_shader;
3115
3116 sctx->b.b.delete_vs_state = si_delete_shader_selector;
3117 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
3118 sctx->b.b.delete_tes_state = si_delete_shader_selector;
3119 sctx->b.b.delete_gs_state = si_delete_shader_selector;
3120 sctx->b.b.delete_fs_state = si_delete_shader_selector;
3121 }