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radeonsi: make use of ac_get_spi_shader_z_format()
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "sid.h"
26 #include "gfx9d.h"
27 #include "radeon/r600_cs.h"
28
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_ureg.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41
42 /* SHADER_CACHE */
43
44 /**
45 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
46 * integer.
47 */
48 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
49 {
50 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
51 sizeof(struct tgsi_token);
52 unsigned size = 4 + tgsi_size + sizeof(sel->so);
53 char *result = (char*)MALLOC(size);
54
55 if (!result)
56 return NULL;
57
58 *((uint32_t*)result) = size;
59 memcpy(result + 4, sel->tokens, tgsi_size);
60 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
61 return result;
62 }
63
64 /** Copy "data" to "ptr" and return the next dword following copied data. */
65 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
66 {
67 /* data may be NULL if size == 0 */
68 if (size)
69 memcpy(ptr, data, size);
70 ptr += DIV_ROUND_UP(size, 4);
71 return ptr;
72 }
73
74 /** Read data from "ptr". Return the next dword following the data. */
75 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
76 {
77 memcpy(data, ptr, size);
78 ptr += DIV_ROUND_UP(size, 4);
79 return ptr;
80 }
81
82 /**
83 * Write the size as uint followed by the data. Return the next dword
84 * following the copied data.
85 */
86 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
87 {
88 *ptr++ = size;
89 return write_data(ptr, data, size);
90 }
91
92 /**
93 * Read the size as uint followed by the data. Return both via parameters.
94 * Return the next dword following the data.
95 */
96 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
97 {
98 *size = *ptr++;
99 assert(*data == NULL);
100 if (!*size)
101 return ptr;
102 *data = malloc(*size);
103 return read_data(ptr, *data, *size);
104 }
105
106 /**
107 * Return the shader binary in a buffer. The first 4 bytes contain its size
108 * as integer.
109 */
110 static void *si_get_shader_binary(struct si_shader *shader)
111 {
112 /* There is always a size of data followed by the data itself. */
113 unsigned relocs_size = shader->binary.reloc_count *
114 sizeof(shader->binary.relocs[0]);
115 unsigned disasm_size = shader->binary.disasm_string ?
116 strlen(shader->binary.disasm_string) + 1 : 0;
117 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
118 strlen(shader->binary.llvm_ir_string) + 1 : 0;
119 unsigned size =
120 4 + /* total size */
121 4 + /* CRC32 of the data below */
122 align(sizeof(shader->config), 4) +
123 align(sizeof(shader->info), 4) +
124 4 + align(shader->binary.code_size, 4) +
125 4 + align(shader->binary.rodata_size, 4) +
126 4 + align(relocs_size, 4) +
127 4 + align(disasm_size, 4) +
128 4 + align(llvm_ir_size, 4);
129 void *buffer = CALLOC(1, size);
130 uint32_t *ptr = (uint32_t*)buffer;
131
132 if (!buffer)
133 return NULL;
134
135 *ptr++ = size;
136 ptr++; /* CRC32 is calculated at the end. */
137
138 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
139 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
140 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
141 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
142 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
143 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
144 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
145 assert((char *)ptr - (char *)buffer == size);
146
147 /* Compute CRC32. */
148 ptr = (uint32_t*)buffer;
149 ptr++;
150 *ptr = util_hash_crc32(ptr + 1, size - 8);
151
152 return buffer;
153 }
154
155 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
156 {
157 uint32_t *ptr = (uint32_t*)binary;
158 uint32_t size = *ptr++;
159 uint32_t crc32 = *ptr++;
160 unsigned chunk_size;
161
162 if (util_hash_crc32(ptr, size - 8) != crc32) {
163 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
164 return false;
165 }
166
167 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
168 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
169 ptr = read_chunk(ptr, (void**)&shader->binary.code,
170 &shader->binary.code_size);
171 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
172 &shader->binary.rodata_size);
173 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
174 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
175 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
176 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
177
178 return true;
179 }
180
181 /**
182 * Insert a shader into the cache. It's assumed the shader is not in the cache.
183 * Use si_shader_cache_load_shader before calling this.
184 *
185 * Returns false on failure, in which case the tgsi_binary should be freed.
186 */
187 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
188 void *tgsi_binary,
189 struct si_shader *shader,
190 bool insert_into_disk_cache)
191 {
192 void *hw_binary;
193 struct hash_entry *entry;
194 uint8_t key[CACHE_KEY_SIZE];
195
196 entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
197 if (entry)
198 return false; /* already added */
199
200 hw_binary = si_get_shader_binary(shader);
201 if (!hw_binary)
202 return false;
203
204 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
205 hw_binary) == NULL) {
206 FREE(hw_binary);
207 return false;
208 }
209
210 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
211 disk_cache_compute_key(sscreen->disk_shader_cache, tgsi_binary,
212 *((uint32_t *)tgsi_binary), key);
213 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
214 *((uint32_t *) hw_binary), NULL);
215 }
216
217 return true;
218 }
219
220 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
221 void *tgsi_binary,
222 struct si_shader *shader)
223 {
224 struct hash_entry *entry =
225 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
226 if (!entry) {
227 if (sscreen->disk_shader_cache) {
228 unsigned char sha1[CACHE_KEY_SIZE];
229 size_t tg_size = *((uint32_t *) tgsi_binary);
230
231 disk_cache_compute_key(sscreen->disk_shader_cache,
232 tgsi_binary, tg_size, sha1);
233
234 size_t binary_size;
235 uint8_t *buffer =
236 disk_cache_get(sscreen->disk_shader_cache,
237 sha1, &binary_size);
238 if (!buffer)
239 return false;
240
241 if (binary_size < sizeof(uint32_t) ||
242 *((uint32_t*)buffer) != binary_size) {
243 /* Something has gone wrong discard the item
244 * from the cache and rebuild/link from
245 * source.
246 */
247 assert(!"Invalid radeonsi shader disk cache "
248 "item!");
249
250 disk_cache_remove(sscreen->disk_shader_cache,
251 sha1);
252 free(buffer);
253
254 return false;
255 }
256
257 if (!si_load_shader_binary(shader, buffer)) {
258 free(buffer);
259 return false;
260 }
261 free(buffer);
262
263 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary,
264 shader, false))
265 FREE(tgsi_binary);
266 } else {
267 return false;
268 }
269 } else {
270 if (si_load_shader_binary(shader, entry->data))
271 FREE(tgsi_binary);
272 else
273 return false;
274 }
275 p_atomic_inc(&sscreen->num_shader_cache_hits);
276 return true;
277 }
278
279 static uint32_t si_shader_cache_key_hash(const void *key)
280 {
281 /* The first dword is the key size. */
282 return util_hash_crc32(key, *(uint32_t*)key);
283 }
284
285 static bool si_shader_cache_key_equals(const void *a, const void *b)
286 {
287 uint32_t *keya = (uint32_t*)a;
288 uint32_t *keyb = (uint32_t*)b;
289
290 /* The first dword is the key size. */
291 if (*keya != *keyb)
292 return false;
293
294 return memcmp(keya, keyb, *keya) == 0;
295 }
296
297 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
298 {
299 FREE((void*)entry->key);
300 FREE(entry->data);
301 }
302
303 bool si_init_shader_cache(struct si_screen *sscreen)
304 {
305 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
306 sscreen->shader_cache =
307 _mesa_hash_table_create(NULL,
308 si_shader_cache_key_hash,
309 si_shader_cache_key_equals);
310
311 return sscreen->shader_cache != NULL;
312 }
313
314 void si_destroy_shader_cache(struct si_screen *sscreen)
315 {
316 if (sscreen->shader_cache)
317 _mesa_hash_table_destroy(sscreen->shader_cache,
318 si_destroy_shader_cache_entry);
319 mtx_destroy(&sscreen->shader_cache_mutex);
320 }
321
322 /* SHADER STATES */
323
324 static void si_set_tesseval_regs(struct si_screen *sscreen,
325 struct si_shader_selector *tes,
326 struct si_pm4_state *pm4)
327 {
328 struct tgsi_shader_info *info = &tes->info;
329 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
330 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
331 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
332 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
333 unsigned type, partitioning, topology, distribution_mode;
334
335 switch (tes_prim_mode) {
336 case PIPE_PRIM_LINES:
337 type = V_028B6C_TESS_ISOLINE;
338 break;
339 case PIPE_PRIM_TRIANGLES:
340 type = V_028B6C_TESS_TRIANGLE;
341 break;
342 case PIPE_PRIM_QUADS:
343 type = V_028B6C_TESS_QUAD;
344 break;
345 default:
346 assert(0);
347 return;
348 }
349
350 switch (tes_spacing) {
351 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
352 partitioning = V_028B6C_PART_FRAC_ODD;
353 break;
354 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
355 partitioning = V_028B6C_PART_FRAC_EVEN;
356 break;
357 case PIPE_TESS_SPACING_EQUAL:
358 partitioning = V_028B6C_PART_INTEGER;
359 break;
360 default:
361 assert(0);
362 return;
363 }
364
365 if (tes_point_mode)
366 topology = V_028B6C_OUTPUT_POINT;
367 else if (tes_prim_mode == PIPE_PRIM_LINES)
368 topology = V_028B6C_OUTPUT_LINE;
369 else if (tes_vertex_order_cw)
370 /* for some reason, this must be the other way around */
371 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
372 else
373 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
374
375 if (sscreen->has_distributed_tess) {
376 if (sscreen->info.family == CHIP_FIJI ||
377 sscreen->info.family >= CHIP_POLARIS10)
378 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
379 else
380 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
381 } else
382 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
383
384 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
385 S_028B6C_TYPE(type) |
386 S_028B6C_PARTITIONING(partitioning) |
387 S_028B6C_TOPOLOGY(topology) |
388 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
389 }
390
391 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
392 * whether the "fractional odd" tessellation spacing is used.
393 *
394 * Possible VGT configurations and which state should set the register:
395 *
396 * Reg set in | VGT shader configuration | Value
397 * ------------------------------------------------------
398 * VS as VS | VS | 30
399 * VS as ES | ES -> GS -> VS | 30
400 * TES as VS | LS -> HS -> VS | 14 or 30
401 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
402 *
403 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
404 */
405 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
406 struct si_shader_selector *sel,
407 struct si_shader *shader,
408 struct si_pm4_state *pm4)
409 {
410 unsigned type = sel->type;
411
412 if (sscreen->info.family < CHIP_POLARIS10)
413 return;
414
415 /* VS as VS, or VS as ES: */
416 if ((type == PIPE_SHADER_VERTEX &&
417 (!shader ||
418 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
419 /* TES as VS, or TES as ES: */
420 type == PIPE_SHADER_TESS_EVAL) {
421 unsigned vtx_reuse_depth = 30;
422
423 if (type == PIPE_SHADER_TESS_EVAL &&
424 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
425 PIPE_TESS_SPACING_FRACTIONAL_ODD)
426 vtx_reuse_depth = 14;
427
428 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
429 vtx_reuse_depth);
430 }
431 }
432
433 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
434 {
435 if (shader->pm4)
436 si_pm4_clear_state(shader->pm4);
437 else
438 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
439
440 return shader->pm4;
441 }
442
443 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
444 {
445 struct si_pm4_state *pm4;
446 unsigned vgpr_comp_cnt;
447 uint64_t va;
448
449 assert(sscreen->info.chip_class <= VI);
450
451 pm4 = si_get_shader_pm4_state(shader);
452 if (!pm4)
453 return;
454
455 va = shader->bo->gpu_address;
456 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
457
458 /* We need at least 2 components for LS.
459 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
460 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
461 */
462 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
463
464 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
465 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
466
467 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
468 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
469 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
470 S_00B528_DX10_CLAMP(1) |
471 S_00B528_FLOAT_MODE(shader->config.float_mode);
472 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR) |
473 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
474 }
475
476 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
477 {
478 struct si_pm4_state *pm4;
479 uint64_t va;
480 unsigned ls_vgpr_comp_cnt = 0;
481
482 pm4 = si_get_shader_pm4_state(shader);
483 if (!pm4)
484 return;
485
486 va = shader->bo->gpu_address;
487 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
488
489 if (sscreen->info.chip_class >= GFX9) {
490 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
491 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, va >> 40);
492
493 /* We need at least 2 components for LS.
494 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
495 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
496 */
497 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
498
499 shader->config.rsrc2 =
500 S_00B42C_USER_SGPR(GFX9_TCS_NUM_USER_SGPR) |
501 S_00B42C_USER_SGPR_MSB(GFX9_TCS_NUM_USER_SGPR >> 5) |
502 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
503 } else {
504 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
505 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
506
507 shader->config.rsrc2 =
508 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
509 S_00B42C_OC_LDS_EN(1) |
510 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
511 }
512
513 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
514 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
515 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
516 S_00B428_DX10_CLAMP(1) |
517 S_00B428_FLOAT_MODE(shader->config.float_mode) |
518 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
519
520 if (sscreen->info.chip_class <= VI) {
521 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
522 shader->config.rsrc2);
523 }
524 }
525
526 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
527 {
528 struct si_pm4_state *pm4;
529 unsigned num_user_sgprs;
530 unsigned vgpr_comp_cnt;
531 uint64_t va;
532 unsigned oc_lds_en;
533
534 assert(sscreen->info.chip_class <= VI);
535
536 pm4 = si_get_shader_pm4_state(shader);
537 if (!pm4)
538 return;
539
540 va = shader->bo->gpu_address;
541 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
542
543 if (shader->selector->type == PIPE_SHADER_VERTEX) {
544 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
545 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
546 num_user_sgprs = SI_VS_NUM_USER_SGPR;
547 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
548 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
549 num_user_sgprs = SI_TES_NUM_USER_SGPR;
550 } else
551 unreachable("invalid shader selector type");
552
553 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
554
555 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
556 shader->selector->esgs_itemsize / 4);
557 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
558 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
559 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
560 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
561 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
562 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
563 S_00B328_DX10_CLAMP(1) |
564 S_00B328_FLOAT_MODE(shader->config.float_mode));
565 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
566 S_00B32C_USER_SGPR(num_user_sgprs) |
567 S_00B32C_OC_LDS_EN(oc_lds_en) |
568 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
569
570 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
571 si_set_tesseval_regs(sscreen, shader->selector, pm4);
572
573 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
574 }
575
576 /**
577 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
578 * geometry shader.
579 */
580 static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
581 {
582 enum chip_class chip_class = sel->screen->info.chip_class;
583 unsigned gs_max_vert_out = sel->gs_max_out_vertices;
584 unsigned cut_mode;
585
586 if (gs_max_vert_out <= 128) {
587 cut_mode = V_028A40_GS_CUT_128;
588 } else if (gs_max_vert_out <= 256) {
589 cut_mode = V_028A40_GS_CUT_256;
590 } else if (gs_max_vert_out <= 512) {
591 cut_mode = V_028A40_GS_CUT_512;
592 } else {
593 assert(gs_max_vert_out <= 1024);
594 cut_mode = V_028A40_GS_CUT_1024;
595 }
596
597 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
598 S_028A40_CUT_MODE(cut_mode)|
599 S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
600 S_028A40_GS_WRITE_OPTIMIZE(1) |
601 S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
602 }
603
604 struct gfx9_gs_info {
605 unsigned es_verts_per_subgroup;
606 unsigned gs_prims_per_subgroup;
607 unsigned gs_inst_prims_in_subgroup;
608 unsigned max_prims_per_subgroup;
609 unsigned lds_size;
610 };
611
612 static void gfx9_get_gs_info(struct si_shader_selector *es,
613 struct si_shader_selector *gs,
614 struct gfx9_gs_info *out)
615 {
616 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
617 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
618 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
619 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
620
621 /* All these are in dwords: */
622 /* We can't allow using the whole LDS, because GS waves compete with
623 * other shader stages for LDS space. */
624 const unsigned max_lds_size = 8 * 1024;
625 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
626 unsigned esgs_lds_size;
627
628 /* All these are per subgroup: */
629 const unsigned max_out_prims = 32 * 1024;
630 const unsigned max_es_verts = 255;
631 const unsigned ideal_gs_prims = 64;
632 unsigned max_gs_prims, gs_prims;
633 unsigned min_es_verts, es_verts, worst_case_es_verts;
634
635 assert(gs_num_invocations <= 32); /* GL maximum */
636
637 if (uses_adjacency || gs_num_invocations > 1)
638 max_gs_prims = 127 / gs_num_invocations;
639 else
640 max_gs_prims = 255;
641
642 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
643 * Make sure we don't go over the maximum value.
644 */
645 if (gs->gs_max_out_vertices > 0) {
646 max_gs_prims = MIN2(max_gs_prims,
647 max_out_prims /
648 (gs->gs_max_out_vertices * gs_num_invocations));
649 }
650 assert(max_gs_prims > 0);
651
652 /* If the primitive has adjacency, halve the number of vertices
653 * that will be reused in multiple primitives.
654 */
655 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
656
657 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
658 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
659
660 /* Compute ESGS LDS size based on the worst case number of ES vertices
661 * needed to create the target number of GS prims per subgroup.
662 */
663 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
664
665 /* If total LDS usage is too big, refactor partitions based on ratio
666 * of ESGS item sizes.
667 */
668 if (esgs_lds_size > max_lds_size) {
669 /* Our target GS Prims Per Subgroup was too large. Calculate
670 * the maximum number of GS Prims Per Subgroup that will fit
671 * into LDS, capped by the maximum that the hardware can support.
672 */
673 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
674 max_gs_prims);
675 assert(gs_prims > 0);
676 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
677 max_es_verts);
678
679 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
680 assert(esgs_lds_size <= max_lds_size);
681 }
682
683 /* Now calculate remaining ESGS information. */
684 if (esgs_lds_size)
685 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
686 else
687 es_verts = max_es_verts;
688
689 /* Vertices for adjacency primitives are not always reused, so restore
690 * it for ES_VERTS_PER_SUBGRP.
691 */
692 min_es_verts = gs->gs_input_verts_per_prim;
693
694 /* For normal primitives, the VGT only checks if they are past the ES
695 * verts per subgroup after allocating a full GS primitive and if they
696 * are, kick off a new subgroup. But if those additional ES verts are
697 * unique (e.g. not reused) we need to make sure there is enough LDS
698 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
699 */
700 es_verts -= min_es_verts - 1;
701
702 out->es_verts_per_subgroup = es_verts;
703 out->gs_prims_per_subgroup = gs_prims;
704 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
705 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
706 gs->gs_max_out_vertices;
707 out->lds_size = align(esgs_lds_size, 128) / 128;
708
709 assert(out->max_prims_per_subgroup <= max_out_prims);
710 }
711
712 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
713 {
714 struct si_shader_selector *sel = shader->selector;
715 const ubyte *num_components = sel->info.num_stream_output_components;
716 unsigned gs_num_invocations = sel->gs_num_invocations;
717 struct si_pm4_state *pm4;
718 uint64_t va;
719 unsigned max_stream = sel->max_gs_stream;
720 unsigned offset;
721
722 pm4 = si_get_shader_pm4_state(shader);
723 if (!pm4)
724 return;
725
726 offset = num_components[0] * sel->gs_max_out_vertices;
727 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
728 if (max_stream >= 1)
729 offset += num_components[1] * sel->gs_max_out_vertices;
730 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
731 if (max_stream >= 2)
732 offset += num_components[2] * sel->gs_max_out_vertices;
733 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
734 if (max_stream >= 3)
735 offset += num_components[3] * sel->gs_max_out_vertices;
736 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
737
738 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
739 assert(offset < (1 << 15));
740
741 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, sel->gs_max_out_vertices);
742
743 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
744 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
745 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
746 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
747
748 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
749 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
750 S_028B90_ENABLE(gs_num_invocations > 0));
751
752 va = shader->bo->gpu_address;
753 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
754
755 if (sscreen->info.chip_class >= GFX9) {
756 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
757 unsigned es_type = shader->key.part.gs.es->type;
758 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
759 struct gfx9_gs_info gs_info;
760
761 if (es_type == PIPE_SHADER_VERTEX)
762 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
763 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
764 else if (es_type == PIPE_SHADER_TESS_EVAL)
765 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
766 else
767 unreachable("invalid shader selector type");
768
769 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
770 * VGPR[0:4] are always loaded.
771 */
772 if (sel->info.uses_invocationid)
773 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
774 else if (sel->info.uses_primid)
775 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
776 else if (input_prim >= PIPE_PRIM_TRIANGLES)
777 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
778 else
779 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
780
781 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
782
783 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
784 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, va >> 40);
785
786 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
787 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
788 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
789 S_00B228_DX10_CLAMP(1) |
790 S_00B228_FLOAT_MODE(shader->config.float_mode) |
791 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
792 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
793 S_00B22C_USER_SGPR(GFX9_GS_NUM_USER_SGPR) |
794 S_00B22C_USER_SGPR_MSB(GFX9_GS_NUM_USER_SGPR >> 5) |
795 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
796 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
797 S_00B22C_LDS_SIZE(gs_info.lds_size) |
798 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
799
800 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
801 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
802 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
803 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup));
804 si_pm4_set_reg(pm4, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
805 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup));
806 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
807 shader->key.part.gs.es->esgs_itemsize / 4);
808
809 if (es_type == PIPE_SHADER_TESS_EVAL)
810 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
811
812 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
813 NULL, pm4);
814 } else {
815 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
816 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
817
818 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
819 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
820 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
821 S_00B228_DX10_CLAMP(1) |
822 S_00B228_FLOAT_MODE(shader->config.float_mode));
823 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
824 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
825 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
826 }
827 }
828
829 /**
830 * Compute the state for \p shader, which will run as a vertex shader on the
831 * hardware.
832 *
833 * If \p gs is non-NULL, it points to the geometry shader for which this shader
834 * is the copy shader.
835 */
836 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
837 struct si_shader_selector *gs)
838 {
839 const struct tgsi_shader_info *info = &shader->selector->info;
840 struct si_pm4_state *pm4;
841 unsigned num_user_sgprs;
842 unsigned nparams, vgpr_comp_cnt;
843 uint64_t va;
844 unsigned oc_lds_en;
845 unsigned window_space =
846 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
847 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
848
849 pm4 = si_get_shader_pm4_state(shader);
850 if (!pm4)
851 return;
852
853 /* We always write VGT_GS_MODE in the VS state, because every switch
854 * between different shader pipelines involving a different GS or no
855 * GS at all involves a switch of the VS (different GS use different
856 * copy shaders). On the other hand, when the API switches from a GS to
857 * no GS and then back to the same GS used originally, the GS state is
858 * not sent again.
859 */
860 if (!gs) {
861 unsigned mode = V_028A40_GS_OFF;
862
863 /* PrimID needs GS scenario A. */
864 if (enable_prim_id)
865 mode = V_028A40_GS_SCENARIO_A;
866
867 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
868 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
869 } else {
870 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
871 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
872 }
873
874 if (sscreen->info.chip_class <= VI) {
875 /* Reuse needs to be set off if we write oViewport. */
876 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF,
877 S_028AB4_REUSE_OFF(info->writes_viewport_index));
878 }
879
880 va = shader->bo->gpu_address;
881 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
882
883 if (gs) {
884 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
885 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
886 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
887 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
888 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
889 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
890 */
891 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
892
893 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
894 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
895 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
896 } else {
897 num_user_sgprs = SI_VS_NUM_USER_SGPR;
898 }
899 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
900 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
901 num_user_sgprs = SI_TES_NUM_USER_SGPR;
902 } else
903 unreachable("invalid shader selector type");
904
905 /* VS is required to export at least one param. */
906 nparams = MAX2(shader->info.nr_param_exports, 1);
907 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
908 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
909
910 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
911 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
912 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
913 V_02870C_SPI_SHADER_4COMP :
914 V_02870C_SPI_SHADER_NONE) |
915 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
916 V_02870C_SPI_SHADER_4COMP :
917 V_02870C_SPI_SHADER_NONE) |
918 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
919 V_02870C_SPI_SHADER_4COMP :
920 V_02870C_SPI_SHADER_NONE));
921
922 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
923
924 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
925 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
926 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
927 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
928 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
929 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
930 S_00B128_DX10_CLAMP(1) |
931 S_00B128_FLOAT_MODE(shader->config.float_mode));
932 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
933 S_00B12C_USER_SGPR(num_user_sgprs) |
934 S_00B12C_OC_LDS_EN(oc_lds_en) |
935 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
936 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
937 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
938 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
939 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
940 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
941 if (window_space)
942 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
943 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
944 else
945 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
946 S_028818_VTX_W0_FMT(1) |
947 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
948 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
949 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
950
951 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
952 si_set_tesseval_regs(sscreen, shader->selector, pm4);
953
954 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
955 }
956
957 static unsigned si_get_ps_num_interp(struct si_shader *ps)
958 {
959 struct tgsi_shader_info *info = &ps->selector->info;
960 unsigned num_colors = !!(info->colors_read & 0x0f) +
961 !!(info->colors_read & 0xf0);
962 unsigned num_interp = ps->selector->info.num_inputs +
963 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
964
965 assert(num_interp <= 32);
966 return MIN2(num_interp, 32);
967 }
968
969 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
970 {
971 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
972 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
973
974 /* If the i-th target format is set, all previous target formats must
975 * be non-zero to avoid hangs.
976 */
977 for (i = 0; i < num_targets; i++)
978 if (!(value & (0xf << (i * 4))))
979 value |= V_028714_SPI_SHADER_32_R << (i * 4);
980
981 return value;
982 }
983
984 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
985 {
986 unsigned i, cb_shader_mask = 0;
987
988 for (i = 0; i < 8; i++) {
989 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
990 case V_028714_SPI_SHADER_ZERO:
991 break;
992 case V_028714_SPI_SHADER_32_R:
993 cb_shader_mask |= 0x1 << (i * 4);
994 break;
995 case V_028714_SPI_SHADER_32_GR:
996 cb_shader_mask |= 0x3 << (i * 4);
997 break;
998 case V_028714_SPI_SHADER_32_AR:
999 cb_shader_mask |= 0x9 << (i * 4);
1000 break;
1001 case V_028714_SPI_SHADER_FP16_ABGR:
1002 case V_028714_SPI_SHADER_UNORM16_ABGR:
1003 case V_028714_SPI_SHADER_SNORM16_ABGR:
1004 case V_028714_SPI_SHADER_UINT16_ABGR:
1005 case V_028714_SPI_SHADER_SINT16_ABGR:
1006 case V_028714_SPI_SHADER_32_ABGR:
1007 cb_shader_mask |= 0xf << (i * 4);
1008 break;
1009 default:
1010 assert(0);
1011 }
1012 }
1013 return cb_shader_mask;
1014 }
1015
1016 static void si_shader_ps(struct si_shader *shader)
1017 {
1018 struct tgsi_shader_info *info = &shader->selector->info;
1019 struct si_pm4_state *pm4;
1020 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1021 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1022 uint64_t va;
1023 unsigned input_ena = shader->config.spi_ps_input_ena;
1024
1025 /* we need to enable at least one of them, otherwise we hang the GPU */
1026 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1027 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1028 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1029 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1030 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1031 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1032 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1033 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1034 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1035 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1036 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1037 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1038 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1039 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1040
1041 /* Validate interpolation optimization flags (read as implications). */
1042 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1043 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1044 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1045 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1046 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1047 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1048 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1049 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1050 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1051 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1052 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1053 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1054 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1055 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1056 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1057 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1058 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1059 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1060
1061 /* Validate cases when the optimizations are off (read as implications). */
1062 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1063 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1064 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1065 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1066 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1067 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1068
1069 pm4 = si_get_shader_pm4_state(shader);
1070 if (!pm4)
1071 return;
1072
1073 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1074 * Possible vaules:
1075 * 0 -> Position = pixel center
1076 * 1 -> Position = pixel centroid
1077 * 2 -> Position = at sample position
1078 *
1079 * From GLSL 4.5 specification, section 7.1:
1080 * "The variable gl_FragCoord is available as an input variable from
1081 * within fragment shaders and it holds the window relative coordinates
1082 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1083 * value can be for any location within the pixel, or one of the
1084 * fragment samples. The use of centroid does not further restrict
1085 * this value to be inside the current primitive."
1086 *
1087 * Meaning that centroid has no effect and we can return anything within
1088 * the pixel. Thus, return the value at sample position, because that's
1089 * the most accurate one shaders can get.
1090 */
1091 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1092
1093 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1094 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1095 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1096
1097 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1098 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
1099
1100 /* Ensure that some export memory is always allocated, for two reasons:
1101 *
1102 * 1) Correctness: The hardware ignores the EXEC mask if no export
1103 * memory is allocated, so KILL and alpha test do not work correctly
1104 * without this.
1105 * 2) Performance: Every shader needs at least a NULL export, even when
1106 * it writes no color/depth output. The NULL export instruction
1107 * stalls without this setting.
1108 *
1109 * Don't add this to CB_SHADER_MASK.
1110 */
1111 if (!spi_shader_col_format &&
1112 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1113 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1114
1115 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
1116 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
1117 shader->config.spi_ps_input_addr);
1118
1119 /* Set interpolation controls. */
1120 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1121
1122 /* Set registers. */
1123 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1124 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
1125
1126 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
1127 ac_get_spi_shader_z_format(info->writes_z,
1128 info->writes_stencil,
1129 info->writes_samplemask));
1130
1131 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
1132 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
1133
1134 va = shader->bo->gpu_address;
1135 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1136 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1137 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
1138
1139 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1140 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1141 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1142 S_00B028_DX10_CLAMP(1) |
1143 S_00B028_FLOAT_MODE(shader->config.float_mode));
1144 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1145 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1146 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1147 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1148 }
1149
1150 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1151 struct si_shader *shader)
1152 {
1153 switch (shader->selector->type) {
1154 case PIPE_SHADER_VERTEX:
1155 if (shader->key.as_ls)
1156 si_shader_ls(sscreen, shader);
1157 else if (shader->key.as_es)
1158 si_shader_es(sscreen, shader);
1159 else
1160 si_shader_vs(sscreen, shader, NULL);
1161 break;
1162 case PIPE_SHADER_TESS_CTRL:
1163 si_shader_hs(sscreen, shader);
1164 break;
1165 case PIPE_SHADER_TESS_EVAL:
1166 if (shader->key.as_es)
1167 si_shader_es(sscreen, shader);
1168 else
1169 si_shader_vs(sscreen, shader, NULL);
1170 break;
1171 case PIPE_SHADER_GEOMETRY:
1172 si_shader_gs(sscreen, shader);
1173 break;
1174 case PIPE_SHADER_FRAGMENT:
1175 si_shader_ps(shader);
1176 break;
1177 default:
1178 assert(0);
1179 }
1180 }
1181
1182 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1183 {
1184 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1185 if (sctx->queued.named.dsa)
1186 return sctx->queued.named.dsa->alpha_func;
1187
1188 return PIPE_FUNC_ALWAYS;
1189 }
1190
1191 static void si_shader_selector_key_vs(struct si_context *sctx,
1192 struct si_shader_selector *vs,
1193 struct si_shader_key *key,
1194 struct si_vs_prolog_bits *prolog_key)
1195 {
1196 if (!sctx->vertex_elements)
1197 return;
1198
1199 prolog_key->instance_divisor_is_one =
1200 sctx->vertex_elements->instance_divisor_is_one;
1201 prolog_key->instance_divisor_is_fetched =
1202 sctx->vertex_elements->instance_divisor_is_fetched;
1203
1204 /* Prefer a monolithic shader to allow scheduling divisions around
1205 * VBO loads. */
1206 if (prolog_key->instance_divisor_is_fetched)
1207 key->opt.prefer_mono = 1;
1208
1209 unsigned count = MIN2(vs->info.num_inputs,
1210 sctx->vertex_elements->count);
1211 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1212 }
1213
1214 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1215 struct si_shader_selector *vs,
1216 struct si_shader_key *key)
1217 {
1218 struct si_shader_selector *ps = sctx->ps_shader.cso;
1219
1220 key->opt.clip_disable =
1221 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1222 (vs->info.clipdist_writemask ||
1223 vs->info.writes_clipvertex) &&
1224 !vs->info.culldist_writemask;
1225
1226 /* Find out if PS is disabled. */
1227 bool ps_disabled = true;
1228 if (ps) {
1229 bool ps_modifies_zs = ps->info.uses_kill ||
1230 ps->info.writes_z ||
1231 ps->info.writes_stencil ||
1232 ps->info.writes_samplemask ||
1233 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1234
1235 unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1236 sctx->queued.named.blend->cb_target_mask;
1237 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1238 ps_colormask &= ps->colors_written_4bit;
1239
1240 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1241 (!ps_colormask &&
1242 !ps_modifies_zs &&
1243 !ps->info.writes_memory);
1244 }
1245
1246 /* Find out which VS outputs aren't used by the PS. */
1247 uint64_t outputs_written = vs->outputs_written;
1248 uint64_t inputs_read = 0;
1249
1250 /* ignore POSITION, PSIZE */
1251 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0) |
1252 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0))));
1253
1254 if (!ps_disabled) {
1255 inputs_read = ps->inputs_read;
1256 }
1257
1258 uint64_t linked = outputs_written & inputs_read;
1259
1260 key->opt.kill_outputs = ~linked & outputs_written;
1261 }
1262
1263 /* Compute the key for the hw shader variant */
1264 static inline void si_shader_selector_key(struct pipe_context *ctx,
1265 struct si_shader_selector *sel,
1266 struct si_shader_key *key)
1267 {
1268 struct si_context *sctx = (struct si_context *)ctx;
1269
1270 memset(key, 0, sizeof(*key));
1271
1272 switch (sel->type) {
1273 case PIPE_SHADER_VERTEX:
1274 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1275
1276 if (sctx->tes_shader.cso)
1277 key->as_ls = 1;
1278 else if (sctx->gs_shader.cso)
1279 key->as_es = 1;
1280 else {
1281 si_shader_selector_key_hw_vs(sctx, sel, key);
1282
1283 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1284 key->mono.u.vs_export_prim_id = 1;
1285 }
1286 break;
1287 case PIPE_SHADER_TESS_CTRL:
1288 if (sctx->b.chip_class >= GFX9) {
1289 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1290 key, &key->part.tcs.ls_prolog);
1291 key->part.tcs.ls = sctx->vs_shader.cso;
1292
1293 /* When the LS VGPR fix is needed, monolithic shaders
1294 * can:
1295 * - avoid initializing EXEC in both the LS prolog
1296 * and the LS main part when !vs_needs_prolog
1297 * - remove the fixup for unused input VGPRs
1298 */
1299 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1300
1301 /* The LS output / HS input layout can be communicated
1302 * directly instead of via user SGPRs for merged LS-HS.
1303 * The LS VGPR fix prefers this too.
1304 */
1305 key->opt.prefer_mono = 1;
1306 }
1307
1308 key->part.tcs.epilog.prim_mode =
1309 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1310 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1311 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1312 key->part.tcs.epilog.tes_reads_tess_factors =
1313 sctx->tes_shader.cso->info.reads_tess_factors;
1314
1315 if (sel == sctx->fixed_func_tcs_shader.cso)
1316 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1317 break;
1318 case PIPE_SHADER_TESS_EVAL:
1319 if (sctx->gs_shader.cso)
1320 key->as_es = 1;
1321 else {
1322 si_shader_selector_key_hw_vs(sctx, sel, key);
1323
1324 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1325 key->mono.u.vs_export_prim_id = 1;
1326 }
1327 break;
1328 case PIPE_SHADER_GEOMETRY:
1329 if (sctx->b.chip_class >= GFX9) {
1330 if (sctx->tes_shader.cso) {
1331 key->part.gs.es = sctx->tes_shader.cso;
1332 } else {
1333 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1334 key, &key->part.gs.vs_prolog);
1335 key->part.gs.es = sctx->vs_shader.cso;
1336 }
1337
1338 /* Merged ES-GS can have unbalanced wave usage.
1339 *
1340 * ES threads are per-vertex, while GS threads are
1341 * per-primitive. So without any amplification, there
1342 * are fewer GS threads than ES threads, which can result
1343 * in empty (no-op) GS waves. With too much amplification,
1344 * there are more GS threads than ES threads, which
1345 * can result in empty (no-op) ES waves.
1346 *
1347 * Non-monolithic shaders are implemented by setting EXEC
1348 * at the beginning of shader parts, and don't jump to
1349 * the end if EXEC is 0.
1350 *
1351 * Monolithic shaders use conditional blocks, so they can
1352 * jump and skip empty waves of ES or GS. So set this to
1353 * always use optimized variants, which are monolithic.
1354 */
1355 key->opt.prefer_mono = 1;
1356 }
1357 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1358 break;
1359 case PIPE_SHADER_FRAGMENT: {
1360 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1361 struct si_state_blend *blend = sctx->queued.named.blend;
1362
1363 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1364 sel->info.colors_written == 0x1)
1365 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1366
1367 if (blend) {
1368 /* Select the shader color format based on whether
1369 * blending or alpha are needed.
1370 */
1371 key->part.ps.epilog.spi_shader_col_format =
1372 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1373 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1374 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1375 sctx->framebuffer.spi_shader_col_format_blend) |
1376 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1377 sctx->framebuffer.spi_shader_col_format_alpha) |
1378 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1379 sctx->framebuffer.spi_shader_col_format);
1380 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1381
1382 /* The output for dual source blending should have
1383 * the same format as the first output.
1384 */
1385 if (blend->dual_src_blend)
1386 key->part.ps.epilog.spi_shader_col_format |=
1387 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1388 } else
1389 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1390
1391 /* If alpha-to-coverage is enabled, we have to export alpha
1392 * even if there is no color buffer.
1393 */
1394 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1395 blend && blend->alpha_to_coverage)
1396 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1397
1398 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1399 * to the range supported by the type if a channel has less
1400 * than 16 bits and the export format is 16_ABGR.
1401 */
1402 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
1403 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1404 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1405 }
1406
1407 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1408 if (!key->part.ps.epilog.last_cbuf) {
1409 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1410 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1411 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1412 }
1413
1414 if (rs) {
1415 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1416 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1417 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1418 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1419
1420 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1421 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1422
1423 if (sctx->queued.named.blend) {
1424 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1425 rs->multisample_enable;
1426 }
1427
1428 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1429 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1430 (is_line && rs->line_smooth)) &&
1431 sctx->framebuffer.nr_samples <= 1;
1432 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1433
1434 if (sctx->ps_iter_samples > 1 &&
1435 sel->info.reads_samplemask) {
1436 key->part.ps.prolog.samplemask_log_ps_iter =
1437 util_logbase2(util_next_power_of_two(sctx->ps_iter_samples));
1438 }
1439
1440 if (rs->force_persample_interp &&
1441 rs->multisample_enable &&
1442 sctx->framebuffer.nr_samples > 1 &&
1443 sctx->ps_iter_samples > 1) {
1444 key->part.ps.prolog.force_persp_sample_interp =
1445 sel->info.uses_persp_center ||
1446 sel->info.uses_persp_centroid;
1447
1448 key->part.ps.prolog.force_linear_sample_interp =
1449 sel->info.uses_linear_center ||
1450 sel->info.uses_linear_centroid;
1451 } else if (rs->multisample_enable &&
1452 sctx->framebuffer.nr_samples > 1) {
1453 key->part.ps.prolog.bc_optimize_for_persp =
1454 sel->info.uses_persp_center &&
1455 sel->info.uses_persp_centroid;
1456 key->part.ps.prolog.bc_optimize_for_linear =
1457 sel->info.uses_linear_center &&
1458 sel->info.uses_linear_centroid;
1459 } else {
1460 /* Make sure SPI doesn't compute more than 1 pair
1461 * of (i,j), which is the optimization here. */
1462 key->part.ps.prolog.force_persp_center_interp =
1463 sel->info.uses_persp_center +
1464 sel->info.uses_persp_centroid +
1465 sel->info.uses_persp_sample > 1;
1466
1467 key->part.ps.prolog.force_linear_center_interp =
1468 sel->info.uses_linear_center +
1469 sel->info.uses_linear_centroid +
1470 sel->info.uses_linear_sample > 1;
1471
1472 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1473 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1474 }
1475 }
1476
1477 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1478 break;
1479 }
1480 default:
1481 assert(0);
1482 }
1483
1484 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
1485 memset(&key->opt, 0, sizeof(key->opt));
1486 }
1487
1488 static void si_build_shader_variant(struct si_shader *shader,
1489 int thread_index,
1490 bool low_priority)
1491 {
1492 struct si_shader_selector *sel = shader->selector;
1493 struct si_screen *sscreen = sel->screen;
1494 LLVMTargetMachineRef tm;
1495 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1496 int r;
1497
1498 if (thread_index >= 0) {
1499 if (low_priority) {
1500 assert(thread_index < ARRAY_SIZE(sscreen->tm_low_priority));
1501 tm = sscreen->tm_low_priority[thread_index];
1502 } else {
1503 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1504 tm = sscreen->tm[thread_index];
1505 }
1506 if (!debug->async)
1507 debug = NULL;
1508 } else {
1509 assert(!low_priority);
1510 tm = shader->compiler_ctx_state.tm;
1511 }
1512
1513 r = si_shader_create(sscreen, tm, shader, debug);
1514 if (unlikely(r)) {
1515 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1516 sel->type, r);
1517 shader->compilation_failed = true;
1518 return;
1519 }
1520
1521 if (shader->compiler_ctx_state.is_debug_context) {
1522 FILE *f = open_memstream(&shader->shader_log,
1523 &shader->shader_log_size);
1524 if (f) {
1525 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1526 fclose(f);
1527 }
1528 }
1529
1530 si_shader_init_pm4_state(sscreen, shader);
1531 }
1532
1533 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1534 {
1535 struct si_shader *shader = (struct si_shader *)job;
1536
1537 assert(thread_index >= 0);
1538
1539 si_build_shader_variant(shader, thread_index, true);
1540 }
1541
1542 static const struct si_shader_key zeroed;
1543
1544 static bool si_check_missing_main_part(struct si_screen *sscreen,
1545 struct si_shader_selector *sel,
1546 struct si_compiler_ctx_state *compiler_state,
1547 struct si_shader_key *key)
1548 {
1549 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1550
1551 if (!*mainp) {
1552 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1553
1554 if (!main_part)
1555 return false;
1556
1557 /* We can leave the fence as permanently signaled because the
1558 * main part becomes visible globally only after it has been
1559 * compiled. */
1560 util_queue_fence_init(&main_part->ready);
1561
1562 main_part->selector = sel;
1563 main_part->key.as_es = key->as_es;
1564 main_part->key.as_ls = key->as_ls;
1565
1566 if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
1567 main_part, false,
1568 &compiler_state->debug) != 0) {
1569 FREE(main_part);
1570 return false;
1571 }
1572 *mainp = main_part;
1573 }
1574 return true;
1575 }
1576
1577 /* Select the hw shader variant depending on the current state. */
1578 static int si_shader_select_with_key(struct si_screen *sscreen,
1579 struct si_shader_ctx_state *state,
1580 struct si_compiler_ctx_state *compiler_state,
1581 struct si_shader_key *key,
1582 int thread_index)
1583 {
1584 struct si_shader_selector *sel = state->cso;
1585 struct si_shader_selector *previous_stage_sel = NULL;
1586 struct si_shader *current = state->current;
1587 struct si_shader *iter, *shader = NULL;
1588
1589 again:
1590 /* Check if we don't need to change anything.
1591 * This path is also used for most shaders that don't need multiple
1592 * variants, it will cost just a computation of the key and this
1593 * test. */
1594 if (likely(current &&
1595 memcmp(&current->key, key, sizeof(*key)) == 0)) {
1596 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
1597 if (current->is_optimized) {
1598 memset(&key->opt, 0, sizeof(key->opt));
1599 goto current_not_ready;
1600 }
1601
1602 util_queue_fence_wait(&current->ready);
1603 }
1604
1605 return current->compilation_failed ? -1 : 0;
1606 }
1607 current_not_ready:
1608
1609 /* This must be done before the mutex is locked, because async GS
1610 * compilation calls this function too, and therefore must enter
1611 * the mutex first.
1612 *
1613 * Only wait if we are in a draw call. Don't wait if we are
1614 * in a compiler thread.
1615 */
1616 if (thread_index < 0)
1617 util_queue_fence_wait(&sel->ready);
1618
1619 mtx_lock(&sel->mutex);
1620
1621 /* Find the shader variant. */
1622 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1623 /* Don't check the "current" shader. We checked it above. */
1624 if (current != iter &&
1625 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1626 mtx_unlock(&sel->mutex);
1627
1628 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
1629 /* If it's an optimized shader and its compilation has
1630 * been started but isn't done, use the unoptimized
1631 * shader so as not to cause a stall due to compilation.
1632 */
1633 if (iter->is_optimized) {
1634 memset(&key->opt, 0, sizeof(key->opt));
1635 goto again;
1636 }
1637
1638 util_queue_fence_wait(&iter->ready);
1639 }
1640
1641 if (iter->compilation_failed) {
1642 return -1; /* skip the draw call */
1643 }
1644
1645 state->current = iter;
1646 return 0;
1647 }
1648 }
1649
1650 /* Build a new shader. */
1651 shader = CALLOC_STRUCT(si_shader);
1652 if (!shader) {
1653 mtx_unlock(&sel->mutex);
1654 return -ENOMEM;
1655 }
1656
1657 util_queue_fence_init(&shader->ready);
1658
1659 shader->selector = sel;
1660 shader->key = *key;
1661 shader->compiler_ctx_state = *compiler_state;
1662
1663 /* If this is a merged shader, get the first shader's selector. */
1664 if (sscreen->info.chip_class >= GFX9) {
1665 if (sel->type == PIPE_SHADER_TESS_CTRL)
1666 previous_stage_sel = key->part.tcs.ls;
1667 else if (sel->type == PIPE_SHADER_GEOMETRY)
1668 previous_stage_sel = key->part.gs.es;
1669
1670 /* We need to wait for the previous shader. */
1671 if (previous_stage_sel && thread_index < 0)
1672 util_queue_fence_wait(&previous_stage_sel->ready);
1673 }
1674
1675 /* Compile the main shader part if it doesn't exist. This can happen
1676 * if the initial guess was wrong. */
1677 bool is_pure_monolithic =
1678 sscreen->use_monolithic_shaders ||
1679 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1680
1681 if (!is_pure_monolithic) {
1682 bool ok;
1683
1684 /* Make sure the main shader part is present. This is needed
1685 * for shaders that can be compiled as VS, LS, or ES, and only
1686 * one of them is compiled at creation.
1687 *
1688 * For merged shaders, check that the starting shader's main
1689 * part is present.
1690 */
1691 if (previous_stage_sel) {
1692 struct si_shader_key shader1_key = zeroed;
1693
1694 if (sel->type == PIPE_SHADER_TESS_CTRL)
1695 shader1_key.as_ls = 1;
1696 else if (sel->type == PIPE_SHADER_GEOMETRY)
1697 shader1_key.as_es = 1;
1698 else
1699 assert(0);
1700
1701 mtx_lock(&previous_stage_sel->mutex);
1702 ok = si_check_missing_main_part(sscreen,
1703 previous_stage_sel,
1704 compiler_state, &shader1_key);
1705 mtx_unlock(&previous_stage_sel->mutex);
1706 } else {
1707 ok = si_check_missing_main_part(sscreen, sel,
1708 compiler_state, key);
1709 }
1710 if (!ok) {
1711 FREE(shader);
1712 mtx_unlock(&sel->mutex);
1713 return -ENOMEM; /* skip the draw call */
1714 }
1715 }
1716
1717 /* Keep the reference to the 1st shader of merged shaders, so that
1718 * Gallium can't destroy it before we destroy the 2nd shader.
1719 *
1720 * Set sctx = NULL, because it's unused if we're not releasing
1721 * the shader, and we don't have any sctx here.
1722 */
1723 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1724 previous_stage_sel);
1725
1726 /* Monolithic-only shaders don't make a distinction between optimized
1727 * and unoptimized. */
1728 shader->is_monolithic =
1729 is_pure_monolithic ||
1730 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1731
1732 shader->is_optimized =
1733 !is_pure_monolithic &&
1734 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1735
1736 /* If it's an optimized shader, compile it asynchronously. */
1737 if (shader->is_optimized &&
1738 !is_pure_monolithic &&
1739 thread_index < 0) {
1740 /* Compile it asynchronously. */
1741 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1742 shader, &shader->ready,
1743 si_build_shader_variant_low_priority, NULL);
1744
1745 /* Add only after the ready fence was reset, to guard against a
1746 * race with si_bind_XX_shader. */
1747 if (!sel->last_variant) {
1748 sel->first_variant = shader;
1749 sel->last_variant = shader;
1750 } else {
1751 sel->last_variant->next_variant = shader;
1752 sel->last_variant = shader;
1753 }
1754
1755 /* Use the default (unoptimized) shader for now. */
1756 memset(&key->opt, 0, sizeof(key->opt));
1757 mtx_unlock(&sel->mutex);
1758 goto again;
1759 }
1760
1761 /* Reset the fence before adding to the variant list. */
1762 util_queue_fence_reset(&shader->ready);
1763
1764 if (!sel->last_variant) {
1765 sel->first_variant = shader;
1766 sel->last_variant = shader;
1767 } else {
1768 sel->last_variant->next_variant = shader;
1769 sel->last_variant = shader;
1770 }
1771
1772 mtx_unlock(&sel->mutex);
1773
1774 assert(!shader->is_optimized);
1775 si_build_shader_variant(shader, thread_index, false);
1776
1777 util_queue_fence_signal(&shader->ready);
1778
1779 if (!shader->compilation_failed)
1780 state->current = shader;
1781
1782 return shader->compilation_failed ? -1 : 0;
1783 }
1784
1785 static int si_shader_select(struct pipe_context *ctx,
1786 struct si_shader_ctx_state *state,
1787 struct si_compiler_ctx_state *compiler_state)
1788 {
1789 struct si_context *sctx = (struct si_context *)ctx;
1790 struct si_shader_key key;
1791
1792 si_shader_selector_key(ctx, state->cso, &key);
1793 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1794 &key, -1);
1795 }
1796
1797 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1798 bool streamout,
1799 struct si_shader_key *key)
1800 {
1801 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1802
1803 switch (info->processor) {
1804 case PIPE_SHADER_VERTEX:
1805 switch (next_shader) {
1806 case PIPE_SHADER_GEOMETRY:
1807 key->as_es = 1;
1808 break;
1809 case PIPE_SHADER_TESS_CTRL:
1810 case PIPE_SHADER_TESS_EVAL:
1811 key->as_ls = 1;
1812 break;
1813 default:
1814 /* If POSITION isn't written, it can only be a HW VS
1815 * if streamout is used. If streamout isn't used,
1816 * assume that it's a HW LS. (the next shader is TCS)
1817 * This heuristic is needed for separate shader objects.
1818 */
1819 if (!info->writes_position && !streamout)
1820 key->as_ls = 1;
1821 }
1822 break;
1823
1824 case PIPE_SHADER_TESS_EVAL:
1825 if (next_shader == PIPE_SHADER_GEOMETRY ||
1826 !info->writes_position)
1827 key->as_es = 1;
1828 break;
1829 }
1830 }
1831
1832 /**
1833 * Compile the main shader part or the monolithic shader as part of
1834 * si_shader_selector initialization. Since it can be done asynchronously,
1835 * there is no way to report compile failures to applications.
1836 */
1837 static void si_init_shader_selector_async(void *job, int thread_index)
1838 {
1839 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1840 struct si_screen *sscreen = sel->screen;
1841 LLVMTargetMachineRef tm;
1842 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1843 unsigned i;
1844
1845 assert(!debug->debug_message || debug->async);
1846 assert(thread_index >= 0);
1847 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1848 tm = sscreen->tm[thread_index];
1849
1850 /* Compile the main shader part for use with a prolog and/or epilog.
1851 * If this fails, the driver will try to compile a monolithic shader
1852 * on demand.
1853 */
1854 if (!sscreen->use_monolithic_shaders) {
1855 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1856 void *tgsi_binary = NULL;
1857
1858 if (!shader) {
1859 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1860 return;
1861 }
1862
1863 /* We can leave the fence signaled because use of the default
1864 * main part is guarded by the selector's ready fence. */
1865 util_queue_fence_init(&shader->ready);
1866
1867 shader->selector = sel;
1868 si_parse_next_shader_property(&sel->info,
1869 sel->so.num_outputs != 0,
1870 &shader->key);
1871
1872 if (sel->tokens)
1873 tgsi_binary = si_get_tgsi_binary(sel);
1874
1875 /* Try to load the shader from the shader cache. */
1876 mtx_lock(&sscreen->shader_cache_mutex);
1877
1878 if (tgsi_binary &&
1879 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1880 mtx_unlock(&sscreen->shader_cache_mutex);
1881 } else {
1882 mtx_unlock(&sscreen->shader_cache_mutex);
1883
1884 /* Compile the shader if it hasn't been loaded from the cache. */
1885 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1886 debug) != 0) {
1887 FREE(shader);
1888 FREE(tgsi_binary);
1889 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1890 return;
1891 }
1892
1893 if (tgsi_binary) {
1894 mtx_lock(&sscreen->shader_cache_mutex);
1895 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader, true))
1896 FREE(tgsi_binary);
1897 mtx_unlock(&sscreen->shader_cache_mutex);
1898 }
1899 }
1900
1901 *si_get_main_shader_part(sel, &shader->key) = shader;
1902
1903 /* Unset "outputs_written" flags for outputs converted to
1904 * DEFAULT_VAL, so that later inter-shader optimizations don't
1905 * try to eliminate outputs that don't exist in the final
1906 * shader.
1907 *
1908 * This is only done if non-monolithic shaders are enabled.
1909 */
1910 if ((sel->type == PIPE_SHADER_VERTEX ||
1911 sel->type == PIPE_SHADER_TESS_EVAL) &&
1912 !shader->key.as_ls &&
1913 !shader->key.as_es) {
1914 unsigned i;
1915
1916 for (i = 0; i < sel->info.num_outputs; i++) {
1917 unsigned offset = shader->info.vs_output_param_offset[i];
1918
1919 if (offset <= AC_EXP_PARAM_OFFSET_31)
1920 continue;
1921
1922 unsigned name = sel->info.output_semantic_name[i];
1923 unsigned index = sel->info.output_semantic_index[i];
1924 unsigned id;
1925
1926 switch (name) {
1927 case TGSI_SEMANTIC_GENERIC:
1928 /* don't process indices the function can't handle */
1929 if (index >= SI_MAX_IO_GENERIC)
1930 break;
1931 /* fall through */
1932 default:
1933 id = si_shader_io_get_unique_index(name, index);
1934 sel->outputs_written &= ~(1ull << id);
1935 break;
1936 case TGSI_SEMANTIC_POSITION: /* ignore these */
1937 case TGSI_SEMANTIC_PSIZE:
1938 case TGSI_SEMANTIC_CLIPVERTEX:
1939 case TGSI_SEMANTIC_EDGEFLAG:
1940 break;
1941 }
1942 }
1943 }
1944 }
1945
1946 /* Pre-compilation. */
1947 if (sscreen->debug_flags & DBG(PRECOMPILE) &&
1948 /* GFX9 needs LS or ES for compilation, which we don't have here. */
1949 (sscreen->info.chip_class <= VI ||
1950 (sel->type != PIPE_SHADER_TESS_CTRL &&
1951 sel->type != PIPE_SHADER_GEOMETRY))) {
1952 struct si_shader_ctx_state state = {sel};
1953 struct si_shader_key key;
1954
1955 memset(&key, 0, sizeof(key));
1956 si_parse_next_shader_property(&sel->info,
1957 sel->so.num_outputs != 0,
1958 &key);
1959
1960 /* GFX9 doesn't have LS and ES. */
1961 if (sscreen->info.chip_class >= GFX9) {
1962 key.as_ls = 0;
1963 key.as_es = 0;
1964 }
1965
1966 /* Set reasonable defaults, so that the shader key doesn't
1967 * cause any code to be eliminated.
1968 */
1969 switch (sel->type) {
1970 case PIPE_SHADER_TESS_CTRL:
1971 key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1972 break;
1973 case PIPE_SHADER_FRAGMENT:
1974 key.part.ps.prolog.bc_optimize_for_persp =
1975 sel->info.uses_persp_center &&
1976 sel->info.uses_persp_centroid;
1977 key.part.ps.prolog.bc_optimize_for_linear =
1978 sel->info.uses_linear_center &&
1979 sel->info.uses_linear_centroid;
1980 key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1981 for (i = 0; i < 8; i++)
1982 if (sel->info.colors_written & (1 << i))
1983 key.part.ps.epilog.spi_shader_col_format |=
1984 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1985 break;
1986 }
1987
1988 if (si_shader_select_with_key(sscreen, &state,
1989 &sel->compiler_ctx_state, &key,
1990 thread_index))
1991 fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
1992 }
1993
1994 /* The GS copy shader is always pre-compiled. */
1995 if (sel->type == PIPE_SHADER_GEOMETRY) {
1996 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1997 if (!sel->gs_copy_shader) {
1998 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1999 return;
2000 }
2001
2002 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2003 }
2004 }
2005
2006 /* Return descriptor slot usage masks from the given shader info. */
2007 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2008 uint32_t *const_and_shader_buffers,
2009 uint64_t *samplers_and_images)
2010 {
2011 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2012
2013 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2014 num_constbufs = util_last_bit(info->const_buffers_declared);
2015 /* two 8-byte images share one 16-byte slot */
2016 num_images = align(util_last_bit(info->images_declared), 2);
2017 num_samplers = util_last_bit(info->samplers_declared);
2018
2019 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2020 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2021 *const_and_shader_buffers =
2022 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2023
2024 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2025 start = si_get_image_slot(num_images - 1) / 2;
2026 *samplers_and_images =
2027 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2028 }
2029
2030 static void *si_create_shader_selector(struct pipe_context *ctx,
2031 const struct pipe_shader_state *state)
2032 {
2033 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2034 struct si_context *sctx = (struct si_context*)ctx;
2035 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2036 int i;
2037
2038 if (!sel)
2039 return NULL;
2040
2041 pipe_reference_init(&sel->reference, 1);
2042 sel->screen = sscreen;
2043 sel->compiler_ctx_state.debug = sctx->debug;
2044 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2045
2046 sel->so = state->stream_output;
2047
2048 if (state->type == PIPE_SHADER_IR_TGSI) {
2049 sel->tokens = tgsi_dup_tokens(state->tokens);
2050 if (!sel->tokens) {
2051 FREE(sel);
2052 return NULL;
2053 }
2054
2055 tgsi_scan_shader(state->tokens, &sel->info);
2056 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2057 } else {
2058 assert(state->type == PIPE_SHADER_IR_NIR);
2059
2060 sel->nir = state->ir.nir;
2061
2062 si_nir_scan_shader(sel->nir, &sel->info);
2063
2064 si_lower_nir(sel);
2065 }
2066
2067 sel->type = sel->info.processor;
2068 p_atomic_inc(&sscreen->num_shaders_created);
2069 si_get_active_slot_masks(&sel->info,
2070 &sel->active_const_and_shader_buffers,
2071 &sel->active_samplers_and_images);
2072
2073 /* Record which streamout buffers are enabled. */
2074 for (i = 0; i < sel->so.num_outputs; i++) {
2075 sel->enabled_streamout_buffer_mask |=
2076 (1 << sel->so.output[i].output_buffer) <<
2077 (sel->so.output[i].stream * 4);
2078 }
2079
2080 /* The prolog is a no-op if there are no inputs. */
2081 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2082 sel->info.num_inputs &&
2083 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2084
2085 sel->force_correct_derivs_after_kill =
2086 sel->type == PIPE_SHADER_FRAGMENT &&
2087 sel->info.uses_derivatives &&
2088 sel->info.uses_kill &&
2089 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2090
2091 /* Set which opcode uses which (i,j) pair. */
2092 if (sel->info.uses_persp_opcode_interp_centroid)
2093 sel->info.uses_persp_centroid = true;
2094
2095 if (sel->info.uses_linear_opcode_interp_centroid)
2096 sel->info.uses_linear_centroid = true;
2097
2098 if (sel->info.uses_persp_opcode_interp_offset ||
2099 sel->info.uses_persp_opcode_interp_sample)
2100 sel->info.uses_persp_center = true;
2101
2102 if (sel->info.uses_linear_opcode_interp_offset ||
2103 sel->info.uses_linear_opcode_interp_sample)
2104 sel->info.uses_linear_center = true;
2105
2106 switch (sel->type) {
2107 case PIPE_SHADER_GEOMETRY:
2108 sel->gs_output_prim =
2109 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2110 sel->gs_max_out_vertices =
2111 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2112 sel->gs_num_invocations =
2113 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2114 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2115 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2116 sel->gs_max_out_vertices;
2117
2118 sel->max_gs_stream = 0;
2119 for (i = 0; i < sel->so.num_outputs; i++)
2120 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2121 sel->so.output[i].stream);
2122
2123 sel->gs_input_verts_per_prim =
2124 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2125 break;
2126
2127 case PIPE_SHADER_TESS_CTRL:
2128 /* Always reserve space for these. */
2129 sel->patch_outputs_written |=
2130 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2131 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2132 /* fall through */
2133 case PIPE_SHADER_VERTEX:
2134 case PIPE_SHADER_TESS_EVAL:
2135 for (i = 0; i < sel->info.num_outputs; i++) {
2136 unsigned name = sel->info.output_semantic_name[i];
2137 unsigned index = sel->info.output_semantic_index[i];
2138
2139 switch (name) {
2140 case TGSI_SEMANTIC_TESSINNER:
2141 case TGSI_SEMANTIC_TESSOUTER:
2142 case TGSI_SEMANTIC_PATCH:
2143 sel->patch_outputs_written |=
2144 1ull << si_shader_io_get_unique_index_patch(name, index);
2145 break;
2146
2147 case TGSI_SEMANTIC_GENERIC:
2148 /* don't process indices the function can't handle */
2149 if (index >= SI_MAX_IO_GENERIC)
2150 break;
2151 /* fall through */
2152 default:
2153 sel->outputs_written |=
2154 1ull << si_shader_io_get_unique_index(name, index);
2155 break;
2156 case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
2157 case TGSI_SEMANTIC_EDGEFLAG:
2158 break;
2159 }
2160 }
2161 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2162
2163 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2164 * conflicts, i.e. each vertex will start at a different bank.
2165 */
2166 if (sctx->b.chip_class >= GFX9)
2167 sel->esgs_itemsize += 4;
2168 break;
2169
2170 case PIPE_SHADER_FRAGMENT:
2171 for (i = 0; i < sel->info.num_inputs; i++) {
2172 unsigned name = sel->info.input_semantic_name[i];
2173 unsigned index = sel->info.input_semantic_index[i];
2174
2175 switch (name) {
2176 case TGSI_SEMANTIC_GENERIC:
2177 /* don't process indices the function can't handle */
2178 if (index >= SI_MAX_IO_GENERIC)
2179 break;
2180 /* fall through */
2181 default:
2182 sel->inputs_read |=
2183 1ull << si_shader_io_get_unique_index(name, index);
2184 break;
2185 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2186 break;
2187 }
2188 }
2189
2190 for (i = 0; i < 8; i++)
2191 if (sel->info.colors_written & (1 << i))
2192 sel->colors_written_4bit |= 0xf << (4 * i);
2193
2194 for (i = 0; i < sel->info.num_inputs; i++) {
2195 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2196 int index = sel->info.input_semantic_index[i];
2197 sel->color_attr_index[index] = i;
2198 }
2199 }
2200 break;
2201 }
2202
2203 /* PA_CL_VS_OUT_CNTL */
2204 bool misc_vec_ena =
2205 sel->info.writes_psize || sel->info.writes_edgeflag ||
2206 sel->info.writes_layer || sel->info.writes_viewport_index;
2207 sel->pa_cl_vs_out_cntl =
2208 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2209 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2210 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2211 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2212 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2213 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2214 sel->clipdist_mask = sel->info.writes_clipvertex ?
2215 SIX_BITS : sel->info.clipdist_writemask;
2216 sel->culldist_mask = sel->info.culldist_writemask <<
2217 sel->info.num_written_clipdistance;
2218
2219 /* DB_SHADER_CONTROL */
2220 sel->db_shader_control =
2221 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2222 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2223 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2224 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2225
2226 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2227 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2228 sel->db_shader_control |=
2229 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2230 break;
2231 case TGSI_FS_DEPTH_LAYOUT_LESS:
2232 sel->db_shader_control |=
2233 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2234 break;
2235 }
2236
2237 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2238 *
2239 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2240 * --|-----------|------------|------------|--------------------|-------------------|-------------
2241 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2242 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2243 * 2 | false | true | n/a | LateZ | 1 | 0
2244 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2245 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2246 *
2247 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2248 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2249 *
2250 * Don't use ReZ without profiling !!!
2251 *
2252 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2253 * shaders.
2254 */
2255 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2256 /* Cases 3, 4. */
2257 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2258 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2259 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2260 } else if (sel->info.writes_memory) {
2261 /* Case 2. */
2262 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2263 S_02880C_EXEC_ON_HIER_FAIL(1);
2264 } else {
2265 /* Case 1. */
2266 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2267 }
2268
2269 (void) mtx_init(&sel->mutex, mtx_plain);
2270 util_queue_fence_init(&sel->ready);
2271
2272 struct util_async_debug_callback async_debug;
2273 bool wait =
2274 (sctx->debug.debug_message && !sctx->debug.async) ||
2275 sctx->is_debug ||
2276 si_can_dump_shader(sscreen, sel->info.processor);
2277
2278 if (wait) {
2279 u_async_debug_init(&async_debug);
2280 sel->compiler_ctx_state.debug = async_debug.base;
2281 }
2282
2283 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
2284 &sel->ready, si_init_shader_selector_async,
2285 NULL);
2286
2287 if (wait) {
2288 util_queue_fence_wait(&sel->ready);
2289 u_async_debug_drain(&async_debug, &sctx->debug);
2290 u_async_debug_cleanup(&async_debug);
2291 }
2292
2293 return sel;
2294 }
2295
2296 static void si_update_streamout_state(struct si_context *sctx)
2297 {
2298 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2299
2300 if (!shader_with_so)
2301 return;
2302
2303 sctx->streamout.enabled_stream_buffers_mask =
2304 shader_with_so->enabled_streamout_buffer_mask;
2305 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2306 }
2307
2308 static void si_update_clip_regs(struct si_context *sctx,
2309 struct si_shader_selector *old_hw_vs,
2310 struct si_shader *old_hw_vs_variant,
2311 struct si_shader_selector *next_hw_vs,
2312 struct si_shader *next_hw_vs_variant)
2313 {
2314 if (next_hw_vs &&
2315 (!old_hw_vs ||
2316 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2317 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2318 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2319 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2320 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2321 !old_hw_vs_variant ||
2322 !next_hw_vs_variant ||
2323 old_hw_vs_variant->key.opt.clip_disable !=
2324 next_hw_vs_variant->key.opt.clip_disable))
2325 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2326 }
2327
2328 static void si_update_common_shader_state(struct si_context *sctx)
2329 {
2330 sctx->uses_bindless_samplers =
2331 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2332 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2333 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2334 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2335 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2336 sctx->uses_bindless_images =
2337 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2338 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2339 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2340 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2341 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2342 sctx->do_update_shaders = true;
2343 }
2344
2345 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2346 {
2347 struct si_context *sctx = (struct si_context *)ctx;
2348 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2349 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2350 struct si_shader_selector *sel = state;
2351
2352 if (sctx->vs_shader.cso == sel)
2353 return;
2354
2355 sctx->vs_shader.cso = sel;
2356 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2357 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2358
2359 si_update_common_shader_state(sctx);
2360 si_update_vs_viewport_state(sctx);
2361 si_set_active_descriptors_for_shader(sctx, sel);
2362 si_update_streamout_state(sctx);
2363 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2364 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2365 }
2366
2367 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2368 {
2369 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2370 (sctx->tes_shader.cso &&
2371 sctx->tes_shader.cso->info.uses_primid) ||
2372 (sctx->tcs_shader.cso &&
2373 sctx->tcs_shader.cso->info.uses_primid) ||
2374 (sctx->gs_shader.cso &&
2375 sctx->gs_shader.cso->info.uses_primid) ||
2376 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2377 sctx->ps_shader.cso->info.uses_primid);
2378 }
2379
2380 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2381 {
2382 struct si_context *sctx = (struct si_context *)ctx;
2383 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2384 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2385 struct si_shader_selector *sel = state;
2386 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2387
2388 if (sctx->gs_shader.cso == sel)
2389 return;
2390
2391 sctx->gs_shader.cso = sel;
2392 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2393 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2394
2395 si_update_common_shader_state(sctx);
2396 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2397
2398 if (enable_changed) {
2399 si_shader_change_notify(sctx);
2400 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2401 si_update_tess_uses_prim_id(sctx);
2402 }
2403 si_update_vs_viewport_state(sctx);
2404 si_set_active_descriptors_for_shader(sctx, sel);
2405 si_update_streamout_state(sctx);
2406 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2407 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2408 }
2409
2410 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2411 {
2412 struct si_context *sctx = (struct si_context *)ctx;
2413 struct si_shader_selector *sel = state;
2414 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2415
2416 if (sctx->tcs_shader.cso == sel)
2417 return;
2418
2419 sctx->tcs_shader.cso = sel;
2420 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2421 si_update_tess_uses_prim_id(sctx);
2422
2423 si_update_common_shader_state(sctx);
2424
2425 if (enable_changed)
2426 sctx->last_tcs = NULL; /* invalidate derived tess state */
2427
2428 si_set_active_descriptors_for_shader(sctx, sel);
2429 }
2430
2431 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2432 {
2433 struct si_context *sctx = (struct si_context *)ctx;
2434 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2435 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2436 struct si_shader_selector *sel = state;
2437 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2438
2439 if (sctx->tes_shader.cso == sel)
2440 return;
2441
2442 sctx->tes_shader.cso = sel;
2443 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2444 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2445 si_update_tess_uses_prim_id(sctx);
2446
2447 si_update_common_shader_state(sctx);
2448 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2449
2450 if (enable_changed) {
2451 si_shader_change_notify(sctx);
2452 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2453 }
2454 si_update_vs_viewport_state(sctx);
2455 si_set_active_descriptors_for_shader(sctx, sel);
2456 si_update_streamout_state(sctx);
2457 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2458 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2459 }
2460
2461 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2462 {
2463 struct si_context *sctx = (struct si_context *)ctx;
2464 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2465 struct si_shader_selector *sel = state;
2466
2467 /* skip if supplied shader is one already in use */
2468 if (old_sel == sel)
2469 return;
2470
2471 sctx->ps_shader.cso = sel;
2472 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2473
2474 si_update_common_shader_state(sctx);
2475 if (sel) {
2476 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2477 si_update_tess_uses_prim_id(sctx);
2478
2479 if (!old_sel ||
2480 old_sel->info.colors_written != sel->info.colors_written)
2481 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2482
2483 if (sctx->screen->has_out_of_order_rast &&
2484 (!old_sel ||
2485 old_sel->info.writes_memory != sel->info.writes_memory ||
2486 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
2487 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
2488 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2489 }
2490 si_set_active_descriptors_for_shader(sctx, sel);
2491 }
2492
2493 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2494 {
2495 if (shader->is_optimized) {
2496 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2497 &shader->ready);
2498 }
2499
2500 util_queue_fence_destroy(&shader->ready);
2501
2502 if (shader->pm4) {
2503 switch (shader->selector->type) {
2504 case PIPE_SHADER_VERTEX:
2505 if (shader->key.as_ls) {
2506 assert(sctx->b.chip_class <= VI);
2507 si_pm4_delete_state(sctx, ls, shader->pm4);
2508 } else if (shader->key.as_es) {
2509 assert(sctx->b.chip_class <= VI);
2510 si_pm4_delete_state(sctx, es, shader->pm4);
2511 } else {
2512 si_pm4_delete_state(sctx, vs, shader->pm4);
2513 }
2514 break;
2515 case PIPE_SHADER_TESS_CTRL:
2516 si_pm4_delete_state(sctx, hs, shader->pm4);
2517 break;
2518 case PIPE_SHADER_TESS_EVAL:
2519 if (shader->key.as_es) {
2520 assert(sctx->b.chip_class <= VI);
2521 si_pm4_delete_state(sctx, es, shader->pm4);
2522 } else {
2523 si_pm4_delete_state(sctx, vs, shader->pm4);
2524 }
2525 break;
2526 case PIPE_SHADER_GEOMETRY:
2527 if (shader->is_gs_copy_shader)
2528 si_pm4_delete_state(sctx, vs, shader->pm4);
2529 else
2530 si_pm4_delete_state(sctx, gs, shader->pm4);
2531 break;
2532 case PIPE_SHADER_FRAGMENT:
2533 si_pm4_delete_state(sctx, ps, shader->pm4);
2534 break;
2535 }
2536 }
2537
2538 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2539 si_shader_destroy(shader);
2540 free(shader);
2541 }
2542
2543 void si_destroy_shader_selector(struct si_context *sctx,
2544 struct si_shader_selector *sel)
2545 {
2546 struct si_shader *p = sel->first_variant, *c;
2547 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2548 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2549 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2550 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2551 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2552 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2553 };
2554
2555 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2556
2557 if (current_shader[sel->type]->cso == sel) {
2558 current_shader[sel->type]->cso = NULL;
2559 current_shader[sel->type]->current = NULL;
2560 }
2561
2562 while (p) {
2563 c = p->next_variant;
2564 si_delete_shader(sctx, p);
2565 p = c;
2566 }
2567
2568 if (sel->main_shader_part)
2569 si_delete_shader(sctx, sel->main_shader_part);
2570 if (sel->main_shader_part_ls)
2571 si_delete_shader(sctx, sel->main_shader_part_ls);
2572 if (sel->main_shader_part_es)
2573 si_delete_shader(sctx, sel->main_shader_part_es);
2574 if (sel->gs_copy_shader)
2575 si_delete_shader(sctx, sel->gs_copy_shader);
2576
2577 util_queue_fence_destroy(&sel->ready);
2578 mtx_destroy(&sel->mutex);
2579 free(sel->tokens);
2580 ralloc_free(sel->nir);
2581 free(sel);
2582 }
2583
2584 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2585 {
2586 struct si_context *sctx = (struct si_context *)ctx;
2587 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2588
2589 si_shader_selector_reference(sctx, &sel, NULL);
2590 }
2591
2592 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2593 struct si_shader *vs, unsigned name,
2594 unsigned index, unsigned interpolate)
2595 {
2596 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2597 unsigned j, offset, ps_input_cntl = 0;
2598
2599 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2600 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2601 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2602
2603 if (name == TGSI_SEMANTIC_PCOORD ||
2604 (name == TGSI_SEMANTIC_TEXCOORD &&
2605 sctx->sprite_coord_enable & (1 << index))) {
2606 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2607 }
2608
2609 for (j = 0; j < vsinfo->num_outputs; j++) {
2610 if (name == vsinfo->output_semantic_name[j] &&
2611 index == vsinfo->output_semantic_index[j]) {
2612 offset = vs->info.vs_output_param_offset[j];
2613
2614 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2615 /* The input is loaded from parameter memory. */
2616 ps_input_cntl |= S_028644_OFFSET(offset);
2617 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2618 if (offset == AC_EXP_PARAM_UNDEFINED) {
2619 /* This can happen with depth-only rendering. */
2620 offset = 0;
2621 } else {
2622 /* The input is a DEFAULT_VAL constant. */
2623 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2624 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2625 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2626 }
2627
2628 ps_input_cntl = S_028644_OFFSET(0x20) |
2629 S_028644_DEFAULT_VAL(offset);
2630 }
2631 break;
2632 }
2633 }
2634
2635 if (name == TGSI_SEMANTIC_PRIMID)
2636 /* PrimID is written after the last output. */
2637 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2638 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2639 /* No corresponding output found, load defaults into input.
2640 * Don't set any other bits.
2641 * (FLAT_SHADE=1 completely changes behavior) */
2642 ps_input_cntl = S_028644_OFFSET(0x20);
2643 /* D3D 9 behaviour. GL is undefined */
2644 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2645 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2646 }
2647 return ps_input_cntl;
2648 }
2649
2650 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
2651 {
2652 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2653 struct si_shader *ps = sctx->ps_shader.current;
2654 struct si_shader *vs = si_get_vs_state(sctx);
2655 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2656 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2657
2658 if (!ps || !ps->selector->info.num_inputs)
2659 return;
2660
2661 num_interp = si_get_ps_num_interp(ps);
2662 assert(num_interp > 0);
2663 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
2664
2665 for (i = 0; i < psinfo->num_inputs; i++) {
2666 unsigned name = psinfo->input_semantic_name[i];
2667 unsigned index = psinfo->input_semantic_index[i];
2668 unsigned interpolate = psinfo->input_interpolate[i];
2669
2670 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
2671 interpolate));
2672 num_written++;
2673
2674 if (name == TGSI_SEMANTIC_COLOR) {
2675 assert(index < ARRAY_SIZE(bcol_interp));
2676 bcol_interp[index] = interpolate;
2677 }
2678 }
2679
2680 if (ps->key.part.ps.prolog.color_two_side) {
2681 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2682
2683 for (i = 0; i < 2; i++) {
2684 if (!(psinfo->colors_read & (0xf << (i * 4))))
2685 continue;
2686
2687 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
2688 i, bcol_interp[i]));
2689 num_written++;
2690 }
2691 }
2692 assert(num_interp == num_written);
2693 }
2694
2695 /**
2696 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2697 */
2698 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2699 {
2700 if (sctx->init_config_has_vgt_flush)
2701 return;
2702
2703 /* Done by Vulkan before VGT_FLUSH. */
2704 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2705 si_pm4_cmd_add(sctx->init_config,
2706 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2707 si_pm4_cmd_end(sctx->init_config, false);
2708
2709 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2710 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2711 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2712 si_pm4_cmd_end(sctx->init_config, false);
2713 sctx->init_config_has_vgt_flush = true;
2714 }
2715
2716 /* Initialize state related to ESGS / GSVS ring buffers */
2717 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2718 {
2719 struct si_shader_selector *es =
2720 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2721 struct si_shader_selector *gs = sctx->gs_shader.cso;
2722 struct si_pm4_state *pm4;
2723
2724 /* Chip constants. */
2725 unsigned num_se = sctx->screen->info.max_se;
2726 unsigned wave_size = 64;
2727 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2728 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2729 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2730 */
2731 unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se;
2732 unsigned alignment = 256 * num_se;
2733 /* The maximum size is 63.999 MB per SE. */
2734 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2735
2736 /* Calculate the minimum size. */
2737 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2738 wave_size, alignment);
2739
2740 /* These are recommended sizes, not minimum sizes. */
2741 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2742 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2743 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2744 gs->max_gsvs_emit_size;
2745
2746 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2747 esgs_ring_size = align(esgs_ring_size, alignment);
2748 gsvs_ring_size = align(gsvs_ring_size, alignment);
2749
2750 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2751 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2752
2753 /* Some rings don't have to be allocated if shaders don't use them.
2754 * (e.g. no varyings between ES and GS or GS and VS)
2755 *
2756 * GFX9 doesn't have the ESGS ring.
2757 */
2758 bool update_esgs = sctx->b.chip_class <= VI &&
2759 esgs_ring_size &&
2760 (!sctx->esgs_ring ||
2761 sctx->esgs_ring->width0 < esgs_ring_size);
2762 bool update_gsvs = gsvs_ring_size &&
2763 (!sctx->gsvs_ring ||
2764 sctx->gsvs_ring->width0 < gsvs_ring_size);
2765
2766 if (!update_esgs && !update_gsvs)
2767 return true;
2768
2769 if (update_esgs) {
2770 pipe_resource_reference(&sctx->esgs_ring, NULL);
2771 sctx->esgs_ring =
2772 si_aligned_buffer_create(sctx->b.b.screen,
2773 R600_RESOURCE_FLAG_UNMAPPABLE,
2774 PIPE_USAGE_DEFAULT,
2775 esgs_ring_size, alignment);
2776 if (!sctx->esgs_ring)
2777 return false;
2778 }
2779
2780 if (update_gsvs) {
2781 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2782 sctx->gsvs_ring =
2783 si_aligned_buffer_create(sctx->b.b.screen,
2784 R600_RESOURCE_FLAG_UNMAPPABLE,
2785 PIPE_USAGE_DEFAULT,
2786 gsvs_ring_size, alignment);
2787 if (!sctx->gsvs_ring)
2788 return false;
2789 }
2790
2791 /* Create the "init_config_gs_rings" state. */
2792 pm4 = CALLOC_STRUCT(si_pm4_state);
2793 if (!pm4)
2794 return false;
2795
2796 if (sctx->b.chip_class >= CIK) {
2797 if (sctx->esgs_ring) {
2798 assert(sctx->b.chip_class <= VI);
2799 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2800 sctx->esgs_ring->width0 / 256);
2801 }
2802 if (sctx->gsvs_ring)
2803 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2804 sctx->gsvs_ring->width0 / 256);
2805 } else {
2806 if (sctx->esgs_ring)
2807 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2808 sctx->esgs_ring->width0 / 256);
2809 if (sctx->gsvs_ring)
2810 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2811 sctx->gsvs_ring->width0 / 256);
2812 }
2813
2814 /* Set the state. */
2815 if (sctx->init_config_gs_rings)
2816 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2817 sctx->init_config_gs_rings = pm4;
2818
2819 if (!sctx->init_config_has_vgt_flush) {
2820 si_init_config_add_vgt_flush(sctx);
2821 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2822 }
2823
2824 /* Flush the context to re-emit both init_config states. */
2825 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2826 si_context_gfx_flush(sctx, PIPE_FLUSH_ASYNC, NULL);
2827
2828 /* Set ring bindings. */
2829 if (sctx->esgs_ring) {
2830 assert(sctx->b.chip_class <= VI);
2831 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
2832 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2833 true, true, 4, 64, 0);
2834 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
2835 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2836 false, false, 0, 0, 0);
2837 }
2838 if (sctx->gsvs_ring) {
2839 si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
2840 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2841 false, false, 0, 0, 0);
2842 }
2843
2844 return true;
2845 }
2846
2847 static void si_shader_lock(struct si_shader *shader)
2848 {
2849 mtx_lock(&shader->selector->mutex);
2850 if (shader->previous_stage_sel) {
2851 assert(shader->previous_stage_sel != shader->selector);
2852 mtx_lock(&shader->previous_stage_sel->mutex);
2853 }
2854 }
2855
2856 static void si_shader_unlock(struct si_shader *shader)
2857 {
2858 if (shader->previous_stage_sel)
2859 mtx_unlock(&shader->previous_stage_sel->mutex);
2860 mtx_unlock(&shader->selector->mutex);
2861 }
2862
2863 /**
2864 * @returns 1 if \p sel has been updated to use a new scratch buffer
2865 * 0 if not
2866 * < 0 if there was a failure
2867 */
2868 static int si_update_scratch_buffer(struct si_context *sctx,
2869 struct si_shader *shader)
2870 {
2871 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2872 int r;
2873
2874 if (!shader)
2875 return 0;
2876
2877 /* This shader doesn't need a scratch buffer */
2878 if (shader->config.scratch_bytes_per_wave == 0)
2879 return 0;
2880
2881 /* Prevent race conditions when updating:
2882 * - si_shader::scratch_bo
2883 * - si_shader::binary::code
2884 * - si_shader::previous_stage::binary::code.
2885 */
2886 si_shader_lock(shader);
2887
2888 /* This shader is already configured to use the current
2889 * scratch buffer. */
2890 if (shader->scratch_bo == sctx->scratch_buffer) {
2891 si_shader_unlock(shader);
2892 return 0;
2893 }
2894
2895 assert(sctx->scratch_buffer);
2896
2897 if (shader->previous_stage)
2898 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
2899
2900 si_shader_apply_scratch_relocs(shader, scratch_va);
2901
2902 /* Replace the shader bo with a new bo that has the relocs applied. */
2903 r = si_shader_binary_upload(sctx->screen, shader);
2904 if (r) {
2905 si_shader_unlock(shader);
2906 return r;
2907 }
2908
2909 /* Update the shader state to use the new shader bo. */
2910 si_shader_init_pm4_state(sctx->screen, shader);
2911
2912 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2913
2914 si_shader_unlock(shader);
2915 return 1;
2916 }
2917
2918 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2919 {
2920 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2921 }
2922
2923 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2924 {
2925 return shader ? shader->config.scratch_bytes_per_wave : 0;
2926 }
2927
2928 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
2929 {
2930 if (!sctx->tes_shader.cso)
2931 return NULL; /* tessellation disabled */
2932
2933 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
2934 sctx->fixed_func_tcs_shader.current;
2935 }
2936
2937 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2938 {
2939 unsigned bytes = 0;
2940
2941 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2942 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2943 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2944 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2945
2946 if (sctx->tes_shader.cso) {
2947 struct si_shader *tcs = si_get_tcs_current(sctx);
2948
2949 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
2950 }
2951 return bytes;
2952 }
2953
2954 static bool si_update_scratch_relocs(struct si_context *sctx)
2955 {
2956 struct si_shader *tcs = si_get_tcs_current(sctx);
2957 int r;
2958
2959 /* Update the shaders, so that they are using the latest scratch.
2960 * The scratch buffer may have been changed since these shaders were
2961 * last used, so we still need to try to update them, even if they
2962 * require scratch buffers smaller than the current size.
2963 */
2964 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2965 if (r < 0)
2966 return false;
2967 if (r == 1)
2968 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2969
2970 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2971 if (r < 0)
2972 return false;
2973 if (r == 1)
2974 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2975
2976 r = si_update_scratch_buffer(sctx, tcs);
2977 if (r < 0)
2978 return false;
2979 if (r == 1)
2980 si_pm4_bind_state(sctx, hs, tcs->pm4);
2981
2982 /* VS can be bound as LS, ES, or VS. */
2983 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2984 if (r < 0)
2985 return false;
2986 if (r == 1) {
2987 if (sctx->tes_shader.current)
2988 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2989 else if (sctx->gs_shader.current)
2990 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2991 else
2992 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2993 }
2994
2995 /* TES can be bound as ES or VS. */
2996 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2997 if (r < 0)
2998 return false;
2999 if (r == 1) {
3000 if (sctx->gs_shader.current)
3001 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3002 else
3003 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3004 }
3005
3006 return true;
3007 }
3008
3009 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3010 {
3011 unsigned current_scratch_buffer_size =
3012 si_get_current_scratch_buffer_size(sctx);
3013 unsigned scratch_bytes_per_wave =
3014 si_get_max_scratch_bytes_per_wave(sctx);
3015 unsigned scratch_needed_size = scratch_bytes_per_wave *
3016 sctx->scratch_waves;
3017 unsigned spi_tmpring_size;
3018
3019 if (scratch_needed_size > 0) {
3020 if (scratch_needed_size > current_scratch_buffer_size) {
3021 /* Create a bigger scratch buffer */
3022 r600_resource_reference(&sctx->scratch_buffer, NULL);
3023
3024 sctx->scratch_buffer = (struct r600_resource*)
3025 si_aligned_buffer_create(&sctx->screen->b,
3026 R600_RESOURCE_FLAG_UNMAPPABLE,
3027 PIPE_USAGE_DEFAULT,
3028 scratch_needed_size, 256);
3029 if (!sctx->scratch_buffer)
3030 return false;
3031
3032 si_mark_atom_dirty(sctx, &sctx->scratch_state);
3033 si_context_add_resource_size(&sctx->b.b,
3034 &sctx->scratch_buffer->b.b);
3035 }
3036
3037 if (!si_update_scratch_relocs(sctx))
3038 return false;
3039 }
3040
3041 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3042 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3043 "scratch size should already be aligned correctly.");
3044
3045 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3046 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3047 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3048 sctx->spi_tmpring_size = spi_tmpring_size;
3049 si_mark_atom_dirty(sctx, &sctx->scratch_state);
3050 }
3051 return true;
3052 }
3053
3054 static void si_init_tess_factor_ring(struct si_context *sctx)
3055 {
3056 bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
3057 sctx->b.family != CHIP_CARRIZO &&
3058 sctx->b.family != CHIP_STONEY;
3059 /* This must be one less than the maximum number due to a hw limitation.
3060 * Various hardware bugs in SI, CIK, and GFX9 need this.
3061 */
3062 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
3063 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
3064 sctx->screen->info.max_se;
3065 unsigned offchip_granularity;
3066
3067 switch (sctx->screen->tess_offchip_block_dw_size) {
3068 default:
3069 assert(0);
3070 /* fall through */
3071 case 8192:
3072 offchip_granularity = V_03093C_X_8K_DWORDS;
3073 break;
3074 case 4096:
3075 offchip_granularity = V_03093C_X_4K_DWORDS;
3076 break;
3077 }
3078
3079 assert(!sctx->tf_ring);
3080 /* Use 64K alignment for both rings, so that we can pass the address
3081 * to shaders as one SGPR containing bits [16:47].
3082 */
3083 sctx->tf_ring = si_aligned_buffer_create(sctx->b.b.screen,
3084 R600_RESOURCE_FLAG_UNMAPPABLE,
3085 PIPE_USAGE_DEFAULT,
3086 32768 * sctx->screen->info.max_se,
3087 64 * 1024);
3088 if (!sctx->tf_ring)
3089 return;
3090
3091 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
3092
3093 sctx->tess_offchip_ring =
3094 si_aligned_buffer_create(sctx->b.b.screen,
3095 R600_RESOURCE_FLAG_UNMAPPABLE,
3096 PIPE_USAGE_DEFAULT,
3097 max_offchip_buffers *
3098 sctx->screen->tess_offchip_block_dw_size * 4,
3099 64 * 1024);
3100 if (!sctx->tess_offchip_ring)
3101 return;
3102
3103 si_init_config_add_vgt_flush(sctx);
3104
3105 uint64_t offchip_va = r600_resource(sctx->tess_offchip_ring)->gpu_address;
3106 uint64_t factor_va = r600_resource(sctx->tf_ring)->gpu_address;
3107 assert((offchip_va & 0xffff) == 0);
3108 assert((factor_va & 0xffff) == 0);
3109
3110 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_offchip_ring),
3111 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3112 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tf_ring),
3113 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3114
3115 /* Append these registers to the init config state. */
3116 if (sctx->b.chip_class >= CIK) {
3117 if (sctx->b.chip_class >= VI)
3118 --max_offchip_buffers;
3119
3120 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3121 S_030938_SIZE(sctx->tf_ring->width0 / 4));
3122 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3123 factor_va >> 8);
3124 if (sctx->b.chip_class >= GFX9)
3125 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3126 factor_va >> 40);
3127 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3128 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3129 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
3130 } else {
3131 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
3132 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3133 S_008988_SIZE(sctx->tf_ring->width0 / 4));
3134 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3135 factor_va >> 8);
3136 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3137 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
3138 }
3139
3140 if (sctx->b.chip_class >= GFX9) {
3141 si_pm4_set_reg(sctx->init_config,
3142 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
3143 GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
3144 offchip_va >> 16);
3145 si_pm4_set_reg(sctx->init_config,
3146 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
3147 GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
3148 factor_va >> 16);
3149 } else {
3150 si_pm4_set_reg(sctx->init_config,
3151 R_00B430_SPI_SHADER_USER_DATA_HS_0 +
3152 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
3153 offchip_va >> 16);
3154 si_pm4_set_reg(sctx->init_config,
3155 R_00B430_SPI_SHADER_USER_DATA_HS_0 +
3156 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
3157 factor_va >> 16);
3158 }
3159
3160 /* Flush the context to re-emit the init_config state.
3161 * This is done only once in a lifetime of a context.
3162 */
3163 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3164 sctx->b.initial_gfx_cs_size = 0; /* force flush */
3165 si_context_gfx_flush(sctx, PIPE_FLUSH_ASYNC, NULL);
3166 }
3167
3168 /**
3169 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
3170 * VS passes its outputs to TES directly, so the fixed-function shader only
3171 * has to write TESSOUTER and TESSINNER.
3172 */
3173 static void si_generate_fixed_func_tcs(struct si_context *sctx)
3174 {
3175 struct ureg_src outer, inner;
3176 struct ureg_dst tessouter, tessinner;
3177 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
3178
3179 if (!ureg)
3180 return; /* if we get here, we're screwed */
3181
3182 assert(!sctx->fixed_func_tcs_shader.cso);
3183
3184 outer = ureg_DECL_system_value(ureg,
3185 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
3186 inner = ureg_DECL_system_value(ureg,
3187 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
3188
3189 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
3190 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
3191
3192 ureg_MOV(ureg, tessouter, outer);
3193 ureg_MOV(ureg, tessinner, inner);
3194 ureg_END(ureg);
3195
3196 sctx->fixed_func_tcs_shader.cso =
3197 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
3198 }
3199
3200 static void si_update_vgt_shader_config(struct si_context *sctx)
3201 {
3202 /* Calculate the index of the config.
3203 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3204 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
3205 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
3206
3207 if (!*pm4) {
3208 uint32_t stages = 0;
3209
3210 *pm4 = CALLOC_STRUCT(si_pm4_state);
3211
3212 if (sctx->tes_shader.cso) {
3213 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3214 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3215
3216 if (sctx->gs_shader.cso)
3217 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3218 S_028B54_GS_EN(1) |
3219 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3220 else
3221 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3222 } else if (sctx->gs_shader.cso) {
3223 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3224 S_028B54_GS_EN(1) |
3225 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3226 }
3227
3228 if (sctx->b.chip_class >= GFX9)
3229 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3230
3231 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3232 }
3233 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3234 }
3235
3236 bool si_update_shaders(struct si_context *sctx)
3237 {
3238 struct pipe_context *ctx = (struct pipe_context*)sctx;
3239 struct si_compiler_ctx_state compiler_state;
3240 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3241 struct si_shader *old_vs = si_get_vs_state(sctx);
3242 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3243 struct si_shader *old_ps = sctx->ps_shader.current;
3244 unsigned old_spi_shader_col_format =
3245 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3246 int r;
3247
3248 compiler_state.tm = sctx->tm;
3249 compiler_state.debug = sctx->debug;
3250 compiler_state.is_debug_context = sctx->is_debug;
3251
3252 /* Update stages before GS. */
3253 if (sctx->tes_shader.cso) {
3254 if (!sctx->tf_ring) {
3255 si_init_tess_factor_ring(sctx);
3256 if (!sctx->tf_ring)
3257 return false;
3258 }
3259
3260 /* VS as LS */
3261 if (sctx->b.chip_class <= VI) {
3262 r = si_shader_select(ctx, &sctx->vs_shader,
3263 &compiler_state);
3264 if (r)
3265 return false;
3266 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3267 }
3268
3269 if (sctx->tcs_shader.cso) {
3270 r = si_shader_select(ctx, &sctx->tcs_shader,
3271 &compiler_state);
3272 if (r)
3273 return false;
3274 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3275 } else {
3276 if (!sctx->fixed_func_tcs_shader.cso) {
3277 si_generate_fixed_func_tcs(sctx);
3278 if (!sctx->fixed_func_tcs_shader.cso)
3279 return false;
3280 }
3281
3282 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3283 &compiler_state);
3284 if (r)
3285 return false;
3286 si_pm4_bind_state(sctx, hs,
3287 sctx->fixed_func_tcs_shader.current->pm4);
3288 }
3289
3290 if (sctx->gs_shader.cso) {
3291 /* TES as ES */
3292 if (sctx->b.chip_class <= VI) {
3293 r = si_shader_select(ctx, &sctx->tes_shader,
3294 &compiler_state);
3295 if (r)
3296 return false;
3297 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3298 }
3299 } else {
3300 /* TES as VS */
3301 r = si_shader_select(ctx, &sctx->tes_shader,
3302 &compiler_state);
3303 if (r)
3304 return false;
3305 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3306 }
3307 } else if (sctx->gs_shader.cso) {
3308 if (sctx->b.chip_class <= VI) {
3309 /* VS as ES */
3310 r = si_shader_select(ctx, &sctx->vs_shader,
3311 &compiler_state);
3312 if (r)
3313 return false;
3314 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3315
3316 si_pm4_bind_state(sctx, ls, NULL);
3317 si_pm4_bind_state(sctx, hs, NULL);
3318 }
3319 } else {
3320 /* VS as VS */
3321 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3322 if (r)
3323 return false;
3324 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3325 si_pm4_bind_state(sctx, ls, NULL);
3326 si_pm4_bind_state(sctx, hs, NULL);
3327 }
3328
3329 /* Update GS. */
3330 if (sctx->gs_shader.cso) {
3331 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3332 if (r)
3333 return false;
3334 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3335 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3336
3337 if (!si_update_gs_ring_buffers(sctx))
3338 return false;
3339 } else {
3340 si_pm4_bind_state(sctx, gs, NULL);
3341 if (sctx->b.chip_class <= VI)
3342 si_pm4_bind_state(sctx, es, NULL);
3343 }
3344
3345 si_update_vgt_shader_config(sctx);
3346
3347 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3348 si_mark_atom_dirty(sctx, &sctx->clip_regs);
3349
3350 if (sctx->ps_shader.cso) {
3351 unsigned db_shader_control;
3352
3353 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3354 if (r)
3355 return false;
3356 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3357
3358 db_shader_control =
3359 sctx->ps_shader.cso->db_shader_control |
3360 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3361
3362 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3363 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3364 sctx->flatshade != rs->flatshade) {
3365 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3366 sctx->flatshade = rs->flatshade;
3367 si_mark_atom_dirty(sctx, &sctx->spi_map);
3368 }
3369
3370 if (sctx->screen->rbplus_allowed &&
3371 si_pm4_state_changed(sctx, ps) &&
3372 (!old_ps ||
3373 old_spi_shader_col_format !=
3374 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3375 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
3376
3377 if (sctx->ps_db_shader_control != db_shader_control) {
3378 sctx->ps_db_shader_control = db_shader_control;
3379 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3380 if (sctx->screen->dpbb_allowed)
3381 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
3382 }
3383
3384 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3385 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3386 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3387
3388 if (sctx->b.chip_class == SI)
3389 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3390
3391 if (sctx->framebuffer.nr_samples <= 1)
3392 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
3393 }
3394 }
3395
3396 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3397 si_pm4_state_enabled_and_changed(sctx, hs) ||
3398 si_pm4_state_enabled_and_changed(sctx, es) ||
3399 si_pm4_state_enabled_and_changed(sctx, gs) ||
3400 si_pm4_state_enabled_and_changed(sctx, vs) ||
3401 si_pm4_state_enabled_and_changed(sctx, ps)) {
3402 if (!si_update_spi_tmpring_size(sctx))
3403 return false;
3404 }
3405
3406 if (sctx->b.chip_class >= CIK) {
3407 if (si_pm4_state_enabled_and_changed(sctx, ls))
3408 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3409 else if (!sctx->queued.named.ls)
3410 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3411
3412 if (si_pm4_state_enabled_and_changed(sctx, hs))
3413 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3414 else if (!sctx->queued.named.hs)
3415 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3416
3417 if (si_pm4_state_enabled_and_changed(sctx, es))
3418 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3419 else if (!sctx->queued.named.es)
3420 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3421
3422 if (si_pm4_state_enabled_and_changed(sctx, gs))
3423 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3424 else if (!sctx->queued.named.gs)
3425 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3426
3427 if (si_pm4_state_enabled_and_changed(sctx, vs))
3428 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3429 else if (!sctx->queued.named.vs)
3430 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3431
3432 if (si_pm4_state_enabled_and_changed(sctx, ps))
3433 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3434 else if (!sctx->queued.named.ps)
3435 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3436 }
3437
3438 sctx->do_update_shaders = false;
3439 return true;
3440 }
3441
3442 static void si_emit_scratch_state(struct si_context *sctx,
3443 struct r600_atom *atom)
3444 {
3445 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3446
3447 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3448 sctx->spi_tmpring_size);
3449
3450 if (sctx->scratch_buffer) {
3451 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
3452 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3453 RADEON_PRIO_SCRATCH_BUFFER);
3454 }
3455 }
3456
3457 void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type,
3458 unsigned num_layers)
3459 {
3460 struct pipe_context *pipe = &sctx->b.b;
3461 unsigned vs_blit_property;
3462 void **vs;
3463
3464 switch (type) {
3465 case UTIL_BLITTER_ATTRIB_NONE:
3466 vs = num_layers > 1 ? &sctx->vs_blit_pos_layered :
3467 &sctx->vs_blit_pos;
3468 vs_blit_property = SI_VS_BLIT_SGPRS_POS;
3469 break;
3470 case UTIL_BLITTER_ATTRIB_COLOR:
3471 vs = num_layers > 1 ? &sctx->vs_blit_color_layered :
3472 &sctx->vs_blit_color;
3473 vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR;
3474 break;
3475 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
3476 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
3477 assert(num_layers == 1);
3478 vs = &sctx->vs_blit_texcoord;
3479 vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD;
3480 break;
3481 default:
3482 assert(0);
3483 return NULL;
3484 }
3485 if (*vs)
3486 return *vs;
3487
3488 struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX);
3489 if (!ureg)
3490 return NULL;
3491
3492 /* Tell the shader to load VS inputs from SGPRs: */
3493 ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS, vs_blit_property);
3494 ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true);
3495
3496 /* This is just a pass-through shader with 1-3 MOV instructions. */
3497 ureg_MOV(ureg,
3498 ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0),
3499 ureg_DECL_vs_input(ureg, 0));
3500
3501 if (type != UTIL_BLITTER_ATTRIB_NONE) {
3502 ureg_MOV(ureg,
3503 ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0),
3504 ureg_DECL_vs_input(ureg, 1));
3505 }
3506
3507 if (num_layers > 1) {
3508 struct ureg_src instance_id =
3509 ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0);
3510 struct ureg_dst layer =
3511 ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
3512
3513 ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X),
3514 ureg_scalar(instance_id, TGSI_SWIZZLE_X));
3515 }
3516 ureg_END(ureg);
3517
3518 *vs = ureg_create_shader_and_destroy(ureg, pipe);
3519 return *vs;
3520 }
3521
3522 void si_init_shader_functions(struct si_context *sctx)
3523 {
3524 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
3525 si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
3526 si_emit_scratch_state);
3527
3528 sctx->b.b.create_vs_state = si_create_shader_selector;
3529 sctx->b.b.create_tcs_state = si_create_shader_selector;
3530 sctx->b.b.create_tes_state = si_create_shader_selector;
3531 sctx->b.b.create_gs_state = si_create_shader_selector;
3532 sctx->b.b.create_fs_state = si_create_shader_selector;
3533
3534 sctx->b.b.bind_vs_state = si_bind_vs_shader;
3535 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
3536 sctx->b.b.bind_tes_state = si_bind_tes_shader;
3537 sctx->b.b.bind_gs_state = si_bind_gs_shader;
3538 sctx->b.b.bind_fs_state = si_bind_ps_shader;
3539
3540 sctx->b.b.delete_vs_state = si_delete_shader_selector;
3541 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
3542 sctx->b.b.delete_tes_state = si_delete_shader_selector;
3543 sctx->b.b.delete_gs_state = si_delete_shader_selector;
3544 sctx->b.b.delete_fs_state = si_delete_shader_selector;
3545 }