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gallium/radeon: eliminate fast color clear before sharing
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/u_hash.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
39 #include "util/u_simple_shaders.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
45 * integer.
46 */
47 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
48 {
49 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
50 sizeof(struct tgsi_token);
51 unsigned size = 4 + tgsi_size + sizeof(sel->so);
52 char *result = (char*)MALLOC(size);
53
54 if (!result)
55 return NULL;
56
57 *((uint32_t*)result) = size;
58 memcpy(result + 4, sel->tokens, tgsi_size);
59 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
60 return result;
61 }
62
63 /** Copy "data" to "ptr" and return the next dword following copied data. */
64 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
65 {
66 memcpy(ptr, data, size);
67 ptr += DIV_ROUND_UP(size, 4);
68 return ptr;
69 }
70
71 /** Read data from "ptr". Return the next dword following the data. */
72 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
73 {
74 memcpy(data, ptr, size);
75 ptr += DIV_ROUND_UP(size, 4);
76 return ptr;
77 }
78
79 /**
80 * Write the size as uint followed by the data. Return the next dword
81 * following the copied data.
82 */
83 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
84 {
85 *ptr++ = size;
86 return write_data(ptr, data, size);
87 }
88
89 /**
90 * Read the size as uint followed by the data. Return both via parameters.
91 * Return the next dword following the data.
92 */
93 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
94 {
95 *size = *ptr++;
96 assert(*data == NULL);
97 *data = malloc(*size);
98 return read_data(ptr, *data, *size);
99 }
100
101 /**
102 * Return the shader binary in a buffer. The first 4 bytes contain its size
103 * as integer.
104 */
105 static void *si_get_shader_binary(struct si_shader *shader)
106 {
107 /* There is always a size of data followed by the data itself. */
108 unsigned relocs_size = shader->binary.reloc_count *
109 sizeof(shader->binary.relocs[0]);
110 unsigned disasm_size = strlen(shader->binary.disasm_string) + 1;
111 unsigned size =
112 4 + /* total size */
113 4 + /* CRC32 of the data below */
114 align(sizeof(shader->config), 4) +
115 align(sizeof(shader->info), 4) +
116 4 + align(shader->binary.code_size, 4) +
117 4 + align(shader->binary.rodata_size, 4) +
118 4 + align(relocs_size, 4) +
119 4 + align(disasm_size, 4);
120 void *buffer = CALLOC(1, size);
121 uint32_t *ptr = (uint32_t*)buffer;
122
123 if (!buffer)
124 return NULL;
125
126 *ptr++ = size;
127 ptr++; /* CRC32 is calculated at the end. */
128
129 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
130 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
131 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
132 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
133 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
134 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
135 assert((char *)ptr - (char *)buffer == size);
136
137 /* Compute CRC32. */
138 ptr = (uint32_t*)buffer;
139 ptr++;
140 *ptr = util_hash_crc32(ptr + 1, size - 8);
141
142 return buffer;
143 }
144
145 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
146 {
147 uint32_t *ptr = (uint32_t*)binary;
148 uint32_t size = *ptr++;
149 uint32_t crc32 = *ptr++;
150 unsigned chunk_size;
151
152 if (util_hash_crc32(ptr, size - 8) != crc32) {
153 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
154 return false;
155 }
156
157 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
158 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
159 ptr = read_chunk(ptr, (void**)&shader->binary.code,
160 &shader->binary.code_size);
161 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
162 &shader->binary.rodata_size);
163 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
164 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
165 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
166
167 return true;
168 }
169
170 /**
171 * Insert a shader into the cache. It's assumed the shader is not in the cache.
172 * Use si_shader_cache_load_shader before calling this.
173 *
174 * Returns false on failure, in which case the tgsi_binary should be freed.
175 */
176 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
177 void *tgsi_binary,
178 struct si_shader *shader)
179 {
180 void *hw_binary = si_get_shader_binary(shader);
181
182 if (!hw_binary)
183 return false;
184
185 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
186 hw_binary) == NULL) {
187 FREE(hw_binary);
188 return false;
189 }
190
191 return true;
192 }
193
194 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
195 void *tgsi_binary,
196 struct si_shader *shader)
197 {
198 struct hash_entry *entry =
199 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
200 if (!entry)
201 return false;
202
203 return si_load_shader_binary(shader, entry->data);
204 }
205
206 static uint32_t si_shader_cache_key_hash(const void *key)
207 {
208 /* The first dword is the key size. */
209 return util_hash_crc32(key, *(uint32_t*)key);
210 }
211
212 static bool si_shader_cache_key_equals(const void *a, const void *b)
213 {
214 uint32_t *keya = (uint32_t*)a;
215 uint32_t *keyb = (uint32_t*)b;
216
217 /* The first dword is the key size. */
218 if (*keya != *keyb)
219 return false;
220
221 return memcmp(keya, keyb, *keya) == 0;
222 }
223
224 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
225 {
226 FREE((void*)entry->key);
227 FREE(entry->data);
228 }
229
230 bool si_init_shader_cache(struct si_screen *sscreen)
231 {
232 pipe_mutex_init(sscreen->shader_cache_mutex);
233 sscreen->shader_cache =
234 _mesa_hash_table_create(NULL,
235 si_shader_cache_key_hash,
236 si_shader_cache_key_equals);
237 return sscreen->shader_cache != NULL;
238 }
239
240 void si_destroy_shader_cache(struct si_screen *sscreen)
241 {
242 if (sscreen->shader_cache)
243 _mesa_hash_table_destroy(sscreen->shader_cache,
244 si_destroy_shader_cache_entry);
245 pipe_mutex_destroy(sscreen->shader_cache_mutex);
246 }
247
248 /* SHADER STATES */
249
250 static void si_set_tesseval_regs(struct si_shader *shader,
251 struct si_pm4_state *pm4)
252 {
253 struct tgsi_shader_info *info = &shader->selector->info;
254 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
255 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
256 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
257 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
258 unsigned type, partitioning, topology;
259
260 switch (tes_prim_mode) {
261 case PIPE_PRIM_LINES:
262 type = V_028B6C_TESS_ISOLINE;
263 break;
264 case PIPE_PRIM_TRIANGLES:
265 type = V_028B6C_TESS_TRIANGLE;
266 break;
267 case PIPE_PRIM_QUADS:
268 type = V_028B6C_TESS_QUAD;
269 break;
270 default:
271 assert(0);
272 return;
273 }
274
275 switch (tes_spacing) {
276 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
277 partitioning = V_028B6C_PART_FRAC_ODD;
278 break;
279 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
280 partitioning = V_028B6C_PART_FRAC_EVEN;
281 break;
282 case PIPE_TESS_SPACING_EQUAL:
283 partitioning = V_028B6C_PART_INTEGER;
284 break;
285 default:
286 assert(0);
287 return;
288 }
289
290 if (tes_point_mode)
291 topology = V_028B6C_OUTPUT_POINT;
292 else if (tes_prim_mode == PIPE_PRIM_LINES)
293 topology = V_028B6C_OUTPUT_LINE;
294 else if (tes_vertex_order_cw)
295 /* for some reason, this must be the other way around */
296 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
297 else
298 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
299
300 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
301 S_028B6C_TYPE(type) |
302 S_028B6C_PARTITIONING(partitioning) |
303 S_028B6C_TOPOLOGY(topology));
304 }
305
306 static void si_shader_ls(struct si_shader *shader)
307 {
308 struct si_pm4_state *pm4;
309 unsigned num_sgprs, num_user_sgprs;
310 unsigned vgpr_comp_cnt;
311 uint64_t va;
312
313 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
314 if (!pm4)
315 return;
316
317 va = shader->bo->gpu_address;
318 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
319
320 /* We need at least 2 components for LS.
321 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
322 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 1;
323
324 num_user_sgprs = SI_LS_NUM_USER_SGPR;
325 num_sgprs = shader->config.num_sgprs;
326 if (num_user_sgprs > num_sgprs) {
327 /* Last 2 reserved SGPRs are used for VCC */
328 num_sgprs = num_user_sgprs + 2;
329 }
330 assert(num_sgprs <= 104);
331
332 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
333 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
334
335 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
336 S_00B528_SGPRS((num_sgprs - 1) / 8) |
337 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
338 S_00B528_DX10_CLAMP(1) |
339 S_00B528_FLOAT_MODE(shader->config.float_mode);
340 shader->config.rsrc2 = S_00B52C_USER_SGPR(num_user_sgprs) |
341 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
342 }
343
344 static void si_shader_hs(struct si_shader *shader)
345 {
346 struct si_pm4_state *pm4;
347 unsigned num_sgprs, num_user_sgprs;
348 uint64_t va;
349
350 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
351 if (!pm4)
352 return;
353
354 va = shader->bo->gpu_address;
355 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
356
357 num_user_sgprs = SI_TCS_NUM_USER_SGPR;
358 num_sgprs = shader->config.num_sgprs;
359 /* One SGPR after user SGPRs is pre-loaded with tessellation factor
360 * buffer offset. */
361 if ((num_user_sgprs + 1) > num_sgprs) {
362 /* Last 2 reserved SGPRs are used for VCC */
363 num_sgprs = num_user_sgprs + 1 + 2;
364 }
365 assert(num_sgprs <= 104);
366
367 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
368 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
369 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
370 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
371 S_00B428_SGPRS((num_sgprs - 1) / 8) |
372 S_00B428_DX10_CLAMP(1) |
373 S_00B428_FLOAT_MODE(shader->config.float_mode));
374 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
375 S_00B42C_USER_SGPR(num_user_sgprs) |
376 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
377 }
378
379 static void si_shader_es(struct si_shader *shader)
380 {
381 struct si_pm4_state *pm4;
382 unsigned num_sgprs, num_user_sgprs;
383 unsigned vgpr_comp_cnt;
384 uint64_t va;
385
386 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
387
388 if (!pm4)
389 return;
390
391 va = shader->bo->gpu_address;
392 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
393
394 if (shader->selector->type == PIPE_SHADER_VERTEX) {
395 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
396 num_user_sgprs = SI_ES_NUM_USER_SGPR;
397 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
398 vgpr_comp_cnt = 3; /* all components are needed for TES */
399 num_user_sgprs = SI_TES_NUM_USER_SGPR;
400 } else
401 unreachable("invalid shader selector type");
402
403 num_sgprs = shader->config.num_sgprs;
404 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
405 if ((num_user_sgprs + 1) > num_sgprs) {
406 /* Last 2 reserved SGPRs are used for VCC */
407 num_sgprs = num_user_sgprs + 1 + 2;
408 }
409 assert(num_sgprs <= 104);
410
411 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
412 shader->selector->esgs_itemsize / 4);
413 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
414 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
415 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
416 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
417 S_00B328_SGPRS((num_sgprs - 1) / 8) |
418 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
419 S_00B328_DX10_CLAMP(1) |
420 S_00B328_FLOAT_MODE(shader->config.float_mode));
421 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
422 S_00B32C_USER_SGPR(num_user_sgprs) |
423 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
424
425 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
426 si_set_tesseval_regs(shader, pm4);
427 }
428
429 /**
430 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
431 * geometry shader.
432 */
433 static uint32_t si_vgt_gs_mode(struct si_shader *shader)
434 {
435 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
436 unsigned cut_mode;
437
438 if (gs_max_vert_out <= 128) {
439 cut_mode = V_028A40_GS_CUT_128;
440 } else if (gs_max_vert_out <= 256) {
441 cut_mode = V_028A40_GS_CUT_256;
442 } else if (gs_max_vert_out <= 512) {
443 cut_mode = V_028A40_GS_CUT_512;
444 } else {
445 assert(gs_max_vert_out <= 1024);
446 cut_mode = V_028A40_GS_CUT_1024;
447 }
448
449 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
450 S_028A40_CUT_MODE(cut_mode)|
451 S_028A40_ES_WRITE_OPTIMIZE(1) |
452 S_028A40_GS_WRITE_OPTIMIZE(1);
453 }
454
455 static void si_shader_gs(struct si_shader *shader)
456 {
457 unsigned gs_vert_itemsize = shader->selector->gsvs_vertex_size;
458 unsigned gsvs_itemsize = shader->selector->max_gsvs_emit_size >> 2;
459 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
460 struct si_pm4_state *pm4;
461 unsigned num_sgprs, num_user_sgprs;
462 uint64_t va;
463 unsigned max_stream = shader->selector->max_gs_stream;
464
465 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
466 assert(gsvs_itemsize < (1 << 15));
467
468 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
469
470 if (!pm4)
471 return;
472
473 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader));
474
475 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
476 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
477 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
478
479 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
480
481 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, shader->selector->gs_max_out_vertices);
482
483 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
484 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
485 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
486 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
487
488 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
489 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
490 S_028B90_ENABLE(gs_num_invocations > 0));
491
492 va = shader->bo->gpu_address;
493 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
494 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
495 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
496
497 num_user_sgprs = SI_GS_NUM_USER_SGPR;
498 num_sgprs = shader->config.num_sgprs;
499 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
500 if ((num_user_sgprs + 2) > num_sgprs) {
501 /* Last 2 reserved SGPRs are used for VCC */
502 num_sgprs = num_user_sgprs + 2 + 2;
503 }
504 assert(num_sgprs <= 104);
505
506 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
507 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
508 S_00B228_SGPRS((num_sgprs - 1) / 8) |
509 S_00B228_DX10_CLAMP(1) |
510 S_00B228_FLOAT_MODE(shader->config.float_mode));
511 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
512 S_00B22C_USER_SGPR(num_user_sgprs) |
513 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
514 }
515
516 /**
517 * Compute the state for \p shader, which will run as a vertex shader on the
518 * hardware.
519 *
520 * If \p gs is non-NULL, it points to the geometry shader for which this shader
521 * is the copy shader.
522 */
523 static void si_shader_vs(struct si_shader *shader, struct si_shader *gs)
524 {
525 struct si_pm4_state *pm4;
526 unsigned num_sgprs, num_user_sgprs;
527 unsigned nparams, vgpr_comp_cnt;
528 uint64_t va;
529 unsigned window_space =
530 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
531 bool enable_prim_id = si_vs_exports_prim_id(shader);
532
533 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
534
535 if (!pm4)
536 return;
537
538 /* We always write VGT_GS_MODE in the VS state, because every switch
539 * between different shader pipelines involving a different GS or no
540 * GS at all involves a switch of the VS (different GS use different
541 * copy shaders). On the other hand, when the API switches from a GS to
542 * no GS and then back to the same GS used originally, the GS state is
543 * not sent again.
544 */
545 if (!gs) {
546 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
547 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
548 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
549 } else {
550 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
551 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
552 }
553
554 va = shader->bo->gpu_address;
555 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
556
557 if (gs) {
558 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
559 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
560 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
561 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
562 num_user_sgprs = SI_VS_NUM_USER_SGPR;
563 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
564 vgpr_comp_cnt = 3; /* all components are needed for TES */
565 num_user_sgprs = SI_TES_NUM_USER_SGPR;
566 } else
567 unreachable("invalid shader selector type");
568
569 num_sgprs = shader->config.num_sgprs;
570 if (num_user_sgprs > num_sgprs) {
571 /* Last 2 reserved SGPRs are used for VCC */
572 num_sgprs = num_user_sgprs + 2;
573 }
574 assert(num_sgprs <= 104);
575
576 /* VS is required to export at least one param. */
577 nparams = MAX2(shader->info.nr_param_exports, 1);
578 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
579 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
580
581 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
582 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
583 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
584 V_02870C_SPI_SHADER_4COMP :
585 V_02870C_SPI_SHADER_NONE) |
586 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
587 V_02870C_SPI_SHADER_4COMP :
588 V_02870C_SPI_SHADER_NONE) |
589 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
590 V_02870C_SPI_SHADER_4COMP :
591 V_02870C_SPI_SHADER_NONE));
592
593 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
594 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
595 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
596 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
597 S_00B128_SGPRS((num_sgprs - 1) / 8) |
598 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
599 S_00B128_DX10_CLAMP(1) |
600 S_00B128_FLOAT_MODE(shader->config.float_mode));
601 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
602 S_00B12C_USER_SGPR(num_user_sgprs) |
603 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
604 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
605 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
606 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
607 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
608 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
609 if (window_space)
610 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
611 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
612 else
613 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
614 S_028818_VTX_W0_FMT(1) |
615 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
616 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
617 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
618
619 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
620 si_set_tesseval_regs(shader, pm4);
621 }
622
623 static unsigned si_get_ps_num_interp(struct si_shader *ps)
624 {
625 struct tgsi_shader_info *info = &ps->selector->info;
626 unsigned num_colors = !!(info->colors_read & 0x0f) +
627 !!(info->colors_read & 0xf0);
628 unsigned num_interp = ps->selector->info.num_inputs +
629 (ps->key.ps.prolog.color_two_side ? num_colors : 0);
630
631 assert(num_interp <= 32);
632 return MIN2(num_interp, 32);
633 }
634
635 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
636 {
637 unsigned value = shader->key.ps.epilog.spi_shader_col_format;
638 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
639
640 /* If the i-th target format is set, all previous target formats must
641 * be non-zero to avoid hangs.
642 */
643 for (i = 0; i < num_targets; i++)
644 if (!(value & (0xf << (i * 4))))
645 value |= V_028714_SPI_SHADER_32_R << (i * 4);
646
647 return value;
648 }
649
650 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
651 {
652 unsigned i, cb_shader_mask = 0;
653
654 for (i = 0; i < 8; i++) {
655 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
656 case V_028714_SPI_SHADER_ZERO:
657 break;
658 case V_028714_SPI_SHADER_32_R:
659 cb_shader_mask |= 0x1 << (i * 4);
660 break;
661 case V_028714_SPI_SHADER_32_GR:
662 cb_shader_mask |= 0x3 << (i * 4);
663 break;
664 case V_028714_SPI_SHADER_32_AR:
665 cb_shader_mask |= 0x9 << (i * 4);
666 break;
667 case V_028714_SPI_SHADER_FP16_ABGR:
668 case V_028714_SPI_SHADER_UNORM16_ABGR:
669 case V_028714_SPI_SHADER_SNORM16_ABGR:
670 case V_028714_SPI_SHADER_UINT16_ABGR:
671 case V_028714_SPI_SHADER_SINT16_ABGR:
672 case V_028714_SPI_SHADER_32_ABGR:
673 cb_shader_mask |= 0xf << (i * 4);
674 break;
675 default:
676 assert(0);
677 }
678 }
679 return cb_shader_mask;
680 }
681
682 static void si_shader_ps(struct si_shader *shader)
683 {
684 struct tgsi_shader_info *info = &shader->selector->info;
685 struct si_pm4_state *pm4;
686 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
687 unsigned num_sgprs, num_user_sgprs;
688 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
689 uint64_t va;
690 bool has_centroid;
691 unsigned input_ena = shader->config.spi_ps_input_ena;
692
693 /* we need to enable at least one of them, otherwise we hang the GPU */
694 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
695 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
696 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
697 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
698 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
699 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
700 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
701 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
702
703 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
704
705 if (!pm4)
706 return;
707
708 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
709 * Possible vaules:
710 * 0 -> Position = pixel center
711 * 1 -> Position = pixel centroid
712 * 2 -> Position = at sample position
713 *
714 * From GLSL 4.5 specification, section 7.1:
715 * "The variable gl_FragCoord is available as an input variable from
716 * within fragment shaders and it holds the window relative coordinates
717 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
718 * value can be for any location within the pixel, or one of the
719 * fragment samples. The use of centroid does not further restrict
720 * this value to be inside the current primitive."
721 *
722 * Meaning that centroid has no effect and we can return anything within
723 * the pixel. Thus, return the value at sample position, because that's
724 * the most accurate one shaders can get.
725 */
726 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
727
728 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
729 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
730 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
731
732 spi_shader_col_format = si_get_spi_shader_col_format(shader);
733 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
734
735 /* This must be non-zero for alpha-test/kill to work.
736 * The hardware ignores the EXEC mask if no export memory is allocated.
737 * Don't add this to CB_SHADER_MASK.
738 */
739 if (!spi_shader_col_format &&
740 !info->writes_z && !info->writes_stencil && !info->writes_samplemask &&
741 (shader->selector->info.uses_kill ||
742 shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS))
743 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
744
745 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
746 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
747 shader->config.spi_ps_input_addr);
748
749 /* Set interpolation controls. */
750 has_centroid = G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena) ||
751 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena);
752
753 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
754 S_0286D8_BC_OPTIMIZE_DISABLE(has_centroid);
755
756 /* Set registers. */
757 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
758 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
759
760 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
761 info->writes_samplemask ? V_028710_SPI_SHADER_32_ABGR :
762 info->writes_stencil ? V_028710_SPI_SHADER_32_GR :
763 info->writes_z ? V_028710_SPI_SHADER_32_R :
764 V_028710_SPI_SHADER_ZERO);
765
766 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
767 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
768
769 va = shader->bo->gpu_address;
770 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
771 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
772 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
773
774 num_user_sgprs = SI_PS_NUM_USER_SGPR;
775 num_sgprs = shader->config.num_sgprs;
776 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
777 if ((num_user_sgprs + 1) > num_sgprs) {
778 /* Last 2 reserved SGPRs are used for VCC */
779 num_sgprs = num_user_sgprs + 1 + 2;
780 }
781 assert(num_sgprs <= 104);
782
783 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
784 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
785 S_00B028_SGPRS((num_sgprs - 1) / 8) |
786 S_00B028_DX10_CLAMP(1) |
787 S_00B028_FLOAT_MODE(shader->config.float_mode));
788 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
789 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
790 S_00B02C_USER_SGPR(num_user_sgprs) |
791 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
792
793 /* Prefer RE_Z if the shader is complex enough. The requirement is either:
794 * - the shader uses at least 2 VMEM instructions, or
795 * - the code size is at least 50 2-dword instructions or 100 1-dword
796 * instructions.
797 */
798 if (info->num_memory_instructions >= 2 ||
799 shader->binary.code_size > 100*4)
800 shader->z_order = V_02880C_EARLY_Z_THEN_RE_Z;
801 else
802 shader->z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
803 }
804
805 static void si_shader_init_pm4_state(struct si_shader *shader)
806 {
807
808 if (shader->pm4)
809 si_pm4_free_state_simple(shader->pm4);
810
811 switch (shader->selector->type) {
812 case PIPE_SHADER_VERTEX:
813 if (shader->key.vs.as_ls)
814 si_shader_ls(shader);
815 else if (shader->key.vs.as_es)
816 si_shader_es(shader);
817 else
818 si_shader_vs(shader, NULL);
819 break;
820 case PIPE_SHADER_TESS_CTRL:
821 si_shader_hs(shader);
822 break;
823 case PIPE_SHADER_TESS_EVAL:
824 if (shader->key.tes.as_es)
825 si_shader_es(shader);
826 else
827 si_shader_vs(shader, NULL);
828 break;
829 case PIPE_SHADER_GEOMETRY:
830 si_shader_gs(shader);
831 si_shader_vs(shader->gs_copy_shader, shader);
832 break;
833 case PIPE_SHADER_FRAGMENT:
834 si_shader_ps(shader);
835 break;
836 default:
837 assert(0);
838 }
839 }
840
841 static unsigned si_get_alpha_test_func(struct si_context *sctx)
842 {
843 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
844 if (sctx->queued.named.dsa &&
845 !sctx->framebuffer.cb0_is_integer)
846 return sctx->queued.named.dsa->alpha_func;
847
848 return PIPE_FUNC_ALWAYS;
849 }
850
851 /* Compute the key for the hw shader variant */
852 static inline void si_shader_selector_key(struct pipe_context *ctx,
853 struct si_shader_selector *sel,
854 union si_shader_key *key)
855 {
856 struct si_context *sctx = (struct si_context *)ctx;
857 unsigned i;
858
859 memset(key, 0, sizeof(*key));
860
861 switch (sel->type) {
862 case PIPE_SHADER_VERTEX:
863 if (sctx->vertex_elements) {
864 unsigned count = MIN2(sel->info.num_inputs,
865 sctx->vertex_elements->count);
866 for (i = 0; i < count; ++i)
867 key->vs.prolog.instance_divisors[i] =
868 sctx->vertex_elements->elements[i].instance_divisor;
869 }
870 if (sctx->tes_shader.cso)
871 key->vs.as_ls = 1;
872 else if (sctx->gs_shader.cso)
873 key->vs.as_es = 1;
874
875 if (!sctx->gs_shader.cso && sctx->ps_shader.cso &&
876 sctx->ps_shader.cso->info.uses_primid)
877 key->vs.epilog.export_prim_id = 1;
878 break;
879 case PIPE_SHADER_TESS_CTRL:
880 key->tcs.epilog.prim_mode =
881 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
882 break;
883 case PIPE_SHADER_TESS_EVAL:
884 if (sctx->gs_shader.cso)
885 key->tes.as_es = 1;
886 else if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
887 key->tes.epilog.export_prim_id = 1;
888 break;
889 case PIPE_SHADER_GEOMETRY:
890 break;
891 case PIPE_SHADER_FRAGMENT: {
892 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
893 struct si_state_blend *blend = sctx->queued.named.blend;
894
895 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
896 sel->info.colors_written == 0x1)
897 key->ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
898
899 if (blend) {
900 /* Select the shader color format based on whether
901 * blending or alpha are needed.
902 */
903 key->ps.epilog.spi_shader_col_format =
904 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
905 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
906 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
907 sctx->framebuffer.spi_shader_col_format_blend) |
908 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
909 sctx->framebuffer.spi_shader_col_format_alpha) |
910 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
911 sctx->framebuffer.spi_shader_col_format);
912 } else
913 key->ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
914
915 /* If alpha-to-coverage is enabled, we have to export alpha
916 * even if there is no color buffer.
917 */
918 if (!(key->ps.epilog.spi_shader_col_format & 0xf) &&
919 blend && blend->alpha_to_coverage)
920 key->ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
921
922 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
923 * to the range supported by the type if a channel has less
924 * than 16 bits and the export format is 16_ABGR.
925 */
926 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII)
927 key->ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
928
929 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
930 if (!key->ps.epilog.last_cbuf) {
931 key->ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
932 key->ps.epilog.color_is_int8 &= sel->info.colors_written;
933 }
934
935 if (rs) {
936 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
937 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
938 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
939 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
940
941 key->ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
942
943 if (sctx->queued.named.blend) {
944 key->ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
945 rs->multisample_enable &&
946 !sctx->framebuffer.cb0_is_integer;
947 }
948
949 key->ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
950 key->ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
951 (is_line && rs->line_smooth)) &&
952 sctx->framebuffer.nr_samples <= 1;
953 key->ps.epilog.clamp_color = rs->clamp_fragment_color;
954
955 key->ps.prolog.force_persample_interp =
956 rs->force_persample_interp &&
957 rs->multisample_enable &&
958 sctx->framebuffer.nr_samples > 1 &&
959 sctx->ps_iter_samples > 1 &&
960 (sel->info.uses_persp_center ||
961 sel->info.uses_persp_centroid ||
962 sel->info.uses_linear_center ||
963 sel->info.uses_linear_centroid);
964 }
965
966 key->ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
967 break;
968 }
969 default:
970 assert(0);
971 }
972 }
973
974 /* Select the hw shader variant depending on the current state. */
975 static int si_shader_select_with_key(struct pipe_context *ctx,
976 struct si_shader_ctx_state *state,
977 union si_shader_key *key)
978 {
979 struct si_context *sctx = (struct si_context *)ctx;
980 struct si_shader_selector *sel = state->cso;
981 struct si_shader *current = state->current;
982 struct si_shader *iter, *shader = NULL;
983 int r;
984
985 /* Check if we don't need to change anything.
986 * This path is also used for most shaders that don't need multiple
987 * variants, it will cost just a computation of the key and this
988 * test. */
989 if (likely(current && memcmp(&current->key, key, sizeof(*key)) == 0))
990 return 0;
991
992 pipe_mutex_lock(sel->mutex);
993
994 /* Find the shader variant. */
995 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
996 /* Don't check the "current" shader. We checked it above. */
997 if (current != iter &&
998 memcmp(&iter->key, key, sizeof(*key)) == 0) {
999 state->current = iter;
1000 pipe_mutex_unlock(sel->mutex);
1001 return 0;
1002 }
1003 }
1004
1005 /* Build a new shader. */
1006 shader = CALLOC_STRUCT(si_shader);
1007 if (!shader) {
1008 pipe_mutex_unlock(sel->mutex);
1009 return -ENOMEM;
1010 }
1011 shader->selector = sel;
1012 shader->key = *key;
1013
1014 r = si_shader_create(sctx->screen, sctx->tm, shader, &sctx->b.debug);
1015 if (unlikely(r)) {
1016 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1017 sel->type, r);
1018 FREE(shader);
1019 pipe_mutex_unlock(sel->mutex);
1020 return r;
1021 }
1022 si_shader_init_pm4_state(shader);
1023
1024 if (!sel->last_variant) {
1025 sel->first_variant = shader;
1026 sel->last_variant = shader;
1027 } else {
1028 sel->last_variant->next_variant = shader;
1029 sel->last_variant = shader;
1030 }
1031 state->current = shader;
1032 pipe_mutex_unlock(sel->mutex);
1033 return 0;
1034 }
1035
1036 static int si_shader_select(struct pipe_context *ctx,
1037 struct si_shader_ctx_state *state)
1038 {
1039 union si_shader_key key;
1040
1041 si_shader_selector_key(ctx, state->cso, &key);
1042 return si_shader_select_with_key(ctx, state, &key);
1043 }
1044
1045 static void *si_create_shader_selector(struct pipe_context *ctx,
1046 const struct pipe_shader_state *state)
1047 {
1048 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1049 struct si_context *sctx = (struct si_context*)ctx;
1050 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1051 int i;
1052
1053 if (!sel)
1054 return NULL;
1055
1056 sel->tokens = tgsi_dup_tokens(state->tokens);
1057 if (!sel->tokens) {
1058 FREE(sel);
1059 return NULL;
1060 }
1061
1062 sel->so = state->stream_output;
1063 tgsi_scan_shader(state->tokens, &sel->info);
1064 sel->type = util_pipe_shader_from_tgsi_processor(sel->info.processor);
1065 p_atomic_inc(&sscreen->b.num_shaders_created);
1066
1067 /* Set which opcode uses which (i,j) pair. */
1068 if (sel->info.uses_persp_opcode_interp_centroid)
1069 sel->info.uses_persp_centroid = true;
1070
1071 if (sel->info.uses_linear_opcode_interp_centroid)
1072 sel->info.uses_linear_centroid = true;
1073
1074 if (sel->info.uses_persp_opcode_interp_offset ||
1075 sel->info.uses_persp_opcode_interp_sample)
1076 sel->info.uses_persp_center = true;
1077
1078 if (sel->info.uses_linear_opcode_interp_offset ||
1079 sel->info.uses_linear_opcode_interp_sample)
1080 sel->info.uses_linear_center = true;
1081
1082 switch (sel->type) {
1083 case PIPE_SHADER_GEOMETRY:
1084 sel->gs_output_prim =
1085 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1086 sel->gs_max_out_vertices =
1087 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1088 sel->gs_num_invocations =
1089 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1090 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
1091 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
1092 sel->gs_max_out_vertices;
1093
1094 sel->max_gs_stream = 0;
1095 for (i = 0; i < sel->so.num_outputs; i++)
1096 sel->max_gs_stream = MAX2(sel->max_gs_stream,
1097 sel->so.output[i].stream);
1098
1099 sel->gs_input_verts_per_prim =
1100 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
1101 break;
1102
1103 case PIPE_SHADER_VERTEX:
1104 case PIPE_SHADER_TESS_CTRL:
1105 case PIPE_SHADER_TESS_EVAL:
1106 for (i = 0; i < sel->info.num_outputs; i++) {
1107 unsigned name = sel->info.output_semantic_name[i];
1108 unsigned index = sel->info.output_semantic_index[i];
1109
1110 switch (name) {
1111 case TGSI_SEMANTIC_TESSINNER:
1112 case TGSI_SEMANTIC_TESSOUTER:
1113 case TGSI_SEMANTIC_PATCH:
1114 sel->patch_outputs_written |=
1115 1llu << si_shader_io_get_unique_index(name, index);
1116 break;
1117 default:
1118 sel->outputs_written |=
1119 1llu << si_shader_io_get_unique_index(name, index);
1120 }
1121 }
1122 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
1123 break;
1124
1125 case PIPE_SHADER_FRAGMENT:
1126 for (i = 0; i < 8; i++)
1127 if (sel->info.colors_written & (1 << i))
1128 sel->colors_written_4bit |= 0xf << (4 * i);
1129
1130 for (i = 0; i < sel->info.num_inputs; i++) {
1131 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
1132 int index = sel->info.input_semantic_index[i];
1133 sel->color_attr_index[index] = i;
1134 }
1135 }
1136 break;
1137 }
1138
1139 /* DB_SHADER_CONTROL */
1140 sel->db_shader_control =
1141 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
1142 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
1143 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
1144 S_02880C_KILL_ENABLE(sel->info.uses_kill);
1145
1146 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
1147 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1148 sel->db_shader_control |=
1149 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
1150 break;
1151 case TGSI_FS_DEPTH_LAYOUT_LESS:
1152 sel->db_shader_control |=
1153 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
1154 break;
1155 }
1156
1157 /* Compile the main shader part for use with a prolog and/or epilog. */
1158 if (sel->type != PIPE_SHADER_GEOMETRY &&
1159 !sscreen->use_monolithic_shaders) {
1160 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1161 void *tgsi_binary;
1162
1163 if (!shader)
1164 goto error;
1165
1166 shader->selector = sel;
1167
1168 tgsi_binary = si_get_tgsi_binary(sel);
1169
1170 /* Try to load the shader from the shader cache. */
1171 pipe_mutex_lock(sscreen->shader_cache_mutex);
1172
1173 if (tgsi_binary &&
1174 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1175 FREE(tgsi_binary);
1176 } else {
1177 /* Compile the shader if it hasn't been loaded from the cache. */
1178 if (si_compile_tgsi_shader(sscreen, sctx->tm, shader, false,
1179 &sctx->b.debug) != 0) {
1180 FREE(shader);
1181 FREE(tgsi_binary);
1182 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1183 goto error;
1184 }
1185
1186 if (tgsi_binary &&
1187 !si_shader_cache_insert_shader(sscreen, tgsi_binary, shader))
1188 FREE(tgsi_binary);
1189 }
1190 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1191
1192 sel->main_shader_part = shader;
1193 }
1194
1195 /* Pre-compilation. */
1196 if (sel->type == PIPE_SHADER_GEOMETRY ||
1197 sscreen->b.debug_flags & DBG_PRECOMPILE) {
1198 struct si_shader_ctx_state state = {sel};
1199 union si_shader_key key;
1200
1201 memset(&key, 0, sizeof(key));
1202
1203 /* Set reasonable defaults, so that the shader key doesn't
1204 * cause any code to be eliminated.
1205 */
1206 switch (sel->type) {
1207 case PIPE_SHADER_TESS_CTRL:
1208 key.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1209 break;
1210 case PIPE_SHADER_FRAGMENT:
1211 key.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1212 for (i = 0; i < 8; i++)
1213 if (sel->info.colors_written & (1 << i))
1214 key.ps.epilog.spi_shader_col_format |=
1215 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1216 break;
1217 }
1218
1219 if (si_shader_select_with_key(ctx, &state, &key))
1220 goto error;
1221 }
1222
1223 pipe_mutex_init(sel->mutex);
1224 return sel;
1225
1226 error:
1227 fprintf(stderr, "radeonsi: can't create a shader\n");
1228 tgsi_free_tokens(sel->tokens);
1229 FREE(sel);
1230 return NULL;
1231 }
1232
1233 /**
1234 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
1235 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
1236 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
1237 * called to emit the rest.
1238 */
1239 static void si_update_viewports_and_scissors(struct si_context *sctx)
1240 {
1241 struct tgsi_shader_info *info = si_get_vs_info(sctx);
1242
1243 if (!info || !info->writes_viewport_index)
1244 return;
1245
1246 if (sctx->scissors.dirty_mask)
1247 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
1248 if (sctx->viewports.dirty_mask)
1249 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
1250 }
1251
1252 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1253 {
1254 struct si_context *sctx = (struct si_context *)ctx;
1255 struct si_shader_selector *sel = state;
1256
1257 if (sctx->vs_shader.cso == sel)
1258 return;
1259
1260 sctx->vs_shader.cso = sel;
1261 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
1262 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1263 si_update_viewports_and_scissors(sctx);
1264 }
1265
1266 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
1267 {
1268 struct si_context *sctx = (struct si_context *)ctx;
1269 struct si_shader_selector *sel = state;
1270 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
1271
1272 if (sctx->gs_shader.cso == sel)
1273 return;
1274
1275 sctx->gs_shader.cso = sel;
1276 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
1277 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1278 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1279
1280 if (enable_changed)
1281 si_shader_change_notify(sctx);
1282 si_update_viewports_and_scissors(sctx);
1283 }
1284
1285 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
1286 {
1287 struct si_context *sctx = (struct si_context *)ctx;
1288 struct si_shader_selector *sel = state;
1289 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
1290
1291 if (sctx->tcs_shader.cso == sel)
1292 return;
1293
1294 sctx->tcs_shader.cso = sel;
1295 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
1296
1297 if (enable_changed)
1298 sctx->last_tcs = NULL; /* invalidate derived tess state */
1299 }
1300
1301 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
1302 {
1303 struct si_context *sctx = (struct si_context *)ctx;
1304 struct si_shader_selector *sel = state;
1305 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
1306
1307 if (sctx->tes_shader.cso == sel)
1308 return;
1309
1310 sctx->tes_shader.cso = sel;
1311 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
1312 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1313 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1314
1315 if (enable_changed) {
1316 si_shader_change_notify(sctx);
1317 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
1318 }
1319 si_update_viewports_and_scissors(sctx);
1320 }
1321
1322 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1323 {
1324 struct si_context *sctx = (struct si_context *)ctx;
1325 struct si_shader_selector *sel = state;
1326
1327 /* skip if supplied shader is one already in use */
1328 if (sctx->ps_shader.cso == sel)
1329 return;
1330
1331 sctx->ps_shader.cso = sel;
1332 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
1333 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1334 }
1335
1336 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
1337 {
1338 if (shader->pm4) {
1339 switch (shader->selector->type) {
1340 case PIPE_SHADER_VERTEX:
1341 if (shader->key.vs.as_ls)
1342 si_pm4_delete_state(sctx, ls, shader->pm4);
1343 else if (shader->key.vs.as_es)
1344 si_pm4_delete_state(sctx, es, shader->pm4);
1345 else
1346 si_pm4_delete_state(sctx, vs, shader->pm4);
1347 break;
1348 case PIPE_SHADER_TESS_CTRL:
1349 si_pm4_delete_state(sctx, hs, shader->pm4);
1350 break;
1351 case PIPE_SHADER_TESS_EVAL:
1352 if (shader->key.tes.as_es)
1353 si_pm4_delete_state(sctx, es, shader->pm4);
1354 else
1355 si_pm4_delete_state(sctx, vs, shader->pm4);
1356 break;
1357 case PIPE_SHADER_GEOMETRY:
1358 si_pm4_delete_state(sctx, gs, shader->pm4);
1359 si_pm4_delete_state(sctx, vs, shader->gs_copy_shader->pm4);
1360 break;
1361 case PIPE_SHADER_FRAGMENT:
1362 si_pm4_delete_state(sctx, ps, shader->pm4);
1363 break;
1364 }
1365 }
1366
1367 si_shader_destroy(shader);
1368 free(shader);
1369 }
1370
1371 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
1372 {
1373 struct si_context *sctx = (struct si_context *)ctx;
1374 struct si_shader_selector *sel = (struct si_shader_selector *)state;
1375 struct si_shader *p = sel->first_variant, *c;
1376 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
1377 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
1378 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
1379 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
1380 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
1381 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
1382 };
1383
1384 if (current_shader[sel->type]->cso == sel) {
1385 current_shader[sel->type]->cso = NULL;
1386 current_shader[sel->type]->current = NULL;
1387 }
1388
1389 while (p) {
1390 c = p->next_variant;
1391 si_delete_shader(sctx, p);
1392 p = c;
1393 }
1394
1395 if (sel->main_shader_part)
1396 si_delete_shader(sctx, sel->main_shader_part);
1397
1398 pipe_mutex_destroy(sel->mutex);
1399 free(sel->tokens);
1400 free(sel);
1401 }
1402
1403 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
1404 struct si_shader *vs, unsigned name,
1405 unsigned index, unsigned interpolate)
1406 {
1407 struct tgsi_shader_info *vsinfo = &vs->selector->info;
1408 unsigned j, ps_input_cntl = 0;
1409
1410 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
1411 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
1412 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1413
1414 if (name == TGSI_SEMANTIC_PCOORD ||
1415 (name == TGSI_SEMANTIC_TEXCOORD &&
1416 sctx->sprite_coord_enable & (1 << index))) {
1417 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
1418 }
1419
1420 for (j = 0; j < vsinfo->num_outputs; j++) {
1421 if (name == vsinfo->output_semantic_name[j] &&
1422 index == vsinfo->output_semantic_index[j]) {
1423 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[j]);
1424 break;
1425 }
1426 }
1427
1428 if (name == TGSI_SEMANTIC_PRIMID)
1429 /* PrimID is written after the last output. */
1430 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
1431 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
1432 /* No corresponding output found, load defaults into input.
1433 * Don't set any other bits.
1434 * (FLAT_SHADE=1 completely changes behavior) */
1435 ps_input_cntl = S_028644_OFFSET(0x20);
1436 }
1437 return ps_input_cntl;
1438 }
1439
1440 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
1441 {
1442 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1443 struct si_shader *ps = sctx->ps_shader.current;
1444 struct si_shader *vs = si_get_vs_state(sctx);
1445 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
1446 unsigned i, num_interp, num_written = 0, bcol_interp[2];
1447
1448 if (!ps || !ps->selector->info.num_inputs)
1449 return;
1450
1451 num_interp = si_get_ps_num_interp(ps);
1452 assert(num_interp > 0);
1453 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
1454
1455 for (i = 0; i < psinfo->num_inputs; i++) {
1456 unsigned name = psinfo->input_semantic_name[i];
1457 unsigned index = psinfo->input_semantic_index[i];
1458 unsigned interpolate = psinfo->input_interpolate[i];
1459
1460 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
1461 interpolate));
1462 num_written++;
1463
1464 if (name == TGSI_SEMANTIC_COLOR) {
1465 assert(index < ARRAY_SIZE(bcol_interp));
1466 bcol_interp[index] = interpolate;
1467 }
1468 }
1469
1470 if (ps->key.ps.prolog.color_two_side) {
1471 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
1472
1473 for (i = 0; i < 2; i++) {
1474 if (!(psinfo->colors_read & (0xf << (i * 4))))
1475 continue;
1476
1477 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
1478 i, bcol_interp[i]));
1479 num_written++;
1480 }
1481 }
1482 assert(num_interp == num_written);
1483 }
1484
1485 /**
1486 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1487 */
1488 static void si_init_config_add_vgt_flush(struct si_context *sctx)
1489 {
1490 if (sctx->init_config_has_vgt_flush)
1491 return;
1492
1493 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1494 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1495 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1496 si_pm4_cmd_end(sctx->init_config, false);
1497 sctx->init_config_has_vgt_flush = true;
1498 }
1499
1500 /* Initialize state related to ESGS / GSVS ring buffers */
1501 static bool si_update_gs_ring_buffers(struct si_context *sctx)
1502 {
1503 struct si_shader_selector *es =
1504 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
1505 struct si_shader_selector *gs = sctx->gs_shader.cso;
1506 struct si_pm4_state *pm4;
1507
1508 /* Chip constants. */
1509 unsigned num_se = sctx->screen->b.info.max_se;
1510 unsigned wave_size = 64;
1511 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1512 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1513 unsigned alignment = 256 * num_se;
1514 /* The maximum size is 63.999 MB per SE. */
1515 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1516
1517 /* Calculate the minimum size. */
1518 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
1519 wave_size, alignment);
1520
1521 /* These are recommended sizes, not minimum sizes. */
1522 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1523 es->esgs_itemsize * gs->gs_input_verts_per_prim;
1524 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1525 gs->max_gsvs_emit_size * (gs->max_gs_stream + 1);
1526
1527 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1528 esgs_ring_size = align(esgs_ring_size, alignment);
1529 gsvs_ring_size = align(gsvs_ring_size, alignment);
1530
1531 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1532 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1533
1534 /* Some rings don't have to be allocated if shaders don't use them.
1535 * (e.g. no varyings between ES and GS or GS and VS)
1536 */
1537 bool update_esgs = esgs_ring_size &&
1538 (!sctx->esgs_ring ||
1539 sctx->esgs_ring->width0 < esgs_ring_size);
1540 bool update_gsvs = gsvs_ring_size &&
1541 (!sctx->gsvs_ring ||
1542 sctx->gsvs_ring->width0 < gsvs_ring_size);
1543
1544 if (!update_esgs && !update_gsvs)
1545 return true;
1546
1547 if (update_esgs) {
1548 pipe_resource_reference(&sctx->esgs_ring, NULL);
1549 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1550 PIPE_USAGE_DEFAULT,
1551 esgs_ring_size);
1552 if (!sctx->esgs_ring)
1553 return false;
1554 }
1555
1556 if (update_gsvs) {
1557 pipe_resource_reference(&sctx->gsvs_ring, NULL);
1558 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1559 PIPE_USAGE_DEFAULT,
1560 gsvs_ring_size);
1561 if (!sctx->gsvs_ring)
1562 return false;
1563 }
1564
1565 /* Create the "init_config_gs_rings" state. */
1566 pm4 = CALLOC_STRUCT(si_pm4_state);
1567 if (!pm4)
1568 return false;
1569
1570 if (sctx->b.chip_class >= CIK) {
1571 if (sctx->esgs_ring)
1572 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
1573 sctx->esgs_ring->width0 / 256);
1574 if (sctx->gsvs_ring)
1575 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
1576 sctx->gsvs_ring->width0 / 256);
1577 } else {
1578 if (sctx->esgs_ring)
1579 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
1580 sctx->esgs_ring->width0 / 256);
1581 if (sctx->gsvs_ring)
1582 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
1583 sctx->gsvs_ring->width0 / 256);
1584 }
1585
1586 /* Set the state. */
1587 if (sctx->init_config_gs_rings)
1588 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
1589 sctx->init_config_gs_rings = pm4;
1590
1591 if (!sctx->init_config_has_vgt_flush) {
1592 si_init_config_add_vgt_flush(sctx);
1593 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1594 }
1595
1596 /* Flush the context to re-emit both init_config states. */
1597 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1598 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1599
1600 /* Set ring bindings. */
1601 if (sctx->esgs_ring) {
1602 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
1603 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1604 true, true, 4, 64, 0);
1605 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
1606 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1607 false, false, 0, 0, 0);
1608 }
1609 if (sctx->gsvs_ring)
1610 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
1611 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
1612 false, false, 0, 0, 0);
1613 return true;
1614 }
1615
1616 static void si_update_gsvs_ring_bindings(struct si_context *sctx)
1617 {
1618 unsigned gsvs_itemsize = sctx->gs_shader.cso->max_gsvs_emit_size;
1619 uint64_t offset;
1620
1621 if (!sctx->gsvs_ring || gsvs_itemsize == sctx->last_gsvs_itemsize)
1622 return;
1623
1624 sctx->last_gsvs_itemsize = gsvs_itemsize;
1625
1626 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
1627 sctx->gsvs_ring, gsvs_itemsize,
1628 64, true, true, 4, 16, 0);
1629
1630 offset = gsvs_itemsize * 64;
1631 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_1,
1632 sctx->gsvs_ring, gsvs_itemsize,
1633 64, true, true, 4, 16, offset);
1634
1635 offset = (gsvs_itemsize * 2) * 64;
1636 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_2,
1637 sctx->gsvs_ring, gsvs_itemsize,
1638 64, true, true, 4, 16, offset);
1639
1640 offset = (gsvs_itemsize * 3) * 64;
1641 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_3,
1642 sctx->gsvs_ring, gsvs_itemsize,
1643 64, true, true, 4, 16, offset);
1644 }
1645
1646 /**
1647 * @returns 1 if \p sel has been updated to use a new scratch buffer
1648 * 0 if not
1649 * < 0 if there was a failure
1650 */
1651 static int si_update_scratch_buffer(struct si_context *sctx,
1652 struct si_shader *shader)
1653 {
1654 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1655 int r;
1656
1657 if (!shader)
1658 return 0;
1659
1660 /* This shader doesn't need a scratch buffer */
1661 if (shader->config.scratch_bytes_per_wave == 0)
1662 return 0;
1663
1664 /* This shader is already configured to use the current
1665 * scratch buffer. */
1666 if (shader->scratch_bo == sctx->scratch_buffer)
1667 return 0;
1668
1669 assert(sctx->scratch_buffer);
1670
1671 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
1672
1673 /* Replace the shader bo with a new bo that has the relocs applied. */
1674 r = si_shader_binary_upload(sctx->screen, shader);
1675 if (r)
1676 return r;
1677
1678 /* Update the shader state to use the new shader bo. */
1679 si_shader_init_pm4_state(shader);
1680
1681 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1682
1683 return 1;
1684 }
1685
1686 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1687 {
1688 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
1689 }
1690
1691 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
1692 {
1693 return shader ? shader->config.scratch_bytes_per_wave : 0;
1694 }
1695
1696 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1697 {
1698 unsigned bytes = 0;
1699
1700 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
1701 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
1702 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
1703 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
1704 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
1705 return bytes;
1706 }
1707
1708 static bool si_update_spi_tmpring_size(struct si_context *sctx)
1709 {
1710 unsigned current_scratch_buffer_size =
1711 si_get_current_scratch_buffer_size(sctx);
1712 unsigned scratch_bytes_per_wave =
1713 si_get_max_scratch_bytes_per_wave(sctx);
1714 unsigned scratch_needed_size = scratch_bytes_per_wave *
1715 sctx->scratch_waves;
1716 unsigned spi_tmpring_size;
1717 int r;
1718
1719 if (scratch_needed_size > 0) {
1720 if (scratch_needed_size > current_scratch_buffer_size) {
1721 /* Create a bigger scratch buffer */
1722 pipe_resource_reference(
1723 (struct pipe_resource**)&sctx->scratch_buffer,
1724 NULL);
1725
1726 sctx->scratch_buffer =
1727 si_resource_create_custom(&sctx->screen->b.b,
1728 PIPE_USAGE_DEFAULT, scratch_needed_size);
1729 if (!sctx->scratch_buffer)
1730 return false;
1731 sctx->emit_scratch_reloc = true;
1732 }
1733
1734 /* Update the shaders, so they are using the latest scratch. The
1735 * scratch buffer may have been changed since these shaders were
1736 * last used, so we still need to try to update them, even if
1737 * they require scratch buffers smaller than the current size.
1738 */
1739 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
1740 if (r < 0)
1741 return false;
1742 if (r == 1)
1743 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1744
1745 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
1746 if (r < 0)
1747 return false;
1748 if (r == 1)
1749 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1750
1751 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
1752 if (r < 0)
1753 return false;
1754 if (r == 1)
1755 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1756
1757 /* VS can be bound as LS, ES, or VS. */
1758 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
1759 if (r < 0)
1760 return false;
1761 if (r == 1) {
1762 if (sctx->tes_shader.current)
1763 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1764 else if (sctx->gs_shader.current)
1765 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1766 else
1767 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1768 }
1769
1770 /* TES can be bound as ES or VS. */
1771 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
1772 if (r < 0)
1773 return false;
1774 if (r == 1) {
1775 if (sctx->gs_shader.current)
1776 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1777 else
1778 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1779 }
1780 }
1781
1782 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1783 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1784 "scratch size should already be aligned correctly.");
1785
1786 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1787 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1788 if (spi_tmpring_size != sctx->spi_tmpring_size) {
1789 sctx->spi_tmpring_size = spi_tmpring_size;
1790 sctx->emit_scratch_reloc = true;
1791 }
1792 return true;
1793 }
1794
1795 static void si_init_tess_factor_ring(struct si_context *sctx)
1796 {
1797 assert(!sctx->tf_ring);
1798
1799 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1800 PIPE_USAGE_DEFAULT,
1801 32768 * sctx->screen->b.info.max_se);
1802 if (!sctx->tf_ring)
1803 return;
1804
1805 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1806
1807 si_init_config_add_vgt_flush(sctx);
1808
1809 /* Append these registers to the init config state. */
1810 if (sctx->b.chip_class >= CIK) {
1811 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
1812 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1813 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
1814 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1815 } else {
1816 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
1817 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1818 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
1819 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1820 }
1821
1822 /* Flush the context to re-emit the init_config state.
1823 * This is done only once in a lifetime of a context.
1824 */
1825 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1826 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1827 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1828
1829 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
1830 SI_RING_TESS_FACTOR, sctx->tf_ring, 0,
1831 sctx->tf_ring->width0, false, false, 0, 0, 0);
1832 }
1833
1834 /**
1835 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1836 * VS passes its outputs to TES directly, so the fixed-function shader only
1837 * has to write TESSOUTER and TESSINNER.
1838 */
1839 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1840 {
1841 struct ureg_src const0, const1;
1842 struct ureg_dst tessouter, tessinner;
1843 struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
1844
1845 if (!ureg)
1846 return; /* if we get here, we're screwed */
1847
1848 assert(!sctx->fixed_func_tcs_shader.cso);
1849
1850 ureg_DECL_constant2D(ureg, 0, 1, SI_DRIVER_STATE_CONST_BUF);
1851 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1852 SI_DRIVER_STATE_CONST_BUF);
1853 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1854 SI_DRIVER_STATE_CONST_BUF);
1855
1856 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1857 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1858
1859 ureg_MOV(ureg, tessouter, const0);
1860 ureg_MOV(ureg, tessinner, const1);
1861 ureg_END(ureg);
1862
1863 sctx->fixed_func_tcs_shader.cso =
1864 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1865 }
1866
1867 static void si_update_vgt_shader_config(struct si_context *sctx)
1868 {
1869 /* Calculate the index of the config.
1870 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1871 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
1872 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1873
1874 if (!*pm4) {
1875 uint32_t stages = 0;
1876
1877 *pm4 = CALLOC_STRUCT(si_pm4_state);
1878
1879 if (sctx->tes_shader.cso) {
1880 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1881 S_028B54_HS_EN(1);
1882
1883 if (sctx->gs_shader.cso)
1884 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1885 S_028B54_GS_EN(1) |
1886 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1887 else
1888 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1889 } else if (sctx->gs_shader.cso) {
1890 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1891 S_028B54_GS_EN(1) |
1892 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1893 }
1894
1895 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1896 }
1897 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1898 }
1899
1900 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
1901 {
1902 struct pipe_stream_output_info *so = &shader->so;
1903 uint32_t enabled_stream_buffers_mask = 0;
1904 int i;
1905
1906 for (i = 0; i < so->num_outputs; i++)
1907 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
1908 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
1909 sctx->b.streamout.stride_in_dw = shader->so.stride;
1910 }
1911
1912 bool si_update_shaders(struct si_context *sctx)
1913 {
1914 struct pipe_context *ctx = (struct pipe_context*)sctx;
1915 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1916 int r;
1917
1918 /* Update stages before GS. */
1919 if (sctx->tes_shader.cso) {
1920 if (!sctx->tf_ring) {
1921 si_init_tess_factor_ring(sctx);
1922 if (!sctx->tf_ring)
1923 return false;
1924 }
1925
1926 /* VS as LS */
1927 r = si_shader_select(ctx, &sctx->vs_shader);
1928 if (r)
1929 return false;
1930 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1931
1932 if (sctx->tcs_shader.cso) {
1933 r = si_shader_select(ctx, &sctx->tcs_shader);
1934 if (r)
1935 return false;
1936 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1937 } else {
1938 if (!sctx->fixed_func_tcs_shader.cso) {
1939 si_generate_fixed_func_tcs(sctx);
1940 if (!sctx->fixed_func_tcs_shader.cso)
1941 return false;
1942 }
1943
1944 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader);
1945 if (r)
1946 return false;
1947 si_pm4_bind_state(sctx, hs,
1948 sctx->fixed_func_tcs_shader.current->pm4);
1949 }
1950
1951 r = si_shader_select(ctx, &sctx->tes_shader);
1952 if (r)
1953 return false;
1954
1955 if (sctx->gs_shader.cso) {
1956 /* TES as ES */
1957 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1958 } else {
1959 /* TES as VS */
1960 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1961 si_update_so(sctx, sctx->tes_shader.cso);
1962 }
1963 } else if (sctx->gs_shader.cso) {
1964 /* VS as ES */
1965 r = si_shader_select(ctx, &sctx->vs_shader);
1966 if (r)
1967 return false;
1968 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1969 } else {
1970 /* VS as VS */
1971 r = si_shader_select(ctx, &sctx->vs_shader);
1972 if (r)
1973 return false;
1974 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1975 si_update_so(sctx, sctx->vs_shader.cso);
1976 }
1977
1978 /* Update GS. */
1979 if (sctx->gs_shader.cso) {
1980 r = si_shader_select(ctx, &sctx->gs_shader);
1981 if (r)
1982 return false;
1983 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1984 si_pm4_bind_state(sctx, vs, sctx->gs_shader.current->gs_copy_shader->pm4);
1985 si_update_so(sctx, sctx->gs_shader.cso);
1986
1987 if (!si_update_gs_ring_buffers(sctx))
1988 return false;
1989
1990 si_update_gsvs_ring_bindings(sctx);
1991 } else {
1992 si_pm4_bind_state(sctx, gs, NULL);
1993 si_pm4_bind_state(sctx, es, NULL);
1994 }
1995
1996 si_update_vgt_shader_config(sctx);
1997
1998 if (sctx->ps_shader.cso) {
1999 unsigned db_shader_control;
2000
2001 r = si_shader_select(ctx, &sctx->ps_shader);
2002 if (r)
2003 return false;
2004 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2005
2006 db_shader_control =
2007 sctx->ps_shader.cso->db_shader_control |
2008 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS) |
2009 S_02880C_Z_ORDER(sctx->ps_shader.current->z_order);
2010
2011 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
2012 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
2013 sctx->flatshade != rs->flatshade) {
2014 sctx->sprite_coord_enable = rs->sprite_coord_enable;
2015 sctx->flatshade = rs->flatshade;
2016 si_mark_atom_dirty(sctx, &sctx->spi_map);
2017 }
2018
2019 if (sctx->b.family == CHIP_STONEY && si_pm4_state_changed(sctx, ps))
2020 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2021
2022 if (sctx->ps_db_shader_control != db_shader_control) {
2023 sctx->ps_db_shader_control = db_shader_control;
2024 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2025 }
2026
2027 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.ps.epilog.poly_line_smoothing) {
2028 sctx->smoothing_enabled = sctx->ps_shader.current->key.ps.epilog.poly_line_smoothing;
2029 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2030
2031 if (sctx->b.chip_class == SI)
2032 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2033 }
2034 }
2035
2036 if (si_pm4_state_changed(sctx, ls) ||
2037 si_pm4_state_changed(sctx, hs) ||
2038 si_pm4_state_changed(sctx, es) ||
2039 si_pm4_state_changed(sctx, gs) ||
2040 si_pm4_state_changed(sctx, vs) ||
2041 si_pm4_state_changed(sctx, ps)) {
2042 if (!si_update_spi_tmpring_size(sctx))
2043 return false;
2044 }
2045 return true;
2046 }
2047
2048 void si_init_shader_functions(struct si_context *sctx)
2049 {
2050 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
2051
2052 sctx->b.b.create_vs_state = si_create_shader_selector;
2053 sctx->b.b.create_tcs_state = si_create_shader_selector;
2054 sctx->b.b.create_tes_state = si_create_shader_selector;
2055 sctx->b.b.create_gs_state = si_create_shader_selector;
2056 sctx->b.b.create_fs_state = si_create_shader_selector;
2057
2058 sctx->b.b.bind_vs_state = si_bind_vs_shader;
2059 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
2060 sctx->b.b.bind_tes_state = si_bind_tes_shader;
2061 sctx->b.b.bind_gs_state = si_bind_gs_shader;
2062 sctx->b.b.bind_fs_state = si_bind_ps_shader;
2063
2064 sctx->b.b.delete_vs_state = si_delete_shader_selector;
2065 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
2066 sctx->b.b.delete_tes_state = si_delete_shader_selector;
2067 sctx->b.b.delete_gs_state = si_delete_shader_selector;
2068 sctx->b.b.delete_fs_state = si_delete_shader_selector;
2069 }