2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
29 #include "si_shader.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "util/u_memory.h"
34 #include "util/u_simple_shaders.h"
36 static void si_shader_es(struct si_shader
*shader
)
38 struct si_pm4_state
*pm4
;
39 unsigned num_sgprs
, num_user_sgprs
;
40 unsigned vgpr_comp_cnt
;
43 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
48 va
= shader
->bo
->gpu_address
;
49 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_DATA
);
51 vgpr_comp_cnt
= shader
->uses_instanceid
? 3 : 0;
53 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
54 num_sgprs
= shader
->num_sgprs
;
55 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
56 if ((num_user_sgprs
+ 1) > num_sgprs
) {
57 /* Last 2 reserved SGPRs are used for VCC */
58 num_sgprs
= num_user_sgprs
+ 1 + 2;
60 assert(num_sgprs
<= 104);
62 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
63 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
64 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
65 S_00B328_VGPRS((shader
->num_vgprs
- 1) / 4) |
66 S_00B328_SGPRS((num_sgprs
- 1) / 8) |
67 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
68 S_00B328_DX10_CLAMP(1));
69 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
70 S_00B32C_USER_SGPR(num_user_sgprs
));
73 static void si_shader_gs(struct si_shader
*shader
)
75 unsigned gs_vert_itemsize
= shader
->selector
->info
.num_outputs
* (16 >> 2);
76 unsigned gs_max_vert_out
= shader
->selector
->gs_max_out_vertices
;
77 unsigned gsvs_itemsize
= gs_vert_itemsize
* gs_max_vert_out
;
79 struct si_pm4_state
*pm4
;
80 unsigned num_sgprs
, num_user_sgprs
;
83 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
84 assert(gsvs_itemsize
< (1 << 15));
86 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
91 if (gs_max_vert_out
<= 128) {
92 cut_mode
= V_028A40_GS_CUT_128
;
93 } else if (gs_max_vert_out
<= 256) {
94 cut_mode
= V_028A40_GS_CUT_256
;
95 } else if (gs_max_vert_out
<= 512) {
96 cut_mode
= V_028A40_GS_CUT_512
;
98 assert(gs_max_vert_out
<= 1024);
99 cut_mode
= V_028A40_GS_CUT_1024
;
102 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
,
103 S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
104 S_028A40_CUT_MODE(cut_mode
)|
105 S_028A40_ES_WRITE_OPTIMIZE(1) |
106 S_028A40_GS_WRITE_OPTIMIZE(1));
108 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, gsvs_itemsize
);
109 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, gsvs_itemsize
);
110 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, gsvs_itemsize
);
112 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
113 util_bitcount64(shader
->selector
->gs_used_inputs
) * (16 >> 2));
114 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, gsvs_itemsize
);
116 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, gs_max_vert_out
);
118 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, gs_vert_itemsize
);
120 va
= shader
->bo
->gpu_address
;
121 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_DATA
);
122 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
123 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, va
>> 40);
125 num_user_sgprs
= SI_GS_NUM_USER_SGPR
;
126 num_sgprs
= shader
->num_sgprs
;
127 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
128 if ((num_user_sgprs
+ 2) > num_sgprs
) {
129 /* Last 2 reserved SGPRs are used for VCC */
130 num_sgprs
= num_user_sgprs
+ 2 + 2;
132 assert(num_sgprs
<= 104);
134 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
135 S_00B228_VGPRS((shader
->num_vgprs
- 1) / 4) |
136 S_00B228_SGPRS((num_sgprs
- 1) / 8) |
137 S_00B228_DX10_CLAMP(1));
138 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
139 S_00B22C_USER_SGPR(num_user_sgprs
));
142 static void si_shader_vs(struct si_shader
*shader
)
144 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
145 struct si_pm4_state
*pm4
;
146 unsigned num_sgprs
, num_user_sgprs
;
147 unsigned nparams
, i
, vgpr_comp_cnt
;
149 unsigned window_space
=
150 shader
->selector
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
152 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
157 va
= shader
->bo
->gpu_address
;
158 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_DATA
);
160 vgpr_comp_cnt
= shader
->uses_instanceid
? 3 : 0;
162 if (shader
->is_gs_copy_shader
)
163 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
165 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
167 num_sgprs
= shader
->num_sgprs
;
168 if (num_user_sgprs
> num_sgprs
) {
169 /* Last 2 reserved SGPRs are used for VCC */
170 num_sgprs
= num_user_sgprs
+ 2;
172 assert(num_sgprs
<= 104);
174 /* Certain attributes (position, psize, etc.) don't count as params.
175 * VS is required to export at least one param and r600_shader_from_tgsi()
176 * takes care of adding a dummy export.
178 for (nparams
= 0, i
= 0 ; i
< info
->num_outputs
; i
++) {
179 switch (info
->output_semantic_name
[i
]) {
180 case TGSI_SEMANTIC_CLIPVERTEX
:
181 case TGSI_SEMANTIC_POSITION
:
182 case TGSI_SEMANTIC_PSIZE
:
191 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
192 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
194 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
195 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
196 S_02870C_POS1_EXPORT_FORMAT(shader
->nr_pos_exports
> 1 ?
197 V_02870C_SPI_SHADER_4COMP
:
198 V_02870C_SPI_SHADER_NONE
) |
199 S_02870C_POS2_EXPORT_FORMAT(shader
->nr_pos_exports
> 2 ?
200 V_02870C_SPI_SHADER_4COMP
:
201 V_02870C_SPI_SHADER_NONE
) |
202 S_02870C_POS3_EXPORT_FORMAT(shader
->nr_pos_exports
> 3 ?
203 V_02870C_SPI_SHADER_4COMP
:
204 V_02870C_SPI_SHADER_NONE
));
206 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
207 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, va
>> 40);
208 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
209 S_00B128_VGPRS((shader
->num_vgprs
- 1) / 4) |
210 S_00B128_SGPRS((num_sgprs
- 1) / 8) |
211 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
212 S_00B128_DX10_CLAMP(1));
213 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
214 S_00B12C_USER_SGPR(num_user_sgprs
) |
215 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
216 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
217 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
218 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
219 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
));
221 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
222 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
224 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
225 S_028818_VTX_W0_FMT(1) |
226 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
227 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
228 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
231 static void si_shader_ps(struct si_shader
*shader
)
233 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
234 struct si_pm4_state
*pm4
;
235 unsigned i
, spi_ps_in_control
;
236 unsigned num_sgprs
, num_user_sgprs
;
237 unsigned spi_baryc_cntl
= 0, spi_ps_input_ena
;
240 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
245 for (i
= 0; i
< info
->num_inputs
; i
++) {
246 switch (info
->input_semantic_name
[i
]) {
247 case TGSI_SEMANTIC_POSITION
:
248 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
250 * 0 -> Position = pixel center (default)
251 * 1 -> Position = pixel centroid
252 * 2 -> Position = at sample position
254 switch (info
->input_interpolate_loc
[i
]) {
255 case TGSI_INTERPOLATE_LOC_CENTROID
:
256 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(1);
258 case TGSI_INTERPOLATE_LOC_SAMPLE
:
259 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
263 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
264 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
265 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
270 spi_ps_in_control
= S_0286D8_NUM_INTERP(shader
->nparam
) |
271 S_0286D8_BC_OPTIMIZE_DISABLE(1);
273 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
274 spi_ps_input_ena
= shader
->spi_ps_input_ena
;
275 /* we need to enable at least one of them, otherwise we hang the GPU */
276 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena
) ||
277 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) ||
278 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) ||
279 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena
) ||
280 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena
) ||
281 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
) ||
282 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
) ||
283 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena
));
285 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, spi_ps_input_ena
);
286 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
, spi_ps_input_ena
);
287 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
289 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
, shader
->spi_shader_z_format
);
290 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
,
291 shader
->spi_shader_col_format
);
292 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, shader
->cb_shader_mask
);
294 va
= shader
->bo
->gpu_address
;
295 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_DATA
);
296 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
297 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, va
>> 40);
299 num_user_sgprs
= SI_PS_NUM_USER_SGPR
;
300 num_sgprs
= shader
->num_sgprs
;
301 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
302 if ((num_user_sgprs
+ 1) > num_sgprs
) {
303 /* Last 2 reserved SGPRs are used for VCC */
304 num_sgprs
= num_user_sgprs
+ 1 + 2;
306 assert(num_sgprs
<= 104);
308 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
309 S_00B028_VGPRS((shader
->num_vgprs
- 1) / 4) |
310 S_00B028_SGPRS((num_sgprs
- 1) / 8) |
311 S_00B028_DX10_CLAMP(1));
312 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
313 S_00B02C_EXTRA_LDS_SIZE(shader
->lds_size
) |
314 S_00B02C_USER_SGPR(num_user_sgprs
));
317 static void si_shader_init_pm4_state(struct si_shader
*shader
)
319 switch (shader
->selector
->type
) {
320 case PIPE_SHADER_VERTEX
:
321 if (shader
->key
.vs
.as_es
)
322 si_shader_es(shader
);
324 si_shader_vs(shader
);
326 case PIPE_SHADER_GEOMETRY
:
327 si_shader_gs(shader
);
328 si_shader_vs(shader
->gs_copy_shader
);
330 case PIPE_SHADER_FRAGMENT
:
331 si_shader_ps(shader
);
338 /* Compute the key for the hw shader variant */
339 static INLINE
void si_shader_selector_key(struct pipe_context
*ctx
,
340 struct si_shader_selector
*sel
,
341 union si_shader_key
*key
)
343 struct si_context
*sctx
= (struct si_context
*)ctx
;
344 memset(key
, 0, sizeof(*key
));
346 if (sel
->type
== PIPE_SHADER_VERTEX
) {
348 if (!sctx
->vertex_elements
)
351 for (i
= 0; i
< sctx
->vertex_elements
->count
; ++i
)
352 key
->vs
.instance_divisors
[i
] = sctx
->vertex_elements
->elements
[i
].instance_divisor
;
354 if (sctx
->gs_shader
) {
356 key
->vs
.gs_used_inputs
= sctx
->gs_shader
->gs_used_inputs
;
358 } else if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
359 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
360 key
->ps
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
361 key
->ps
.export_16bpc
= sctx
->framebuffer
.export_16bpc
;
363 if (sctx
->queued
.named
.rasterizer
) {
364 key
->ps
.color_two_side
= sctx
->queued
.named
.rasterizer
->two_side
;
365 key
->ps
.flatshade
= sctx
->queued
.named
.rasterizer
->flatshade
;
367 if (sctx
->queued
.named
.blend
) {
368 key
->ps
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
369 sctx
->queued
.named
.rasterizer
->multisample_enable
&&
370 !sctx
->framebuffer
.cb0_is_integer
;
373 if (sctx
->queued
.named
.dsa
) {
374 key
->ps
.alpha_func
= sctx
->queued
.named
.dsa
->alpha_func
;
376 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
377 if (sctx
->framebuffer
.cb0_is_integer
)
378 key
->ps
.alpha_func
= PIPE_FUNC_ALWAYS
;
380 key
->ps
.alpha_func
= PIPE_FUNC_ALWAYS
;
385 /* Select the hw shader variant depending on the current state. */
386 static int si_shader_select(struct pipe_context
*ctx
,
387 struct si_shader_selector
*sel
)
389 union si_shader_key key
;
390 struct si_shader
* shader
= NULL
;
393 si_shader_selector_key(ctx
, sel
, &key
);
395 /* Check if we don't need to change anything.
396 * This path is also used for most shaders that don't need multiple
397 * variants, it will cost just a computation of the key and this
399 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
403 /* lookup if we have other variants in the list */
404 if (sel
->num_shaders
> 1) {
405 struct si_shader
*p
= sel
->current
, *c
= p
->next_variant
;
407 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
413 p
->next_variant
= c
->next_variant
;
419 shader
->next_variant
= sel
->current
;
420 sel
->current
= shader
;
422 shader
= CALLOC(1, sizeof(struct si_shader
));
423 shader
->selector
= sel
;
426 shader
->next_variant
= sel
->current
;
427 sel
->current
= shader
;
428 r
= si_shader_create((struct si_screen
*)ctx
->screen
, shader
);
430 R600_ERR("Failed to build shader variant (type=%u) %d\n",
436 si_shader_init_pm4_state(shader
);
443 static void *si_create_shader_state(struct pipe_context
*ctx
,
444 const struct pipe_shader_state
*state
,
445 unsigned pipe_shader_type
)
447 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
450 sel
->type
= pipe_shader_type
;
451 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
452 sel
->so
= state
->stream_output
;
453 tgsi_scan_shader(state
->tokens
, &sel
->info
);
455 switch (pipe_shader_type
) {
456 case PIPE_SHADER_GEOMETRY
:
457 sel
->gs_output_prim
=
458 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
459 sel
->gs_max_out_vertices
=
460 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
462 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
463 unsigned name
= sel
->info
.input_semantic_name
[i
];
464 unsigned index
= sel
->info
.input_semantic_index
[i
];
467 case TGSI_SEMANTIC_PRIMID
:
470 sel
->gs_used_inputs
|=
471 1llu << si_shader_io_get_unique_index(name
, index
);
479 static void *si_create_fs_state(struct pipe_context
*ctx
,
480 const struct pipe_shader_state
*state
)
482 return si_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
485 static void *si_create_gs_state(struct pipe_context
*ctx
,
486 const struct pipe_shader_state
*state
)
488 return si_create_shader_state(ctx
, state
, PIPE_SHADER_GEOMETRY
);
491 static void *si_create_vs_state(struct pipe_context
*ctx
,
492 const struct pipe_shader_state
*state
)
494 return si_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
497 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
499 struct si_context
*sctx
= (struct si_context
*)ctx
;
500 struct si_shader_selector
*sel
= state
;
502 if (sctx
->vs_shader
== sel
|| !sel
)
505 sctx
->vs_shader
= sel
;
506 sctx
->clip_regs
.dirty
= true;
509 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
511 struct si_context
*sctx
= (struct si_context
*)ctx
;
512 struct si_shader_selector
*sel
= state
;
514 if (sctx
->gs_shader
== sel
)
517 sctx
->gs_shader
= sel
;
518 sctx
->clip_regs
.dirty
= true;
519 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
522 static void si_make_dummy_ps(struct si_context
*sctx
)
524 if (!sctx
->dummy_pixel_shader
) {
525 sctx
->dummy_pixel_shader
=
526 util_make_fragment_cloneinput_shader(&sctx
->b
.b
, 0,
527 TGSI_SEMANTIC_GENERIC
,
528 TGSI_INTERPOLATE_CONSTANT
);
532 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
534 struct si_context
*sctx
= (struct si_context
*)ctx
;
535 struct si_shader_selector
*sel
= state
;
537 /* skip if supplied shader is one already in use */
538 if (sctx
->ps_shader
== sel
)
541 /* use a dummy shader if binding a NULL shader */
543 si_make_dummy_ps(sctx
);
544 sel
= sctx
->dummy_pixel_shader
;
547 sctx
->ps_shader
= sel
;
550 static void si_delete_shader_selector(struct pipe_context
*ctx
,
551 struct si_shader_selector
*sel
)
553 struct si_context
*sctx
= (struct si_context
*)ctx
;
554 struct si_shader
*p
= sel
->current
, *c
;
558 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
559 si_pm4_delete_state(sctx
, gs
, p
->pm4
);
560 si_pm4_delete_state(sctx
, vs
, p
->gs_copy_shader
->pm4
);
561 } else if (sel
->type
== PIPE_SHADER_FRAGMENT
)
562 si_pm4_delete_state(sctx
, ps
, p
->pm4
);
563 else if (p
->key
.vs
.as_es
)
564 si_pm4_delete_state(sctx
, es
, p
->pm4
);
566 si_pm4_delete_state(sctx
, vs
, p
->pm4
);
567 si_shader_destroy(ctx
, p
);
576 static void si_delete_vs_shader(struct pipe_context
*ctx
, void *state
)
578 struct si_context
*sctx
= (struct si_context
*)ctx
;
579 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
581 if (sctx
->vs_shader
== sel
) {
582 sctx
->vs_shader
= NULL
;
585 si_delete_shader_selector(ctx
, sel
);
588 static void si_delete_gs_shader(struct pipe_context
*ctx
, void *state
)
590 struct si_context
*sctx
= (struct si_context
*)ctx
;
591 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
593 if (sctx
->gs_shader
== sel
) {
594 sctx
->gs_shader
= NULL
;
597 si_delete_shader_selector(ctx
, sel
);
600 static void si_delete_ps_shader(struct pipe_context
*ctx
, void *state
)
602 struct si_context
*sctx
= (struct si_context
*)ctx
;
603 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
605 if (sctx
->ps_shader
== sel
) {
606 sctx
->ps_shader
= NULL
;
609 si_delete_shader_selector(ctx
, sel
);
612 static void si_update_spi_map(struct si_context
*sctx
)
614 struct si_shader
*ps
= sctx
->ps_shader
->current
;
615 struct si_shader
*vs
= si_get_vs_state(sctx
);
616 struct tgsi_shader_info
*psinfo
= &ps
->selector
->info
;
617 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
618 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
621 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
622 unsigned name
= psinfo
->input_semantic_name
[i
];
623 unsigned index
= psinfo
->input_semantic_index
[i
];
624 unsigned interpolate
= psinfo
->input_interpolate
[i
];
625 unsigned param_offset
= ps
->ps_input_param_offset
[i
];
627 if (name
== TGSI_SEMANTIC_POSITION
)
628 /* Read from preloaded VGPRs, not parameters */
634 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
635 (interpolate
== TGSI_INTERPOLATE_COLOR
&&
636 ps
->key
.ps
.flatshade
)) {
637 tmp
|= S_028644_FLAT_SHADE(1);
640 if (name
== TGSI_SEMANTIC_GENERIC
&&
641 sctx
->sprite_coord_enable
& (1 << index
)) {
642 tmp
|= S_028644_PT_SPRITE_TEX(1);
645 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
646 if (name
== vsinfo
->output_semantic_name
[j
] &&
647 index
== vsinfo
->output_semantic_index
[j
]) {
648 tmp
|= S_028644_OFFSET(vs
->vs_output_param_offset
[j
]);
653 if (j
== vsinfo
->num_outputs
) {
654 /* No corresponding output found, load defaults into input */
655 tmp
|= S_028644_OFFSET(0x20);
659 R_028644_SPI_PS_INPUT_CNTL_0
+ param_offset
* 4,
662 if (name
== TGSI_SEMANTIC_COLOR
&&
663 ps
->key
.ps
.color_two_side
) {
664 name
= TGSI_SEMANTIC_BCOLOR
;
670 si_pm4_set_state(sctx
, spi
, pm4
);
673 /* Initialize state related to ESGS / GSVS ring buffers */
674 static void si_init_gs_rings(struct si_context
*sctx
)
676 unsigned esgs_ring_size
= 128 * 1024;
677 unsigned gsvs_ring_size
= 64 * 1024 * 1024;
679 assert(!sctx
->gs_rings
);
680 sctx
->gs_rings
= CALLOC_STRUCT(si_pm4_state
);
682 sctx
->esgs_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
683 PIPE_USAGE_DEFAULT
, esgs_ring_size
);
685 sctx
->gsvs_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
686 PIPE_USAGE_DEFAULT
, gsvs_ring_size
);
688 if (sctx
->b
.chip_class
>= CIK
) {
689 si_pm4_set_reg(sctx
->gs_rings
, R_030900_VGT_ESGS_RING_SIZE
,
690 esgs_ring_size
/ 256);
691 si_pm4_set_reg(sctx
->gs_rings
, R_030904_VGT_GSVS_RING_SIZE
,
692 gsvs_ring_size
/ 256);
694 si_pm4_set_reg(sctx
->gs_rings
, R_0088C8_VGT_ESGS_RING_SIZE
,
695 esgs_ring_size
/ 256);
696 si_pm4_set_reg(sctx
->gs_rings
, R_0088CC_VGT_GSVS_RING_SIZE
,
697 gsvs_ring_size
/ 256);
700 si_set_ring_buffer(&sctx
->b
.b
, PIPE_SHADER_VERTEX
, SI_RING_ESGS
,
701 sctx
->esgs_ring
, 0, esgs_ring_size
,
703 si_set_ring_buffer(&sctx
->b
.b
, PIPE_SHADER_GEOMETRY
, SI_RING_ESGS
,
704 sctx
->esgs_ring
, 0, esgs_ring_size
,
706 si_set_ring_buffer(&sctx
->b
.b
, PIPE_SHADER_VERTEX
, SI_RING_GSVS
,
707 sctx
->gsvs_ring
, 0, gsvs_ring_size
,
711 void si_update_shaders(struct si_context
*sctx
)
713 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
715 if (sctx
->gs_shader
) {
716 si_shader_select(ctx
, sctx
->gs_shader
);
717 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
->current
->pm4
);
718 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
->current
->gs_copy_shader
->pm4
);
720 sctx
->b
.streamout
.stride_in_dw
= sctx
->gs_shader
->so
.stride
;
722 si_shader_select(ctx
, sctx
->vs_shader
);
723 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
->current
->pm4
);
726 si_init_gs_rings(sctx
);
727 if (sctx
->emitted
.named
.gs_rings
!= sctx
->gs_rings
)
728 sctx
->b
.flags
|= R600_CONTEXT_VGT_FLUSH
;
729 si_pm4_bind_state(sctx
, gs_rings
, sctx
->gs_rings
);
731 si_set_ring_buffer(ctx
, PIPE_SHADER_GEOMETRY
, SI_RING_GSVS
,
733 sctx
->gs_shader
->gs_max_out_vertices
*
734 sctx
->gs_shader
->info
.num_outputs
* 16,
735 64, true, true, 4, 16);
738 sctx
->gs_on
= CALLOC_STRUCT(si_pm4_state
);
740 si_pm4_set_reg(sctx
->gs_on
, R_028B54_VGT_SHADER_STAGES_EN
,
741 S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
743 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
));
745 si_pm4_bind_state(sctx
, gs_onoff
, sctx
->gs_on
);
747 si_shader_select(ctx
, sctx
->vs_shader
);
748 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
->current
->pm4
);
750 sctx
->b
.streamout
.stride_in_dw
= sctx
->vs_shader
->so
.stride
;
753 sctx
->gs_off
= CALLOC_STRUCT(si_pm4_state
);
755 si_pm4_set_reg(sctx
->gs_off
, R_028A40_VGT_GS_MODE
, 0);
756 si_pm4_set_reg(sctx
->gs_off
, R_028B54_VGT_SHADER_STAGES_EN
, 0);
758 si_pm4_bind_state(sctx
, gs_onoff
, sctx
->gs_off
);
759 si_pm4_bind_state(sctx
, gs_rings
, NULL
);
760 si_pm4_bind_state(sctx
, gs
, NULL
);
761 si_pm4_bind_state(sctx
, es
, NULL
);
764 si_shader_select(ctx
, sctx
->ps_shader
);
766 if (!sctx
->ps_shader
->current
) {
767 struct si_shader_selector
*sel
;
769 /* use a dummy shader if compiling the shader (variant) failed */
770 si_make_dummy_ps(sctx
);
771 sel
= sctx
->dummy_pixel_shader
;
772 si_shader_select(ctx
, sel
);
773 sctx
->ps_shader
->current
= sel
->current
;
776 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
->current
->pm4
);
778 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
779 sctx
->sprite_coord_enable
!= sctx
->queued
.named
.rasterizer
->sprite_coord_enable
) {
780 sctx
->sprite_coord_enable
= sctx
->queued
.named
.rasterizer
->sprite_coord_enable
;
781 si_update_spi_map(sctx
);
784 if (sctx
->ps_db_shader_control
!= sctx
->ps_shader
->current
->db_shader_control
) {
785 sctx
->ps_db_shader_control
= sctx
->ps_shader
->current
->db_shader_control
;
786 sctx
->db_render_state
.dirty
= true;
790 void si_init_shader_functions(struct si_context
*sctx
)
792 sctx
->b
.b
.create_vs_state
= si_create_vs_state
;
793 sctx
->b
.b
.create_gs_state
= si_create_gs_state
;
794 sctx
->b
.b
.create_fs_state
= si_create_fs_state
;
796 sctx
->b
.b
.bind_vs_state
= si_bind_vs_shader
;
797 sctx
->b
.b
.bind_gs_state
= si_bind_gs_shader
;
798 sctx
->b
.b
.bind_fs_state
= si_bind_ps_shader
;
800 sctx
->b
.b
.delete_vs_state
= si_delete_vs_shader
;
801 sctx
->b
.b
.delete_gs_state
= si_delete_gs_shader
;
802 sctx
->b
.b
.delete_fs_state
= si_delete_ps_shader
;